Mechanism for a system-on-chip to enter or exit a retention-level voltage in a low-power mode

Abstract

The present invention discloses a computing device, system and method. The computing device includes a memory storing instructions and a processing circuit coupled to the memory, the processing circuit being configured to execute the instructions to process a first control signal and a second control signal from corresponding first and second control pins of a computing platform. The processing circuit is further configured to further cause the computing platform to transition between a low power state and a hold power state based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform, without transitioning to an operating power state therebetween.

Description

Technical Field

[0001] The embodiments described herein generally relate to power management related to a system-on-chip. Background Art

[0002] Advances in semiconductor processing and logic design have allowed an increase in the amount of logic that may be present on an integrated circuit device. As a result, computer system configurations have evolved from single or multiple integrated circuits in a system to multiple hardware threads, multiple cores, multiple devices, and / or complete systems on a single integrated circuit. Additionally, as the density of integrated circuits has grown, the power requirements of computing systems (ranging from embedded systems to servers) have also increased. Moreover, software inefficiencies and their requirements on hardware have also contributed to increased energy consumption in computing devices. There is a need for energy efficiency and energy conservation related to integrated circuits. These needs will make integrated systems, such as those on wearable devices, more prevalent. Brief Description of the Drawings

[0003] For simplicity and clarity of illustration, the elements shown in the figures are not necessarily drawn to scale. For example, for clarity, the dimensions of some elements may be exaggerated relative to other elements. Additionally, reference numerals may be repeated among the figures to indicate corresponding or similar elements. These drawings are listed below.

[0004] Figure 1 is a control signal logic state diagram of a control signal at a standby (STDBY) pin on a SoC according to the prior art to move the SoC between a low power state and a hold state; Figure 1

[0005] Figure 2 is a schematic diagram of a hardware device including a SoC coupled to a PMIC according to some illustrative embodiments;

[0006] Figure 3 is similar to Figure 2

[0007] Figure 4 is a diagram showing the logic states of the inside of the SoC moving between a low power state and a hold state;

[0008] Figure 5 is a flowchart of a first method according to some illustrative embodiments; and

[0009] Figure 6 is a flowchart of a second method according to some illustrative embodiments. Detailed Description

[0010] ​​In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of some embodiments. However, those of ordinary skill in the art will understand that some embodiments may be practiced without these specific details. In other instances, well-known methods, procedures, components, units, and / or circuits have not been described in detail so as not to obscure the discussion.

[0011] For the sake of brevity and clarity of illustration, the drawings show a general construction manner, and descriptions and details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the discussion of the described embodiments of the present invention. Additionally, the elements in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements in the figures may be enlarged relative to other elements to help improve the understanding of the disclosed embodiments. The same reference numerals in different figures represent the same elements, while similar reference numerals may but do not necessarily represent similar elements.

[0012] The terms "first", "second", "third", "fourth", etc. in the specification and claims are used to distinguish between similar elements and do not necessarily describe a particular sequence or temporal order. It should be understood that such terms are interchangeable under appropriate circumstances so that the embodiments of the present invention described herein can, for example, be operated in an order different from that shown herein or in other ways. Similarly, if a method is described herein as including a series of acts, the order of such acts presented herein is not necessarily the only order in which such acts can be performed, and certain of the described acts may be omitted and / or certain other acts not described herein may be added to the method. Further, the terms "comprising", "including", "having", and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a series of elements need not be limited to those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.

[0013] In the specification and claims, the terms "left", "right", "front", "back", "top", "bottom", "above", "below", etc., if any, are used for descriptive purposes only and do not necessarily describe a permanent relative position. It should be understood that such terms are interchangeable under appropriate circumstances so that the embodiments of the present invention described herein can, for example, be operated in an orientation different from that shown herein or in other ways. The term "coupled" as used herein is defined as connecting directly or indirectly in an electrical or non-electrical manner. Objects described herein as being "adjacent" to each other, depending on the context in which the phrase is used, may be in physical contact with each other, in close proximity to each other, or in the same general area or region as each other. The occurrence of the phrase "in one embodiment" in this document does not necessarily all refer to the same embodiment.

[0014] While the following embodiments are described with reference to energy savings and energy efficiency in particular integrated circuits such as in a computing platform or a processor, other embodiments may be applied to other types of integrated circuits and logic devices. Similar techniques and teachings of the embodiments described herein may be applied to other types of circuits or semiconductor devices that would also benefit from better energy efficiency and energy savings. For example, the disclosed embodiments are not limited to any particular type of computer system such as, for example, a wearable device. That is, the disclosed embodiments may be used in many different system types, ranging from server computers (e.g., tower, rack, blade, microserver, etc.), communication systems, storage systems, desktop computers of any configuration, laptop computers, notebooks, tablets (including 2:1 tablets, phablets, etc.), and may also be used in other devices such as handheld devices, wearable devices, IoT devices, etc.

[0015] Embodiments may be implemented in terminals such as wearable devices, mobile phones, smartphones and phablets, tablets, laptops, desktops, microservers, servers, etc. Further, the apparatus, methods, and systems described herein are not limited to physical computing devices but may also relate to software optimizations for energy savings and energy efficiency. As will become apparent in the following description, embodiments of the methods, apparatus, and systems described herein (whether referring to hardware, firmware, software, or a combination thereof) are crucial for the future of "green technology", e.g., for energy savings and energy efficiency in products that encompass a large portion of the U.S. economy.

[0016] Various use cases or key performance indicators (KPIs) in battery-operated market segments including wearable devices, phones, certain sensors, etc., typically have high power targets. These high-requirement power consumption target use cases typically include small devices (e.g., wearable devices) that must maintain battery power for long periods. Customers tend to compare the power consumption performance of a high-requirement power consumption target use case SoC (e.g., how long the system may run out of battery power) with the power consumption performance of an SoC on a computing platform that, in addition to the SoC, includes discrete functional blocks that can meet the KPI requirements when the SoC is in a retention power state. For a high-requirement power consumption target use case SoC, only the functional modules on the SoC can provide the functions that meet the KPI requirements. Therefore, it is difficult for the SoC to enter a retention power state where some of its functional blocks on the SoC must still consume power to achieve the KPI. Thus, as far as customers are concerned, comparing the power consumption performance of an SoC on a platform that includes the above discrete functional blocks on the one hand, with the power performance of an SoC on a small-size device such as a wearable device on the other hand, poses a challenge to providing power management functions for the latter SoC to boost its power consumption performance to the same level as the former SoC.

[0017] Examples of the Always-On Connectivity (AOAC) SoC functionality on a high-power target device can include a voice wake-up function that requires a circuit block of the SoC to always be listening and looking for a key phrase. Another example includes a pedometer-like function that requires the SoC to continuously poll an external sensor. The KPIs associated with such AOAC functionality can be achieved in the retention power state of the SoC. The retention power state of the SoC corresponds to the absolute minimum of the voltage applied to the SoC to keep its AOAC circuit blocks running. AOAC use cases may benefit from switching between the retention-level power state or voltage (Vretention) and the low-power state or voltage (Vmin), where the voltage supplied to the SoC is higher than Vretention but lower than the operating power state or operating voltage VNN at which the SoC circuit blocks are fully awake and operational.

[0018] Existing SoCs on platforms with high-power target use cases have a mechanism to send control signals to an external power management integrated circuit (PMIC) (and by external PMIC, we mean a PMIC different from the SoC) to let the PMIC know when to control the voltage of the SoC to enter / exit its low-power mode, but there is no mechanism that allows the SoC to transition between the low-power state and the retention power state in the transition state of the operating power state without waking up the SoC, i.e., without exiting the reduced power state. The "reduced power state" refers to all power states below VNN, including the aforementioned low-power state and retention power state.

[0019] As will be mentioned below, the S0 power state for the SoC corresponds to the SoC with its logic rails on and at the operating voltage, where the logic is either active or clock-gated or power-gated. The S0i1 power state of the SoC corresponds to the VNN rail (operating voltage rail) controlled by the PMIC being off, and the VNNAON rail (reduced power rail) controlled by the PMIC being on at the Vmin level. At S0i1, a small portion of the logic may be on, where VNNAON is either active or clock-gated or power-gated. Additionally, the S0i3 power state of the SoC corresponds to the off state of the VNN rail controlled by the PMIC, where the VNNAON rail is at the Vretention level. Only a small portion of the logic remains on, and the maximum frequency can be, for example, 32 kHz. Here, the logic can remain active, but there is no signal swing, and all clocks except the 32 kHz clock may be off.

[0020] Figure 1FIG. 100 is a diagram of the control signal logic state at the standby (STDBY) pin on an AOAC type system-on-chip according to the prior art. Figure 1 The time domain is shown in the horizontal direction, and the power state of the SoC, the control signal logic state of the control signal at the STDBY pin, and the voltage states of the operating power state voltage pin VNN 103 and the reduced power state voltage pin VNNAON 104 of the prior art SoC are shown in the top power state band 101. "Control signal logic state" refers to the logic state of the control signal, that is, the logic state indicated by the control signal to the receiver of the control signal. The logic state can be, for example, an on state or an off state. As Figure 1 shown in the example prior art figure, the control signal (seen on the control signal logic state line 102) emitted from the STDBY pin of the SoC moves or transitions between the off logic state (lower part of the line) and the on logic state (higher part of the line). The transition of the control signal logic state of the STDBY pin corresponds to the power state of the SoC as shown in band 101. The off logic state of the STDBY pin corresponds to the operating power state or S0 of the SoC, while the on logic state of the STDBY pin corresponds to the low power state of the SoC, which includes the low power state S0i1 and the hold power state S0i3. As Figure 1 shown, in each case, the control signal from the STDBY pin transitioning between the off state (S0) and the on state (S0i1 or S0i3) causes the control signal logic state to transition between the operating power state S0, the low power state S0i1, and the hold power state S0i3. Each logic state of the STDBY pin control signal can be communicated to a controller, such as a PMIC, via the STDBY pin. Then, the PMIC can, as shown by arrow 105: (1) drive the VNN voltage pin to a lower power state (S0i1 or S0i3) since the control signal from the STDBY pin is in the on logic state. (2) drive the VNNAON voltage pin to the hold power state (S0i3) or drive it to the low power state (S0i1) since the control signal from the STDBY pin is in the off logic state. As Figure 1 shown by the hysteresis time 106 in, there may be a hysteresis time between the time of the change in the control logic state of the STDBY pin and the time of the response of the VNN or VNNAON pin. The hysteresis time 106 may be caused by the time required for the control signal from the STDBY pin to be transmitted to the PMIC, the processing time within the PMIC, and the time required for the PMIC to implement a voltage conversion on VNN or VNNAON.

[0021] Since there is only one STDBY pin on the prior art SoC, therefore, as Figure 1As shown by the I2C line in [reference], the prior art solution communicates the definition of the reduced power state of the SoC to the PMIC via an Inter-Integrated Circuit (I2C) interface. As Figure 1 shown, an I2C signal (shown as a diamond) 107 is communicated from the SoC to the PMIC to transfer the low power state Vmin or the retention power state Vretention of the SoC to the PMIC. However, using the I2C protocol requires the Vmin state of the SoC. Therefore, considering that other low power mode KPIs will also be effective for the SoC in addition to the I2C interface, the SoC must transition to the operating power state (perform a full wake-up to S0), and the operating power state requires the PMIC to provide all voltage rails to the operating power state of the SoC.

[0022] As still seen in Figure 1 [reference], according to the prior art, in order to transition the SoC power state to S0i3 (retention power state), the SoC must wake up to its operating power state S0 to allow the I2C interface to communicate with the PMIC. Therefore, the prior art solution for AOAC type SoCs presents solutions with relatively high latency for entering and exiting the low power state Vmin and the retention power state Vretention. To communicate with the PMIC to determine whether the SoC needs to be in the low power state or the retention power state, it must return to the operating power consumption state, which disadvantageously results in a power loss of many milliwatts.

[0023] To save power in some of these AOAC use cases, the SoC may need to perform an aggressive transition between the low power state and the retention power consumption state without the need to fully wake up to its operating power state. In this way, while achieving the KPIs, it remains within the range of its power performance target. When the SoC is in the low power state in a battery-operated device, the above advantages benefit key SoC KPIs, such as sensor hub KPIs, on-die Wi-Fi / BT / GNSS pings, on-die modem pings, etc.

[0024] When the SoC is in a low-power state, it keeps certain circuit blocks or certain parts of circuit blocks (such as interconnects, on-die modems, audio, and sensor hub circuit blocks) on a voltage rail that is kept on (e.g., via the VNNAON pin), while the remaining SoC voltage rails (such as VNN and VSRAM) are all turned off to save power. When the VNN rail is turned off in turn, the circuit blocks that need to be kept in the on-voltage state have active and inactive duty cycles, so that VNNAON remains at Vmin when active (low-power state of the SoC), and VNNAON remains at Vretention when inactive. The above is the only way for the SoC power to be low enough to be comparable to any external discrete KPI solution. However, the delays in entering and exiting the Vmin and Vretention levels are critical and need to be as low as possible, e.g., a few microseconds.

[0025] Some illustrative embodiments provide a mechanism for the SoC to communicate with the PMIC so that the PMIC can control the SoC voltage to be controlled between the Vmin level and the Vretention level without moving to the operating power state in between. To achieve the above purpose, one embodiment contemplates providing a vSTDBY pin in addition to the existing standby (STBY) pin on the SoC input / output interface. This new vSTDBY pin is used to communicate a control signal to the PMIC to inform the PMIC that the SoC needs to perform an aggressive transition between the Vmin and Vretention power states without entering the operating power state through VNN in between, and at the same time maintain the low-power state / mode (including Vmin and Vretention, but not including VNN). The assertion / de-assertion control signal to the PMIC's vSTDBY pin can be processed in power management hardware that can operate at a hold-level voltage such as using 32KHz.

[0026] Now referring to Figure 2 , a block diagram of a computer system 200 and components present in the computer system according to an embodiment of the present invention is shown. Figure 2 Can be used to implement any of the operations that will be further described with respect to the embodiments, such as the exemplary operations described below with respect to Figures 3 to 5 described.

[0027] System 200 can include any combination of components, some of which are shown by way of example in the drawings. These components can be implemented as ICs suitable for a computer system, parts thereof, discrete electronic devices or other modules, logic, hardware, software, firmware, or a combination thereof, or can be implemented as components incorporated into the computer system's rack in other ways. It should also be noted that Figure 2The block diagram is intended to show a high-level view of many components of a computer system. However, it should be understood that some of the components shown may be omitted, additional components may exist, and different arrangements of the components shown may occur in other embodiments.

[0028] For example, the computer system 200 may be a mobile low-power system, such as a wearable device, a low-power sensor, a tablet computer, a phablet, or other convertible or stand-alone systems, such as a stand-alone mobile system or a non-mobile system.

[0029] As Figure 2 shown, in one embodiment, the computer system 200 may include an SoC 202. Generally, the SoC 202 may integrate multiple circuit blocks including processing circuits (e.g., intellectual property / IP blocks) into a common package, where different circuit blocks may perform different functions. The circuit blocks (e.g., the individual blocks of the SoC 202), may be connected to one or more voltage rails ( Figure 2 the dashed lines in) via a power management circuit (PMC) 206 on the SoC, via voltage pins VNN 223 (controlled by the PMIC and used to drive the operating power state) and VNNAON 221 (controlled by the PMIC and used to drive reduced power states, including the hold power state and the low power state), and the circuit blocks may be placed independently in different power states to improve energy efficiency and / or reduce energy consumption. The transition of the circuit blocks within the SoC 202 between different power states may be achieved by control signals provided to the circuit blocks and traveling through a control signal path shown by the connection lines between the circuit blocks as Figure 2 in. The control signal path may include an I2C signal path, or other types of control signal paths known to those skilled in the art. The various circuit blocks on the computer system 200 may be functionally interconnected / coupled in a well-known manner.

[0030] According to some illustrative embodiments, certain platforms may include a single VNNAON rail and may include an internally derived VNN equivalent rail (i.e., without using the VNN pins on the SoC). In this case, the embodiment may allow switching between the Vmin and Vretention states only by controlling the voltage input on the (VNNAON) rail.

[0031] The circuit block may include multiple processing circuits, such as a series of wireless baseband processors (BB) 205, a transceiver 214 including a front-end module circuit and a radio integrated circuit (not shown) coupled to respective baseband processors, a video encoder / decoder (video codec) 215, an audio encoder / decoder 217, a display unit 209, a sensor hub 212, an application processor 210, and a PMC 206. Each processing circuit may include a microprocessor, a multi-core processor, a multi-threaded processor, an ultra-low voltage processor, an embedded processor, or other known processing elements or circuits. In the illustrated embodiment, the SoC 202 may serve as the main processing unit and central hub for communicating with many different components of the system 200. However, the embodiments are not limited to the SoC, and the scope also includes power regulation and management for any collection of processing circuits, whether on the SoC or discrete.

[0032] The SoC may further include a display unit 209, which may include a high-definition LCD or LED panel. The display panel may also provide touchscreen functionality. The display panel may operate in multiple modes. In a first mode, the display panel may be arranged in a transparent state, in which the display panel is transparent to visible light. In various embodiments, most of the display panel may be a display except for a border around the perimeter. When the system is operating in laptop mode and the display panel is operating in the transparent state, the user may view the information displayed on the display panel while also viewing the objects behind the display. Additionally, the information displayed on the display panel may be viewed by the user located behind the display. Alternatively, the operating state of the display panel may be an opaque state, in which visible light does not transmit through the display panel.

[0033] SoC 202 may further include a memory unit 213. The SoC may further include one or more flash memory devices (not shown for simplicity) coupled to one or more processors, for example, via a Serial Peripheral Interface (SPI). The flash memory devices may provide non-volatile storage of system software, including basic input / output software (BIOS) and other firmware of the system. The memory unit 213 on the SoC 202 and the memory 232 on the computing system 200 may each be implemented via a plurality of memory devices or modules to provide a given amount of system memory. In one embodiment, one or more of the memory unit 213 or the memory 232 may operate according to a Joint Electron Device Engineering Council (JEDEC) Low Power Double Data Rate (LPDDR)-based design (e.g., according to the current LPDDR2 standard of JEDEC JESD 209-2E (released in April 2009), or the next-generation LPDDR standards known as LPDDR3 or LPDDR4 that will provide an extension to LPDDR2 to increase bandwidth). In various embodiments, the individual storage devices may have different package types, such as a Single Die Package (SDP), a Dual Die Package (DDP), or a Quad Die Package (QDP). Other memory implementations are also possible, such as other types of memory modules, e.g., different types of Dual In-line Memory Modules (DIMMs) including but not limited to microDIMM, MiniDIMM. In one embodiment, one or more of the memory unit 213 or the memory 232 may be sized between 2GB and 16GB and may be configured as a DDR3LM package or an LPDDR2 or LPDDR3 memory. The memory unit 213 may be configured as a mass storage device such as a Hard Disk Drive (HDD) or a Solid State Drive (SSD). Memories 213 and 232 may further include volatile memory.

[0034] SoC 202 may further include wireless connection circuitry via the wireless BB 205, transceiver 214, and antenna 226, where each of the wireless BB 205, transceiver 214, and antenna 226 may correspond to a specific wireless communication protocol, such as a Near Field Communication (NFC), Wi-Fi, or Bluetooth (BT) standard. Additionally, the wireless BB 205, transceiver 214, and antenna 226 may provide wireless wide area communication, for example, according to a cellular or other wireless wide area protocol.

[0035] For sensing computing and other purposes, different sensors may exist as part of the SoC, as shown by sensor hub 212. Sensor hub 212 may include certain inertial and environmental sensors, as well as their interconnections with application processor 210 and PMC 206 as shown. These sensors may include, for example, accelerometers, ambient light sensors (ALS), compasses, gyroscopes, and thermal sensors. Using various inertial and environmental sensors that are part of the SoC or otherwise present on computer system 200, many sensors can enable different use cases. These use cases can perform advanced computing operations including sensing computing, and can also enhance power management / battery life, security, and system responsiveness.

[0036] SoC 202 may further include PMC 206, which may be implemented in hardware, software, and / or firmware, and may operate to provide voltage regulation and power management within different circuit blocks of SoC 202. As will be explained in further detail in conjunction with Figures 3 - 6 PMC 206 may be coupled, for example, to standby pin 220 and vSTDBY pin 222 to receive and process or forward control signals from the PMIC to transition the power state within one or more circuit blocks of SoC 202.

[0037] SoC 202 may further include internal bus 218 to allow routing of control connections shown by the connecting lines in Figure 2 The connecting lines depicted in SoC 202 are schematic diagrams of some exemplary control signal paths within computer system 200, and other configurations and other control signal paths are within the knowledge of those skilled in the art. The control signal paths may include I2C interconnections to carry control signals to and from different processing circuits.

[0038] There may also be various input / output (I / O) devices shown by block 225 on SoC 202, for example, including power pins, control pins, and other pins as would be recognized by those skilled in the art. Among the I / O components of SoC 202, standby pin 220 and vSTDBY pin 222 are provided to receive and send control signals. For example, standby pin 220 and vSTDBY pin 222 may receive control signals from power management integrated circuit (PMIC) 204 of computer system 200, and may send those control signals to PMC 206 of SoC 202 to cause the power state of the SoC to change between various possible power states, in a manner that will be further described below with respect to some illustrative embodiments. Although Figure 1The PMIC 204 is shown external to the SoC 202, but embodiments within its scope include providing a PMIC or on-die regulator that functions similarly to the PMIC on the SoC 202 itself, where in such a case, the on-die regulator would regulate VNN and / or VNNAON within the SoC 202.

[0039] Referring now to computer system 200, the system may in turn include a plurality of various circuit blocks, such as, for example, PMIC 204, a battery 234 that powers different circuit blocks, an Ethernet interface 236, a controller 228, a touch panel 238 that provides display capabilities and user input via touch, where the touch panel 238 includes a virtual keyboard provided on the display of the touch panel. To provide a wired network connection, computer system 200 may include an Ethernet interface (IF) 236. A peripheral hub within the input / output unit 235 may implement an interface to various peripheral devices, such as may be coupled to system 200 through any one of a variety of ports or other connectors. Any circuit block of computer system 200 may be functionally coupled to any circuit block of SoC 202 in a known manner.

[0040] In addition to the internal PMC within the SoC, computer system 200 may also include functionality within SoC 202 provided by PMIC 204, PMC 206. PMIC 204 may be coupled to SoC 202 to provide platform-based power management, e.g., power management based on whether the system is powered by battery 234 or by AC power via an AC adapter (not shown). In addition to this power-based power management, PMIC 204 may also perform platform power management activities based on environmental and usage conditions. Further still, PMIC 204 may communicate control and status information to SoC 202 to cause different power management actions within SoC 202. PMIC 204 may include hardware, software, and / or firmware that performs power management operations with respect to SoC 202 as well as with respect to other components of computer system 200. PMIC 204 may provide control signals to control pins on SoC 202, e.g., in the illustrated embodiment, to standby pin 220 and vSTDBY pin 222 as well as other possible pins, in order to generate appropriate regulated voltages within the various components of the SoC. The PMIC is configured to implement various power state transitions within SoC 202 in order to conserve power. According to some exemplary embodiments, during power management, while other power planes may be powered down or turned off when the processor enters certain deep sleep states, a hold power plane may remain powered on to support certain circuit blocks of the SoC.

[0041] It should be noted that although Figure 2The connections between the various components of computer system 200 are shown in the form of connecting lines, but it should be understood that the control and voltage connections or rails are for the purpose of only showing examples of possible connections and can be implemented in any manner based on the knowledge of those skilled in the art to achieve the advantages of the embodiments described herein. Additionally, it should be understood that although not shown for ease of reference and description, there are other rails within computer system 200, including other control rails and pins, voltage rails and pins, and other rails and pins within the knowledge of those skilled in the art. Although not shown for ease of illustration, it should be understood that there may be other components within computer system 200, such as one or more independent graphics processors, core logic, non-core logic, and other components such as internal memory (e.g., one or more levels of cache memory hierarchies, etc.). Additionally, as previously described, power management according to embodiments is not limited to power management within the SoC, but rather relates to power management within any computing platform that includes multiple circuit blocks.

[0042] Each of PMC 206 and PMIC 204 may include one or more IP (intellectual property) or functional blocks. Each IP block may include circuitry that performs different functions, such as logic units and storage cores. The storage core may include volatile storage units that are continuously supplied with a power voltage to maintain the stored data. In some exemplary embodiments, the memory core may include static random access memory (SRAM) units. In other exemplary embodiments, the memory core may include dynamic random access memory (DRAM) units. Each logic unit may further include peripheral circuitry (not shown) for controlling the memory core.

[0043] Figure 3 is similar to Figure 2 FIG. 300, which shows the control signal logic states of the control signals at the STANDBY pin and the vSTANDBY pin according to some illustrative embodiments. Similar to Figure 1 is similar, Figure 3 displays the time domain in the horizontal direction and shows the power state of the SoC displayed in the top power state band 301, the control signal logic state line 302 of the control signal at the STANDBY pin, and the control signal logic state line 330 of the control signal at the vSTANDBY pin. Similar to Figure 1 , the logic state of each control pin, STANDBY or vSTANDBY, may include, for example, an on state or an off state. As in Figure 3As shown in the example, the control signal issued from the STDBY pin or the vSTDBY pin of the SoC may move or transition between the off logic state (the lower part of the line) and the on logic state (the higher part of the line) as seen from the control signal logic state lines 302 and 330. As shown, the transition of the control signal logic state of the STDBY pin and the vSTDBY pin corresponds to the transition of different power states of the SoC. Here, compared with the prior art, the additional vSTDBY pin is used to convey whether the reduced power state should correspond to the low power state at Vmin or the retention power state at Vretention, which will be further explained below. Thus, compared with the prior art (e.g., Figure 1 ), there will be no need for I2C communication to communicate this information, and the SoC will not need to move to the operating power state before transitioning between the low power state and the retention power state.

[0044] Still referring to Figure 3 , the off logic state of the STDBY pin corresponds to the operating power state or S0 of the SoC, and the off logic state of the STDBY pin corresponds to the operating power state of the SoC at S0, and the on logic state of the STDBY pin corresponds to the reduced power state of the SoC, and the reduced power state includes the low power states at Vmin and S0i1 and the retention power states at Vretention and S0i3. As Figure 1 shown, the transition of the control signal logic state between the operating power state S0 and the reduced power state is in each case caused by the control signal from the STDBY pin transitioning between the off state (S0) and the on state (S0i1 or S0i3). Each logic state of the STDBY pin control signal can be communicated to the controller, such as the PMIC, via the STDBY pin. Additionally, when the STDBY pin is already at S0, the transition of the control signal logic state between the low power state and the retention power state is in each case caused by the control signal from the vSTDBY pin transitioning between the off state (S0 or S0i1) and the on state (S0i3). Therefore, the PMIC can use the combination of the control signals from the STDBY and vSTDBY pins to determine whether the SoC needs to be placed in the low power state or the retention power consumption state.

[0045] Still referring to Figure 3 , for example, although both the STDBY pin and the vSTDBY pin are in the same logic off state, the SoC may be in the S0 power state. When the STDBY pin is on and the vSTDBY pin is off, the SoC may be in the S0i1 power state, and when both the STDBY pin and the vSTDBY pin are in the same logic on, the SoC may be in the S0i3 power state. As Figure 3As shown, the STDBY pin can be used as the envelope of the vSTDBY pin, which means that if the STDBY pin is already in the on state, the vSTDBY pin may only be in the on state. Therefore, the vSTDBY pin needs to be in the off state before the STDBY pin can switch to the off state.

[0046] After receiving control signals from the STDBY pin and the vSTDBY pin, the PMIC can then: (1) drive the VNN voltage pin between the operating power state and the reduced power state due to the combination of signals from the STDBY pin and the vSTDBY pin; and (2) drive the VNNAON voltage pin to the retention power state (S0i3) or to the low power state (S0i1) due to the combination of signals from the STDBY pin and the vSTDBY pin. Similar to Figure 1 there may be a latency between the time of the control logic state transition of the STDBY pin and the vSTDBY pin and the time the VNN or VNNAON pin responds under the control of the PMIC. The time latency may still be caused by the time required for the control signals from the STDBY pin and the vSTDBY pin to be transmitted to the PMIC, the processing time within the PMIC, and the time required for the PMIC to implement the voltage conversion on the VNN or VNNAON.

[0047] Advantageously, using a second control pin, such as the vSTDBY pin described above, can significantly reduce the waiting time for the SoC (e.g., AOAC SoC) to transition between the low power state and the retention power consumption state, and further save a significant amount of energy by avoiding the need to move to the operating power state for the transition, thus improving the power consumption performance of the SoC to be comparable to that of the SoC on a computing platform using a discrete KPI solution.

[0048] Figure 4 is a diagram showing the logical states inside the SoC moving between the low power state and the retention state, e.g., moving from Figure 3 the first S0i1 state of Figure 3 to the first S0i3 state of Figure 3 and Figure 4 substantially is a diagram focusing on Figure 3 a series of power state transitions of Figure 4 More specifically, Figure 2 shows the STDBY pin, the vSTDBY pin, and the PMC (e.g., Figure 2The logic state of the interconnection between given circuit blocks of the SoC 202). A given circuit block or "hold circuit block" can be any circuit block that will be in a hold state during the hold power state of the SoC, such as, for example, Figure 2 the sensor hub 212. Figure 4 Also shown is the voltage state of the VNNAON pin of the SoC, such as Figure 2 VNNAON 221. Similar to Figure 1 , Figure 3 the time domain is shown in the horizontal direction, and the power state of the SoC shown in the top power state band 401, the control signal logic state of the control signal 402 at the STDBY pin, and the control signal logic state of the control signal at the vSTDBY pin 430 are shown.

[0049] Still referring to Figure 4 , line 402 shows that when the SoC is in a reduced power state transitioning between S0i1 and S0i3, the control signal logic state of the STDBY pin is flat in the on state. When the hold circuit block needs to enter the hold power state, it can send a control signal of type IP_VNNAON_ACTIVE_REQ 403 to the PMC by transitioning the control signal logic state of the communication between the hold circuit block and the PMIC from the on state to the off state (during time 442), to request the PMC to control the vSTDBY pin to send a control signal to the PMIC asking the PMIC to switch the VNNAON pin to the hold voltage value. After the hysteresis time 440, the vSTDBY pin control signal logic state thus changes from the off state to the on state (during time 444). When the vSTDBY control signal logic state transitions, the PMC sends a PMC control signal of type PMC_VNNAON_ACTIVE_ACK 405 (by transitioning the logic state of PMC_VNNAON_ACTIVE from the on state to the off state during time 448) to the hold circuit block to confirm that the vSTDBY control signal logic state has transitioned to the on state. After the hysteresis time 450 after the time when the vSTDBY pin control signal logic state transitions to the on state, the VNNAON voltage pin controlled by the PMIC enters the hold state during time 452, as shown by line 407.

[0050] When the hold circuit block needs to enter the low-power state, a control signal of type IP_VNNAON_ACTIVE_REQ can be sent to the PMC by changing the logic state of the control signal for the communication between the hold circuit block and the PMIC from the off state to the on state (after time 442), to request the PMC to control the vSTDBY pin to send a control signal to the PMIC to request the PMIC to switch the VNNAON pin from the hold voltage value to the low-power value, as shown in line 407. Thus, after the hysteresis time 446, the logic state of the vSTDBY pin control signal changes from the on state to the off state (after time 444).

[0051] When the logic state of the vSTDBY control signal switches back to the off state, the VNNAON pin remains at the hold voltage level. After the hysteresis time, the VNNAON voltage pin switches to the Vmin level, at which time, after time 448, the PMC_VNNAON_ACTIVE_ACK control signal changes from the off state back to the on state.

[0052] Figure 5 is a flowchart of a first method according to some illustrative embodiments. At operation 502, the method includes sending corresponding control signals to a power management integrated circuit (PMIC) from a first control pin and a second control pin of a computing platform. At operation 504, the method includes transitioning the platform between a low-power state and a hold-power state based on a combination of the control signals without entering a working-power state therebetween, including transitioning at least a portion of the platform using at least one voltage pin coupled to a plurality of circuit blocks and controlled by the PMIC.

[0053] Figure 6 is a flowchart of a second method according to some illustrative embodiments. Operation 602 includes processing a first control signal and a second control signal from a corresponding first control pin and a second control pin of a computing platform. Operation 604 includes transitioning the computing platform between a low-power state and a hold-power state based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform without transitioning to a working-power state therebetween.

[0054] According to some illustrative embodiments, a computing platform such as SoC 202 or a computer system 200 such as Figure 2 can include a plurality of circuit blocks, such as any one of circuit blocks 204, 206, 209, 210, 212, 214, 215, 217 of SoC 202. The computing platform may also include at least one voltage pin coupled to the plurality of circuit blocks, such as Figure 2 voltage pins VNNAON 221 and VNN 223. The voltage pins will be controlled by, for example Figure 2is controlled by a power management integrated circuit (PMIC) 204, and causes at least a portion of the platform to transition between an operating power state, a low power state, and a retention power state. The computing platform further includes a first control pin, such as Figure 2 the STANDBY pin 220, and further includes a second control pin, such as Figure 2 the vSTANDBY pin 222, which is configured to send a corresponding control signal to the PMIC. The PMIC will control at least one voltage pin based on a combination of the control signals to cause at least a portion of the platform to transition between the low power state and the retention power state without transitioning to the operating power state therebetween.

[0055] According to some illustrative embodiments, a computing device such as Figure 2 the PMIC 204 or a computing system such as Figure 2 includes a memory (such as a memory within the PMIC) storing instructions and a processing circuit coupled to the memory, the processing circuit being configured to execute the instructions to process a first control signal and a second control signal from a corresponding first control pin and a second control pin of the computing platform. The first control pin may correspond, for example, to Figure 2 the STANDBY pin 220, and the second control pin may correspond, for example, to Figure 2 the vSTANDBY pin 222. The processing circuit further causes the computing platform to transition between the low power state and the retention power state based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform (such as Figure 2 the voltage pin VNNAON 221) without transitioning to the operating power state therebetween.

[0056] As described herein, examples may include or operate on logic or multiple components, modules, or mechanisms. A module is a tangible entity (e.g., hardware) capable of performing particular operations when operating. A module includes hardware. In one example, the hardware may be specifically configured to perform particular operations (e.g., hardwired). In another example, the hardware may include a configurable execution unit (e.g., transistors, circuitry, etc.) and a computer-readable medium containing instructions that configure the execution unit to perform particular operations when operating. The configuration may be performed under the guidance of the execution unit or a loading mechanism. Thus, when the device is operating, the execution unit is communicatively coupled to the computer-readable medium. In this example, the execution unit may be a member of more than one module. For example, when operating, the execution unit may be configured by a first set of instructions to implement a first module at one point in time and may be reconfigured by a second set of instructions to implement a second module at a second point in time.

[0057] For example, again referring to Figure 2, the storage units or memories internal to each of PMC 206 and PMIC 204, or memory 232, or other memories or combinations of memories on system 200 may include machine-readable media having stored thereon one or more sets of data structures or instructions (e.g., software) embodied or utilized by any of the techniques or functions described herein. During execution of instructions by a machine, the instructions may also reside, completely or at least partially, within the main memory, within static memory, or within the processing circuitry. In an example, one or any combination of the processing circuitry, main memory, static memory, or other storage devices may constitute machine-readable media.

[0058] Some illustrative embodiments may be implemented in whole or in part in software and / or firmware. The software and / or firmware may take the form of instructions embodied in or on a non-transitory computer-readable storage medium. Those instructions may then be read and executed by one or more processors to enable performance of the operations described herein. Those instructions may then be read and executed by one or more processors to cause Figure 2 system 200 to perform the methods and / or operations described herein. The instructions may be in any suitable form, such as but not limited to source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. Such computer-readable media may include any tangible non-transitory medium for storing information in one or more computer-readable forms, such as but not limited to read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory, etc.

[0059] The functions, operations, components, and / or features described herein with reference to one or more embodiments may be combined with, or used in conjunction with, one or more other functions, operations, components, and / or features described herein with reference to one or more other embodiments, and vice versa.

[0060] Example:

[0061] The following examples relate to additional embodiments.

[0062] Example 1 includes a computing platform that includes: a plurality of circuit blocks; at least one voltage pin coupled to the plurality of circuit blocks and controlled by a power management integrated circuit (PMIC) to cause at least a portion of the platform to transition between an operating power state, a low power state, and a retention power state; a first control pin and a second control pin configured to send respective control signals to the PMIC, the PMIC controlling the at least one voltage pin based on a combination of the control signals to cause at least a portion of the platform to transition between the low power state and the retention power state without transitioning to the operating power state therebetween.

[0063] Example 2 includes the subject matter of Example 1, and optionally, wherein: each respective control signal is used to indicate an on-logic state or an off-logic state for a respective one of the first control pin and the second control pin; and the same logic state between the first control pin and the second control pin is used to indicate one of an operating power state or a hold power state, and wherein a different logic state between the first control pin and the second control pin is used to indicate a hold power state.

[0064] Example 3 includes the subject matter of Example 2, and optionally, wherein: a logic state of both off for the first control pin and the second control pin is used to indicate an operating power state, a logic state of both on for the first control pin and the second control pin is used to indicate a hold power state; and an on-logic state of the first control pin and an off-logic state of the second control pin indicate a low power state.

[0065] Example 4 includes the subject matter of Example 3, and optionally, wherein an on-logic state of the first control pin serves as an envelope for an on-logic state of the second control pin.

[0066] Example 5 includes the subject matter of Example 1, and optionally, wherein the first control pin is a STANDBY pin and the second control pin is a vSTANDBY pin.

[0067] Example 6 includes the subject matter of Example 1, and optionally, further includes a power management circuit (PMC) coupled to the second control pin, the PMC being configured to send a PMC control signal to the second control pin to request the second control pin to change its logic state.

[0068] Example 7 includes the subject matter of Example 1, and optionally, wherein the voltage pin includes a VNNAON pin configured to be coupled to a voltage rail of a PMIC.

[0069] Example 8 includes the subject matter of Example 1, and optionally, wherein the computing platform is a system-on-chip.

[0070] Example 9 includes the subject matter of any one of Examples 1-8, and optionally, further includes a PMIC, wherein at least one voltage pin, the first control pin, and the second control pin are coupled to the PMIC.

[0071] Example 10 includes the subject matter of Example 9, and optionally, further includes a wireless connection circuit.

[0072] Example 11 includes a method to be executed on a computing platform including multiple circuit blocks, the method including: sending respective control signals from a first control pin and a second control pin of the computing platform to a power management integrated circuit (PMIC); and based on a combination of the control signals, transitioning the platform between a low power state and a hold power state without entering an operating power state therebetween, including transitioning at least a portion of the platform using at least one voltage pin coupled to the multiple circuit blocks and controlled by the PMIC.

[0073] Example 12 includes the subject matter of Example 11, and optionally, wherein: each respective control signal is used to indicate an on logic state or an off logic state for a respective one of the first control pin and the second control pin; and the same logic state between the first control pin and the second control pin is used to indicate one of an operating power state or a hold power state, and wherein a different logic state between the first control pin and the second control pin is used to indicate a hold power state.

[0074] Example 13 includes the subject matter of Example 12, and optionally, wherein an off logic state for both the first control pin and the second control pin is used to indicate an operating power state, and an on logic state for both the first control pin and the second control pin is used to indicate a hold power state.

[0075] Example 14 includes the subject matter of Example 13, and optionally, wherein an on logic state of the first control pin and an off logic state of the second control pin indicate a low power state.

[0076] Example 15 includes the subject matter of Example 14, and optionally, wherein an on logic state of the first control pin serves as an envelope for an on logic state of the second control pin.

[0077] Example 16 includes the subject matter of Example 11, and optionally, wherein the first control pin is a STANDBY pin and the second control pin is a vSTANDBY pin.

[0078] Example 17 includes the subject matter of Example 11, and further includes sending a power management circuit control signal to the second control pin to request the second control pin to change its logic state.

[0079] Example 18 includes a product that includes one or more tangible computer-readable non-transitory storage media that include computer-executable instructions that, when executed by at least one computer processor, cause the at least one computer processor to implement operations on a computing platform that includes a plurality of circuit blocks, the operations including: sending respective control signals from a first control pin and a second control pin of the computing platform to a power management integrated circuit (PMIC); and causing the platform to transition between a low power state and a hold power state based on a combination of the control signals without entering an operating power state therebetween, including causing at least a portion of the platform to transition using at least one voltage pin coupled to the plurality of circuit blocks and controlled by the PMIC.

[0080] Example 19 includes the subject matter of Example 18, and optionally, wherein each respective control signal is used to indicate an on logic state or an off logic state for a respective one of the first control pin and the second control pin; and the same logic state between the first control pin and the second control pin is used to indicate one of an operating power state or a hold power state, and wherein a different logic state between the first control pin and the second control pin is used to indicate a hold power state.

[0081] Example 20 includes the subject matter of Example 19, and optionally, wherein an off logic state for both the first control pin and the second control pin is used to indicate an operating power state, and an on logic state for both the first control pin and the second control pin is used to indicate a hold power state.

[0082] Example 21 includes the subject matter of Example 20, and optionally, wherein an on logic state of the first control pin and an off logic state of the second control pin are used to indicate a low power state.

[0083] Example 22 includes the subject matter of Example 21, and optionally, wherein an on logic state of the first control pin serves as an envelope for an on logic state of the second control pin.

[0084] Example 23 includes the subject matter of Example 18, and optionally, wherein the first control pin is a STANDBY pin and the second control pin is a vSTANDBY pin.

[0085] Example 24 includes the subject matter of Example 18, and optionally, the operations further include sending a power management circuit control signal to the second control pin to request that the second control pin change its logic state.

[0086] Example 25 includes a computing platform that includes a plurality of circuit blocks and further includes: a module for sending respective control signals from a first control pin and a second control pin of the computing platform to a power management integrated circuit (PMIC); and a module for transitioning the platform between a low power state and a hold power state based on a combination of the control signals without transitioning to an operating power state therebetween, including transitioning at least a portion of the platform using at least one voltage pin coupled to the plurality of circuit blocks and controlled by the PMIC.

[0087] Example 26 includes the subject matter of Example 25, and optionally, wherein: each respective control signal is used to indicate an on logic state or an off logic state for a respective one of the first control pin and the second control pin; and the same logic state between the first control pin and the second control pin is used to indicate one of an operating power state or a hold power state, and wherein a different logic state between the first control pin and the second control pin is used to indicate a hold power state.

[0088] Example 27 includes the subject matter of Example 26, and optionally, wherein an off logic state for both the first control pin and the second control pin is used to indicate an operating power state, and an on logic state for both the first control pin and the second control pin is used to indicate a hold power state.

[0089] Example 28 includes the subject matter of Example 27, and optionally, wherein an on logic state of the first control pin and an off logic state of the second control pin are used to indicate a low power state.

[0090] Example 29 includes the subject matter of Example 28, and optionally, wherein an on logic state of the first control pin serves as an envelope for an on logic state of the second control pin.

[0091] Example 30 includes the subject matter of Example 25, and optionally, wherein the first control pin is a STANDBY pin and the second control pin is a vSTANDBY pin.

[0092] Example 31 includes the subject matter of Example 25, and optionally, further includes a module for sending a power management circuit control signal to the second control pin to request that the second control pin change its logic state.

[0093] Example 32 includes a computing device that includes a memory storing instructions and a processing circuit coupled to the memory, the processing circuit being configured to execute the instructions to: process a first control signal and a second control signal from a respective first control pin and a second control pin of a computing platform; and transition the computing platform between a low power state and a hold power state based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform without transitioning to an operating power state therebetween.

[0094] Example 33 includes the subject matter of Example 32, and optionally, wherein: each respective control signal is used to indicate an on logic state or an off logic state for a respective one of the first control pin and the second control pin; and the same logic state between the first control pin and the second control pin is used to indicate one of a working power state or a holding power state, and wherein a different logic state between the first control pin and the second control pin is used to indicate a holding power state.

[0095] Example 34 includes the subject matter of Example 33, and optionally, wherein: the logic state where both the first control pin and the second control pin are off is used to indicate a working power state, and the logic state where both the first control pin and the second control pin are on is used to indicate a holding power state.

[0096] Example 35 includes the subject matter of Example 32, and optionally, wherein the processing circuit further causes the computing platform to transition between a working power state, a low power state, and a holding power state by controlling the power supply to at least one voltage pin of the computing platform.

[0097] Example 36 includes the subject matter of Example 32, and optionally, wherein the at least one voltage pin includes a VNNAON pin, and the processing circuit is coupled to the VNNAON pin.

[0098] Example 37 includes the subject matter of Example 32, and optionally, wherein the computing device includes a power management integrated circuit (PMIC).

[0099] Example 38 includes the subject matter of Example 37, and optionally, further includes a system on a chip (SoC), wherein the at least one voltage pin, the first control pin, and the second control pin are coupled to the PMIC.

[0100] Example 39 includes the subject matter of any one of Examples 32 - 38, and optionally, further includes a wireless connection circuit.

[0101] Example 40 includes a method for execution on a computing device, the method comprising: processing a first control signal and a second control signal from respective first and second control pins of a computing platform; and transitioning the computing platform between a low power state and a holding power state based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform without transitioning to a working power state therebetween.

[0102] Example 41 includes the subject matter of Example 40, and optionally, wherein: a logic state in which both the first control pin and the second control pin are off is used to indicate an operating power state, and a logic state in which both the first control pin and the second control pin are on is used to indicate a retention power state; and the same logic state between the first control pin and the second control pin is used to indicate one of the operating power state or the retention power state, and wherein a different logic state between the first control pin and the second control pin is used to indicate the retention power state.

[0103] Example 42 includes the subject matter of Example 41, and optionally, wherein: a logic state in which both the first control pin and the second control pin are off is used to indicate an operating power state, and a logic state in which both the first control pin and the second control pin are on is used to indicate a retention power state; and an on logic state of the first control pin and an off logic state of the second control pin are used to indicate a low power state.

[0104] Example 43 includes the subject matter of Example 40, and optionally, wherein the operation further includes transitioning the computing platform between an operating power state, a low power state, and a retention power state by controlling a power supply to at least one voltage pin of the computing platform.

[0105] Example 44 includes the subject matter of Example 40, and optionally, wherein the at least one voltage pin includes a VNNAON pin, and the processing circuit is coupled to the VNNAON pin.

[0106] Example 45 includes the subject matter of Example 40, and optionally, wherein the computing device includes a power management integrated circuit (PMIC), and the computing platform includes a system-on-chip (SoC).

[0107] Example 46 includes the subject matter of Example 41, and optionally, wherein the at least one voltage pin, the first control pin, and the second control pin are part of the SoC and are used to couple to the PMIC.

[0108] Example 47 includes a product that includes one or more tangible computer-readable non-transitory storage media that include computer-executable instructions that, when executed by at least one processing circuit, cause the at least one processing circuit to perform operations on a computing device, the operations including: processing a first control signal and a second control signal from respective first and second control pins of a computing platform; and transitioning the computing platform between a low power state and a retention power state based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform without transitioning to an operating power state therebetween.

[0109] Example 48 includes the subject matter of Example 47, and optionally, wherein: a logic state where both the first control pin and the second control pin are off is used to indicate an operating power state, and a logic state where both the first control pin and the second control pin are on is used to indicate a retention power state; and the same logic state between the first control pin and the second control pin is used to indicate one of the operating power state or the retention power state, and wherein a different logic state between the first control pin and the second control pin is used to indicate the retention power state.

[0110] Example 49 includes the subject matter of Example 48, and optionally, wherein: a logic state where both the first control pin and the second control pin are off is used to indicate an operating power state, and a logic state where both the first control pin and the second control pin are on is used to indicate a retention power state; and an on logic state of the first control pin and an off logic state of the second control pin are used to indicate a low power state.

[0111] Example 50 includes the subject matter of Example 47, and optionally, wherein the operation further includes transitioning the computing platform between an operating power state, a low power state, and a retention power state by controlling the power supply to at least one voltage pin of the computing platform.

[0112] Example 51 includes the subject matter of Example 47, and optionally, wherein the at least one voltage pin includes a VNNAON pin, and the processing circuit is coupled to the VNNAON pin.

[0113] Example 52 includes the subject matter of Example 47, and optionally, wherein the computing device includes a power management integrated circuit (PMIC), and the computing platform includes a system on a chip (SoC).

[0114] Example 53 includes the subject matter of Example 48, and optionally, wherein the at least one voltage pin, the first control pin, and the second control pin are part of the SoC and are used to couple to the PMIC.

[0115] Example 54 includes a computing device that includes: means for processing a first control signal and a second control signal from respective first and second control pins of a computing platform; and a module for transitioning the computing platform between a low power state and a retention power state based on a combination of the first control signal and the second control signal and using at least one voltage pin on the platform without transitioning to an operating power state therebetween.

[0116] Example 55 includes the subject matter of Example 54, and optionally, wherein: a logic state in which both the first control pin and the second control pin are off is used to indicate an operating power state, and a logic state in which both the first control pin and the second control pin are on is used to indicate a hold power state; and an on logic state of the first control pin and an off logic state of the second control pin are used to indicate a low power state.

[0117] Example 56 includes the subject matter of Example 55, and optionally, wherein: a logic state in which both the first control pin and the second control pin are off is used to indicate an operating power state, and a logic state in which both the first control pin and the second control pin are on is used to indicate a hold power state; and an on logic state of the first control pin and an off logic state of the second control pin are used to indicate a low power state.

[0118] Example 57 includes the subject matter of Example 54, and optionally, further includes a module for causing the computing platform to transition between an operating power state, a low power state, and a hold power state by controlling the power supply to at least one voltage pin of the computing platform.

[0119] Although certain features have been shown and described herein, many modifications, substitutions, changes, and equivalents will occur to those skilled in the art. Accordingly, it is to be understood that the appended claims are intended to cover all such modifications and changes that fall within the true spirit of the present disclosure.

Claims

1. A computing platform, comprising: A plurality of circuit blocks; At least one voltage pin, coupled to the plurality of circuit blocks and controlled by a power management integrated circuit (PMIC) to cause at least a portion of the platform to transition between an operating power state, a low power state, and a retention power state; And A first control pin and a second control pin configured to send respective control signals to the PMIC, the PMIC controlling the at least one voltage pin based on a combination of the control signals to cause at least a portion of the platform to transition between the low power state and the retention power state without transitioning to the operating power state therebetween; wherein each respective control signal is used to indicate an on logic state or an off logic state for a respective one of the first control pin and the second control pin.

2. The computing platform according to claim 1, wherein: The same logic state between the first control pin and the second control pin is used to indicate one of the operating power state or the retention power state, and wherein a different logic state between the first control pin and the second control pin is used to indicate the retention power state.

3. The computing platform according to claim 2, wherein: The logic state where both the first control pin and the second control pin are off is used to indicate the operating power state, the logic state where both the first control pin and the second control pin are on is used to indicate the retention power state; and The on logic state of the first control pin and the off logic state of the second control pin indicate the low power state.

4. The computing platform according to claim 3, wherein, The on logic state of the first control pin serves as an envelope for the on logic state of the second control pin.

5. The computing platform according to claim 1, wherein, The first control pin is a STANDBY pin, and the second control pin is a vSTANDBY pin.

6. The computing platform according to claim 1, further comprising a power management circuit (PMC) coupled to the second control pin, the PMC being configured to send a PMC control signal to the second control pin to request the second control pin to change its logic state.

7. The computing platform according to claim 1, wherein, The voltage pin includes a VNNAON pin configured to be coupled to a voltage rail of the PMIC.

8. The computing platform according to claim 1, wherein, The computing platform is a system-on-chip.

9. The computing platform according to any one of claims 1 to 8 further includes the PMIC, wherein, The at least one voltage pin, the first control pin, and the second control pin are coupled to the PMIC.

10. The computing platform according to claim 9, further comprising a wireless connection circuit.

11. A method performed on a computing platform including a plurality of circuit blocks, the method comprising: Sending respective control signals from a first control pin and a second control pin of the computing platform to a power management integrated circuit (PMIC); And Based on a combination of control signals, causing the platform to transition between a low-power state and a hold power state without entering a working power state therebetween, including causing at least a portion of the platform to transition using at least one voltage pin coupled to the plurality of circuit blocks and controlled by the PMIC; wherein each respective control signal is used to indicate an on logic state or an off logic state for a respective one of the first control pin and the second control pin.

12. The method according to claim 11, wherein: The same logic state between the first control pin and the second control pin is used to indicate one of the working power state or the hold power state, and wherein a different logic state between the first control pin and the second control pin is used to indicate the hold power state.

13. The method according to claim 12, wherein, The logic state where both the first control pin and the second control pin are off is used to indicate the working power state, and the logic state where both the first control pin and the second control pin are on is used to indicate the hold power state.

14. The method according to claim 13, wherein, The on logic state of the first control pin and the off logic state of the second control pin are used to indicate the low-power state.

15. The method according to claim 14, wherein, The on logic state of the first control pin serves as an envelope for the on logic state of the second control pin.

16. The method according to claim 11, wherein, The first control pin is a STANDBY pin, and the second control pin is a vSTANDBY pin.

17. The method according to claim 11, further comprising sending a power management circuit control signal to the second control pin to request that the second control pin change its logic state.

18. A computing platform, comprising a plurality of circuit blocks, and further comprising: A module for sending respective control signals from a first control pin and a second control pin of the computing platform to a power management integrated circuit PMIC; And A module for causing the platform to transition between a low-power state and a hold power state based on a combination of control signals without entering a working power state therebetween, including causing at least a portion of the platform to transition using at least one voltage pin coupled to the plurality of circuit blocks and controlled by the PMIC; wherein each respective control signal is used to indicate an on logic state or an off logic state for a respective one of the first control pin and the second control pin.

19. The computing platform according to claim 18, wherein: The same logic state between the first control pin and the second control pin is used to indicate one of the working power state or the hold power state, and wherein a different logic state between the first control pin and the second control pin is used to indicate the hold power state.

20. The computing platform according to claim 19, wherein, The logic state where both the first control pin and the second control pin are off is used to indicate the working power state, and the logic state where both the first control pin and the second control pin are on is used to indicate the hold power state.

21. The computing platform according to claim 20, wherein, The on logic state of the first control pin and the off logic state of the second control pin are used to indicate the low-power state.

22. The computing platform according to claim 21, wherein, The on-logic state of the first control pin serves as an envelope for the on-logic state of the second control pin.

23. The computing platform according to claim 18, wherein, The first control pin is the STDBY pin, and the second control pin is the vSTDBY pin.

24. The computing platform according to claim 18, further comprising: A module for sending a power management circuit control signal to the second control pin to request the second control pin to change its logic state.

25. A machine-readable medium including code that, when executed, will cause a machine to perform the method according to any one of claims 11 to 17.

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