Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided, wherein reliability and yield are improved by reducing or preventing the expansion of cracks that may occur in a chip sawing process. The semiconductor device comprises: a substrate comprising a first chip region and a scribe line region surrounding the first chip region; a first low-k insulating film on the substrate in the first chip region comprising a first insulating material having a dielectric constant less than that of silicon oxide; a wiring structure on the substrate in the scribe line region comprising a second low-k insulating film and a wiring pattern in the second low-k insulating film, the second low-k insulating film comprising the first insulating material; and a first protective insulating film between the first low-k insulating film and the wiring structure comprising a second insulating material different from the first insulating material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0124978, filed on October 19, 2018, the disclosure of which is hereby incorporated by reference in its entirety into this application. Technical Field

[0003] The present inventive concept relates to a semiconductor device and a method for manufacturing the same. More particularly, the present inventive concept relates to a semiconductor device including a protective insulating film in a scribe street region and a method for manufacturing the same. Background Art

[0004] The semiconductor chips may be formed by a dicing sawing process for cutting a semiconductor wafer having integrated circuit elements formed thereon. During the dicing sawing process, a saw blade may cut the semiconductor wafer along a scribe line region, thereby physically separating a plurality of semiconductor chips.

[0005] As integrated circuit elements are required to have greater capacity and higher integration, the area occupied by the scribe line region in the semiconductor wafer may be reduced. Therefore, for example, the risk of damaging the integrated circuit elements due to stress applied to the semiconductor chip during the dice sawing process may increase. Summary of the invention

[0006] Aspects of the inventive concept provide a semiconductor device in which reliability and / or productivity / yield can be improved by reducing or preventing the propagation of cracks that may occur in a die sawing process.

[0007] Aspects of the inventive concept also provide a method of manufacturing a semiconductor device, wherein reliability and / or productivity / yield of the semiconductor device may be improved by reducing or preventing the propagation of cracks that may occur during a die sawing process.

[0008] The technical problems solved by the inventive concept are not limited to the above-mentioned technical problems, and those skilled in the art can clearly understand from the following description other technical problems that can be solved by the inventive concept but are not specifically mentioned.

[0009] According to various aspects of the present invention, a semiconductor device is provided, comprising: a substrate, the substrate comprising a first chip region and a scribe line region surrounding the first chip region; a first low-k insulating film on the substrate in the first chip region, the first low-k insulating film comprising a first insulating material having a dielectric constant less than that of silicon oxide; a wiring structure on the substrate in the scribe line region, the wiring structure comprising a second low-k insulating film and a wiring pattern in the second low-k insulating film, the second low-k insulating film comprising the first insulating material; and a first protective insulating film between the first low-k insulating film and the wiring structure, the first protective insulating film comprising a second insulating material different from the first insulating material.

[0010] According to various aspects of the present invention, a semiconductor device is provided, comprising: a substrate, the substrate comprising a first chip region, a second chip region and a scribe line region located between the first chip region and the second chip region; a first low-k insulating film located on the substrate in the first chip region, the first low-k insulating film comprising a first insulating material having a dielectric constant less than that of silicon oxide; a second low-k insulating film located on the substrate in the second chip region, the second low-k insulating film comprising the first insulating material; a third low-k insulating film located on the substrate in the scribe line region, the third low-k insulating film comprising the first insulating material; a first protective insulating film located between the first low-k insulating film and the third low-k insulating film, the first protective insulating film comprising a second insulating material different from the first insulating material; and a second protective insulating film located between the second low-k insulating film and the third low-k insulating film, the second protective insulating film comprising the second insulating material.

[0011] According to various aspects of the present invention, there is provided a semiconductor device comprising: a substrate comprising a chip region and a scribe line region surrounding the chip region, the scribe line region comprising a project region and a protection region between the chip region and the project region; a first interlayer insulating film on the substrate, the first interlayer insulating film comprising silicon oxide; a low-k insulating film on the first interlayer insulating film, the low-k insulating film defining a groove in the protection region and comprising a low-k material having a dielectric constant less than that of silicon oxide; a wiring pattern formed in the low-k insulating film in the project region; and a protection insulating film filling the groove and comprising silicon oxide.

[0012] According to various aspects of the present invention, a method for manufacturing a semiconductor device is provided, the method comprising: providing a substrate, the substrate comprising a chip area and a scribe line area surrounding the chip area, the scribe line area comprising a project area and a protection area located between the chip area and the project area; forming a first interlayer insulating film and a low-k insulating film on the substrate, the low-k insulating film being located on the first interlayer insulating film and comprising a first insulating material having a dielectric constant lower than that of silicon oxide; forming a groove in the low-k insulating film in the protection area, the groove exposing a top surface of the first interlayer insulating film; and forming a protective insulating film in the groove, the protective insulating film comprising a second insulating material different from the first insulating material. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The above and other aspects and features of the present inventive concept will become more apparent by describing in detail exemplary embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0014] Figure 1 is a schematic top view of a semiconductor device according to some embodiments of the inventive concept.

[0015] Figure 2 It is shown Figure 1 Schematic layout diagram of area S1 in FIG.

[0016] Figure 3 It is shown Figure 1 Schematic layout diagram of area S2 in FIG.

[0017] Figure 4 It is along Figure 3 A cross-sectional view taken along line AA in FIG.

[0018] Figure 5 is a view illustrating a protective insulating film of a semiconductor device according to some embodiments of the inventive concept.

[0019] Figure 6 is a schematic layout diagram of a semiconductor device according to some embodiments of the inventive concept.

[0020] Figures 7 to 9 is along Figure 6 Various cross-sectional views taken along line BB in FIG.

[0021] Fig.10 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0022] Fig.11 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0023] Fig.12 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the inventive concept.

[0024] Fig.13 is a schematic layout diagram of a semiconductor device according to some embodiments of the inventive concept.

[0025] Fig.14 It is along Fig.13 Cross-sectional view taken along line CC in FIG.

[0026] Fig.15 It is along Fig.13 A cross-sectional view taken along line DD in FIG.

[0027] Fig.16 is a schematic layout diagram of a semiconductor device according to some embodiments of the inventive concept.

[0028] Fig.17 It is along Fig.16 A cross-sectional view taken along line EE in FIG.

[0029] Fig.18 is a schematic layout diagram of a semiconductor device according to some embodiments of the inventive concept.

[0030] Fig.19 It is along Fig.18 A cross-sectional view taken along line FF in FIG.

[0031] Fig. 20 is a schematic layout diagram of a semiconductor device according to some embodiments of the inventive concept.

[0032] Fig.21 It is along Fig. 20 A cross-sectional view taken along line GG in FIG.

[0033] Fig. 22 is a schematic top view of a semiconductor chip according to some embodiments of the inventive concept.

[0034] Fig.23 It is along Fig. 22 A cross-sectional view taken along line HH in FIG.

[0035] Fig.24 is a schematic cross-sectional view of a semiconductor package according to some embodiments of the inventive concept.

[0036] Figure 25 to Figure 27 are diagrams illustrating intermediate steps of a method of fabricating a semiconductor device according to some embodiments of the inventive concept.

[0037] Figure 28 to Figure 31 are diagrams illustrating intermediate steps of a method of fabricating a semiconductor device according to some embodiments of the inventive concept. DETAILED DESCRIPTION

[0038] In the following, reference will be made to Figures 1 to 21 Semiconductor devices according to some embodiments of the inventive concept are described.

[0039] Figure 1 is a schematic top view of a semiconductor device according to some embodiments of the inventive concept. Figure 2 It is shown Figure 1 Schematic layout diagram of area S1 in FIG. Figure 3 It is shown Figure 1 Schematic layout diagram of area S2 in FIG. Figure 4 It is along Figure 3 A cross-sectional view taken along line AA in FIG.

[0040] Reference Figures 1 to 4 , a semiconductor device according to some embodiments includes a substrate 100 , a first interlayer insulating film 200 , a first wiring structure 310 , a second wiring structure 320 , a third wiring structure 330 , a second interlayer insulating film 400 , a first protective insulating film 340 , and a second protective insulating film 350 .

[0041] Although terms such as first and second are used to describe various elements or components, these elements and components are not limited by these terms. These terms are used to distinguish a single element or component from other elements or components. Therefore, within the scope of the present invention, the first element or component to be described below may be a second element or component.

[0042] The substrate 100 may be bulk silicon or silicon on insulator (SOI). Alternatively, the substrate 100 may be a silicon substrate, or may include, but is not limited to, other materials such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. The substrate 100 may refer to, for example, a semiconductor wafer 10.

[0043] The substrate 100 may include a plurality of chip regions MC and scribe street regions SL.

[0044] A semiconductor chip may be formed in each chip region MC. For example, a semiconductor element such as a storage element or a logic element may be formed in each chip region MC. In addition, the semiconductor element may include various individual elements. For example, the individual elements may include a metal oxide semiconductor field effect transistor (MOSFET) such as a complementary metal oxide semiconductor (CMOS) transistor, an image sensor such as a system LSI (large scale integrated circuit) and a CIS (CMOS image sensor), a MEMS (micro-electromechanical system), various other active elements, and passive elements.

[0045] The scribe lane region SL may surround each chip region MC. As used herein, an element or region described as surrounding another element or region may completely surround the other element or region, partially surround the other element or region, or extend along the periphery of the other element or region. For example, the scribe lane region SL may be in the form or shape of a linear lane having a substantially constant width. Multiple chip regions MC may be separated or segmented from one another by a small piece sawing process performed along the scribe lane region SL.

[0046] Each chip region MC may be separated from each other by a scribe line region SL. Figure 3 As shown, the plurality of chip regions MC may include a first chip region MC1 and a second chip region MC2 separated from each other by a scribe line region SL. For example, the first chip region MC1 and the second chip region MC2 may be arranged along a first direction X, and the scribe line region SL may extend along a second direction Y intersecting the first direction X between the first chip region MC1 and the second chip region MC2.

[0047] The scribe street region SL may include a project region CR and a protection region PR.

[0048] Various project patterns of the semiconductor device according to some embodiments may be formed in the project region CR. For example, project patterns such as a TEG (Test Element Group) module, an alignment key, and a MI (Metrology and Inspection) may be formed in the project region CR, but are not limited thereto.

[0049] The protection region PR may be interposed between the project region CR and each chip region MC. In some embodiments, the protection region PR may surround each chip region MC, and the project region CR may surround the protection region PR.

[0050] For example, Figure 3 As shown, the protection region PR may include a first protection region PR1 between the project region CR and the first chip region MC1 , and a second protection region PR2 between the project region CR and the second chip region MC2 .

[0051] The first interlayer insulating film 200 may be formed on the substrate 100. Figure 4 In the figure, although the first interlayer insulating film 200 is shown as a single layer, this is only for convenience of explanation and the present disclosure is not limited thereto. For example, the first interlayer insulating film 200 may be formed by stacking a plurality of insulating films.

[0052] In some embodiments, the first integrated circuit element TR1 and the second integrated circuit element TR2 may be disposed on the substrate 100. The first interlayer insulating film 200 may cover the first integrated circuit element TR1 and the second integrated circuit element TR2. The first integrated circuit element TR1 and the second integrated circuit element TR2 may include, for example, transistors. For example, a gate electrode structure may be formed on one side of the substrate 100, and impurities may be doped into the substrate 100 at both sides of the gate electrode structure to form the first integrated circuit element TR1 and the second integrated circuit element TR2.

[0053] The first wiring structure 310, the second wiring structure 320, and the third wiring structure 330 may be formed on the first interlayer insulating film 200. Specifically, the first wiring structure 310 may be formed on the first interlayer insulating film 200 of the first chip region MC1, the second wiring structure 320 may be formed on the first interlayer insulating film 200 of the second chip region MC2, and the third wiring structure 330 may be formed on the first interlayer insulating film 200 of the project region CR.

[0054] The first wiring structure 310, the second wiring structure 320, and the third wiring structure 330 may respectively include low-k insulating films 312, 322, and 332 and wiring patterns 314, 324, and 334. For example, the first wiring structure 310 may include a first low-k insulating film 312 and a first wiring pattern 314, the second wiring structure 320 may include a second low-k insulating film 322 and a second wiring pattern 324, and the third wiring structure 330 may include a third low-k insulating film 332 and a third wiring pattern 334.

[0055] The first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332 may include a first insulating material. In some embodiments, the first insulating material may be a low-k material having a lower dielectric constant than silicon oxide. For example, the first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332 may include, but are not limited to, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof.

[0056] Each of the first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332 is shown as a single layer, but this is only for convenience of explanation, and the present disclosure is not limited thereto. For example, each of the first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332 may be formed by stacking a plurality of insulating films.

[0057] The first wiring pattern 314 , the second wiring pattern 324 , and the third wiring pattern 334 may be formed in the first low-k insulating film 312 , the second low-k insulating film 322 , and the third low-k insulating film 332 , respectively.

[0058] In some embodiments, the first wiring pattern 314 and the second wiring pattern 324 may be electrically connected to the first integrated circuit element TR1 and the second integrated circuit element TR2 on the substrate 100, respectively. For example, a first lower via 210 penetrating the first interlayer insulating film 200 to connect the first integrated circuit element TR1 and the first wiring pattern 314 may be formed. In addition, for example, a second lower via 220 penetrating the first interlayer insulating film 200 to connect the second integrated circuit element TR2 and the second wiring pattern 324 may be formed.

[0059] In some embodiments, the first lower via 210 and the second lower via 220 may be formed at the same level.

[0060] The third wiring pattern 334 may include various item patterns in the item region CR For example, the third wiring pattern 334 may include item patterns such as a TEG module, an alignment key, and a MI.

[0061] The first wiring pattern 314, the second wiring pattern 324, and the third wiring pattern 334 may include a conductive material. For example, the first wiring pattern 314, the second wiring pattern 324, and the third wiring pattern 334 may include, but are not limited to: metals such as tungsten, nickel, cobalt, and tantalum; metal silicides such as tungsten silicide, nickel silicide, cobalt silicide, and tantalum silicide; polysilicon doped with impurities; or combinations thereof.

[0062] In some embodiments, the first wiring structure 310, the second wiring structure 320, and the third wiring structure 330 may be formed at the same level. In this specification, "the same level" means that these wiring structures are formed by the same manufacturing operation or process. For example, the first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332 may have substantially the same material composition, and the first wiring pattern 314, the second wiring pattern 324, and the third wiring pattern 334 may have substantially the same material composition.

[0063] In some embodiments, the heights of the respective bottom surfaces of the first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332 may be substantially the same relative to the substrate 100. For example, a height H11 of the bottom surface of the first low-k insulating film 312 may be substantially the same as a height H12 of the bottom surface of the third low-k insulating film 332 based on the top surface of the substrate 100.

[0064] The second interlayer insulating film 400 may be formed on the first wiring structure 310, the second wiring structure 320, and the third wiring structure 330. Figure 4 4. Although shown as a single layer in FIG. 4, this is only for convenience of explanation, and the present disclosure is not limited thereto. For example, the second interlayer insulating film 400 may be formed by stacking a plurality of insulating films.

[0065] In some embodiments, the first conductive film 414, the second conductive film 424, and the third conductive film 434 may be formed in the second interlayer insulating film 400. The first conductive film 414 may be formed in the second interlayer insulating film 400 of the first chip region MC1, the second conductive film 424 may be formed in the second interlayer insulating film 400 of the second chip region MC2, and the third conductive film 434 may be formed in the second interlayer insulating film 400 of the project region CR.

[0066] In some embodiments, the first wiring pattern 314, the second wiring pattern 324, and the third wiring pattern 334 may be electrically connected to the first conductive film 414, the second conductive film 424, and the third conductive film 434, respectively. For example, a first upper via 412 penetrating the second interlayer insulating film 400 to connect the first wiring pattern 314 and the first conductive film 414 may be formed. In addition, for example, a second upper via 422 penetrating the second interlayer insulating film 400 to connect the second wiring pattern 324 and the second conductive film 424 may be formed. In addition, for example, a third upper via 432 penetrating the second interlayer insulating film 400 to connect the third wiring pattern 334 and the third conductive film 434 may be formed.

[0067] In some embodiments, the first conductive film 414, the second conductive film 424, and the third conductive film 434 may be formed at the same level. In addition, in some embodiments, the first upper via 412, the second upper via 422, and the third upper via 432 may be formed at the same level.

[0068] The first interlayer insulating film 200 and the second interlayer insulating film 400 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, FOX (flowable oxide), TOSZ (Toho Silazane), USG (undoped silicate glass), BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), TEOS (tetraethyl orthosilicate), PETEOS (plasma enhanced tetraethyl orthosilicate), FSG (fluorosilicate glass), CDO (carbon-doped silicon oxide), dry gel, aerogel, amorphous fluorinated carbon, OSG (organosilicate glass), polyparaxylene, BCB (bisbenzocyclobutene), SiLK, polyimide, porous polymer materials or combinations thereof.

[0069] The first protective insulating film 340 may be interposed between the first low-k insulating film 312 and the third low-k insulating film 332. For example, a first trench T1 may be formed in the second interlayer insulating film 400 and the low-k insulating film in the first protective region PR1. In some embodiments, the bottom surface of the first trench T1 may expose a portion of the top surface of the first interlayer insulating film 200. The first protective insulating film 340 may fill the first trench T1. Therefore, the first protective insulating film 340 may be formed on the first interlayer insulating film 200 in the first protective region PR1. In some embodiments, the first protective insulating film 340 may surround the first chip region MC1.

[0070] The second protection insulating film 350 may be interposed between the second low-k insulating film 322 and the third low-k insulating film 332. For example, a second trench T2 may be formed in the second interlayer insulating film 400 and the low-k insulating film in the second protection region PR2. In some embodiments, the bottom surface of the second trench T2 may expose a portion of the top surface of the first interlayer insulating film 200. The second protection insulating film 350 may fill the second trench T2. Therefore, the second protection insulating film 350 may be formed on the first interlayer insulating film 200 in the second protection region PR2. In some embodiments, the second protection insulating film 350 may surround the second chip region MC2.

[0071] The first protective insulating film 340 and the second protective insulating film 350 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, FOX (flowable oxide), TOSZ (Toho Silazane), USG (undoped silicate glass), BSG (borosilicate glass), PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), TEOS (tetraethyl orthosilicate), PETEOS (plasma enhanced tetraethyl orthosilicate), FSG (fluorosilicate glass), CDO (carbon-doped silicon oxide), dry gel, aerogel, amorphous fluorinated carbon, OSG (organosilicate glass), polyparaxylene, BCB (bisbenzocyclobutene), SiLK, polyimide, porous polymer materials or combinations thereof.

[0072] In some embodiments, the first protection insulating film 340 and the second protection insulating film 350 may include a second insulating material different from the first insulating material of the low-k insulating films 312, 322, 332. In some embodiments, the second insulating material may include silicon oxide having a higher dielectric constant than the first insulating material. For example, the first protection insulating film 340 and the second protection insulating film 350 may include TEOS (tetraethyl orthosilicate).

[0073] In some embodiments, the first protective insulating film 340 and the second protective insulating film 350 may include the same material as the first interlayer insulating film 200 and / or the second interlayer insulating film 400. For example, the first protective insulating film 340, the second protective insulating film 350, the first interlayer insulating film 200, and the second interlayer insulating film 400 may include the same silicon oxide. For example, each of the first protective insulating film 340, the second protective insulating film 350, the first interlayer insulating film 200, and the second interlayer insulating film 400 may include TEOS (tetraethyl orthosilicate).

[0074] Figure 4 The boundary between the first protective insulating film 340 and the first interlayer insulating film 200, and the boundary between the first protective insulating film 340 and the second interlayer insulating film 400 are shown, but this is only for the convenience of explanation, and the present disclosure is not limited thereto. For example, when the first protective insulating film 340, the first interlayer insulating film 200, and the second interlayer insulating film 400 have the same material configuration, the boundary between the first protective insulating film 340 and the first interlayer insulating film 200 and / or the boundary between the first protective insulating film 340 and the second interlayer insulating film 400 may not exist or be invisible. Similarly, the boundary between the second protective insulating film 350 and the first interlayer insulating film 200 and / or the boundary between the second protective insulating film 350 and the second interlayer insulating film 400 may not exist or be invisible.

[0075] In some embodiments, the height of each bottom surface of the first protection insulating film 340 and the second protection insulating film 350 may be lower than the height of each bottom surface of the first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332 relative to the substrate 100. For example, the height H13 of the bottom surface of the first protection insulating film 340 may be lower than the height H11 of the bottom surface of the first low-k insulating film 312 and the height H12 of the bottom surface of the third low-k insulating film 332 based on the top surface of the substrate 100.

[0076] In some embodiments, a capping insulating film 410 may be further formed on the second interlayer insulating film 400. Figure 4 , the capping insulating film 410 is shown as being on or covering the respective top surfaces of the first protective insulating film 340 and the second protective insulating film 350, but the present disclosure is not limited thereto. For example, the first protective insulating film 340 and the second protective insulating film 350 may be formed to penetrate or pass through the capping insulating film 410.

[0077] The capping insulating film 410 may include, but is not limited to, silicon nitride and / or silicon oxynitride, for example.

[0078] Figure 5is a view illustrating a protective insulating film of a semiconductor device according to some embodiments of the inventive concept.

[0079] Reference Figures 1 to 5 , the first chip region MC1 and the second chip region MC2 may be separated from each other by a small piece sawing process performed along the scribe line region SL. For example, the saw blade 20 may be placed in the scribe line region SL and the second interlayer insulating film 400, and the first interlayer insulating film 200 and the substrate 100 may be cut sequentially by the saw blade 20.

[0080] Although Figure 5 It is shown that the small piece sawing process is performed by the saw blade 20, but this is only an example and the present disclosure is not limited thereto. For example, the small piece sawing process described above may be performed by other processes such as a laser sawing process. For example, a laser may be provided in the scribe line region SL to sequentially cut the second interlayer insulating film 400, the first interlayer insulating film 200, and the substrate 100.

[0081] Meanwhile, when the saw blade 20 performs a small piece sawing process along the scribe line region SL, the saw blade 20 may cause stress, such as physical friction, to the low-k insulating films 312 and 322 that are susceptible to stress damage. Such stress may cause cracks 30 to develop inside the semiconductor device, which results in a decrease in reliability and / or productivity / yield of the semiconductor chips in the chip region MC.

[0082] However, in the semiconductor device according to some embodiments, by forming the protection region PR (in which the protection insulating film, for example, the first protection insulating film 340 and the second protection insulating film 350 are formed) in the scribe line region SL adjacent to the chip region MC, the cracks 30 generated by the saw blade 20 or other separation processes can be effectively reduced or prevented from developing. Therefore, a semiconductor device with improved reliability and / or productivity / yield can be provided.

[0083] Furthermore, in the semiconductor device according to some embodiments, by forming the protection region PR between the project region CR and the chip region MC, various project patterns of the semiconductor device may coexist with wiring patterns in the chip region MC.

[0084] In addition, in the semiconductor device according to some embodiments, when a protective insulating film (e.g., a first protective insulating film 340 and a second protective insulating film 350) including the same material as the interlayer insulating film (e.g., a first interlayer insulating film 200 and a second interlayer insulating film 400) is formed in the protection region PR, the steps (e.g., manufacturing steps) and / or structural deformation of the semiconductor device can be reduced or minimized.

[0085] Figure 6is a schematic layout diagram of a semiconductor device according to some embodiments of the inventive concept. Figures 7 to 9 is along Figure 6 For ease of explanation, the various cross-sectional views taken along line BB in FIG. Figures 1 to 5 The repeated portion of the provided description.

[0086] Reference Figure 6 and Figure 7 , in the semiconductor device according to some embodiments, the substrate 100 further includes a first peripheral region DR1 and a second peripheral region DR2.

[0087] The first peripheral region DR1 may be between the first chip region MC1 and the first protection region PR1, and the second peripheral region DR2 may be between the second chip region MC2 and the second protection region PR2. In some embodiments, the first peripheral region DR1 may surround the first chip region MC1, and the second peripheral region DR2 may surround the second chip region MC2.

[0088] In some embodiments, the wiring structure may be formed in the first peripheral region DR1 or the second peripheral region DR2. For example, the first peripheral wiring structure 510 may be formed in the first peripheral region DR1, and the second peripheral wiring structure 520 may be formed in the second peripheral region DR2.

[0089] exist Figure 7 , the first peripheral region DR1 and the second peripheral region DR2 are illustrated as including the wiring structure, but the present disclosure is not limited thereto. For example, one of the first peripheral region DR1 and the second peripheral region DR2 may not include the wiring structure.

[0090] In addition, although the first peripheral wiring structure 510 is shown as being formed by the first lower via 210, the first wiring pattern 314, the first upper via 412 and the first conductive film 414, the present disclosure is not limited thereto. Similarly, although the second peripheral wiring structure 520 is shown as being formed by the second lower via 220, the second wiring pattern 324, the second upper via 422 and the second conductive film 424, the present disclosure is not limited thereto.

[0091] In some embodiments, the first peripheral wiring structure 510 may include a first barrier structure 512, a first guard ring structure 514, and a first crack detection circuit (CDC) structure 516 sequentially arranged in a direction from the scribe line region SL to the first chip region MC1. Similarly, the second peripheral wiring structure 520 may include a second barrier structure 522, a second guard ring structure 524, and a second crack detection circuit structure 526 sequentially arranged in a direction from the scribe line region SL to the second chip region MC2.

[0092] The first blocking structure 512 and the second blocking structure 522 can prevent cracks caused by the saw blade 20 (eg, Figure 5 30) develops to the chip region MC. The first guard ring structure 514 and the second guard ring structure 524 may surround the chip region MC in a ring or ring shape. The first crack detection circuit structure 516 and the second crack detection circuit structure 526 may include a circuit for detecting cracks caused by the saw blade 20 (e.g., Figure 5 30) circuit in FIG.

[0093] Reference Figure 6 and Figure 8 In the semiconductor device according to some embodiments, the first protective insulating film 340 and the second protective insulating film 350 may extend to contact the top surface of the substrate 100 .

[0094] For example, respective bottom surfaces of the first trench T1 and the second trench T2 may expose the top surface of the substrate 100. Thus, respective bottom surfaces of the first protective insulating film 340 and the second protective insulating film 350 may contact the top surface of the substrate 100.

[0095] Reference Figure 6 and Fig. 9 In the semiconductor device according to some embodiments, relative to the substrate 100, the heights of the respective bottom surfaces of the first protective insulating film 340 and the second protective insulating film 350 are substantially the same as the heights of the respective bottom surfaces of the first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332.

[0096] For example, a height H14 of the bottom surface of the first protective insulating film 340 may be substantially the same as a height H11 of the bottom surface of the first low-k insulating film 312 and a height H12 of the bottom surface of the third low-k insulating film 332 based on the top surface of the substrate 100 .

[0097] Fig.10 1 is a cross-sectional view showing a semiconductor device according to some embodiments of the present invention. Figures 1 to 5 The repeated portion of the provided description.

[0098] Reference Figure 3 and Fig.10 In the semiconductor device according to some embodiments, relative to the substrate 100, the heights of the respective top surfaces of the first protective insulating film 340 and the second protective insulating film 350 are substantially the same as the heights of the respective top surfaces of the first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332.

[0099] For example, a height H23 of the top surface of the first protective insulating film 340 may be substantially the same as a height H21 of the top surface of the first low-k insulating film 312 and a height H22 of the top surface of the third low-k insulating film 332 based on the top surface of the substrate 100 .

[0100] Fig.10 1 and 10. The height of the bottom surfaces of the first protective insulating film 340 and the second protective insulating film 350 is lower than the height of the bottom surfaces of the first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332 relative to the substrate 100, but the present disclosure is not limited thereto. Figure 8 and Fig. 9 As described above, the heights of the respective bottom surfaces of the first protective insulating film 340 and the second protective insulating film 350 may be various.

[0101] Fig.11 1 is a cross-sectional view showing a semiconductor device according to some embodiments of the present invention. Figures 1 to 5 The repeated portion of the provided description.

[0102] Reference Fig.11 In the semiconductor device according to some embodiments, the first low-k insulating film 312 and the third low-k insulating film 332 are spaced apart from each other by a distance different from the distance at which the second low-k insulating film 322 and the third low-k insulating film 332 are spaced apart from each other.

[0103] For example, the width W11 of the first protective insulating film 340 may be different from the width W12 of the second protective insulating film 350. Here, the width refers to the width in the direction (eg, first direction X) in which the first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332 are arranged.

[0104] Fig.12 1 is a cross-sectional view showing a semiconductor device according to some embodiments of the present invention. Figures 1 to 11 The repeated portion of the provided description.

[0105] Reference Fig.12 , the semiconductor device according to some embodiments may further include a conductive pad 620 .

[0106] The conductive pad 620 may be formed on the second interlayer insulating film 400. In some embodiments, the conductive pad 620 may be formed on the capping insulating film 410.

[0107] In some embodiments, the conductive pad 620 may be electrically connected to the third wiring pattern 334. For example, a fourth upper via 610 penetrating the second interlayer insulating film 400 and the capping insulating film 410 to connect the third conductive film 434 and the conductive pad 620 may be formed.

[0108] In some embodiments, a passivation film 630 exposing the top surface of the conductive pad 620 may also be formed. The passivation film 630 may extend along the top surface of the capping insulating film 410. In addition, the passivation film 630 may expose at least a portion of the top surface of the conductive pad 620. For example, the passivation film 630 may include an opening 632 exposing a portion of the top surface of the conductive pad 620. The passivation film 630 may include, for example, silicon nitride.

[0109] Although the conductive pad 620 is shown as being formed only in the project region CR, the present disclosure is not limited thereto. For example, the conductive pad 620 may be formed in the first chip region MC1 and / or the second chip region MC2.

[0110] Fig.13 is a schematic layout diagram of a semiconductor device according to some embodiments of the inventive concept. Fig.14 It is along Fig.13 Cross-sectional view taken along line CC in FIG. Fig.15 It is along Fig.13 For the convenience of explanation, the reference will be briefly explained or omitted. Figures 1 to 12 The repeated portion of the provided description.

[0111] Reference Figures 13 to 15 , in the semiconductor device according to some embodiments, the third wiring structure 330 includes a plurality of item patterns spaced apart from each other.

[0112] For example, the third wiring structure 330 may include a first item pattern 330a and a second item pattern 330b that are electrically separated from each other. Each of the first item pattern 330a and the second item pattern 330b may include a third low-k insulating film 332 and a third wiring pattern 334. Therefore, each of the first item pattern 330a and the second item pattern 330b may include various item patterns in the item region CR. For example, each of the first item pattern 330a and the second item pattern 330b may include item patterns such as a TEG module, an alignment key, and a MI.

[0113] The first item pattern 330a and the second item pattern 330b are shown to be arranged along the second direction Y, but the present disclosure is not limited thereto. For example, the first item pattern 330a and the second item pattern 330b may be arranged along various directions such as the first direction X.

[0114] exist Fig.13 and Fig.15 , it is shown that the third low-k insulating film 332 is interposed between the first item pattern 330a and the second item pattern 330b. For example, the third low-k insulating film 332 without forming the third wiring pattern 334 is formed between the first item pattern 330a and the second item pattern 330b, and the first item pattern 330a and the second item pattern 330b can be electrically separated. However, the present disclosure is not limited thereto, and there may be no third low-k insulating film 332 interposed between the first item pattern 330a and the second item pattern 330b. For example, the first item pattern 330a and the second item pattern 330b may be separated from each other by the first interlayer insulating film 200 and / or the second interlayer insulating film 400.

[0115] Fig.16 is a schematic layout diagram of a semiconductor device according to some embodiments of the inventive concept. Fig.17 It is along Fig.16 For ease of explanation, the description will be briefly described or reference will be omitted. Figures 1 to 15 The repeated portion of the provided description.

[0116] Reference Fig.16 and Fig.17 , the semiconductor device according to some embodiments further includes a third protective insulating film 360 between the first protective insulating film 340 and the second protective insulating film 350 .

[0117] The third protective insulating film 360 may be formed in the item region CR. For example, the third protective insulating film 360 may be interposed between the first item pattern 330a and the second item pattern 330b.

[0118] In some embodiments, the third protective insulating film 360 may include a second insulating material. For example, the first protective insulating film 340, the second protective insulating film 350, and the third protective insulating film 360 may include the same silicon oxide. For example, each of the first protective insulating film 340, the second protective insulating film 350, and the third protective insulating film 360 may include TEOS (tetraethyl orthosilicate).

[0119] In some embodiments, the third protective insulating film 360 may connect a portion of the first protective insulating film 340 and a portion of the second protective insulating film 350. For example, a third trench T3 may be formed in the second interlayer insulating film 400 and the low-k insulating film in the scribe line region SL. Subsequently, the first protective insulating film 340, the second protective insulating film 350, and the third protective insulating film 360 filling the third trench T3 may be formed.

[0120] Fig.18 is a schematic layout diagram of a semiconductor device according to some embodiments of the inventive concept. Fig.19 It is along Fig.18 For ease of explanation, the following description will be briefly described or omitted. Figures 1 to 17 The repeated portion of the provided description.

[0121] Reference Fig.18 and Fig.19 In the semiconductor device according to some embodiments, the first protective insulating film 340 and / or the second protective insulating film 350 is discontinuous.

[0122] For example, the first protective insulating film 340 may include a first partial protective insulating film 340a and a second partial protective insulating film 340b spaced apart from each other. The first partial protective insulating film 340a and the second partial protective insulating film 340b may be arranged, for example, along the second direction Y. Similarly, the second protective insulating film 350 may include a third partial protective insulating film 350a and a fourth partial protective insulating film 350b spaced apart from each other.

[0123] In some embodiments, the fourth wiring structure 335 may be formed between the first partial protective insulating film 340 a and the second partial protective insulating film 340 b and / or between the third partial protective insulating film 350 a and the fourth partial protective insulating film 350 b .

[0124] In some embodiments, the fourth wiring structure 335 may include a third low-k insulating film 332 and a third wiring pattern 334. Fig.19 As shown, the third low-k insulating film 332 and the third wiring pattern 334 may extend to the protection region PR (eg, the second protection region PR2 ). Therefore, a fourth wiring structure 335 may be formed between the second wiring structure 320 and the third wiring structure 330 .

[0125] Fig. 20 is a schematic layout diagram of a semiconductor device according to some embodiments of the inventive concept. Fig.21 It is along Fig. 20 For ease of explanation, the description will be briefly described or reference will be omitted. Figures 1 to 19 The repeated portion of the provided description.

[0126] Reference Fig. 20 and Fig.21 , the semiconductor device according to some embodiments further includes an insertion insulating film 370 in the protection region PR (eg, the first protection region PR1 and the second protection region PR2 ).

[0127] The insertion insulating film 370 may be formed, for example, between the first partial protective insulating film 340 a and the second partial protective insulating film 340 b and / or between the third partial protective insulating film 350 a and the fourth partial protective insulating film 350 b .

[0128] In some embodiments, the insertion insulating film 370 may include a third insulating material different from the second insulating material. For example, the third insulating material may be a low-k material having a dielectric constant lower than that of silicon oxide. The first insulating material and the third insulating material may be the same as or different from each other.

[0129] exist Fig.21 , the height of the bottom surface of the first protective insulating film 340 is shown to be substantially the same as the height of the bottom surface of the insertion insulating film 370 relative to the substrate 100, but the present disclosure is not limited thereto. For example, based on the top surface of the substrate 100, the height H13 of the bottom surface of the first protective insulating film 340 may be different from the height H31 of the bottom surface of the insertion insulating film 370.

[0130] Fig. 22 is a schematic top view of a semiconductor chip according to some embodiments of the inventive concept. Fig.23 It is along Fig. 22 For ease of explanation, the description will be briefly described or reference will be omitted. Figures 1 to 21 The repeated portion of the provided description.

[0131] Fig. 22 and Fig.23 Shown including reference Figures 1 to 5 The semiconductor chip of the semiconductor device described above is only an example, and the semiconductor chip can be made by using Figures 6 to 21 The semiconductor device described is manufactured.

[0132] Reference Fig. 22 and Fig.23 According to some embodiments, the semiconductor chip includes a chip region MC and a remaining protection region RPR. For ease of explanation, the chip region MC is exemplarily described as Figures 1 to 5 The first chip region MC1 in the.

[0133] The remaining protection region RPR may be a portion of the scribe line region SL that is not removed by the small piece sawing process. Figure 5 As discussed in the description of , the first chip region MC1 may be cut and separated by a small chip sawing process performed along the dicing street region SL. The remaining protection region RPR may be a portion of the protection region PR in the dicing street region SL surrounding the first chip region MC1 that is not removed by the small chip sawing process. Fig.23As shown, the remaining protection region RPR may contact a portion of the second interlayer insulating film 400 and a portion of the first interlayer insulating film 200 , and may continuously extend between a portion of the second interlayer insulating film 400 and a portion of the first interlayer insulating film 200 .

[0134] In some embodiments, the remaining protection region RPR may completely surround the chip region MC. However, the present disclosure is not limited thereto, and depending on a die sawing process to be performed, the remaining protection region RPR may not completely surround the chip region MC.

[0135] The first protective insulating film 340 may be formed on the first interlayer insulating film 200 in the remaining protective region RPR. In some embodiments, the first protective insulating film 340 may completely surround the chip region MC. However, the present disclosure is not limited thereto, and may be formed on the first interlayer insulating film 200 in the remaining protective region RPR. Figures 18 to 21 The first protective insulating film 340 may not completely surround the chip region MC.

[0136] Fig.24 1 is a schematic cross-sectional view of a semiconductor package according to some embodiments of the present invention. Figures 1 to 23 The repeated portion of the provided description.

[0137] Reference Fig.24 , a semiconductor package according to some embodiments includes a semiconductor chip 1000 , a package substrate 1100 , and a molding member 1200 .

[0138] The semiconductor chip 1000 may be, for example, Fig. 22 and Fig.23 For example, the semiconductor chip 1000 may include a Figures 1 to 21 A semiconductor chip of a semiconductor device is described.

[0139] The semiconductor chip 1000 may be mounted on a package substrate 1100. The package substrate 1100 may be, for example, a printed circuit board (PCB) or a ceramic substrate. In some embodiments, the semiconductor chip 1000 may be electrically connected to the package substrate 1100 through a first connection member 1300. For example, the first connection member 1300 may electrically connect a chip pad 1010 of the semiconductor chip 1000 and an upper wiring 1110 of the package substrate 1100.

[0140] In some embodiments, the package substrate 1100 may be electrically connected to an external device through the second connection member 1400. For example, the second connection member 1400 may electrically connect the lower wiring 1120 of the package substrate 1100 to the external device.

[0141] The semiconductor chip 1000 is shown as being mounted on the package substrate 1100 by flip chip bonding, but this is merely an example, and the semiconductor chip 1000 may be mounted on the package substrate 1100 by various mounting methods such as tape automated bonding (TAB).

[0142] The molding member 1200 may be formed on the package substrate 1100. The molding member 1200 may cover the semiconductor chip 1000. The molding member 1200 may protect the semiconductor chip 1000.

[0143] The molding member 1200 may include, but is not limited to, epoxy molding compound (EMC) or polyimide, for example.

[0144] In the following, reference will be made to Figures 1 to 31 Methods for fabricating a semiconductor device according to some embodiments of the inventive concept are described.

[0145] Figure 25 to Figure 27 is a diagram showing an intermediate step of a method for manufacturing a semiconductor device according to some embodiments of the present inventive concept. Figures 1 to 21 The repeated portion of the provided description.

[0146] Reference Fig.25 , a first interlayer insulating film 200 , a wiring structure 300 , and a second interlayer insulating film 400 are sequentially formed on a substrate 100 .

[0147] The wiring structure 300 may include a low-k insulating film 302 and a wiring pattern 304 .

[0148] The low-k insulating film 302 may include a first insulating material. In some embodiments, the first insulating material may be a low-k material having a dielectric constant lower than that of silicon oxide.

[0149] The wiring pattern 304 may be formed in the low-k insulating film 302. The wiring pattern 304 may include a conductive material.

[0150] In some embodiments, before forming the first interlayer insulating film 200, the first integrated circuit element TR1 and the second integrated circuit element TR2 may be further formed on the substrate 100. In some embodiments, a first lower via 210 and a second lower via 220 for connecting the first integrated circuit element TR1 and the second integrated circuit element TR2 to the wiring pattern 304 may be further formed in the first interlayer insulating film 200.

[0151] In some embodiments, a conductive film 404 may be further formed on the wiring structure 300. In some embodiments, an upper via 402 for connecting the conductive film 404 and the wiring pattern 304 may be further formed in the second interlayer insulating film 400.

[0152] In some embodiments, the first interlayer insulating film 200 and / or the second interlayer insulating film 400 may include silicon oxide. For example, each of the first interlayer insulating film 200 and the second interlayer insulating film 400 may include TEOS (tetraethyl orthosilicate).

[0153] Although not shown, in some embodiments, a capping insulating film 410 may be further formed on the second interlayer insulating film 400. The capping insulating film 410 may include, but is not limited to, silicon nitride and / or silicon nitride oxide, for example.

[0154] Reference Fig.26 , the wiring structure 300 in the first protection region PR1 and the second protection region PR2 is removed.

[0155] For example, portions of the second interlayer insulating film 400, the conductive film 404, the upper via 402, the low-k insulating film 302, and the wiring pattern 304 in the first protection region PR1 may be removed, and the first trench T1 may be formed. In addition, for example, portions of the second interlayer insulating film 400, the conductive film 404, the upper via 402, the low-k insulating film 302, and the wiring pattern 304 in the second protection region PR2 may be removed, and the second trench T2 may be formed.

[0156] Thus, a first wiring structure 310 in the first chip region MC1 , a second wiring structure 320 in the second chip region MC2 , and a third wiring structure 330 in the item region CR may be formed.

[0157] In some embodiments, the first trench T1 and the second trench T2 may be formed to expose a portion of the top surface of the first interlayer insulating film 200. The respective bottom surfaces of the first trench T1 and the second trench T2 are shown to be lower than the respective bottom surfaces of the first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332, and higher than the top surface of the substrate 100, but the present disclosure is not limited thereto. For example, the respective bottom surfaces of one or more of the first trench T1 and the second trench T2 may be disposed on the same plane or coplanar with the respective bottom surfaces of the first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332, or may be disposed on the same plane or coplanar with the top surface of the substrate 100. In this specification, the term "same" means not only completely the same thing, but also includes slight differences that may occur due to process margins, etc.

[0158] Reference Fig. 27 , a first protective insulating film 340 is formed in the first trench T1 , and a second protective insulating film 350 is formed in the second trench T2 .

[0159] In some embodiments, the first protective insulating film 340 and the second protective insulating film 350 may include a second insulating material different from the first insulating material. In some embodiments, the second insulating material may include silicon oxide having a dielectric constant higher than that of the first insulating material. For example, the first protective insulating film 340 and the second protective insulating film 350 may include TEOS (tetraethyl orthosilicate).

[0160] In some embodiments, the first protective insulating film 340 and the second protective insulating film 350 may include the same material as the first interlayer insulating film 200 and the second interlayer insulating film 400. For example, the first protective insulating film 340, the second protective insulating film 350, the first interlayer insulating film 200 and the second interlayer insulating film 400 may include the same silicon oxide. For example, each of the first protective insulating film 340, the second protective insulating film 350, the first interlayer insulating film 200 and the second interlayer insulating film 400 may include TEOS (tetraethyl orthosilicate).

[0161] Although the first protective insulating film 340 and the second protective insulating film 350 are shown as completely filling the first trench T1 and the second trench T2, respectively, the present disclosure is not limited thereto. For example, the first protective insulating film 340 may only fill a portion of the first trench T1, and the second protective insulating film 350 may only fill a portion of the second trench T2. That is, as used herein, the elements of the filling region may partially or completely fill the region. For example, in contrast to the illustrated configuration, the respective top surfaces of the first protective insulating film 340 and the second protective insulating film 350 may be arranged on the same plane as the respective top surfaces of the first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332 or be arranged to be coplanar with them.

[0162] That is, by forming the first and second protective insulating films 340 and 350 in the scribe street regions SL adjacent to the chip region MC, a manufacturing method capable of manufacturing a semiconductor device with improved reliability and / or productivity / yield may be provided.

[0163] Figure 28 to Figure 31 is a diagram showing an intermediate step of a method for manufacturing a semiconductor device according to some embodiments of the present inventive concept. Figures 1 to 27 The repeated portion of the provided description.

[0164] Reference Fig.28 , a first interlayer insulating film 200 and a wiring structure 300 are sequentially formed on the substrate 100. Since the formation of the first interlayer insulating film 200 and the wiring structure 300 is similar to that of the reference Fig.25 described, and therefore a detailed description thereof will not be provided.

[0165] Reference Fig.29 , the wiring structure 300 in the first protection region PR1 and the second protection region PR2 is removed.

[0166] For example, the first trench T1 may be formed by removing portions of the low-k insulating film 302 and the wiring pattern 304 in the first protection region PR1. Also, for example, the second trench T2 may be formed by removing portions of the low-k insulating film 302 and the wiring pattern 304 in the second protection region PR2.

[0167] Thus, a first wiring structure 310 in the first chip region MC1 , a second wiring structure 320 in the second chip region MC2 , and a third wiring structure 330 in the item region CR may be formed.

[0168] Reference Fig.30 , a first protective insulating film 340 is formed in the first trench T1 , and a second protective insulating film 350 is formed in the second trench T2 .

[0169] In some embodiments, the first protection insulating film 340 and the second protection insulating film 350 may completely fill the first trench T1 and the second trench T2, respectively. Therefore, the respective top surfaces of the first protection insulating film 340 and the second protection insulating film 350 may be disposed on the same plane or coplanar with the respective top surfaces of the first low-k insulating film 312, the second low-k insulating film 322, and the third low-k insulating film 332.

[0170] Reference Fig.31 A second interlayer insulating film 400 is formed on the first wiring structure 310 , the second wiring structure 320 , the third wiring structure 330 , and the first and second protective insulating films 340 and 350 .

[0171] In some embodiments, the second interlayer insulating film 400 may include silicon oxide. For example, the second interlayer insulating film 400 may include TEOS (tetraethyl orthosilicate).

[0172] In some embodiments, the second interlayer insulating film 400 may include the same material as the first protective insulating film 340 and the second protective insulating film 350. For example, the first protective insulating film 340, the second protective insulating film 350 and the second interlayer insulating film 400 may include the same silicon oxide. For example, each of the first protective insulating film 340, the second protective insulating film 350 and the second interlayer insulating film 400 may include TEOS (tetraethyl orthosilicate).

[0173] In some embodiments, a conductive film 404 may be further formed in the second interlayer insulating film 400. In some embodiments, an upper via 402 for connecting the conductive film 404 and the wiring pattern 304 may be further formed in the second interlayer insulating film 400.

[0174] Those skilled in the art will appreciate that many changes and modifications may be made to the preferred embodiments without departing substantially from the principles of the present invention. Therefore, the preferred embodiments of the present invention disclosed are used in a general and descriptive sense only and not for limiting purposes.

Claims

1. A semiconductor device, comprising: A substrate, the substrate comprising a first chip region and a scribe line region surrounding the first chip region; a first low-k insulating film on the substrate in the first chip region, the first low-k insulating film comprising a first insulating material having a dielectric constant smaller than that of silicon oxide; a wiring structure on the substrate in the scribe line region, the wiring structure comprising a first item pattern and a second item pattern electrically separated from each other, wherein each of the first item pattern and the second item pattern comprises a second low-k insulating film and a wiring pattern in the second low-k insulating film, the second low-k insulating film comprising the first insulating material; a first protective insulating film between the first low-k insulating film and the wiring structure, the first protective insulating film including a second insulating material different from the first insulating material; and A third protective insulating film is located between the first item pattern and the second item pattern, and the third protective insulating film includes the second insulating material.

2. The semiconductor device according to claim 1, wherein The dielectric constant of the second insulating material is greater than the dielectric constant of the first insulating material.

3. The semiconductor device according to claim 2, wherein: The second insulating material includes silicon oxide.

4. The semiconductor device according to claim 1, wherein: The substrate further includes a second chip region separated from the first chip region by the scribe line region, and The semiconductor device further comprises: a third low-k insulating film located on the substrate in the second chip region, the third low-k insulating film comprising the first insulating material; and A second protective insulating film is located between the third low-k insulating film and the wiring structure.

5. The semiconductor device according to claim 4, wherein: The second protective insulating film includes the second insulating material.

6. The semiconductor device according to claim 1, further comprising: A first interlayer insulating film is located between the substrate and the first protective insulating film.

7. The semiconductor device according to claim 6, further comprising: A second interlayer insulating film is located on the first protective insulating film, wherein the first protective insulating film continuously extends from the second interlayer insulating film to the first interlayer insulating film.

8. A semiconductor device comprising: A substrate, the substrate comprising a first chip region, a second chip region, and a scribe line region between the first chip region and the second chip region; a first low-k insulating film on the substrate in the first chip region, the first low-k insulating film comprising a first insulating material having a dielectric constant smaller than that of silicon oxide; a second low-k insulating film located on the substrate in the second chip region, the second low-k insulating film comprising the first insulating material; a third low-k insulating film located on the substrate in the scribe line region, the third low-k insulating film comprising the first insulating material; a first protective insulating film located between the first low-k insulating film and the third low-k insulating film, the first protective insulating film comprising a second insulating material different from the first insulating material; as well as a second protective insulating film located between the second low-k insulating film and the third low-k insulating film, the second protective insulating film comprising the second insulating material, The distance between the first low-k insulating film and the third low-k insulating film is different from the distance between the second low-k insulating film and the third low-k insulating film.

9. The semiconductor device according to claim 8, further comprising: a first integrated circuit element located on the substrate in the first chip region; as well as A first wiring pattern located in the first low-k insulating film is electrically connected to the first integrated circuit element.

10. The semiconductor device according to claim 8, further comprising: A third wiring pattern is located in the third low-k insulating film.

11. The semiconductor device according to claim 8, wherein The first low-k insulating film, the second low-k insulating film, and the third low-k insulating film are at the same level with respect to the substrate.

12. The semiconductor device according to claim 8, wherein The second insulating material includes silicon oxide.

13. A semiconductor device comprising: A substrate, the substrate comprising a chip region and a scribe line region surrounding the chip region, the scribe line region comprising a protection region and a project region at the periphery of the chip region; a first interlayer insulating film located on the substrate, the first interlayer insulating film comprising silicon oxide; a low-k insulating film on the first interlayer insulating film, the low-k insulating film defining a trench in the protection region and comprising a low-k material having a dielectric constant smaller than that of silicon oxide; a wiring pattern in the low-k insulating film in the project area, wherein the wiring pattern includes a first project pattern and a second project pattern electrically separated from each other; a first protective insulating film filling the trench and including silicon oxide; and A second protective insulating film is located between the first item pattern and the second item pattern, and the second protective insulating film includes silicon oxide.

14. The semiconductor device according to claim 13, wherein: Each of the first interlayer insulating film and the first protective insulating film includes tetraethyl orthosilicate.

15. The semiconductor device according to claim 13, wherein: The protection area surrounds the chip area, and wherein the project area surrounds the protection area, and the wiring pattern is included in the project area.

16. The semiconductor device according to claim 13, wherein: The first protective insulating film includes a first partial protective insulating film and a second partial protective insulating film separated from each other.

17. The semiconductor device according to claim 16, wherein: A portion of the low-k insulating film is interposed between the first portion of the protective insulating film and the second portion of the protective insulating film.

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