DCDC converter based on PCB planar inductor

Abstract

The present invention belongs to the technical field of DC-DC converters, and specifically relates to a DC-DC converter based on a PCB planar inductor. The converter comprises: a PCB planar inductor, one end of which is connected to an input voltage; a current sampling circuit, the input end of which is connected to the other end of the PCB planar inductor; a drive circuit, the input end of which is connected to the output end of the current sampling circuit; and a first power transistor, the output end of the drive circuit being connected to the first power transistor, and the input end of the current sampling circuit being connected to the first power transistor. The present invention can accurately sample and limit the peak value of the inductor, operate normally at high frequencies, and avoid EMI interference.

Description

Technical Field

[0001] The present invention belongs to the technical field of DCDC converters, and in particular relates to a DCDC converter based on a PCB planar inductor. Background Art

[0002] Power inductors are critical components in DC-DC converters, responsible for both energy storage and release. With increasingly fierce competition in the DC-DC market, reducing costs has become a major challenge for designers. Traditional DC-DC converters typically use wirewound and multilayer inductors, which offer high inductance but are expensive. However, coreless planar inductors made from PCBs offer low cost and are ideal for low-cost DC-DC converters.

[0003] However, compared to wire-wound and multilayer inductors, PCB planar inductors have a significant disadvantage: their relatively low inductance. With a turn count of 10 mils, a trace width of 8 mils, and a trace spacing of 10 mils, the inductance reaches only about 500 nH. Considering both area and cost, practical inductance values ​​are typically limited to around 100-200 nH. Such low inductance results in very rapid rise and fall times for the inductor current. The inductor current sensing circuit must be capable of high-speed sampling; otherwise, accurate current sampling will be inaccurate, and the peak current cannot be properly limited, potentially causing sudden high current overheating and damaging the chip. Because the peak current must be limited, the DC-DC converter must use a high-frequency clock to maintain load capacity. To achieve a wide input and output voltage range, the high-level duration of the minimum duty cycle pulse and the low-level duration of the maximum duty cycle pulse must be sufficiently short at this high-frequency clock. If the driver circuit operates normally within these short pulse times, the LX voltage will inevitably fluctuate rapidly, thus affecting the DC-DC converter's EMI performance.

[0004] In summary, the use of PCB planar inductors can greatly reduce DCDC costs. However, since their inductance values ​​are generally small, they can lead to a series of problems such as inductor current sampling, high-frequency driving, and EMI interference.

[0005] In order to solve these problems, the present invention provides a DCDC converter based on PCB planar inductors. Summary of the Invention

[0006] An object of the present invention is to solve at least the above problems and / or disadvantages and to provide at least the advantages which will be described hereinafter.

[0007] Another object of the present invention is to provide a DCDC converter based on a PCB planar inductor, which can perform high-speed sampling of the inductor current, thereby preventing the inductor current peak from reaching too high a level.

[0008] In order to achieve these purposes and other advantages according to the present invention, the present invention provides a DCDC converter based on a PCB planar inductor, comprising:

[0009] A PCB plane inductor, one end of which is connected to the input voltage;

[0010] a current sampling circuit, the input end of which is connected to the other end of the PCB plane inductor;

[0011] a driving circuit, an input end of which is connected to the output end of the current sampling circuit;

[0012] A first power tube, the output end of the driving circuit is connected to the first power tube, and the input end of the current sampling circuit is connected to the first power tube.

[0013] The present invention can perform high-speed sampling of the inductor current, thereby ensuring that the inductor current peak value does not reach too high. In a high-frequency working state, combined with a drive circuit, while reducing the rise and fall time of the power tube, it ensures that the LX voltage has sufficient conversion time, thereby ensuring that the EMI interference of the converter does not worsen.

[0014] Preferably, a comparator is further included, wherein the negative input terminal of the comparator is connected to the output terminal of the current sampling circuit, the positive input terminal of the comparator is connected to the output voltage circuit, and the output terminal of the comparator is connected to the driving circuit.

[0015] Preferably, the output voltage circuit further includes an error amplifier, a resistor R0, a resistor R1, a resistor R2 and a capacitor C0, one end of the resistor R1 is connected to one end of the output voltage, the other end of the resistor R1 is respectively connected to the negative input end of the error amplifier and one end of the resistor R2, the other end of the resistor R2 is connected to the ground, the positive input end of the error amplifier is a reference voltage, and the output end of the error amplifier is connected to the positive input end of the comparator; the two ends of the resistor R0 and the capacitor C0 are respectively connected to the two ends of the output voltage, preferably, a compensation circuit is further included, the compensation circuit is connected to the positive input end of the comparator, the compensation circuit includes capacitor C0, capacitor C1 and resistor Rcl, one end of the capacitor C0 and capacitor C1 connected in parallel is connected to the ground, and the parallel end of the capacitor C1 is connected in series with the resistor Rcl and connected to the positive input end of the comparator.

[0016] Preferably, the current sampling circuit has a dual-loop structure, comprising a fast loop and a slow loop, wherein the input end of the fast loop is connected to the drain of the first power tube, the input end of the slow loop is connected to the drain of the current sampling tube, and the output ends of the fast loop and the slow loop output current signals;

[0017] The gate of the first power tube is connected to the gate of the current sampling tube, and the source of the first power tube and the source of the current sampling tube are connected to the ground.

[0018] Preferably, the current sampling circuit further includes a first inverter, a plurality of N-type MOS transistors and a plurality of P-type MOS transistors, the plurality of N-type MOS transistors are defined as MN1, MN2, MN3, MN4, MN5, MN6, and MN7, and the plurality of P-type MOS transistors are defined as MP1, MP2, MP3, MP4, MP5, MP6, and MP7;

[0019] Among them, the MN7 is connected to the first power tube, the MN1, the MN2 and the MN5 respectively, the MN6, the MN3, the MN4 and the MP7 are all connected to the current sampling tube, and the current sampling tube is connected to the inverter and then connected to the MN5 and the MN6; the MN1 to MN4 are connected together, the MN1 is connected to the MP4, the MP4 is connected to the MP5, and the MP5 is connected to the MP6 and the MN4; the MN2 is connected to the MP2 and MP6, the MN3 is connected to MP3, MP6, MP7 and MP8, the MN4 is connected to MP6 and MP5, and the MP1, MP2 and MP3 are connected.

[0020] Preferably, the loop connected by the MN1, MN4, MP4, MP5 and MP6 forms a fast loop, and the loop connected by the MN2, MN3 and MP7 forms a slow loop.

[0021] Preferably, the driving circuit includes a second inverter, a pull-up driving circuit and a pull-down driving circuit, the input end of the second inverter is connected to the input end of the pull-down driving circuit, the output end of the second inverter is connected to the input end of the pull-up driving circuit, and the output ends of the pull-up driving circuit and the pull-down driving circuit are connected to the first power tube.

[0022] Preferably, the pull-up drive circuit includes a first delay, an OR gate, and two P-type MOS transistors, the two P-type MOS transistors being defined as MP9 and MP10, the output end of the second inverter being respectively connected to the input end of the first delay and the input end of the OR gate, the output end of the first delay being connected to the input end of the OR gate, the output end of the OR gate being connected to MP9, and the MP9 being connected to MP10; the pull-down drive circuit includes a second delay, an AND gate, and two N-type MOS transistors, the two N-type MOS transistors being defined as MN8 and MN9, the input end of the second inverter being connected to the input end of the second delay, the output end of the second inverter being connected to the input end of the AND gate, the output end of the second delay being connected to the input end of the AND gate, the output end of the AND gate being connected to MN8, and MN8 being connected to MN9;

[0023] The drains of MP9, MP10, MN8 and MN9 are connected to the first power tube.

[0024] Preferably, a diode D is further included, wherein the anode of the diode D is connected to the drain of the first power tube, and the cathode of the diode is connected to the output voltage.

[0025] The present invention has at least the following beneficial effects:

[0026] 1. The DCDC converter based on PCB planar inductors provided by the present invention uses an inductor current sampling circuit with a dual-loop structure, which can perform high-speed and accurate sampling of the inductor current, thereby ensuring that the inductor current peak does not reach too high.

[0027] 2. The DCDC converter based on PCB planar inductors provided by the present invention adopts segmented acceleration of the drive in high-frequency working state to ensure that the LX voltage has sufficient conversion time, thereby ensuring that the EMI interference of the converter will not worsen.

[0028] 3. The DCDC converter based on PCB planar inductor provided by the present invention adopts a driving circuit that can greatly reduce the rise and fall time without affecting the EMI characteristics.

[0029] 4. The DCDC converter based on PCB planar inductors provided by the present invention can greatly reduce DCDC costs and expand the scope of popularization and application. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 This is a circuit schematic diagram of a DCDC converter based on PCB planar inductors according to the present invention;

[0031] Figure 2 is a schematic diagram of the current sampling circuit of the present invention;

[0032] Figure 3 is a schematic diagram of the driving circuit of the present invention;

[0033] Figure 4 is a schematic diagram of the logic processing circuit of the present invention;

[0034] Figure 5 It is a waveform diagram of the drive on and off time and LX of the present invention;

[0035] Figure 6 It is the waveform diagram of the traditional drive opening and closing time and LX;

[0036] Wherein, Vin: input voltage, Vo: output voltage, Ci: input capacitance, L: PCB plane inductance, LX: drain of the first power tube, BG: first power tube, D: freewheeling diode, Co: output capacitance, Ro: load resistance, EA: error amplifier, VREF: reference voltage, Vea: output signal of the error amplifier, Vfb: divided voltage signal of the output voltage, CMP2: comparator, OCP: overcurrent signal generated after sampling, Vsense: current sampling signal, PWMON: duty cycle control signal, BG_ON: precursor control signal of the first power tube, BG_DRV: drive signal, BG_SEN: current sampling tube, LXS: drain of the current sampling tube, DLY1: first delay, DLY2: second delay, INV1: first inverter, INV2: second inverter, OR1: OR gate, ND1: AND gate. DETAILED DESCRIPTION

[0037] The present invention will be described in further detail below in conjunction with the accompanying drawings so that those skilled in the art can implement the invention with reference to the description.

[0038] In this specification, when an element is referred to as being “connected or coupled to” another element or “disposed in” another element, it may be “directly” connected or coupled to the other element or “directly” disposed in the other element. Or it may be connected or coupled to the other element or disposed in the other element with other elements interposed therebetween, unless it is referred to as being “directly coupled or connected to” the other element or “directly disposed” in the other element. In addition, it should be understood that when an element is referred to as being “on the other element,” “above the other element,” “under the other element,” or “under the other element,” it may be “directly” in contact with the other element or in contact with the other element with other elements interposed therebetween, unless it is referred to as being in direct contact with the other element.

[0039] The present invention provides a DCDC converter based on PCB planar inductance, such as Figure 1 As shown, including:

[0040] A PCB plane inductor, one end of which is connected to the input voltage Vin;

[0041] A current sampling circuit, the input end of which is connected to the other end of the PCB plane inductor through the LX;

[0042] a driving circuit, an input end of which is connected to the output end of the current sampling circuit;

[0043] A first power tube, the output end of the driving circuit is connected to the gate of the first power tube, the input end of the current sampling circuit is connected to the drain LX of the first power tube, and the source of the first power tube is connected to the ground.

[0044] The present invention can perform high-speed sampling of the inductor current, thereby ensuring that the inductor current peak value does not reach too high. In a high-frequency working state, combined with a drive circuit, while reducing the rise and fall time of the power tube, it ensures that the LX voltage has sufficient conversion time, thereby ensuring that the EMI interference of the converter does not worsen.

[0045] Specifically, it also includes a comparator, wherein the negative input terminal of the comparator is connected to the output terminal of the current sampling circuit, the positive input terminal of the comparator is connected to the output voltage circuit, and the output terminal of the comparator is connected to the drive circuit; the negative input terminal of the comparator is connected to the output terminal of the current sampling circuit, and the positive input terminal of the comparator is connected to the output voltage, that is, after comparing the current sampling signal Vsense collected by the current sampling circuit with the output voltage, a duty cycle control signal PWMON is generated, and then the duty cycle control signal PWMON is input to the drive circuit to increase its driving capability and generate a drive signal to drive the first power tube to be turned on and off.

[0046] Before the duty cycle control signal PWMON is input to the driving circuit, the overcurrent signal OCP generated by the current sampling circuit and the duty cycle control signal PWMON can also be processed in the following way: the overcurrent signal OCP generated by the current sampling circuit and the duty cycle control signal PWMON are simultaneously processed logically, wherein the logic processing is performed by the logic processing circuit, such as Figure 4 As shown, the logic processing circuit includes an inverter and an AND gate. The input end of the inverter is connected to the output end of the current sampling circuit outputting the OCP overcurrent signal. The output end of the inverter is connected to one end of the input of the AND gate. The other end of the input of the AND gate is connected to the output end of the comparator. The output end of the AND gate is connected to the drive circuit. When the inductor current of the comparator is too high, the OCP signal is high. After passing through the inverter and the AND gate, the BG_ON signal is forced to be pulled low, thereby turning off the power tube BG and protecting the DCDC from overheating and burning.

[0047] Specifically, the output voltage circuit also includes an error amplifier EA, a resistor R0, a resistor R1, a resistor R2 and a capacitor C0, wherein Co is an output capacitor and Ro is a load resistor, which are respectively connected to the two ends of Vo; R1 and R2 are a voltage-dividing resistor string, the negative input end of the error amplifier is connected to the divided voltage of the output voltage, the positive input end of the error amplifier is a reference voltage VREF, and the output end of the error amplifier is connected to the positive input end of the comparator; the two ends of the resistor R0 and the capacitor C0 are respectively connected to the two ends of the output voltage, one end of the resistor R1 is connected to one end of the output voltage, the other end of the resistor R1 is respectively connected to the negative input end of the error amplifier and one end of the resistor R2, the other end of the resistor R2 is connected to ground, R1 and R2 are a voltage-dividing resistor string, and its divided voltage value is connected to the negative end of EA.

[0048] Specifically, a compensation circuit is further included. The compensation circuit is connected to the positive input terminal of the comparator. The compensation circuit includes a capacitor C0, a capacitor C1, and a resistor Rcl. One end of the capacitor C0 and the capacitor C1 connected in parallel is connected to the ground, and the other end of the capacitor C1 connected in parallel is connected in series with the resistor Rcl and then connected to the positive input terminal of the comparator. The compensation circuit is to ensure the stability of the DCDC loop.

[0049] like Figure 1 As shown, the inductor uses a PCB planar inductor, and the circuit adopts PWM peak current mode control. Due to the low inductance value, the DCDC frequency is higher than the traditional DCDC frequency, and a new circuit architecture is invented for the current sampling circuit and the drive circuit. Figure 3-1 In the figure, Ci is the input capacitor, connected to the two ends of the input voltage Vin; L is the PCB plane inductor, with its two ends connected to Vin and the power tube drain LX respectively; BG is the power tube, the drain is connected to the inductor, and the source is connected to the ground; D is the freewheeling diode, the positive electrode is connected to LX, and the negative electrode is connected to the output Vo; Co is the output capacitor, Ro is the load resistor, connected to the two ends of Vo respectively; R1 and R2 are the voltage divider resistor string, and their voltage divider value is connected to the negative end of EA; VREF is the reference voltage, connected to the positive end of EA; EA is the error amplifier, and the output Vea is connected to the compensation circuit composed of Rc1, C1 and C0, and enters the positive end of the comparator CMP2; the current sampling circuit samples the current when the first power tube BG is turned on (that is, the inductor current when BG is turned on), connected to LX for current sampling, and the overcurrent signal OCP generated after sampling enters the logic processing circuit. When OCP is high, the logic processing circuit for logic processing will generate a signal to turn off BG (such as Figure 4As shown in FIG, another current sampling signal Vsense generated after current sampling is connected to the negative terminal of the comparator CMP2, and compared with Vea to generate a duty cycle control signal PWMON which is input to the logic processing circuit; the logic processing circuit generates a precursor control signal BG_ON for the first power tube BG_ON, which enters the drive circuit, increases its drive capability, and generates a drive signal BG_DRV; BG_DRV is connected to the gate of the first power tube BG to control its on and off.

[0050] The operating principle of the DCDC converter based on a PCB planar inductor provided by the present invention is as follows: when the output voltage is low, the output feedback voltage is compared with VREF, and the output error signal Vea becomes higher after passing through the error amplifier EA. The duty cycle of the PWMON control signal obtained after comparison with the inductor current sampling signal becomes larger. Then, the duty cycle of the drive signal BG_DRV signal obtained after processing by the drive circuit becomes larger, thereby increasing the inductor current and releasing more energy to the output, increasing the output voltage and maintaining the output voltage stable. When the output voltage is high, the output feedback voltage is compared with VREF, and the output error signal Vea becomes lower after passing through the error amplifier EA. The duty cycle of the PWMON control signal obtained after comparison with the inductor current sampling signal becomes smaller. Then, the duty cycle of the drive signal BG_DRV signal obtained after processing by the drive circuit becomes smaller, thereby reducing the inductor current and releasing less energy to the output, thereby reducing the output voltage and maintaining the output voltage stable.

[0051] On the basis of the above embodiment, another embodiment is provided. Figure 2 As shown, the current sampling circuit has a dual-loop structure, which includes a fast loop and a slow loop. The input end of the fast loop is connected to the drain of the first power tube, the input end of the slow loop is connected to the drain of the current sampling tube, and the output ends of the fast loop and the slow loop output current signals. The current sampling circuit of the present invention adopts dual-loop control, which can accurately sample when the inductor current rises rapidly.

[0052] The gate of the first power transistor is connected to the gate of the current sampling transistor, and the source of the first power transistor and the source of the current sampling transistor are connected to ground. BG is a power transistor, and BG_SEN is a current sampling transistor. The gates of both transistors are connected to the drive signal BG_DRV, and the sources are connected to ground. The drain of BG is connected to LX, and the drain of BG_SEN is connected to LXS.

[0053] Specifically, the current sampling circuit further includes a first inverter, a plurality of N-type MOS transistors and a plurality of P-type MOS transistors, the plurality of N-type MOS transistors are defined as MN1, MN2, MN3, MN4, MN5, MN6, and MN7, and the plurality of P-type MOS transistors are defined as MP1, MP2, MP3, MP4, MP5, MP6, and MP7;

[0054] Among them, MN7 is a switch tube, the gate of which is connected to BG_DRV, the drain of which is connected to LX, and the source of which is respectively connected to the source of MN1, MN2, and the drain of MN5. BG_DRV is connected to the gates of MN5 and MN6 after an inverter. The source terminals of MN5 and MN6 are both connected to the ground potential. The drain of MN6, the source terminals of MN3 and MN4, and the drain of MP7 are all connected to LXS. The gates of MN1 to MN4 are connected together, the drain of MN1 is connected to the drain of MP4, and the drain and gate of MN2 are connected to point B, forming a diode connection mode. Point B is connected to the drain terminals of MP2 and MP6, the drain of MN3 is connected to the drain of MP3, the source terminal of MP6, and the gate terminals of MP7 and MP8 are connected to point A, and the drain of MN4 is connected to the gate of MP6 and the drain of MP5 at point C. The gates of MP1, MP2 and MP3 are connected, and the drain of MP1 is connected; the drain of MP8 is connected to the resistor R2, the generated current sampling signal Vsense is connected to the positive pole of the comparator, and the reference voltage VREF is connected to the negative pole of the comparator. After comparison, the overcurrent signal OCP is obtained.

[0055] like Figure 2 As shown, MP1, MP2 and MP3 form a current mirror to provide current for the circuit. MN2 and MN3 are clamping circuits to ensure that the voltages of LX and LXS are equal. BG is a power tube, and BG_SEN is a sampling tube. When LX and LXS are equal, BG_SEN will proportionally mirror the current of BG. MN5, MN6 and MN7 are switching tubes. The loop connected by MN1, MN4, MP4~MP6 forms a fast loop. The loop connected by MP7, MN2 and MN3 forms a slow loop. MP8 and MP7 are current mirrors. C2 and C3 are the parasitic capacitances of MP7. R2 converts the sampled current into a sampled voltage Vsense, which is compared with VREF to obtain the peak current overcurrent signal OCP.

[0056] The current sampling circuit operates as follows: When the power transistor BG is off (i.e., BG_DRV is low), current sampling is not performed. Therefore, BG and BG_SEN are both off, MN7 is off, and MN5 and MN6 are on. At this time, the clamping circuit formed by MP3 and MP4 remains operational to avoid wasting time reestablishing the loop when BG turns on in the next cycle. When BG is on (i.e., BG_DRV is high), current sampling is required. BG and BG_SEN are both on, MN7 is on, and MN5 and MN6 are off. At this time, MN2 and MN3, due to the same current, clamp LX and LXS to equal voltages. BG_SEN proportionally mirrors the current on BG1 (at this point, the current on BG1 is equal to the inductor current). This current is then mirrored through MP7 to MP8, ultimately converted to Vsense and compared with VREF to generate an overcurrent OCP signal. Since the MP7 tube is generally large in size (due to the need to use mA-level sampling current), the parasitic capacitances C2 and C3 of MP7 are also relatively large. Therefore, the negative feedback loop composed of MP7, MN2 and MN3 is slow. When BG is turned on, the voltage at point A needs to be reduced, and the discharge of C1 and C2 will cause a large current in MN3. However, the current on MN2 will be very small due to the charging of the gate capacitance of MN2 and MN3. Therefore, LX and LXS are not equal. When the inductor current rises quickly, the circuit cannot perform sampling correctly. At this time, a fast feedback loop composed of MN1, MN4, MP4~MP6 is required to accelerate the sampling process. The principle is: when BG is turned on, the existence of parasitic capacitance will cause the current of MN3 to be greater than that of MN2. Since MN4 is a mirror image of MN3's current, and MN1 is a mirror image of MN2's current, the gate voltage of MP6, point C, will be pulled down, turning on points A and B. As a result, the current through MN3 decreases and the current through MN2 increases. The process continues until the currents of MN2 and MN3 are equal and stabilize, thereby making LX and LXS equal, and the circuit is correctly sampled.

[0057] On the basis of the above embodiment, another embodiment is provided. Figure 3 As shown, the driving circuit includes a second inverter, a pull-up driving circuit and a pull-down driving circuit, the input end of the second inverter is connected to the input end of the pull-down driving circuit, the output end of the second inverter is connected to the input end of the pull-up driving circuit, and the output ends of the pull-up driving circuit and the pull-down driving circuit are connected to the first power tube.

[0058] Specifically, the pull-up drive circuit includes a first delay, an OR gate, and two P-type MOS transistors, the two P-type MOS transistors are defined as MP9 and MP10, the output end of the second inverter is respectively connected to the input end of the first delay and the input end of the OR gate, the output end of the first delay is connected to the input end of the OR gate, the output end of the OR gate is connected to MP9, and the MP9 is connected to MP10; the pull-down drive circuit includes a second delay, an AND gate, and two N-type MOS transistors, the two N-type MOS transistors are defined as MN8 and MN9, the input end of the second inverter is connected to the input end of the second delay, the output end of the second inverter is connected to the input end of the AND gate, the output end of the second delay is connected to the input end of the AND gate, the output end of the AND gate is connected to MN8, and MN8 is connected to MN9.

[0059] The drains of MP9, MP10, MN8 and MN9 are connected to the first power tube.

[0060] like Figure 3 As shown, the precursor BG_ON is connected to the input of the inverter INV and the delay unit DLY2; the output signal A of the inverter INV is connected to the input of the delay unit DLY1, the input of the OR gate OR1 and the AND gate ND1, and the gates of MP2 and MN2; the output D of DLY1 is connected to the other input of OR1, and the output E of DLY2 is connected to the other input of ND1; the output B of OR1 is connected to the gate of MP1, and the output C of ND1 is connected to the gate of MN1; the drains of MP1, MP2, MN1 and MN2 are connected to obtain the output signal BG_DRV, the sources of MP1 and MP2 are connected to the power supply voltage, and the sources of MN1 and MN2 are connected to the ground potential.

[0061] like Figure 6 Figure 2 shows the waveforms of the drive signal and LX in a conventional drive circuit. First, the turn-on process is described. When the pre-driver signal BG_ON is high, the drive signal BG_DRV begins to rise. The rise time is t1. During this period, the current on the power transistor BG rapidly increases to the inductor current, but the LX voltage remains unchanged. During period t2, the drive enters the Miller plateau of the power transistor, BG_DRV remains unchanged, and the LX voltage gradually decreases to 0. After entering period t3, the drive signal BG_DRV continues to rise to its maximum voltage, while the LX voltage remains at 0. The turn-off process is similar to the turn-on process: during period t4, the drive signal BG_DRV decreases until it enters the Miller plateau of the power transistor, during which the LX voltage remains at 0. During period t5, the drive enters the Miller plateau of the power transistor, the drive signal BG_DRV remains unchanged, and the LX voltage gradually rises to its maximum voltage. During period t6, the drive signal continues to decrease until it reaches 0. During this period, the LX voltage remains at its maximum, and the current on BG1 rapidly decreases to 0.

[0062] Because the minimum duty cycle high-level duration and maximum duty cycle low-level duration of a DC-DC converter based on PCB planar inductance are very short, the turn-on and turn-off processes of the power transistor BG must be accelerated, that is, the durations t1+t2+t3 and t4+t5+t6 must be shortened. If the overall drive capability is increased, the rise and fall speeds of LX will inevitably increase, which will affect the EMI performance of the DC-DC converter. From the above analysis, we can see that the rise and fall speeds of LX are only related to t2 and t5 (i.e., the Miller plateau time). Therefore, t2 and t5 can be kept unchanged, while t1, t3, t4, and t6 can be shortened.

[0063] Therefore, the operating principle of the drive circuit of the present invention is as follows: when the current drive BG_ON changes from low to high (i.e., when the power tube is turned on), the voltage at point A becomes low, and the voltage at point C obtained through the AND gate is also low, so MN1 and MN2 are turned off, and MP2 is turned on. Due to the existence of DLY1, the voltage at point D does not jump and remains high during the delay time, so at this time point B is also high, and MP1 is turned off; after the delay ends, point D jumps to low, and point B also becomes low. At this time, MP1 will turn on the acceleration pull-up BG_DRV. The delay time is ≥ t1 + t2, and the acceleration period is t3. When the current drive BG_ON changes from high to low (that is, when the power tube is turned off), the voltage at point A jumps to high, and the voltage at point B obtained through the OR gate is also high, so MP1 and MP2 are turned off, MN2 is turned on, and because of the existence of DLY2, the voltage at point E is still high during the delay time, so the voltage at point C is also high at this time, and MN1 is also turned on, which will accelerate the pull-down of BG_DRV. If the delay period is ≤ t4, the accelerated period is t4; after the delay ends, the voltage at point E jumps to low, so the voltage at point C also jumps to low, MN1 is turned off, and the times t5 and t6 are not affected.

[0064] like Figure 3 and Figure 5 As shown, the driving circuit provided by the present invention is mainly to shorten the relatively long time periods t3 and t4, such as Figure 5 The waveform diagram of the driver's on / off timing and LX in this embodiment shows that, in this example, t1, t2, t5, and t6 remain unchanged, resulting in unchanged LX's rise and fall times, and the circuit's EMI performance is improved. t3 and t4 are significantly reduced to t3' and t4', significantly reducing both BG_DRV's rise and fall times. This new driver is suitable for high-frequency applications with both low and high duty cycles. If higher frequencies are required, t1 and t6 can be further reduced, but this is not detailed here.

[0065] In addition, the present invention further includes a diode D, the anode of the diode D is connected to the drain of the first power tube, and the cathode of the diode is connected to the output voltage.

[0066] An input capacitor Ci is also included, which is connected across the input voltage Vin.

[0067] The present invention provides a DC-DC converter based on a PCB planar inductor. The inductor current sampling circuit designed in this invention adopts a dual-loop structure, which can sample the inductor current at high speed, thereby ensuring that the inductor current peak does not reach too high. In the high-frequency operating state, this patent adopts segmented acceleration of the drive, while reducing the rise and fall time of the power tube, ensuring sufficient conversion time for the LX voltage, thereby ensuring that the EMI interference of the converter is not aggravated.

[0068] It is obvious that those skilled in the art can obtain various effects that have not been directly mentioned according to the various embodiments from the various structures according to the embodiments of the present invention.

[0069] Although the embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and exemplary embodiments. They can be applied to a variety of fields suitable for the present invention. Further modifications will be readily apparent to those skilled in the art. Therefore, the present invention is not limited to the specific details and illustrations shown and described herein without departing from the general concept defined by the claims and their equivalents.

Claims

1. A DC-DC converter based on PCB planar inductor, characterized in that: include: A PCB plane inductor, one end of which is connected to the input voltage; a current sampling circuit, the input end of which is connected to the other end of the PCB plane inductor; a driving circuit, an input end of which is connected to the output end of the current sampling circuit; a first power tube, the output end of the driving circuit being connected to the first power tube, and the input end of the current sampling circuit being connected to the first power tube; The current sampling circuit has a dual-loop structure, which includes a fast loop and a slow loop. The input end of the fast loop is connected to the drain of the first power tube, the input end of the slow loop is connected to the drain of the current sampling tube, and the output ends of the fast loop and the slow loop output current signals. The gate of the first power tube is connected to the gate of the current sampling tube, and the source of the first power tube is connected to the source of the current sampling tube and the ground at the same time; The current sampling circuit further includes a first inverter, a plurality of N-type MOS transistors and a plurality of P-type MOS transistors, the plurality of N-type MOS transistors are defined as MN1, MN2, MN3, MN4, MN5, MN6, and MN7, and the plurality of P-type MOS transistors are defined as MP1, MP2, MP3, MP4, MP5, MP6, and MP7; Among them, the gate of the MN7 is connected to the gate of the first power tube, the drain of the MN7 is connected to the drain of the first power tube, and the source of the MN7 is respectively connected to the source of the MN1, the source of the MN2, and the drain of the MN5; the gate of the current sampling tube is respectively connected to the gate of the MN5 and the gate of the MN6 after passing through the first inverter, the sources of the MN5 and the MN6 are both connected to the ground potential, the drain of the MN6, the sources of the MN3 and MN4, and the drain of the MP7 are all connected to the drain of the current sampling tube; the MN1, MN2, MN3, The gates of MN4 are connected together, the drain of MN1 is connected to the drain of MP4, and the drain and gate of MN2 are both connected to point B, forming a diode connection. Point B is respectively connected to the drain of MP2 and the drain of MP6; the drain of MN3, the drain of MP3, the source of MP6, the gate of MP7, and the gate of MP8 are all connected to point A; the drain of MN4 is respectively connected to the gate of MP6 and the drain of MP5 at point C, and the gate of MP5 is connected to the gate of MP4; the gates of MP1, MP2, and MP3 are connected together, and the drain and gate of MP1 are connected; The loop connected by MN1, MN4, MP4, MP5 and MP6 forms a fast loop, and the loop connected by MN2, MN3 and MP7 forms a slow loop.

2. The DCDC converter based on PCB planar inductor according to claim 1, characterized in that: It also includes a comparator, wherein the negative input terminal of the comparator is connected to the output terminal of the current sampling circuit, the positive input terminal of the comparator is connected to the output voltage circuit, and the output terminal of the comparator is connected to the driving circuit.

3. The DCDC converter based on PCB planar inductor according to claim 2, characterized in that: The output voltage circuit includes an error amplifier, a resistor R0, a resistor R1, a resistor R2 and a capacitor C0, one end of the resistor R1 is connected to one end of the output voltage, the other end of the resistor R1 is respectively connected to the negative input end of the error amplifier and one end of the resistor R2, the other end of the resistor R2 is connected to the ground, the positive input end of the error amplifier is a reference voltage, the output end of the error amplifier is connected to the positive input end of the comparator, and the two ends of the resistor R0 and the capacitor C0 are respectively connected to the two ends of the output voltage.

4. The DCDC converter based on PCB planar inductor according to claim 2, characterized in that: It also includes a compensation circuit, which is connected to the positive input terminal of the comparator. The compensation circuit includes a capacitor C0, a capacitor C1 and a resistor Rcl. One end of the capacitor C0 and the capacitor C1 connected in parallel is connected to the ground, and the other end of the capacitor C1 connected in parallel is connected in series with the resistor Rcl and then connected to the positive input terminal of the comparator.

5. The DCDC converter based on PCB planar inductor according to claim 2, characterized in that: The driving circuit includes a second inverter, a pull-up driving circuit and a pull-down driving circuit, the input end of the second inverter is connected to the input end of the pull-down driving circuit, the output end of the second inverter is connected to the input end of the pull-up driving circuit, and the output ends of the pull-up driving circuit and the pull-down driving circuit are connected to the first power tube.

6. The DCDC converter based on PCB planar inductor according to claim 5, characterized in that: The pull-up driving circuit includes a first delay, an OR gate, and two P-type MOS transistors, which are defined as MP9 and MP10. The output end of the second inverter is respectively connected to the input end of the first delay and the input end of the OR gate. The output end of the first delay is connected to the input end of the OR gate. The output end of the OR gate is connected to MP9, and the MP9 is connected to MP10. The pull-down driving circuit includes a second delay, an AND gate, and two N-type MOS transistors, which are defined as MN8 and MN9. The input end of the second inverter is connected to the input end of the second delay, the output end of the second inverter is connected to the input end of the AND gate, the output end of the second delay is connected to the input end of the AND gate, the output end of the AND gate is connected to MN8, and MN8 is connected to MN9. The drains of MP9, MP10, MN8 and MN9 are connected to the first power tube.

7. The DCDC converter based on PCB planar inductance according to any one of claims 1 to 6, characterized in that: It also includes a diode D, wherein the anode of the diode D is connected to the drain of the first power tube, and the cathode of the diode is connected to the output voltage.

Images