Semiconductor package and method of manufacturing semiconductor package

Abstract

The semiconductor package includes: a package substrate; a first semiconductor device arranged on the package substrate; at least one second semiconductor device on the first semiconductor device, partially covering the first semiconductor device from a top view; a heat dissipation insulation layer coated on the first semiconductor device and the at least one second semiconductor device; a conductive heat dissipation structure arranged on the heat dissipation insulation layer on the portion of the first semiconductor device not covered by the second semiconductor device; and a molding layer on the package substrate, covering the first semiconductor device and the at least one second semiconductor device. The heat dissipation insulation layer is formed of an electrically insulating and thermally conductive material, and the conductive heat dissipation structure is formed of an electrically conductive and thermally conductive material.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2018-0127804 filed on October 24, 2018, with the Korean Intellectual Property Office (KIPO), and Korean Patent Application No. 10-2018-0136392 filed on November 8, 2018, with the KIPO, the contents of each of which are incorporated herein by reference in their entirety. Technical Field

[0003] Example embodiments relate to semiconductor packages and methods of manufacturing semiconductor packages. More particularly, example embodiments relate to a system-in-package including various chips stacked in one package and a method of manufacturing the same. Background Art

[0004] In a system-in-package (SIP), memory devices are affected by the heat from logic devices. Therefore, it is important to provide a heat transfer path for dissipating the heat from the logic devices to the surrounding environment. Although metal materials have many heat transfer advantages, there are limitations to using metal materials inside the package due to their electrical conductivity.

[0005] In the related art, an adhesive member with high thermal conductivity (e.g., a heat sink) may be used to dissipate heat. However, according to these methods, it may be difficult to effectively dissipate heat from the logic device to the surrounding environment. In addition, an adhesive member including a metal material with high thermal conductivity may be limited to being formed on the surface of the device due to its electrical conductivity. Summary of the invention

[0006] Example embodiments provide a semiconductor package having improved heat dissipation performance.

[0007] Example embodiments provide a method of manufacturing the semiconductor package.

[0008] According to an example embodiment, a semiconductor package includes: a package substrate; a first semiconductor device arranged on the package substrate; at least one second semiconductor device on the first semiconductor device, partially covering the first semiconductor device from a top view; a heat dissipation insulation layer coated on the first semiconductor device and the at least one second semiconductor device; a conductive heat dissipation structure arranged on the heat dissipation insulation layer on a portion of the first semiconductor device not covered by the second semiconductor device; and a molding layer on the package substrate, covering the first semiconductor device and the at least one second semiconductor device. The heat dissipation insulation layer is formed of an electrically insulating and thermally conductive material, and the conductive heat dissipation structure is formed of an electrically conductive and thermally conductive material.

[0009] According to an example embodiment, which may be the same or different from the above example, an electronic device includes: a substrate; a first electronic product, arranged on the substrate; at least one second electronic product on the first electronic product, partially covering the first electronic product when viewed from a top view; a heat dissipation insulating layer, coated at least on the top surface of the substrate, the first electronic product, and the second electronic product; a first conductive heat dissipation member, arranged on the heat dissipation insulating layer on a portion of the first electronic product not covered by the second electronic product; and a molding member on the substrate, covering the first electronic product and the second electronic product. The heat dissipation insulating layer is formed of an electrically insulating and thermally conductive material, and the first conductive heat dissipation member is formed of an electrically conductive and thermally conductive material. For example, the electronic device may be a semiconductor package, and the first electronic product and the at least one second electronic product may both be semiconductor devices.

[0010] According to an example embodiment, which may be the same as or different from the above-described example embodiments, an electronic device includes: a substrate; a first electronic product arranged on the substrate; at least one second electronic product on the first electronic product, partially covering the first electronic product when viewed from a top plan, the second electronic product being configured to consume less power than the first electronic product; a heat dissipation insulating layer coated on the substrate, the first electronic product and at least one second electronic product, the heat dissipation insulating layer being formed of an electrically insulating material; a first conductive heat dissipation member arranged on the heat dissipation insulating layer on a portion of the first electronic product not covered by the second electronic product, the first conductive heat dissipation member being formed of a conductive material; and a molding member on the substrate, covering the first electronic product and at least one second electronic product.

[0011] According to an example embodiment, in a method of manufacturing a semiconductor package, a first semiconductor device is stacked on a package substrate. At least one second semiconductor device is stacked on the first semiconductor device to partially cover the first semiconductor device when viewed from a top view. A heat dissipation insulating layer is coated on the first semiconductor device and the second semiconductor device. A first conductive heat dissipation member is formed on the heat dissipation insulating layer on a portion of the first semiconductor device that is not covered by the second semiconductor device. A molding member is formed on the package substrate to cover the first semiconductor device and the second semiconductor device.

[0012] Therefore, heat from the first semiconductor device consuming relatively high power can be quickly dissipated in the vertical direction through the conductive heat dissipation member having high thermal conductivity. Therefore, the heat dissipation performance of the system-in-package can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings. Figures 1 to 31 Represents non-limiting example embodiments described herein.

[0014] Figure 1is a cross-sectional view illustrating a semiconductor package according to example embodiments.

[0015] Figure 2 It shows Figure 1 A plan view of a semiconductor package in FIG.

[0016] Figures 3 to 7 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0017] Figure 8 is a cross-sectional view illustrating a semiconductor package according to example embodiments.

[0018] Figures 9 to 11 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0019] Fig.12 is a cross-sectional view illustrating a semiconductor package according to example embodiments.

[0020] Fig.13 is a cross-sectional view illustrating a semiconductor package according to example embodiments.

[0021] Fig.14 It shows Fig.13 A perspective view of a semiconductor package in FIG.

[0022] Figures 15 to 20 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0023] Fig.21 is a cross-sectional view illustrating a semiconductor package according to example embodiments.

[0024] Figure 22 to Figure 24 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0025] Fig.25 is a cross-sectional view illustrating a semiconductor package according to example embodiments.

[0026] Fig.26 and Fig. 27 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0027] Fig.28 is a cross-sectional view illustrating a semiconductor package according to example embodiments.

[0028] Fig.29 is a cross-sectional view illustrating a semiconductor package according to example embodiments.

[0029] Fig.30 is a cross-sectional view illustrating a semiconductor package according to example embodiments.

[0030] Fig.31 is a cross-sectional view illustrating a semiconductor package according to example embodiments. DETAILED DESCRIPTION

[0031] Hereinafter, example embodiments will be described in detail with reference to the accompanying drawings.

[0032] Figure 1 is a cross-sectional view illustrating a semiconductor package according to example embodiments. Figure 2 It shows Figure 1 A plan view of a semiconductor package in FIG.

[0033] refer to Figure 1 and Figure 2 , the semiconductor package 10 may include a package substrate 100, a first semiconductor device 110, at least one second semiconductor device 120a, 120b, a heat dissipation insulating layer 130, a conductive heat dissipation member 140, and a molding member 150. Additionally, the semiconductor package 10 may be an electronic device such as a system-in-package (SIP). The first semiconductor device 110 may include a first electronic product (e.g., a logic semiconductor device), and the second semiconductor devices 120a, 120b may include a second electronic product (e.g., a memory device). The first electronic product may be a first heat source that consumes a first power, and the second electronic product may be a second heat source that consumes a second power lower than the first power. Therefore, the first semiconductor device 110 may dissipate more heat than the second semiconductor devices 120a, 120b.

[0034] The package substrate 100 may be a substrate having an upper surface and a lower surface opposite to each other. For example, the package substrate 100 may be a printed circuit board (PCB). The printed circuit board may include a multi-circuit board having through holes and various circuit elements therein. As described herein, a semiconductor package refers to one or more semiconductor chips mounted on a package substrate, wherein the semiconductor chip and the package substrate are covered or surrounded by a molding layer or a packaging layer. A semiconductor package is different from a memory module, which generally includes a plurality of memory devices (e.g., semiconductor packages) respectively mounted on one side or both sides of a module board, wherein the memory devices and the module board are not covered by a packaging layer. A memory module generally has a different structure and a different circuit from a semiconductor package.

[0035] The first semiconductor device 110 may be stacked on the package substrate 100. The first semiconductor device 110 may be mounted on the package substrate 100 in, for example, a flip chip bonding manner. The first semiconductor device 110 may be formed by a semiconductor chip separated from a semiconductor wafer, or by a plurality of stacked semiconductor chips separated from a wafer and then mounted on each other, or separated from a group of stacked semiconductor wafers. In one embodiment, the first semiconductor device 110 may be electrically connected to the package substrate 100 via a conductive bump 112.

[0036] A plurality of conductive bumps 112 may be arranged on a plurality of substrate pads on the upper surface of the package substrate 100 to electrically connect the first semiconductor device 110 and the package substrate 100 to each other. An adhesive member 114 may be bottom-filled between the first semiconductor device 110 and the package substrate 100. The adhesive member 114 may include an epoxy material filled between the first semiconductor device 110 and the package substrate 100. More generally, the adhesive member 114 may be described as an underfill or an underfill layer.

[0037] Alternatively, the first semiconductor device 110 may be electrically connected to the package substrate 100 via a bonding wire. In this case, the first semiconductor device 110 may be stacked on the package substrate 100 via an adhesive layer. The items described herein as electrically connected are communicatively connected via a conductive or semiconductive component so that an electrical signal can be passed from one component to another component for use or further transmission. Therefore, a conductive component connected to an electrically insulating component is not electrically connected to the electrically insulating component, which prevents the electrical signal from being further transmitted and does not use the electrical signal.

[0038] In example embodiments, at least one second semiconductor device 120a, 120b may be stacked on the first semiconductor device 110 to partially cover (e.g., partially overlap as viewed from a top view) the first semiconductor device 110. Each of the second semiconductor devices 120a and 120b may partially overlap the first semiconductor device 110. A portion of an upper surface of the first semiconductor device 110 may not be covered by one or both of the second semiconductor devices 120a, 120b and may thus be exposed relative to one or both of the second semiconductor devices 120a, 120b.

[0039] Specifically, two second semiconductor devices 120a, 120b may be stacked on the first semiconductor device 110. The second semiconductor devices 120a, 120b may be arranged on the first semiconductor device 110 to be spaced apart from each other. The second semiconductor devices 120a, 120b may be stacked on the first semiconductor device 110 via an adhesion layer 124. The adhesion layer 124 may include, for example, a polymer material having excellent thermal conductivity relative to other adhesive materials. Examples of polymer materials may be thermally conductive tape, thermally conductive grease, thermally conductive adhesive, etc. The adhesion layer 124 may have, for example, a thermal conductivity of 10 watts / meter-Kelvin (W / (m·K)) or more. The second semiconductor devices 120a, 120b may be electrically connected to the package substrate 100 by bonding wires 122a, 122b.

[0040] The second semiconductor devices 120a, 120b may include memory devices such as DRAM, NAND flash memory, etc. The second semiconductor devices may each include a plurality of stacked semiconductor chips. The number, size, position, etc. of the stacked chips are shown exemplarily, so they are not limited to the above examples.

[0041] In an example embodiment, the heat dissipation insulating layer 130 may be coated on the first semiconductor device 110 and the second semiconductor device 120a, 120b. The heat dissipation insulating layer 130 may be conformally deposited on the entire exposed surface of the package substrate 100, the first semiconductor device 110, and the second semiconductor device 120a, 120b. Therefore, the upper surface of the package substrate 100, the sidewall of the first semiconductor device 110, and the upper surface and sidewall of the second semiconductor device 120a, 120b may be covered by the heat dissipation insulating layer 130. In this way, the heat dissipation insulating layer 130 may be at least conformally deposited on the entire exposed upper surface of the first semiconductor device 110 and the second semiconductor device 120a, 120b.

[0042] The heat dissipation insulating layer 130 may include an electrical insulating material having excellent thermal conductivity relative to typical electrical insulating materials. The heat dissipation insulating layer 130 may include, for example, aluminum oxide (Al 2 O 3 ), boron nitride (BN), aluminum nitride (AlN), ceramic-coated metal balls, etc. The thermally conductive materials described herein include materials that easily transfer heat. Materials with heat transfer properties opposite to those of thermally conductive materials (which tend to prevent heat transfer) can be described as thermally insulating. As an example, the heat dissipation insulating layer 130 may include a material with a thermal conductivity of 10 watts / meter-Kelvin (W / (m·K)) or greater, and in some embodiments, may include a material with a thermal conductivity of 30 watts / meter-Kelvin (W / (m·K)) or greater.

[0043] In an example embodiment, the conductive heat dissipation member 140 may include a first conductive heat dissipation member 142 disposed on the heat dissipation insulation layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120a, 120b. Additionally, the conductive heat dissipation member 140 may further include a second conductive heat dissipation member 143 disposed on the heat dissipation insulation layer 130 on the second semiconductor devices 120a, 120b. The first conductive heat dissipation member 142 and the second conductive heat dissipation member 143 may each be a solid structure and may be continuously formed by a single integral structure extending in a first direction along the length of the first semiconductor device 110 and the second semiconductor devices 120a and 120b. The conductive heat dissipation member 140 may be described as a conductive heat dissipation layer, or as a conductive heat dissipation structure including a first portion and a second (or more) portion.

[0044] The conductive heat dissipation member 140 may include an electrically conductive and thermally conductive material having excellent thermal conductivity, such as metals such as gold (Au), silver (Ag), copper (Cu), graphite, graphene, etc. As an example, the conductive heat dissipation member 140 may include a material having a thermal conductivity higher than 50 watts / meter-Kelvin (W / (m·K)), and in some embodiments, may include a material having a thermal conductivity higher than 100 watts / meter-Kelvin (W / (m·K)). Figure 2 As shown in the example of , the conductive heat dissipation member 140 can extend continuously to have a length greater than each of the second semiconductor devices 120a, 120b. The length can be at least greater than the distance spanned by three adjacent pads 102 (e.g., bonding pads) formed on the packaging substrate. In some embodiments, the conductive heat dissipation member 140 is electrically insulated from any circuit of the first semiconductor device 110, the second semiconductor device 120a, 120b, and the packaging substrate 100, and does not transmit electrical signals to the first semiconductor device 110, the second semiconductor device 120a, 120b, or the packaging substrate 100 or receive electrical signals from the first semiconductor device 110, the second semiconductor device 120a, 120b, or the packaging substrate 100.

[0045] The first conductive heat dissipation member 142 may have a column shape extending from the surface of the heat dissipation insulation layer 130 between the second semiconductor devices 120a, 120b in the vertical direction. The first conductive heat dissipation member 142 may contact the heat dissipation insulation layer 130 on the sidewalls of the second semiconductor devices 120a, 120b, and the heat dissipation insulation layer 130 on the top surface of the package substrate 100. Alternatively, the first conductive heat dissipation member 142 may be arranged to be spaced apart from the heat dissipation insulation layer 130 on the sidewalls of the second semiconductor devices 120a, 120b so that it does not contact the sidewalls of the second semiconductor devices 120a, 120b. It will be understood that when an element is referred to as being "connected" or "coupled" to another element or "on" another element or "between" two elements, the element may be directly connected or coupled to the other element or directly on or between the other element, or there may be an intervening element. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, or "directly on" or "directly between" another element, there are no intervening elements. Other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "adjacent" versus "directly adjacent," etc.). Unless the context indicates otherwise, the term "contacting" as used herein refers to direct connection (i.e., touching).

[0046] The second conductive heat dissipation member 143 may extend laterally on the heat dissipation insulation layer 130 on the second semiconductor devices 120a, 120b. The second conductive heat dissipation member 143 may be in contact with the first conductive heat dissipation member 142 or may be formed integrally with the first conductive heat dissipation member 142. Alternatively, the second conductive heat dissipation member 143 may be arranged to be spaced apart from the sidewall of the first conductive heat dissipation member 142.

[0047] As described above, the second conductive heat dissipation member 143 may be integrally formed with the first conductive heat dissipation member 142. The height of the top surface of the second conductive heat dissipation member 143 relative to the package substrate 100 may be the same as that of the top surface of the first conductive heat dissipation member 142 relative to the package substrate 100.

[0048] In example embodiments, a molding member 150 (also described as a molding layer) may be formed on the package substrate 100 to cover at least a portion of the first semiconductor device 110 and the second semiconductor device 120a, 120b, thereby protecting the first semiconductor device 110 and the second semiconductor device 120a, 120b from the surrounding environment. The molding member 150 may be formed to expose the upper surfaces of the first conductive heat dissipation member 142 and the second conductive heat dissipation member 143 to, for example, the outside of the semiconductor package 10. The height of the top surface of the molding member 150 relative to the top surface of the package substrate 100 may be the same as the height of the top surfaces of the first conductive heat dissipation member 142 and the second conductive heat dissipation member 143 relative to the top surface of the package substrate 100.

[0049] As described above, the semiconductor package 10 may include a first conductive heat dissipation member 142 thermally connected to the first semiconductor device 110 to dissipate heat from the first semiconductor device 110 to the surrounding environment. The semiconductor package 10 may include a second conductive heat dissipation member 143 thermally connected to the second semiconductor devices 120a, 120b to dissipate heat from the second semiconductor devices 120a, 120b to the surrounding environment.

[0050] Heat from the first semiconductor device 110 may be dissipated through the heat dissipation insulating layer 130 and the first conductive heat dissipation member 142. Heat from the second semiconductor devices 120a, 120b may be dissipated through the heat dissipation insulating layer 130 and the second conductive heat dissipation member 143. The first conductive heat dissipation member 142 and the second conductive heat dissipation member 143 may serve as a heat transfer path for dissipating heat from the first semiconductor device 110 and the second semiconductor devices 120a, 120b to the surrounding environment.

[0051] Therefore, heat from the first semiconductor device 110 consuming relatively high power can be quickly dissipated in the vertical direction through the first conductive heat dissipation member 142 having high thermal conductivity. Therefore, heat dissipation performance of the system-in-package can be improved.

[0052] In the following, the manufacturing Figure 1 and Figure 2 An example method for semiconductor packaging in FIG.

[0053] Figures 3 to 7 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0054] refer to Figure 3 and Figure 4 , a first semiconductor device 110 may be stacked on the package substrate 100 , and at least one second semiconductor device 120 a , 120 b may be stacked on the first semiconductor device 110 to partially cover the first semiconductor device 110 .

[0055] First, the first semiconductor device 110 may be stacked on an upper surface of the package substrate 100. For example, the package substrate 110 may include a printed circuit board (PCB), an organic substrate, a ceramic substrate, a module board, or the like.

[0056] The first semiconductor device 110 may be stacked on the package substrate 100. In some embodiments, the first semiconductor device 110 may be mounted on the package substrate 100 in a flip chip bonding manner. For example, the first semiconductor device 110 may be electrically connected to the package substrate 100 via a conductive bump 112. A plurality of conductive bumps 112 may be arranged on a plurality of substrate pads on an upper surface of the package substrate 100 to electrically connect the first semiconductor device 110 and the package substrate 100 to each other.

[0057] After adhering the first semiconductor device 110 on the package substrate 100, an adhesive member 114 may be underfilled between the first semiconductor device 110 and the package substrate 100. The adhesive member 114 may include, for example, an epoxy material filled between the first semiconductor device 110 and the package substrate 100.

[0058] Two second semiconductor devices 120a and 120b may be stacked on the first semiconductor device 110 to partially cover the first semiconductor device 110. The second semiconductor devices 120a, 120b may partially overlap the first semiconductor device 110. A portion of an upper surface of the first semiconductor device 110 may be exposed by the second semiconductor devices 120a, 120b.

[0059] The second semiconductor devices 120a, 120b may be arranged on the first semiconductor device 110 to be spaced apart from each other, so that a gap or space may be formed therebetween. The second semiconductor devices 120a, 120b may be stacked on the first semiconductor device 110 via an adhesion layer 124. The adhesion layer 124 may include a polymer material having excellent thermal conductivity. Examples of the polymer material may be thermally conductive tape, thermally conductive grease, thermally conductive adhesive, etc.

[0060] A wire bonding process may be performed to electrically connect the chip pads of the second semiconductor devices 120a, 120b to the substrate pads of the package substrate 100. The chip pads of the second semiconductor devices 120a, 120b may be electrically connected to the substrate pads of the package substrate 100 through bonding wires 122a, 122b.

[0061] refer to Figure 5 and Figure 6The heat dissipation insulating layer 130 may be coated on the first semiconductor device 110 and the second semiconductor devices 120a, 120b, and the first conductive heat dissipation member 142 may be formed on the heat dissipation insulating layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120a, 120b. The second conductive heat dissipation member 143 may be formed on the heat dissipation insulating layer 130 on the second semiconductor devices 120a, 120b.

[0062] In example embodiments, the heat dissipation insulating layer 130 may be conformally coated on the entire exposed surface (e.g., side surface and upper surface) of the package substrate 100, the first semiconductor device 110, and the second semiconductor devices 120a, 120b, for example, by a spray coating process. An electrically insulating material may be sprayed on the entire exposed surface of the package substrate 100, the first semiconductor device 110, and the second semiconductor devices 120a, 120b, for example, using a nozzle to form the heat dissipation insulating layer 130 having a uniform thickness.

[0063] The electrical insulating material may have excellent thermal conductivity relative to typical electrical insulating materials. The heat dissipation insulating layer 130 may include, for example, aluminum oxide (Al 2 O 3 ), boron nitride (BN), aluminum nitride (AlN), ceramic-coated metal balls, etc.

[0064] Then, the first conductive heat dissipation member 142 may be formed by an application process, a screen printing process, etc. For example, a metal paste may be applied on the heat dissipation insulating layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120a, 120b to form the first conductive heat dissipation member 142. In the application process, a metal paste may be applied on the heat dissipation insulating layer 130 on the second semiconductor devices 120a, 120b to form the second conductive heat dissipation member 143.

[0065] The metal paste can be repeatedly applied using an applicator to form the first conductive heat dissipation member 142 and the second conductive heat dissipation member 143 having a desired shape at a desired position. The metal paste can include, for example, a conductive material having excellent thermal conductivity, such as gold (Au), silver (Ag), copper (Cu), etc.

[0066] The first conductive heat dissipation member 142 may be formed to have a column shape extending in a vertical direction from a surface of the heat dissipation insulation layer 130 between the second semiconductor devices 120a, 120b. The first conductive heat dissipation member 142 may contact the heat dissipation insulation layer 130 on the sidewalls of the second semiconductor devices 120a, 120b. Alternatively, the first conductive heat dissipation member 142 may be arranged to be spaced apart from the heat dissipation insulation layer 130 on the sidewalls of the second semiconductor devices 120a, 120b.

[0067] The second conductive heat dissipation member 143 may be integrally formed with the first conductive heat dissipation member 142. The height of the second conductive heat dissipation member 143 relative to the top surface of the package substrate 100 may be the same as the height of the top surface of the first conductive heat dissipation member 142 relative to the top surface of the package substrate 100.

[0068] refer to Figure 7 , a molding member 150 may be formed on the packaging substrate 100 to cover at least a portion of the first semiconductor device 110 and the second semiconductor device 120a, 120b. The molding member 150 may be a packaging structure formed to expose the upper surfaces of the first conductive heat dissipation member 142 and the second conductive heat dissipation member 143 to, for example, the outside of the semiconductor package. An insulating material such as an epoxy molding compound (EMC) may be coated on the upper surface of the packaging substrate 100, and the coated insulating material may be grinded to expose the upper surfaces of the first conductive heat dissipation member 142 and the second conductive heat dissipation member 143 and have them have a top surface coplanar with the top surface of the molding member 150. Therefore, the height of the top surface of the molding member 150 relative to the top surface of the packaging substrate 100 may be the same as the height of the top surfaces of the first conductive heat dissipation member 142 and the second conductive heat dissipation member 143 relative to the top surface of the packaging substrate 100.

[0069] Then, external connection terminals 104 may be formed on the external connection pads on the lower surface of the package substrate 100 to complete the semiconductor package 10 .

[0070] Figure 8 is a cross-sectional view showing a semiconductor package according to an example embodiment. In addition to the conductive heat dissipation member, the semiconductor package can be Figure 1 The semiconductor packages described are substantially the same or similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repeated descriptions on the above elements will be omitted.

[0071] refer to Figure 8 The conductive heat dissipation member 140 of the semiconductor package 11 may include: a first conductive heat dissipation member 142, which is arranged on the heat dissipation insulation layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120a, 120b; and a second conductive heat dissipation member 143, which is arranged on the heat dissipation insulation layer 130 on the second semiconductor devices 120a, 120b.

[0072] In example embodiments, the molding member 150 may have a through hole 151 formed therein to expose an upper surface of the heat dissipation insulating layer 130 on the first and second semiconductor devices 110 and 120 a and 120 b. The conductive heat dissipation member 140 may be filled in the through hole 151 .

[0073] The width of the through hole 151 may gradually decrease toward the lower portion of the through hole 151, especially for the portion above the second semiconductor devices 120a and 120b. Therefore, the width of the through hole 151 may gradually increase toward the upper portion of the through hole 151. This is consistent with Figure 7 The embodiments are different. Figure 7 , the width of the through-hole in the molding member 150 at a height above the second semiconductor devices 120 a and 120 b is uniform from the bottom to the top.

[0074] In the following, the manufacturing Figure 8 A method for semiconductor packaging.

[0075] Figures 9 to 11 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0076] refer to Fig. 9 , first, you can execute the reference Figures 3 to 5 The same process as described above is used, so that the heat dissipation insulation layer 130 is coated on the first semiconductor device 110 and the second semiconductor device 120a, 120b on the packaging substrate 100, and the molding member 150 is formed on the upper surface of the packaging substrate 100 to cover the first semiconductor device 110 and the second semiconductor device 120a, 120b.

[0077] refer to Fig.10 and Fig.11 , the conductive heat dissipation member 140 may be formed in the molding member 150 to extend from the heat dissipation insulation layer 130 on the first and second semiconductor devices 110 and 120 a and 120 b in a vertical direction.

[0078] First, the molding member 150 may be formed to cover the entire surface of the heat dissipation insulation layer 130, and then the molding member 150 may be partially removed to form a through hole 151 exposing a portion of the upper surface of the heat dissipation insulation layer 130. For example, the through hole 151 may be formed by an etching process, a laser drilling process, or the like.

[0079] Then, the through hole 151 of the molding member 150 may be filled with a conductive material to form a conductive heat dissipation member 140 in contact with the heat dissipation insulating layer 130. The conductive material may be a metal paste including a metal material (e.g., gold (Au), silver (Ag), copper (Cu), etc.). The conductive heat dissipation member 140 may be formed such that the upper surface of the conductive heat dissipation member 140 is exposed from the molding member 150.

[0080] The conductive heat dissipation member 140 may include: a first conductive heat dissipation member 142, which is disposed on the heat dissipation insulation layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120a, 120b; and a second conductive heat dissipation member 143, which is disposed on the heat dissipation insulation layer 130 on the second semiconductor devices 120a, 120b.

[0081] Fig.12 is a cross-sectional view showing a semiconductor package according to an example embodiment. In addition to the conductive heat dissipation member and the heat dissipation insulation layer, the semiconductor package can be similar to the reference Figure 1 The semiconductor packages described are substantially the same or similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repeated descriptions on the above elements will be omitted.

[0082] refer to Fig.12 The conductive heat dissipation member 140 of the semiconductor package 12 may include: a first conductive heat dissipation member 142, which is arranged on the heat dissipation insulation layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120a, 120b; and a second conductive heat dissipation member 143, which is arranged on the heat dissipation insulation layer 130 on the second semiconductor devices 120a, 120b.

[0083] In example embodiments, the heat dissipation insulating layer 130 may cover the bonding wires 122a, 122b on the second semiconductor devices 120a, 120b. The second conductive heat dissipation member 143 may extend laterally to cover the entire upper surface of the second semiconductor devices 120a, 120b. The second conductive heat dissipation member 143 may extend to the region where the bonding wires extend on the second semiconductor devices 120a, 120b. The heat dissipation insulating layer 130 may be interposed between the bonding wires 122a, 122b and the second conductive heat dissipation member 143.

[0084] When the insulating material is sprayed onto the entire exposed surface of the package substrate 100 using a nozzle to form the heat dissipation insulating layer 130, the insulating material may cover the surfaces of the bonding wires 122a, 122b on the second semiconductor devices 120a, 120b. Figure 1 shown, but the same coating may be included in Figure 1 In the embodiment of the present invention, the heat dissipation insulating layer 130 may be coated on the bonding wires 122a and 122b to cover the surfaces of the bonding wires 122a and 122b.

[0085] Therefore, in Fig.12 In the embodiment, since the bonding wires 122a, 122b are electrically insulated by the heat dissipation insulating layer 130, the second conductive heat dissipation member 143 can be formed to a desired position over a relatively large area. Therefore, the heat dissipation performance of the system-in-package can be improved.

[0086] Fig.13 is a cross-sectional view illustrating a semiconductor package according to example embodiments. Fig.14 It shows Fig.13 Except for the second semiconductor device and the conductive heat dissipation member, the semiconductor package can be the same as the reference Figure 1 The semiconductor packages described are substantially the same or similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repeated descriptions on the above elements may be omitted.

[0087] refer to Fig.13 and Fig.14 The second semiconductor devices 120a', 120b' of the semiconductor package 13 may each include a plurality of stacked semiconductor chips. Each of the second semiconductor devices may include, for example, a high bandwidth memory (HBM) device.

[0088] In an example embodiment, two second semiconductor devices 120a', 120b' may be arranged on the first semiconductor device 110 to be spaced apart from each other. The second semiconductor devices 120a', 120b' may each include a buffer die 121a, and first to third memory dies 121b, 121c, 121d sequentially stacked on each other. The buffer die 121a and the first to third memory dies 121b, 121c, 121d may be electrically connected to each other through substrate through vias (TSVs) 125, which may be through silicon vias. The buffer die 121a and the first to third memory dies 121b, 121c, 121d may transmit data signals and control signals to each other through the TSVs 125. The buffer die 121a may be electrically connected to the first semiconductor device 110 through a plurality of conductive bumps 123. The second semiconductor device as an HBM device including four stacked dies (chips) is exemplarily shown, however it may not be limited thereto.

[0089] The heat dissipation insulating layer 130 may be conformally coated on the entire exposed surface of the package substrate 100, the first semiconductor device 110, and the second semiconductor devices 120a', 120b'. Therefore, the heat dissipation insulating layer 130 may be coated on the upper surface of the package substrate 100, the sidewall of the first semiconductor device 110, and the upper surface and sidewall of the second semiconductor devices 120a', 120b'.

[0090] In example embodiments, the conductive heat dissipation member 140' may include a first conductive heat dissipation member 142' disposed on the heat dissipation insulating layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120a', 120b'. The first conductive heat dissipation member 142' may include: a conductive plate 142a (e.g., formed of a conductive and thermally conductive material) on the heat dissipation insulating layer 130 on the first semiconductor device 110, extending laterally and surrounding the second semiconductor devices 120a', 120b'; and at least one conductive pillar 142b (e.g., formed of a conductive and thermally conductive material) extending from the conductive plate 142a in a vertical direction. The width of the conductive plate 142a in the first horizontal direction may be greater than the height in the second vertical direction, and the height of each conductive pillar in the second vertical direction may be greater than the width in at least the first horizontal direction. The conductive plate 142a may extend continuously in the horizontal direction to have a length greater than the length of each of the second semiconductor devices 120a', 120b'. The length of each conductive pillar 142 b continuously extending in the horizontal direction may be at least greater than the distance spanned by two adjacent pads TSV formed in the second semiconductor device 120 a ′ or 120 b ′.

[0091] The conductive plate 142a may be spaced apart from the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a', 120b' (e.g., with a portion of the molding member 150 therebetween). Alternatively, the conductive plate 142a may be in contact with the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a', 120b' without a portion of the molding member 150 therebetween.

[0092] The height to which the conductive pillars 142b extend relative to the top surface of the packaging substrate 100 may be the same as the height of the second semiconductor devices 120a', 120b' relative to the top surface of the packaging substrate 100, so that the top surface of the conductive pillars 142b may be coplanar with the top surface of the second semiconductor devices 120a', 120b'. When each conductive pillar 142b extends in the vertical direction, each conductive pillar 142b may have a uniform width in the first horizontal direction. Each conductive pillar 142b may be spaced apart from the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a', 120b'. Alternatively, one or more of the conductive pillars 142b may contact the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a', 120b'.

[0093] One conductive pillar 142b may be arranged between the second semiconductor devices 120a', 120b'. Two conductive pillars 142b may be arranged outward from the second semiconductor devices 120a', 120b' (e.g., outside the area covered by the second semiconductor devices 120a', 120b'). However, the number, shape, etc. of the conductive pillars are not limited thereto.

[0094] The molding member 150 may be formed on the upper surface of the package substrate 100 to cover at least a portion of the first semiconductor device 110 and the second semiconductor device 120a', 120b'. The molding member 150 may be formed to expose the upper surface of the conductive pillar 142b. The molding member 150 may fill the space between the second semiconductor device 120a', 120b' and the first conductive heat dissipation member 140.

[0095] In the following, the manufacturing Fig.13 A method for semiconductor packaging.

[0096] Figures 15 to 20 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0097] refer to Fig.15 and Fig.16 , first, you can execute the reference Figure 3 and Figure 4 The first semiconductor device 110 and the second semiconductor devices 120 a ′ and 120 b ′ are formed on the package substrate 100 by the same or similar processes as described.

[0098] In example embodiments, two second semiconductor devices 120 a ′, 120 b ′ may be disposed on the first semiconductor device 110 to be spaced apart from each other.

[0099] The second semiconductor devices 120a', 120b' may each include a buffer die 121a, and first to third memory dies 121b, 121c, 121d sequentially stacked on each other. The buffer die 121a and the first to third memory dies 121b, 121c, 121d may be electrically connected to each other through TSVs 125. The buffer die 121a and the first to third memory dies 121b, 121c, 121d may transmit data signals and control signals to each other through TSVs 125. The buffer die 121a may be electrically connected to the first semiconductor device 110 through a plurality of conductive bumps 123.

[0100] refer to Figures 17 to 19 , can be executed with reference Figure 5 and Figure 6 The process described is the same as or similar to the process, so that the heat dissipation insulation layer 130 is coated on the first semiconductor device 110 and the second semiconductor devices 120a', 120b', and the first conductive heat dissipation member 142' is formed on the heat dissipation insulation layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120a', 120b'.

[0101] In an example embodiment, if Fig.18 As shown in , a metal paste may be applied on the heat dissipation insulating layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120a', 120b' to form a conductive plate 142a. The conductive plate 142a may be formed on the heat dissipation insulating layer 130 on the first semiconductor device 110 to extend laterally and surround the second semiconductor devices 120a', 120b'.

[0102] The conductive plate 142a may be spaced apart from the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a', 120b'. Fig.18 As shown, the conductive plate 142 a may contact the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120 a ′, 120 b ′.

[0103] Then, if Fig.19 As shown, a metal paste may be applied on the conductive plate 142 a to form a conductive pillar 142 b .

[0104] The height to which the conductive pillar 142b extends relative to the package substrate 100 may be the same as the height of the second semiconductor devices 120a', 120b' relative to the package substrate 100. When the conductive pillar 142b extends in the vertical direction, the conductive pillar 142b may have a uniform width in the first horizontal direction. The conductive pillar 142b may be spaced apart from the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a', 120b'. Alternatively, the conductive pillar 142b may contact the heat dissipation insulating layer 130 on the sidewalls of the second semiconductor devices 120a', 120b'.

[0105] refer to Fig. 20 , a molding member 150 may be formed on the upper surface of the package substrate 100 to cover at least a portion of the first semiconductor device 110 and the second semiconductor device 120a', 120b'. The molding member 150 may be formed to expose the upper surface of the conductive pillar 142b, for example, to the outside of the semiconductor package. The molding member 150 may fill the space between the second semiconductor devices 120a', 120b' and the first conductive heat dissipation member 140'.

[0106] Then, external connection terminals 104 may be formed on the external connection pads on the lower surface of the package substrate 100 to complete the semiconductor package 13 .

[0107] Fig.21 1 is a cross-sectional view showing a semiconductor package according to an example embodiment. In addition to the conductive pillars, the semiconductor package may be similar to the reference Figure 1The semiconductor packages described are substantially the same or similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repeated descriptions on the above elements will be omitted.

[0108] refer to Fig.21 The first conductive heat dissipation member 142' of the semiconductor package 14 may include: a conductive plate 142a on the heat dissipation insulation layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120a', 120b', extending laterally and surrounding the second semiconductor devices 120a', 120b'; and at least one conductive column 142b extending from the conductive plate 142a in a vertical direction.

[0109] In example embodiments, the molding member 150 may have a through hole 151 formed therein to expose an upper surface of the conductive plate 142 a . The conductive pillar 142 b may be filled in the through hole 151 .

[0110] The width of the via hole 151 may gradually decrease toward a lower portion of the via hole 151. Therefore, the width of the conductive pillar 142b may gradually increase toward an upper portion of the via hole 151.

[0111] In the following, the manufacturing Fig.21 A method for semiconductor packaging.

[0112] Figure 22 to Figure 24 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0113] refer to Fig. 22 , first, you can execute the reference Figures 15 to 20 The process described above is the same as or similar to the process described above, so that the heat dissipation insulating layer 130 is coated on the first semiconductor device 110 and the second semiconductor device 120a', 120b' on the package substrate 100, and the conductive plate 142a is formed on the heat dissipation insulating layer 130 on the first semiconductor device exposed by the second semiconductor device 120a', 120b'. Then, the molding member 150 can be formed on the upper surface of the package substrate 100 to cover the first semiconductor device 110, the second semiconductor device 120a', 120b' and at least a portion of the conductive plate 142a. The molding member 150 can be formed to expose the upper surface of the heat dissipation insulating layer 130 on the second semiconductor device 120a', 120b'.

[0114] refer to Fig.23 and Fig.24 , the conductive pillar 142 b may be formed in the molding member 150 to extend from the conductive plate 142 a in a vertical direction.

[0115] First, the molding member 150 may be partially removed to form a through hole 151 exposing a portion of the upper surface of the conductive pillar 142b. For example, the through hole 151 may be formed by a laser drilling process.

[0116] Then, the through hole 151 of the molding member 150 may be filled with a conductive material to form a conductive column 142b in contact with the conductive plate 142a. The conductive material may be a metal paste including a metal material (e.g., gold (Au), silver (Ag), copper (Cu), etc.). The conductive column 142b may be formed so that the upper surface of the conductive column 142b is exposed from the molding member 150. The upper surface of the conductive column 142b may be coplanar with the top surface of the molding member 150.

[0117] Fig.25 is a cross-sectional view showing a semiconductor package according to an example embodiment. In addition to the first conductive heat dissipation member, the semiconductor package may be similar to the reference Fig.13 The semiconductor packages described are substantially the same or similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repeated descriptions on the above elements will be omitted.

[0118] refer to Fig.25 The semiconductor package 15 may include a first conductive heat dissipation member 142 ″ on the heat dissipation insulation layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120 a ′, 120 b ′. The first conductive heat dissipation member 130 may be arranged to surround the second semiconductor devices 120 a ′, 120 b ′. The first conductive heat dissipation member 142 ″ may contact the heat dissipation insulation layer 130 on the sidewalls of the second semiconductor devices 120 a ′, 120 b ′.

[0119] In an example embodiment, the upper surface of the packaging substrate 100 exposed through the first semiconductor device 110 may be coated with the heat dissipation insulation layer 130. The first conductive heat dissipation member 142" may be arranged on the heat dissipation insulation layer 130 on the packaging substrate 100 exposed through the first semiconductor device 110. The first conductive heat dissipation member 142" may partially cover the entire exposed surface of the packaging substrate 100. For example, the outer peripheral surface of the packaging substrate 100 may not be covered by the first conductive heat dissipation member 142".

[0120] In the following, the manufacturing Fig.25 A method for semiconductor packaging.

[0121] Fig.26 and Fig. 27 is a cross-sectional view illustrating a method of manufacturing a semiconductor package according to example embodiments.

[0122] refer to Fig.26 , first, you can execute the reference Figures 15 to 17 The process is the same as or similar to the process described above, so that the heat dissipation insulation layer 130 is coated on the first semiconductor device 110 and the second semiconductor devices 120a', 120b' on the packaging substrate 100. Then, the first conductive heat dissipation member 142" can be formed on the heat dissipation insulation layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120a', 120b'.

[0123] The first conductive heat dissipation member 142" may be arranged on the heat dissipation insulation layer 130 on the packaging substrate 100 exposed through the first semiconductor device 110. The first conductive heat dissipation member 142" may be formed to partially cover the entire exposed surface of the packaging substrate 100. For example, the outer peripheral surface of the packaging substrate 100 may not be covered by the first conductive heat dissipation member 142".

[0124] refer to Fig. 27 The molding member 150 may be formed on the upper surface of the package substrate 100 to cover at least a portion of the first semiconductor device 110 and the second semiconductor device 120a', 120b'. The molding member 150 may be formed on the heat dissipation insulating layer 130 on the package substrate 100 exposed by the first conductive heat dissipation member 142".

[0125] Fig.28 is a cross-sectional view showing a semiconductor package according to an example embodiment. In addition to the additional third conductive heat dissipation member, the semiconductor package can be similar to the reference Fig.13 The semiconductor packages described are substantially the same or similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repeated descriptions on the above elements will be omitted.

[0126] refer to Fig.28 The semiconductor package 16 may further include a third heat dissipation member 144 disposed on the heat dissipation insulation layer 130 on the package substrate 100 .

[0127] In example embodiments, the upper surface of the package substrate 100 exposed through the first semiconductor device 110 may be coated with the heat dissipation insulation layer 130. The third conductive heat dissipation member 144 may be disposed on the heat dissipation insulation layer 130 on the package substrate 100 exposed through the first semiconductor device 110.

[0128] The third conductive heat dissipation member 144 may be formed together when the conductive pillars 142b of the first conductive heat dissipation member 142' are formed. For example, a metal paste may be applied on the heat dissipation insulating layer 130 on the package substrate 100 exposed by the first semiconductor device 110 to form the third conductive heat dissipation member 144. The height to which the third conductive heat dissipation member 144 extends relative to the package substrate 100 may be the same as the height to which the second semiconductor devices 120a', 120b' and the conductive pillars 142b extend relative to the package substrate 100.

[0129] The molding member 150 may be formed to expose upper surfaces of the conductive pillar 142b and the third conductive heat dissipation member 144. The molding member 150 may fill spaces between the second semiconductor devices 120a', 120b', the first conductive heat dissipation member 142', and the third conductive heat dissipation member 144.

[0130] Fig.29 1 is a cross-sectional view showing a semiconductor package according to an example embodiment. In addition to the first conductive heat dissipation member and the third conductive heat dissipation member, the semiconductor package may be similar to the reference Fig.13 The semiconductor packages described are substantially the same or similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repeated descriptions on the above elements will be omitted.

[0131] refer to Fig.29 The semiconductor package 17 may include: a first conductive heat dissipation member 142 ″′, which is arranged on the heat dissipation insulation layer 130 on the first semiconductor device 110 exposed by the second semiconductor devices 120 a ′, 120 b ′; and a third conductive heat dissipation member 144, which is arranged on the heat dissipation insulation layer 130 on the package substrate 100.

[0132] The first conductive heat dissipation member 142'' may include: a first semiconductor device 110 and a conductive plate 142c on the heat dissipation insulation layer 130 on the packaging substrate 100 exposed through the first semiconductor device 110, extending laterally; and a conductive column 142b extending in a vertical direction from the conductive plate 142c on the first semiconductor device 110 exposed through the second semiconductor devices 120a', 120b'.

[0133] The third conductive heat dissipation member 144 may extend in a vertical direction from the conductive plate 142 c on the package substrate 100 exposed through the first semiconductor device 110 .

[0134] The third conductive heat dissipation member 144 may be formed together when the conductive pillar 142b of the first conductive heat dissipation member 142″′ is formed. For example, a metal paste may be applied on the heat dissipation insulation layer 130 on the package substrate 100 exposed by the first semiconductor device 110 to form the third conductive heat dissipation member 144. The height to which the third conductive heat dissipation member 144 extends relative to the package substrate 100 may be the same as the height to which the second semiconductor devices 120a′, 120b′ and the conductive pillar 142b extend relative to the package substrate 100.

[0135] The molding member 150 may be formed to expose upper surfaces of the conductive pillar 142 b and the third conductive heat dissipation member 144 . The molding member 150 may fill spaces between the second semiconductor devices 120 a ′, 120 b ′, the first conductive heat dissipation member 142 ′″, and the third conductive heat dissipation member 144 .

[0136] Fig.30 is a cross-sectional view showing a semiconductor package according to an example embodiment. In addition to the additional ground line connected to the first conductive heat dissipation member, the semiconductor package can be connected to the reference Fig.25 The semiconductor packages described are substantially the same or similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repeated descriptions on the above elements will be omitted.

[0137] refer to Fig.30 , the package substrate 100 of the semiconductor package 18 may include a ground line 116 electrically connected to the first conductive heat dissipation member 142 ″.

[0138] In example embodiments, a first conductive heat dissipation member 142" may be disposed on the heat dissipation insulation layer 130 on the package substrate 100 exposed by the first semiconductor device 110. The ground line 116 may be electrically connected to the first conductive heat dissipation member 142" on the package substrate 100 so that the first conductive heat dissipation member 142" is grounded.

[0139] Fig.31 is a cross-sectional view showing a semiconductor package according to an example embodiment. In addition to the addition of a heat sink, the semiconductor package can be similar to the reference Fig.25 The semiconductor packages described are substantially the same or similar. Therefore, the same reference numerals will be used to refer to the same or similar elements, and any further repeated descriptions on the above elements will be omitted.

[0140] refer to Fig.31 The semiconductor package 19 may further include a heat sink 160 covering the first conductive heat dissipation member 142 ″. The heat sink 160 may include a conductive adhesive layer 162 and a heat dissipation plate 164 .

[0141] The heat sink 160 may be thermally connected to the first conductive heat dissipation member 142 ″ exposed through the molding member 150 . The heat sink 160 may have a planar area corresponding to the package substrate 100 .

[0142] An electronic device including a semiconductor package according to an example embodiment may include a logic device (e.g., a central processing unit (CPU), a main processing unit (MPU), or an application processor (AP), etc.), and a volatile memory device (e.g., a DRAM device, an HBM device) or a non-volatile memory device (e.g., a flash memory device, a PRAM device, an MRAM device, a ReRAM device, etc.). The electronic device may be specifically implemented by a personal computer PC or a portable electronic device (e.g., a notebook computer, a cellular phone, a personal digital assistant (PDA), and a camera).

[0143] The foregoing is an illustration of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, it will be readily appreciated by those skilled in the art that various modifications may be made to the example embodiments without substantially departing from the novel teachings and advantages of the present invention. Therefore, all such modifications are intended to be included within the scope of the example embodiments as defined in the claims.

Claims

1. A semiconductor package, comprising: Package substrate; A first semiconductor device is arranged on the packaging substrate; at least one second semiconductor device on the first semiconductor device, partially covering the first semiconductor device when viewed from a top view; a heat dissipation insulating layer, coated on the first semiconductor device and the at least one second semiconductor device, the heat dissipation insulating layer being formed of an electrically insulating and thermally conductive material; a conductive heat dissipation structure, formed of an electrically conductive and thermally conductive material and comprising a first portion and a second portion, the first portion being arranged on the heat dissipation insulating layer on a portion of the first semiconductor device not covered by the at least one second semiconductor device, and the second portion being arranged on the heat dissipation insulating layer on the at least one second semiconductor device; as well as The molding layer on the packaging substrate covers the first semiconductor device and the at least one second semiconductor device, Wherein, the molding layer is not formed between the second portion of the conductive heat dissipation structure and the top surface of the at least one second semiconductor device.

2. The semiconductor package according to claim 1, wherein The first portion vertically overlaps the portion of the first semiconductor device; and The second portion vertically overlaps the heat dissipation insulating layer on the at least one second semiconductor device.

3. The semiconductor package according to claim 1, wherein: The first portion of the conductive heat dissipation structure is integrally formed with the second portion of the conductive heat dissipation structure.

4. The semiconductor package according to claim 1, wherein: The height to which the second portion of the conductive heat dissipation structure extends is the same as the height to which the first portion of the conductive heat dissipation structure extends.

5. The semiconductor package according to claim 1, wherein An upper surface of the conductive heat dissipation structure is exposed through the molding layer.

6. The semiconductor package according to claim 1, wherein Each of the at least one second semiconductor device is electrically connected to the package substrate through a bonding wire.

7. The semiconductor package according to claim 6, wherein: The heat dissipation insulating layer covers the bonding wire.

8. The semiconductor package according to claim 7, wherein: The second portion of the conductive heat dissipation structure covers a portion of the bonding wire.

9. The semiconductor package according to claim 1, further comprising: A heat sink covers the conductive heat dissipation structure.

10. The semiconductor package according to claim 1, wherein The heat dissipation insulation layer is conformally formed on top surfaces of the first semiconductor device and the at least one second semiconductor device, and on side surfaces of the at least one second semiconductor device.

11. The semiconductor package according to claim 1, wherein The heat dissipation insulating layer is formed of oxide, nitride or ceramic, and the conductive heat dissipation structure is formed of metal.

12. The semiconductor package according to claim 1, wherein The length of the conductive heat dissipation structure along the first horizontal direction is greater than the distance spanned by three adjacent pads formed on the packaging substrate.

13. The semiconductor package according to claim 1, wherein The conductive heat dissipation structure is electrically insulated from any circuit of the first semiconductor device, the at least one second semiconductor device and the packaging substrate, and does not transmit electrical signals to the first semiconductor device, the at least one second semiconductor device or the packaging substrate, and does not receive electrical signals from the first semiconductor device, the at least one second semiconductor device or the packaging substrate.

14. The semiconductor package according to claim 1, wherein: The first semiconductor device is a logic chip, and each second semiconductor device is a memory device including one or more memory chips.

15. A semiconductor package, comprising: Package substrate; A first semiconductor device is arranged on the packaging substrate; at least one second semiconductor device on the first semiconductor device, partially covering the first semiconductor device when viewed from a top view; a heat dissipation insulating layer, coated on the first semiconductor device and the at least one second semiconductor device, the heat dissipation insulating layer being formed of an electrically insulating and thermally conductive material; a conductive heat dissipation structure, arranged on the heat dissipation insulating layer on a portion of the first semiconductor device not covered by the at least one second semiconductor device, the conductive heat dissipation structure being formed of a conductive and thermally conductive material and comprising a conductive plate and at least one first conductive column on the heat dissipation insulating layer, the conductive plate extending laterally and surrounding each of the at least one second semiconductor device, the at least one first conductive column extending from the conductive plate in a vertical direction; as well as The molding layer on the packaging substrate covers the first semiconductor device and the at least one second semiconductor device.

16. The semiconductor package according to claim 15, wherein: The width of the first conductive pillar gradually increases toward an upper portion of the first conductive pillar.

17. The semiconductor package according to claim 15, wherein: The first conductive pillar has a uniform width along the vertical direction.

18. The semiconductor package according to claim 15, wherein: The upper surface of the packaging substrate is coated with the heat dissipation insulation layer.

19. The semiconductor package according to claim 15, wherein: The upper surface of the packaging substrate is coated with the heat dissipation insulating layer, and the conductive plate is arranged on the heat dissipation insulating layer on the packaging substrate, and Wherein, the conductive heat dissipation structure further includes at least one second conductive column, and the at least one second conductive column extends from the conductive plate on the packaging substrate along a vertical direction.

20. The semiconductor package according to claim 19, wherein The packaging substrate includes a ground line electrically connected to the conductive heat dissipation structure.

21. The semiconductor package according to claim 15, further comprising: A heat sink covers the conductive heat dissipation structure.

22. The semiconductor package according to claim 15, wherein The heat dissipation insulation layer is conformally formed on top surfaces of the first semiconductor device and the at least one second semiconductor device, and on side surfaces of the at least one second semiconductor device.

23. The semiconductor package according to claim 15, wherein The heat dissipation insulating layer is formed of oxide, nitride or ceramic, and the conductive heat dissipation structure is formed of metal.

24. The semiconductor package according to claim 15, wherein The length of the conductive heat dissipation structure along the first horizontal direction is greater than the distance spanned by three adjacent pads formed on the packaging substrate.

25. The semiconductor package according to claim 15, wherein The conductive heat dissipation structure is electrically insulated from any circuit of the first semiconductor device, the at least one second semiconductor device and the packaging substrate, and does not transmit electrical signals to the first semiconductor device, the at least one second semiconductor device or the packaging substrate, and does not receive electrical signals from the first semiconductor device, the at least one second semiconductor device or the packaging substrate.

26. The semiconductor package according to claim 15, wherein The first semiconductor device is a logic chip, and each second semiconductor device is a memory device including one or more memory chips.

27. An electronic device comprising: substrate; A first electronic product, arranged on the substrate; at least one second electronic product on the first electronic product, partially covering the first electronic product when viewed from a top view; a heat dissipation insulating layer, coated at least on the top surfaces of the substrate, the first electronic product and the second electronic product, the heat dissipation insulating layer being formed of an electrically insulating and thermally conductive material; a first conductive heat dissipation member disposed on the heat dissipation insulating layer on a portion of the first electronic product not covered by the second electronic product, the first conductive heat dissipation member being formed of an electrically conductive and thermally conductive material; a second conductive heat dissipation member, arranged on the heat dissipation insulation layer on the second electronic product; as well as The molding member on the substrate covers the first electronic product and the second electronic product, wherein the molding member is not formed between the second conductive heat dissipation member and the top surface of the at least one second electronic product.

28. The electronic device according to claim 27, wherein: The first electronic product consumes a first power, and the second electronic product consumes a second power that is smaller than the first power.

29. The electronic device according to claim 27, wherein: An upper surface of the first conductive heat dissipation member is exposed through the molding member.

30. The electronic device according to claim 27, wherein: The second electronic product is electrically connected to the substrate via bonding wires.

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