Transmitter with power supply rejection

Abstract

An apparatus is described that includes a driver including a push-pull transmitter; a first circuit for sensing a change in a power supply; and a second circuit coupled to the first circuit and to the driver, the second circuit for generating a code based on an output of the first circuit, wherein the code is provided to the driver to adjust a performance parameter of the driver.

Description

[0001] Priority claim

[0002] This application claims priority to U.S. Patent Application No. 15 / 721,535, filed on September 29, 2017, entitled “TRANSMITTER WITH POWER SUPPLY REJECTION,” which is incorporated by reference in its entirety. Background Art

[0003] Current-mode transmitters are generally less sensitive to power supply and process variations. However, current-mode transmitters consume higher power than voltage-mode transmitters. When compared to current-mode transmitters, voltage-mode transmitters are attractive due to their simplicity and lower power consumption. However, typical voltage-mode transmitters suffer from power supply variations that directly affect the transmitter's output voltage swing and timing margin. When voltage-mode transmitters are used for high-speed operation (e.g., transmitters for high-speed Universal Serial Bus 2 (USB2) compatibility, but not limited to, USB3, Peripheral Component Interconnect Express (PCIe), and These challenges are exacerbated when other protocols such as PHY are used. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The embodiments of the present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the present disclosure, which, however, should not be construed as limiting the present disclosure to specific embodiments but are only for explanation and understanding.

[0005] Figure 1 The figure shows a system showing a push-pull driver and receiver.

[0006] Figure 2 The figure shows a drawing showing an eye diagram at a connector of a system.

[0007] Figure 3 The diagram illustrates an apparatus for adjusting the voltage swing of a push-pull driver based on noise on a power supply according to some embodiments of the present disclosure.

[0008] Figure 4 The diagram shows some embodiments according to the present disclosure Figure 3 Schematic view of the device.

[0009] Figure 5 The diagram shows some embodiments according to the present disclosure Figure 3 The calibration logic of the device.

[0010] Figure 6 FIG. 1 illustrates a schematic diagram of a push-pull driver with adjustable voltage swing according to some embodiments of the present disclosure.

[0011] Figure 7 The diagram shows some embodiments according to the present disclosure Figure 3 Timing diagram of the calibration logic of the device.

[0012] Figure 8 FIGURE 1 illustrates a flow chart of a method of calibrating a push-pull driver according to some embodiments of the present disclosure.

[0013] Figure 9 The diagram illustrates a smart device or computer system or system on a chip (SoC) with a push-pull driver having an adjustable voltage swing, according to some embodiments. DETAILED DESCRIPTION

[0014] Some embodiments describe an apparatus for calibrating a driver (e.g., a transmitter) based on power supply noise or variation. In some embodiments, a sensing circuit is used to sense the power supply noise or variation. For example, a filtered power supply is used to power a ring oscillator, and the frequency of the ring oscillator represents the sensed power supply noise. As the noise on the sensed power supply varies, the frequency of the output clock from the ring oscillator also varies. In some embodiments, the clock from the oscillator is compared to a reference clean clock, and a determination is made as to whether the clock is faster or slower than the reference clock. In some embodiments, based on this determination, a digital code is generated for adjusting a performance parameter of the driver output. An example of a performance parameter is the voltage swing at the output of the driver. In some embodiments, a lookup table (LUT) is used to provide a target reference code across process variations. The LUT is useful in determining whether a process band design is at typical, fast, or slow speed.

[0015] There are many technical effects in each embodiment. For example, the power consumption of the driver architecture is reduced because the pre-emphasis circuit can be eliminated. In one example, the power can be reduced by approximately 2mW (milliwatts) to 4mW for each driver, resulting in a saving of approximately 50% of the driver power. The apparatus of each embodiment is mainly a digital solution, which is less sensitive to power supply variations and is easily scalable to newer process technology nodes. In some embodiments, the voltage swing at the output of the driver is adjusted by adjusting the reference current to a desired value without affecting the transmitter output terminal impedance. The apparatus of each embodiment is a universal design that can be used for other high-speed transmitters and other power-sensitive circuits. For example, the digital code generated by the calibration circuit can be used to adjust parameters instead of voltage swing. Other technical effects will be apparent from the embodiments and the accompanying drawings.

[0016] In the following description, numerous details are discussed to provide a more thorough explanation of the embodiments of the present disclosure. However, it will be apparent to those skilled in the art that the embodiments of the present disclosure can be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring the embodiments of the present disclosure.

[0017] Note that in the corresponding figures of the embodiments, signals are represented by lines. Some lines may be thicker to indicate more component signal paths and / or have arrows at one or more ends to indicate the primary direction of information flow. Such indications are not intended to be limiting. Rather, lines may be used in conjunction with one or more exemplary embodiments to facilitate easier understanding of circuits or logic units. As dictated by design needs or preferences, any represented signal may actually include one or more signals that can travel in either direction and may be implemented using any suitable type of signaling scheme.

[0018] Throughout the specification and in the claims, the term "connected" means a direct connection, such as an electrical, mechanical, or magnetic connection, between the things being connected without any intervening devices. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things being connected or an indirect connection through one or more passive or active intervening devices.

[0019] The term "circuit" or "module" may refer to one or more passive and / or active components arranged to cooperate with each other to provide a desired function. The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a / an" and "the" include plural references. The meaning of "in..." includes "in" and "on."

[0020] The term "scaling" generally refers to converting a design (schematic and layout) from one process technology to another and subsequently reducing it in layout area. The term "scaling" also generally refers to reducing layout and device size within the same technology node. The term "scaling" can also refer to adjusting the frequency of a signal relative to another parameter (e.g., power supply level) (e.g., slowing down or speeding up - i.e., shrinking or amplifying, respectively). The term "scaling" can also refer to adjusting the magnitude of the power supply voltage to a circuit(s) (e.g., voltage scaling).

[0021] The terms "substantially," "close," "approximately," "near," and "about" generally refer to within + / - 10% of a target value. Unless otherwise specified, the use of ordinal numbers "first," "second," and "third" in descriptions of common objects merely indicates that different instances of the same object are being referenced and is not intended to imply that the objects so described must be in a given order in terms of ranking or in any other manner, whether in time or space.

[0022] It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are capable of operation in other orientations than those illustrated or otherwise described herein.

[0023] For the purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B), or (A and B). For the purposes of this disclosure, the phrases "A, B, and / or C" mean (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). In the specification and claims, the terms "left," "right," "front," "back," "top," "bottom," "upper," "lower," and the like, if they appear, are used for descriptive purposes and are not necessarily intended to describe permanent relative positions.

[0024] For the purposes of the embodiments, the transistors in the various circuits, modules and logic blocks may be tunneling FETs (TFETs), or some transistors of the various embodiments may include metal oxide semiconductor (MOS) transistors, which include drain, source, gate and body terminals. Transistors may also include tri-gate transistors and FinFET transistors, gate-all-around cylindrical transistors, square wire or rectangular ribbon transistors, or other devices that implement transistor functions, such as carbon nanotubes or spintronic devices. MOSFETs have symmetrical source and drain terminals, i.e., they are identical terminals and are used interchangeably herein. On the other hand, TFET devices have asymmetric source and drain terminals. Those skilled in the art will appreciate that other transistors (e.g., bipolar junction transistors - BJT PNP / NPN, BiCMOS, CMOS, etc.) may be used for some transistors without departing from the scope of this disclosure.

[0025] Figure 1 The figure shows a system 100 showing a push-pull driver and a receiver. The system 100 includes a plurality of push-pull drivers 101 i-n, where 'n' is an integer. The push-pull driver (e.g., 1011) consists of a p-type pull-up device MPd coupled in series with an n-type pull-down device MNd. Input data DataIn (or DIN) is received at the gates of the p-type pull-up device MPd and the n-type pull-down device MNd. The push-pull driver operates at a first power supply (e.g., VCC1p0 indicates a 1.0V power supply). The output of the push-pull driver is coupled to a pass transistor Mdac, which is connected in series with a resistor R. Mdac can operate at a higher power supply (e.g., VCC1p8 indicates a 1.8V power supply) to control how many devices of Mdac need to be turned on. One push-pull driver can generate a first output DP, and the other push-pull driver can generate another output DP, and thereby a differential output can be obtained. These outputs are transmitted via a transmission line 102 by a receiver 103 (here modeled as a pull-down terminal R T )take over.

[0026] The use of a voltage-mode transmitter (e.g., push-pull driver 1011) comes at the cost of wider power supply variations. Power supply variations directly affect the voltage swing Vsw of the signal at the connector (e.g., the output of push-pull driver 1011 connected to transmission line 102). The voltage swing can be expressed as:

[0027] Vsw=VDD*R T / (R T + R PU ) . . . (1)

[0028] Where VDD is the power supply (for example, VCC1p0), R T is the receiver terminal, and R PU is the pull-up impedance.

[0029] Generally speaking, the pull-up impedance R PU and the pull-down resistor R PD The impedance compensation (RCOMP) circuit (not shown) is used for calibration. However, the reference voltage used for such calibration is also derived from the power supply, which is subject to power supply variations. Using a bandgap reference for such calibration would increase the power and area costs of the entire driver architecture.

[0030] Figure 2The figure shows a plot 200 illustrating an eye diagram at a connector of a system. Here, the x-axis is time (ns) and the y-axis is voltage (V). The eye is indicated by indicator 201, while levels 202 and 203 illustrate the upper and lower limits of the voltage swing. Plot 200 shows an eye diagram formed across multiple process corner nodes. Due to power supply variations, the voltage swing changes and more of the area of eye 201 can be used, which can lead to timing and other specification failures. The small eye opening of eye 201 means that additional circuitry along the pull-up and pull-down impedance paths can further reduce the headroom, which in turn reduces the eye height and width. One way to improve eye height and width is to use pre-emphasis circuitry. However, pre-emphasis circuitry adds power to the driver architecture (e.g., 4mW to 8mW).

[0031] Figure 3 The figure shows an apparatus 300 for adjusting the voltage swing of a push-pull driver based on noise (DC or AC) on a power supply according to some embodiments of the present disclosure. In some embodiments, the apparatus 300 includes a low-pass filter (LPF) 301, a power sensing block or circuit 302, calibration logic or circuit 303, and a high-speed driver (pull-up / pull-down branch) 304.

[0032] In some embodiments, LPF 301 is coupled to a first power supply (e.g., VCC_1p0, which refers to a 1.0V power supply) and is used to detect DC (direct current) variations in the first power supply. The output of LPF 301 is VCC_Sense, a filtered version of the first power supply. In this example, the cutoff frequency of the LPF is less than 10 MHz and can be fixed or programmable. In some embodiments, LPF 301 is removed to sense AC (alternating current) variations in the first power supply. In one such embodiment, the first power supply is directly coupled to power sensing block 302.

[0033] In some embodiments, the power supply sense block 302 senses the filtered (or in one case, unfiltered) VCC_Sense and converts the voltage of the power supply into the digital domain. For example, a clock (Sense_out) may be generated whose frequency changes represent changes in VCC_Sense. Thus, noise or variations in VCC_Sense are captured as changes in the clock frequency. In some embodiments, the power supply sense block 302 includes a ring oscillator that includes delay stages that substantially mimic the push-pull driver architecture of the driver 304. For example, most of the driver architecture is minus the current mirror circuit (see later). Figure 4 discussed) is used as a delay stage in a ring oscillator. Return to Reference Figure 3The output of the power sense block 302 is Sense_out, which is compared with a reference clock (Ref_Clock) in the calibration logic 303. In some embodiments, Ref_Clock is a clean clock that can be provided by a crystal oscillator.

[0034] In some embodiments, calibration logic 303 is used to adjust the reference digital code based on the LUT and the compensation code. In some embodiments, the compensation code is an impedance compensation code for adjusting the (pull-up and / or pull-down) impedance of driver 304. The impedance compensation code can be generated by an impedance compensation circuit (also referred to as RCOMP) that adjusts the impedance of the replica driver against a reference or target impedance, and once the impedance of the replica driver is adjusted for process, temperature, and voltage (PVT) variations, it can be provided to driver 304 as an impedance compensation code and also stored in the LUT.

[0035] In some embodiments, the calibration logic 303 generates the frequency (F 感测 (F Sense )) and Ref_Clock(F 参考 (F reference ))'s frequency-time domain ratio N 传感器 (N Sensor ). The time domain is N 传感器 Indicates the change in power supply VCC_Sense relative to the reference.

[0036] F 感测 (V)=1 / 6*(0.69*(Reff*Cg)

[0037] Where Reff is the effective pull-up or pull-down impedance of the replica driver used in the ring oscillator topology in the power sensing block 302 and can be expressed as R CPR +R Tran +R 发射器 (R transmitter ), and where Cg is the input capacitance of the replica driver. As described later, R CPR For the push-pull replica driver’s pull-up or pull-down resistor, R Tran (R 传输 ) is the resistance of the pass gate coupled to the output of the driver's pull-up and pull-down devices, and R 发射器 is the resistance of the resistor coupled in series with the pass gate.

[0038] In some embodiments, the calibration logic 303 generates a digital code N REF (N 参考 ), the digital code N REF With N 传感器In some embodiments, based on the comparison, the calibration logic 303 determines whether the driver needs to be calibrated. For example, when N 传感器 Higher than N REF When a certain amount (eg, predetermined or programmable) is reached, the calibration logic 303 determines that calibration is required and CalibEN (calibration enable) is enabled. In some embodiments, the certain amount is frequency band specific and is stored in a LUT.

[0039] For example, different threshold levels for specific quantities are used for different frequency bands. In some embodiments, when calibration is required, the calibration logic 303 generates a CalibUpdate signal and a digital code VswAdjust (Vsw adjustment) (e.g., 5 bits, [4:0]) to adjust the reference current of the current source of the driver 304. In some embodiments, by adjusting the current intensity of the current source, the output voltage swing of the signal generated by the driver 304 is adjusted to a desired or target level. In some embodiments, the adjustment of the reference current does not change the terminal impedance of the driver 304. In some embodiments, a finite state machine (FSM) is used to control the operation of the calibration logic 303. In some embodiments, the FSM operates after the FSM of the RCOMP circuit generates the impedance compensation code.

[0040] In some embodiments, driver 304 is an enhanced version of driver 101. In some embodiments, driver 304 includes a push-pull circuit having transistors MPd, MNd, and Mdac. In some embodiments, a current mirror network is added to the output of driver 304 to increase or decrease the strength of the signal driven by driver 304 without affecting its terminal impedance. In some embodiments, the strength of the reference current source of the current mirror is adjusted by a digital code VswAdjust from calibration logic 303 and is applied to the current source when CalibUpdate is enabled or asserted. In some embodiments, the current mirror network operates at a higher power supply than the power supply of the push-pull circuit of driver 304. For example, the current mirror network operates at a 1.8V power supply. In some embodiments, the current mirror network operates at a lower power supply (e.g., a 1.0V power supply).

[0041] Figure 4 The diagram shows some embodiments according to the present disclosure Figure 3 Schematic view 400 of an apparatus. It is noted that Figure 4 Those elements in the drawings that have the same reference numbers (or names) as elements in any other figure can operate or function in any manner similar to that described, but are not limited thereto.

[0042] In some embodiments, power sense block 302 includes delay stages (e.g., 402a, 402b, 402c) configured to form a ring oscillator. In some embodiments, each delay stage is a replica of driver 404a. For example, delay stage 402a includes a pull-up transistor with an impedance Reffp, a pull-down transistor with an impedance Reffn, a pass-gate transistor with an impedance Rtran, and a series termination resistor (or package resistor) R coupled together as shown. In some embodiments, VCC_Sense is coupled to the Vcc1p0 node of delay stages 402a-c. In some embodiments, the Vcc1p8 node is coupled to a fixed power supply level of 1.8V. Node names and signal names are used interchangeably herein. For example, Vcc1p8 may refer to node Vcc1p8 or the power supply Vcc1p8 at that node. The output clock Clock_out has a frequency that is a function of the power supply and process. The architecture of the delay stages is such that they have low sensitivity to temperature.

[0043] In some embodiments, the ring oscillator of the power sense block 302 is gated by the CalibEn signal. For example, when calibration is enabled (e.g., when CalibEn is high), the power sense block 302 is activated, which allows sensing of VCC_Sense in the form of an oscillating clock Clock_out. Similarly, when calibration is disabled (e.g., when CalibEn is low), the power sense block 302 is deactivated and Clock_out no longer oscillates.

[0044] Although the embodiment illustrates a ring oscillator having three delay stages 402a, 402b, and 402c, other numbers of stages may be used. For example, three or five delay stages may be used and coupled together in a ring.

[0045] In some embodiments, calibration logic 303 includes a comparator 403a, a filter 403b, decision-making logic 403c, and a LUT 403d. In some embodiments, comparator 403a includes a first input terminal for receiving Clock_out and a second input terminal for receiving a reference clock (Ref Clock). In some embodiments, comparator 403a is a clocked comparator. In some embodiments, the output of comparator 403a is filtered by filter 403b. In some embodiments, the output of comparator 403a is the ratio of Clock_out relative to the reference clock (Ref Clock). By comparing Clock_out with an ideal or nearly ideal reference clock (Ref Clock), a change in power supply VCC_1p0 is determined. In some embodiments, filter 403a is a digital filter. For example, filter 403a is a shift register chain. In some embodiments, filter 403a is an analog filter.

[0046] In some embodiments, the output of filter 403b is processed by decision making logic 403c. The output of decision making logic 403c includes a calibration enable signal (CalibEN), a calibration update signal (CalibUpdate), and a voltage swing adjustment code (VswAdjust). In some embodiments, decision making logic 403c is implemented as a finite state machine (FSM). In some embodiments, the FSM is similar to the reference signal. Figure 5 The described impedance controlled state machines operate in combination.

[0047] Return Reference Figure 4 In some embodiments, driver 304 includes multiple push-pull circuits. To avoid obscuring the embodiments, the architecture of one push-pull circuit 404a is described. In some embodiments, push-pull circuit 404a is similar to 1011. In some embodiments, push-pull circuit 404a includes a pull-up p-type transistor MPd, a pull-down n-type transistor MNd, a programmable pass device Mdac (e.g., an n-type device controlled by a 5-bit digital-to-analog control bit), a package or driver series resistor R (e.g., 45 ohms), and a current mirror circuit 404b. In some embodiments, each push-pull circuit has a corresponding current mirror circuit 404b. In some embodiments, multiple push-pull circuits share the same current mirror circuit 404b. For example, a number 'n' of adjacent push-pull circuits can share the same current mirror circuit 404b.

[0048] In some embodiments, current mirror circuit 404b includes a first reference current source Is1, a second reference current source Is2, and a current mirror device MPcm coupled together as shown. In some embodiments, first reference current source Is1 mirrors current Is2 by a certain factor (e.g., a factor of 1 or more). For example, first reference current source Is1 is a p-type transistor having its gate terminal coupled to the gate terminal of transistor MPcm, its source terminal coupled to Vcc1p8, and its drain terminal coupled to output node DP / DM. Embodiments are not limited to this particular current mirror circuit, and other such circuits that can have variable current strength using digital code may also be used.

[0049] In some embodiments, based on the comparison of the clocks performed by the calibration logic, Is2 is adjusted to adjust the output swing on the node DP / DM. Thus, the transmitter impedance change remains unchanged. The adjustment of the voltage swing on DP / DM can be expressed as:

[0050] Vsw(DP / DM)=Vcc1p0*R T / (R T +R PU )+Is2[4:0]*(R T \\(R Pu (or R PD )));

[0051] Where Is2 is the current digitally adjusted by VswAdjust (which has 5 bits in this example), where R T is the receiver terminal impedance, R PU is the pull-up impedance of driver 404a, and R PD is the pull-down impedance of driver 404a.

[0052] In some embodiments, calibration logic 303 compares Clock_out with a reference clock (Ref Clock) to generate a reference code based on a predetermined target reference count or a target reference count stored in LUT 403d. For example, LUT 403d may have different count values for different frequency bands. Depending on the frequency of Clock_out within the reference clock (Ref Clock) cycle, a specific count value is assigned. According to some embodiments, the count value is then used to generate a code filtered by filter 403b. Decision making logic 403c then uses the output of filter 403b to generate a VswAdjust code for adjusting the reference current Is2 of driver 304. By digitally adjusting the reference current Is2, the voltage swing of the signal on node DP / DM is adjusted.

[0053] Although the various embodiments illustrate the use of a push-pull transmitter architecture, the embodiments are not limited thereto. For example, the various embodiments are also applicable to cases where both the push-up device and the pull-down device are only n-type devices or only p-type devices. In those cases, the duplicate branches will have similar architectures.

[0054] Figure 5 The diagram shows some embodiments according to the present disclosure Figure 3 The calibration logic 500 (eg, 303) of the device is noted. Figure 5 Those elements in the drawings that have the same reference numbers (or names) as elements in any other figure can operate or function in any manner similar to that described, but are not limited thereto.

[0055] Figure 5 The figure shows a functional schematic diagram of calibration logic 500, which includes a counter 501, a register 502 for storing a count value, a sequential device 503, logic 504 for comparing the count value with a reference count, and combinational logic 505. In some embodiments, counter 501 counts the number of pulses in Clock_out in a reference clock (Ref Clock) and stores the count in register 502.

[0056] Here, signal Upload (upload) is used to latch the final counter value for comparison during the lock time. For example, when Upload (Upload) is asserted, the final counter value is latched. The sampled clock is a sampling clock for sampling the counter value. This is a low-frequency clock and is used to latch the final value after the sampling window. This sampled value is used for comparison purposes. In some embodiments, the output of register 502 is sampled and count (Count) is compared with a reference count (Ref count). In some embodiments, Ref (reference) count is a fixed code (for example, an 8-bit count code) provided by Vref. In this example, Vref is a fixed digital code that acts as a reference voltage in the digital domain. Thus, compared to traditional analog signals, Vref is less susceptible to noise. This reference code is fixed and is a programmable code based on what value needs to be programmed. Those skilled in the art will appreciate that an analog signal is any continuous signal for which the time-varying characteristic (variable) of the signal is a representation of some other time-varying quantity, i.e., an analog of another time-varying signal, whereas a digital signal is a physical signal that is a representation (e.g., a representation of an arbitrary bit stream or a representation of a digitized (sampled and analog-to-digital converted)) of a series of discrete values (a quantized discrete-time signal).

[0057] Figure 6FIG. 6 illustrates a schematic diagram 600 (eg, 304) of a push-pull driver with adjustable voltage swing according to some embodiments of the present disclosure. Figure 6 Those elements in the drawings that have the same reference numbers (or names) as elements in any other figure can operate or function in any manner similar to that described, but are not limited thereto.

[0058] Here, a differential version of the driver 304 is shown, wherein the driver comprises a DP portion 601 for driving a first signal on a pad DP and a DM portion 602 for driving a second signal on a pad DM, wherein DM and DP together form a differential signal. Figure 4 , where in the case of driver 601, transistor M1 is identical to transistor MNd, transistor M2 is identical to transistor Mdac, and transistor M3 is identical to transistor MPd. Here, the input signal DIN (Din) is shown as two separate components, datap_pu (for pulling up transistor M3) and datap_pd (for pulling down transistor M1). Figure 4 , where in the case of driver 602, transistor M4 is identical to transistor MNd, transistor M5 is identical to transistor Mdac, and transistor M6 is identical to transistor MPd. Here, the input signal DIN (Din) is shown as two separate components, datam_pu (for pull-up transistor M6) and datam_pd (for pull-down transistor M4).

[0059] In some embodiments, current mirror circuit 404b includes a pair of differential current drivers as shown by circuit 603. In some embodiments, to provide additional pre-emphasis or pre-de-emphasis, transistors M9 and M10 are provided with their own separate current sources IREF_N. In some embodiments, current source Iref_N has an adjustable current intensity controlled by VswAdjust. In some embodiments, transistor M9 is controlled by D_preeadd, and transistor M10 is controlled by Db_preeadd (e.g., the inverse of D_preeadd). Here, D_preeadd and D_pree are signals generated by logic for enabling the current source just before data conversion. In some embodiments, D_preeadd is timed or synchronized with datap_pu, which is the actual transmitted data. In some embodiments, additional pre-emphasis or pre-de-emphasis is not used and is disabled or removed. For example, current source IREF_N, transistors M9 and M10 are removed.

[0060] In some embodiments, current source Iref_P has an adjustable current strength controlled by VswAdjust.In some embodiments, transistor M7 is controlled by D_pree, and transistor M8 is controlled by Db_pree (eg, the inverse of D_pree).

[0061] In one example, if the output swing at node DP or DM differs from the target voltage swing by 50mV, the output swing can be adjusted as follows:

[0062] When driving differential 1;

[0063] V DP =(Vcc1p0+50mV)*(R T / R T +R PU );

[0064] V DM =Iref_P*R T ||R PD ;

[0065] V SW =V DP -V DM ;

[0066] Among them, V DP is the voltage on node DP, V DM is the voltage on node DM, RT is the receiver termination impedance, and RPU is the pull-up impedance of driver 601. In this example, at node DM, a 50 mV shift in the output swing due to variations in Vcc1p0 is compensated by adjusting the current strength of Iref_P by VswAdjust (e.g., a 5-bit code that turns on or off the transistor when the current source generates Iref_P).

[0067] Similarly, when driving differential 0;

[0068] V DP =Iref_P*R T ||R PD ;

[0069] V DM =(Vcc1p0+50mV)*(R T / R T +R PU );

[0070] V SW =V DM -V DP ;

[0071] In this example, a 50mV shift in the output swing due to variations in Vcc1p0 on the DP node is compensated by adjusting the current strength of Iref_P by VswAdjust (eg, a 5-bit code that turns on or off the transistor when the current source generates Iref_P).

[0072] Figure 7 The diagram shows some embodiments according to the present disclosure Figure 3 The timing diagram 700 (eg, 403c) of the calibration logic of the device is shown. Figure 7 Those elements in the drawings that have the same reference numbers (or names) as elements in any other figure can operate or function in any manner similar to that described, but are not limited thereto.

[0073] In some embodiments, a counter (e.g., counter 501) counts the number of Clock_out (same as Vsense_clock) pulses in one clock cycle of the reference clock (Ref Clock) after which the lock and compare window signals are asserted. When the lock and compare window signals are asserted, the count value is compared with a reference count (e.g., Vref[5:0]) and a decision is made to update the calibration code (e.g., VswAdjust). On the subsequent falling edge of the reference clock (Ref Clock), a new VswAdjust code is provided, overwriting the old VswAdjust code.

[0074] Figure 8 FIGURE 800 illustrates a method of calibrating a push-pull driver according to some embodiments of the present disclosure. Figure 8 Those elements in the drawings that have the same reference numbers (or names) as elements in any other figure can operate or function in any manner similar to that described, but are not limited thereto.

[0075] Although the reference Figure 8 The blocks in the flowcharts of FIG. 5 are shown in a particular order, but the order of the actions may also be modified. Therefore, the illustrated embodiments can be performed in a different order, and some actions / blocks may be performed in parallel. According to some embodiments, Figure 8 Some of the blocks and / or operations listed in the flow diagram are optional. The numbering of the blocks presented is for clarity and is not intended to specify the order in which the blocks must operate. In addition, the operations from each flow diagram can be adopted in various combinations.

[0076] At block or operation 801, the Rcomp (impedance compensation) process begins and is allowed to complete. At block 802, a determination is made as to whether the Rcomp process is complete, and if so, the process proceeds to block 803. At block 803, CalibEn is asserted, enabling sensing of the power supply Vcc1p0 by the power sensing block 302. According to some embodiments, blocks 804 through 807 are performed by the calibration logic 303. At block 804, the calibration logic compares Clock_out with a reference clock. Here, Nsensor (NSensor) indicates the timer value of the Vcc sensing power supply block 303. At block 805, the calibration logic compares the number of Clock_out pulses (e.g., count value) with the mapping in LUT 403d and assigns a reference count number (NREF). NREF is then compared to the count value and a VswAdjust code is determined. At block 807, a determination is made as to whether Vsw adjustment is complete. For example, Vsw adjustment is considered complete when the Vswadjust code is applied to the current source. If not completed, the process proceeds to block 804 .

[0077] Figure 9 The figure shows a smart device or computer system or SoC (system on chip) with a push-pull driver having an adjustable voltage swing according to some embodiments. Figure 9 Those elements in the drawings that have the same reference numbers (or names) as elements in any other figure can operate or function in any manner similar to that described, but are not limited thereto.

[0078] Figure 9 The figure illustrates a block diagram of an embodiment of a mobile device in which a flat surface interface connector may be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smartphone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown schematically, and not all components of such a device are shown in computing device 1600.

[0079] According to some embodiments discussed, in some embodiments, computing device 1600 includes a first processor 1610 having one or more configurable interconnects. According to some embodiments, other blocks of computing device 1600 may also include one or more configurable interconnects. Embodiments of the present disclosure may also include a network interface (such as a wireless interface) within 1670 so that system embodiments can be incorporated into wireless devices (e.g., cellular phones or personal digital assistants).

[0080] In one embodiment, processor 1610 (and / or processor 1690) may include one or more physical devices, such as a microprocessor, an application processor, a microcontroller, a programmable logic device, or other processing means. Processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and / or device functions are executed. Processing operations include operations related to I / O (input / output) with a human user and / or with other devices, operations related to power management, and / or operations related to connecting computing device 1600 to another device. Processing operations may also include operations related to audio I / O and / or display I / O.

[0081] In one embodiment, computing device 1600 includes an audio subsystem 1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functionality to the computing device. Audio functionality may include speaker and / or headphone output and microphone input. According to some embodiments, in some embodiments, audio subsystem 1620 includes a device and / or machine executable instructions for avoiding self-listening. Equipment for such functionality may be integrated into computing device 1600 or connected to computing device 1600. In one embodiment, a user interacts with computing device 1600 by providing audio commands received and processed by processor 1610.

[0082] Display subsystem 1630 represents the hardware (e.g., display device) and software (e.g., driver) components that provide a visual and / or tactile display for a user to interact with computing device 1600. Display subsystem 1630 includes a display interface 1632, which includes a specific screen or hardware device for providing a display to the user. In one embodiment, display interface 1632 includes logic separate from processor 1610 for performing at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touchscreen (or touchpad) device that provides both output and input to the user.

[0083] I / O controller 1640 represents hardware devices and software components related to interaction with a user. I / O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and / or display subsystem 1630. In addition, I / O controller 1640 illustrates connection points for additional devices that connect to computing device 1600 through which a user can interact with the system. For example, devices that can be attached to computing device 1600 may include a microphone device, a speaker or stereo system, a video system or other display device, a keyboard or keypad device, or other I / O devices for use with specific applications (such as a card reader or other device).

[0084] As mentioned above, I / O controller 1640 can interact with audio subsystem 1620 and / or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of computing device 1600. In addition, audio output can be provided as an alternative to or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also serves as an input device that can be managed at least in part by I / O controller 1640. Additional buttons or switches can also be present on computing device 1600 to provide I / O functions managed by I / O controller 1640.

[0085] In one embodiment, I / O controller 1640 manages multiple devices, such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that may be included in computing device 1600. Input may be part of direct user interaction, as well as providing environmental input to the system to affect its operation (such as filtering noise, adjusting the display for brightness detection, applying a camera flash, or other features).

[0086] In one embodiment, computing device 1600 includes power management 1650, which manages battery power usage, charging of the battery, and features related to power-saving operations. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include non-volatile (state does not change if power to the memory device is interrupted) and / or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of applications and functions of computing device 1600.

[0087] Elements of the embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing computer-executable instructions (e.g., instructions for implementing any other process discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memories (PCMs), or other types of machine-readable media suitable for storing electronic instructions or computer-executable instructions. For example, embodiments of the present disclosure may be downloaded as a computer program (e.g., BIOS), which may be transmitted from a remote computer (e.g., a server) to a requesting computer (e.g., a client) via a communication link (e.g., a modem or a network connection) by means of a data signal.

[0088] Connectivity 1670 includes hardware devices (e.g., wireless and / or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) for enabling computing device 1600 to communicate with external devices. Computing device 1600 may be a separate device such as another computing device, a wireless access point or base station, as well as a peripheral device such as a head-mounted device, a printer, or other devices.

[0089] Connectivity 1670 can include a variety of different types of connectivity. For purposes of overview, computing device 1600 is illustrated as having cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 generally refers to cellular network connectivity provided by a wireless carrier, such as via GSM (Global System for Mobile Communications) or a variant or derivative thereof, CDMA (Code Division Multiple Access) or a variant or derivative thereof, TDM (Time Division Multiplexing) or a variant or derivative thereof, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular and can include personal area networks (such as Bluetooth, near field, etc.), local area networks (such as Wi-Fi) and / or wide area networks (such as WiMax) or other wireless communications.

[0090] Peripheral connections 1680 include hardware interfaces and connectors for making peripheral connections, as well as software components (e.g., drivers, protocol stacks). It will be understood that computing device 1600 can be a peripheral device connected to other computing devices ("to" 1682), and can also have peripheral devices connected to it ("from" 1684). Computing device 1600 typically has a purpose for connecting to other computing devices for purposes such as managing (e.g., downloading and / or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripheral devices that allow computing device 1600 to control content output, such as to audio-visual or other systems.

[0091] In addition to a dedicated docking connector or other dedicated connection hardware, the computing device 1600 can also establish peripheral connections 1680 via common or standards-based connectors. Common types may include a Universal Serial Bus (USB) connector (which may include any of several different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High-Definition Multimedia Interface (HDMI), FireWire, or other types.

[0092] References in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" mean that the particular features, structures, or characteristics described in conjunction with those embodiments are included in at least some of the embodiments, but not necessarily in all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" do not necessarily refer to the same embodiment. If the specification states that a component, feature, structure, or characteristic "may," "could," or "can" be included, that particular component, feature, structure, or characteristic is not necessarily included. If the specification or claims refer to "a" or "an" element, it does not mean that there is only one of that element. If the specification or claims refer to "an additional" element, it does not exclude the presence of more than one of that additional element.

[0093] In addition, the specific features, structures, functions or characteristics can be combined in any suitable manner in one or more embodiments. For example, the first embodiment can be combined with the second embodiment as long as the specific features, structures, functions or characteristics associated with the first embodiment and the second embodiment are not mutually exclusive.

[0094] Although the present disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications, and variations of such embodiments will be apparent to those skilled in the art in light of the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may utilize the embodiments discussed. The embodiments of the present disclosure are intended to encompass all such alternatives, modifications, and variations that fall within the broad scope of the appended claims.

[0095] In addition, for the sake of simplicity of illustration and discussion and in order not to obscure the present disclosure, well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the presented drawings. In addition, in order to avoid obscuring the present disclosure, and also considering that the details of the implementation of such block diagram arrangements depend largely on the fact that the platform on which the present disclosure will be implemented, the arrangements can be shown in block diagram form (i.e., such details should be fully within the scope of cognition of those skilled in the art). Where specific details (e.g., circuits) are stated to describe example embodiments of the present disclosure, it should be apparent to those of ordinary skill in the art that the present disclosure can be implemented without these specific details or with variations of these specific details. The description is therefore considered to be illustrative rather than restrictive.

[0096] The following examples relate to further embodiments. Details in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to the method or process.

[0097] Example 1. An apparatus comprising: a driver including a push-pull transmitter; a first circuit configured to sense a change in a power supply; and a second circuit coupled to the first circuit and to the driver, wherein the second circuit is configured to generate a code based on an output of the first circuit, wherein the code is provided to the driver to adjust a performance parameter of the driver.

[0098] Example 2. The apparatus of Example 1, wherein the first circuit comprises a ring oscillator comprising a delay stage, wherein the delay stage comprises devices having the same size as those in the driver, and wherein the devices are connected to each other in the same manner as the devices in the driver are connected to each other.

[0099] Example 3. The apparatus of Example 2, comprising a low pass filter coupled to the power supply, wherein an output of the low pass filter is a filtered power supply provided to the ring oscillator as a power supply for the ring oscillator.

[0100] Example 4. The apparatus of any preceding example, wherein the output of the first circuit is a first clock, and wherein the second circuit comprises a digital comparator for comparing the first clock to the second clock.

[0101] Example 5. The apparatus of Example 4, wherein the second clock is generated by a crystal oscillator or an on-die clock.

[0102] Example 6. The apparatus of Example 4, wherein the second circuit comprises a filter coupled to the output of the comparator.

[0103] Example 7. The apparatus of Example 6, wherein the filter comprises a chain of shift registers.

[0104] Example 8. The apparatus of Example 6, wherein the second circuit comprises a finite state machine for generating a code based on an output of the filter.

[0105] Example 9. The apparatus of any preceding example, wherein the driver comprises a current mirror comprising a current source, wherein the strength of the current source is adjustable by code.

[0106] Example 10. The apparatus of any preceding example, wherein the code is applied to the driver at boot time, calibration time, during a time when the link is idle, or during an inter-packet gap.

[0107] Example 11. The apparatus of any preceding example, wherein the performance parameter is a voltage swing at an output of the driver.

[0108] Example 12. An apparatus comprising: a driver capable of operating from two separate and distinct power supplies; a ring oscillator comprising at least three drivers, wherein a single driver of the ring oscillator is a substantial replica of the driver, wherein the ring oscillator is configured to operate from a filtered version of one of the two separate and distinct power supplies; and circuitry for adjusting a performance parameter of the driver based on an output of the ring oscillator.

[0109] Example 13. The apparatus of Example 12, wherein the circuitry is to adjust the performance parameter of the driver at one or more of: a startup time, a calibration time, during a time when the link is idle, or during an inter-packet gap.

[0110] Example 14. The apparatus of any of Examples 12 to 13, wherein the circuit comprises: a comparator for comparing the output of the ring oscillator with a reference clock; a filter coupled to the comparator, wherein the filter is configured to reduce noise in the output of the comparator; and a state machine coupled to an output of the filter, wherein the state machine is configured to generate code for receipt by the driver to adjust a performance parameter of the driver.

[0111] Example 15. The apparatus of Example 14, wherein the filter comprises a chain of shift registers.

[0112] Example 16. The apparatus of Example 14, wherein the reference clock is generated by a crystal oscillator.

[0113] Example 17. The apparatus of any of Examples 12 to 16, wherein the driver is one of a USB-compatible driver, a PCIe-compatible driver, or a MIPIPHY-compatible driver, and wherein the two power supplies include a 1 volt power supply and a 1.8 volt power supply.

[0114] Example 18. The apparatus of any of Examples 12 to 17, wherein the performance parameter is a voltage swing at the output of the driver.

[0115] Example 19. A system comprising: a memory; a processor coupled to the memory, the processor having a universal serial bus (USB)-compatible driver, the USB-compatible driver including a driver having a push-pull transmitter, wherein the processor comprises: a first circuit for sensing a change in power supply; and a second circuit coupled to the first circuit and to the driver, wherein the second circuit is configured to generate a code based on an output of the first circuit, wherein the code is provided to the driver to adjust a performance parameter of the driver; and a wireless interface for allowing the processor to communicate with another device.

[0116] Example 20. The system of Example 19, wherein the first circuit includes a ring oscillator, the ring oscillator including a delay stage, wherein the delay stage includes devices having the same size as those in the driver, and wherein the devices are connected to each other in the same manner as the devices in the driver are connected to each other.

[0117] Example 21. The system of any of Examples 19 to 20, wherein the processor comprises a low pass filter coupled to the power supply, wherein an output of the low pass filter is a filtered power supply provided to the ring oscillator as a power supply for the ring oscillator.

[0118] Example 22. The system of any of the preceding examples 19 to 21, wherein the code is applied to the driver at one or more of: startup time, calibration time, during a time when the link is idle, or during an inter-packet gap.

[0119] Example 23. A system comprising: a memory; a processor coupled to the memory, the processor comprising the apparatus of any of Examples 1 to 11; and a wireless interface for allowing the processor to communicate with another device.

[0120] Example 24. A system comprising: a memory; a processor coupled to the memory, the processor comprising the apparatus of any of Examples 12 to 18; and a wireless interface for allowing the processor to communicate with another device.

[0121] Example 25. An apparatus comprising: means for driving; means for sensing a change in power supply; and means for generating code based on an output of the means for sensing, wherein the code is provided to the means for driving to adjust a performance parameter of the means for driving.

[0122] Example 26. The apparatus of Example 25, wherein the means for sensing comprises devices having the same dimensions as those in the means for driving, and wherein the devices are connected to each other in the same manner as the devices in the means for driving are connected to each other.

[0123] Example 27. The apparatus of Example 26, comprising means for filtering the power supply.

[0124] Example 28. The apparatus of any of preceding Examples 25 to 27, wherein the output of the means for sensing is a first clock, and wherein the means for generating comprises a digital comparator for comparing the first clock to the second clock.

[0125] Example 29. A method comprising: sensing a change in a power supply; and generating code based on the sensed output, wherein the code is provided to a driver to adjust a performance parameter of the driver.

[0126] Example 30. The method of Example 29, comprising filtering the power supply.

[0127] An abstract is provided that will allow the reader to ascertain the nature and gist of the present disclosure. It should be understood that the abstract is not intended to limit the scope or meaning of the claims. The appended claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.

Claims

1. A device for power supply suppression, the device comprising: drivers, including push-pull transmitters; A first circuit for sensing a change in power supply; as well as A second circuit is coupled to the first circuit and to the driver, wherein the second circuit is configured to generate a code according to an output of the first circuit, wherein the code is provided to the driver to adjust a performance parameter of the driver.

2. The device according to claim 1, wherein The first circuit includes a ring oscillator including a delay stage, wherein the delay stage includes devices having the same size as devices in the driver and wherein the devices are connected to each other in the same manner as the devices in the driver are connected to each other.

3. The apparatus of claim 2, comprising a low pass filter coupled to the power supply, wherein The output of the low pass filter is a filtered power supply that is provided to the ring oscillator as a power supply for the ring oscillator.

4. The device according to any one of the preceding claims, wherein The output of the first circuit is a first clock, and wherein the second circuit comprises a digital comparator for comparing the first clock with a second clock.

5. The device according to claim 4, wherein The second clock is generated by a crystal oscillator or an on-die clock.

6. The device according to claim 4, wherein The second circuit includes a filter coupled to an output of the comparator.

7. The device according to claim 6, wherein The filter comprises a chain of shift registers.

8. The device according to claim 6, wherein The second circuit includes a finite state machine for generating the code based on an output of the filter.

9. The device according to any one of the preceding claims 1 to 3 or 5 to 8, wherein The driver includes a current mirror including a current source, wherein the strength of the current source can be adjusted by the code.

10. The device according to any one of the preceding claims 1 to 3 or 5 to 8, wherein The code is applied to the driver at startup time, calibration time, during times when the link is idle, or during inter-packet gaps.

11. The device according to any one of the preceding claims 1 to 3 or 5 to 8, wherein The performance parameter is the voltage swing at the output of the driver.

12. A device for power supply suppression, the device comprising: Driver, capable of operating two separate and distinct power supplies; a ring oscillator comprising at least three drivers, wherein a single driver of the ring oscillator is a substantial replica of the driver, wherein the ring oscillator is configured to operate on a filtered version of one of the two separate and distinct power supplies; and A circuit is configured to adjust a performance parameter of the driver according to an output of the ring oscillator.

13. The device of claim 12, wherein: The circuit is configured to adjust a performance parameter of the driver at one or more of: a startup time, a calibration time, during a time when a link is idle, or during an inter-packet gap.

14. The device according to any one of the preceding claims 12 to 13, wherein The circuit comprises: a comparator for comparing the output of the ring oscillator with a reference clock; a filter coupled to the comparator, wherein the filter is configured to reduce noise in an output of the comparator; and A state machine is coupled to an output of the filter, wherein the state machine is configured to generate code for receipt by the driver to adjust the performance parameter of the driver.

15. The apparatus of claim 14, wherein: The filter comprises a chain of shift registers.

16. The apparatus of claim 14, wherein: The reference clock is generated by a crystal oscillator.

17. The device according to any one of the preceding claims 12 to 13 or 15 to 16, wherein The driver is one of a USB-compatible driver, a PCIe-compatible driver, or a MIPIPHY-compatible driver, and wherein the two power supplies include a 1 volt power supply and a 1.8 volt power supply.

18. The device according to any one of the preceding claims 12 to 13 or 15 to 16, wherein The performance parameter is the voltage swing at the output of the driver.

19. A system for power supply suppression, comprising: Memory; a processor coupled to the memory, the processor having a universal serial bus (USB)-compatible driver, the USB-compatible driver including a driver including a push-pull transmitter, wherein the processor comprises: a first circuit for sensing a change in power supply; and a second circuit coupled to the first circuit and to the driver, wherein the second circuit is configured to generate a code based on an output of the first circuit, wherein the code is provided to the driver to adjust a performance parameter of the driver; and A wireless interface is configured to allow the processor to communicate with another device.

20. The system of claim 19, wherein: The first circuit includes a ring oscillator including a delay stage, wherein the delay stage includes devices having the same size as devices in the driver and wherein the devices are connected to each other in the same manner as the devices in the driver are connected to each other.

21. The system of claim 20, wherein: The processor includes a low pass filter coupled to the power supply, wherein an output of the low pass filter is a filtered power supply provided to the ring oscillator as a power supply for the ring oscillator.

22. A system according to any one of the preceding claims 19 to 20, wherein: The code is applied to the driver at one or more of the following times: startup time, calibration time, during times when the link is idle, or during inter-packet gaps.

23. A system for power supply suppression, comprising: Memory; a processor coupled to the memory, the processor comprising the apparatus according to any one of claims 12 to 18; as well as A wireless interface is configured to allow the processor to communicate with another device.

24. A device for power supply suppression, the device comprising: Devices for driving, including devices for push-pull; means for sensing a change in power supply; as well as means for generating a code based on an output of the means for sensing a change in power supply, wherein the code is provided to the means for driving to adjust a performance parameter of the means for driving.

25. The apparatus of claim 24, wherein: The means for sensing changes in power supply comprises devices having the same size as devices in the means for driving, and wherein the devices are connected to each other in the same manner as the devices in the means for driving are connected to each other.

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