Method and circuit for determining phase continuity of a local oscillator signal and local oscillator signal generating circuit

Abstract

A method for determining phase continuity of a local oscillator signal generated using a frequency divider is provided. The method includes determining at least one sample of the local oscillator signal. The method also includes determining information about the phase continuity using the at least one sample.

Description

Technical Field

[0001] The present disclosure relates to determining virtual phase continuity of a local oscillator (LO) signal. Specifically, examples relate to methods and circuits for determining phase continuity of an LO signal and an LO signal generating circuit. Background Art

[0002] Radio frequency (RF) transceivers integrate multiple (digital) phase-locked loops ((D)PLLs) to generate on-chip LO signals for transmitting and receiving RF signals. One requirement for the LO signal is virtual phase continuity, meaning that the phase of the LO signal should remain virtually continuous during the power-down / power-up cycles of the transmit and / or receive chains (e.g., including the DPLL).

[0003] Typically, a high-frequency oscillator signal is divided by a frequency divider to obtain an LO signal of the desired frequency. Frequency dividers are typically designed for very high frequencies and may not have a static reset. Consequently, when the frequency divider is powered on, the phase of the output LO signal is random. For example, if the frequency divider divides the frequency by two, the phase of the input high-frequency oscillator signal is known, but the phase of the LO signal output by the frequency divider is unknown and may have a phase uncertainty of 180°. This LO signal phase uncertainty can be a major obstacle to achieving virtual phase continuity.

[0004] Therefore, it may be desirable to perform LO phase continuity detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Some examples of apparatus and / or methods will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0006] Figure 1 An example of an LO signal generating circuit using an example of a circuit for determining phase continuity of an LO signal is shown;

[0007] Figure 2 An example of a timing diagram is shown;

[0008] Figure 3 Another example of a circuit for determining phase continuity of an LO signal is shown;

[0009] Figure 4 Another example of a timing diagram is shown;

[0010] Figure 5 Another example of a timing diagram is shown;

[0011] Figure 6 An example of a sampling circuit is shown;

[0012] Figure 7 Another example of a timing diagram is shown;

[0013] Figure 8 Another example of a timing diagram is shown;

[0014] Figure 9 An example of a mobile communication device including circuitry for determining phase continuity of an LO signal is shown; and

[0015] Figure 10 A flow chart illustrating an example of a method for determining phase continuity of an LO signal is shown. DETAILED DESCRIPTION

[0016] Various examples will now be described more fully with reference to the accompanying drawings, in which some examples are shown. In the accompanying drawings, the thickness of lines, layers and / or regions may be exaggerated for clarity.

[0017] Therefore, although other examples can be subjected to various modifications and alternative forms, some specific examples thereof are shown in the drawings and will be described in detail later. However, this detailed description does not limit other examples to the specific forms described. Other examples may encompass all modifications, equivalents, and alternative forms that fall within the scope of this disclosure. Throughout the description of the drawings, the same reference numerals refer to the same or similar elements, and when provided for the same or similar functions, the same or similar elements may be implemented in the same or modified form when compared to each other.

[0018] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, these elements may be directly connected or coupled or connected or coupled via one or more intermediate elements. If two elements A and B are combined using "or", it should be understood that all possible combinations are disclosed, namely, only A, only B, and A and B. An alternative wording for the same combination is "at least one of A and B". The same applies to combinations of more than two elements.

[0019] The terms used to describe specific examples herein are not intended to limit other examples. Whenever a singular form such as "a", "an" and "the" is used and only a single element is not explicitly or implicitly defined as mandatory, other examples may also use multiple elements to implement the same function. Similarly, when a function is subsequently described as being implemented using multiple elements, other examples may use a single element or processing entity to implement the same function. It will also be understood that the terms "comprise" and / or "comprising" specify the presence of the features, integers, steps, operations, processes, actions, elements and / or parts when used, but do not exclude the presence or increase of one or more other features, integers, steps, operations, processes, actions, elements, parts and / or any groups thereof.

[0020] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same common meaning as in the art to which examples belong.

[0021] Figure 1 LO signal generation circuit 190 is shown for generating an LO signal. LO signal generation circuit 190 includes a PLL 170 (e.g., a DPLL) configured to generate a PLL signal 171 (i.e., an oscillation signal). For example, PLL 170 may generate PLL signal 171 based on a reference oscillation signal 172 from a reference source (e.g., a quartz watch, not shown). LO signal generation circuit 190 also includes a frequency divider 180 configured to receive PLL signal 171 and divide the frequency of PLL signal 171 to generate local oscillator signal 101.

[0022] For example, LO signal generation circuit 190 can be used in mobile communication devices or any other electronic circuit requiring an LO signal. During operation, LO signal generation circuit 190 can be (repeatedly) powered down and powered up. In many applications, it is desirable (required) that the phase of local oscillator signal 101 be virtually continuous during the power-down / power-up cycles. That is, after powering up frequency divider 180, the phase of local oscillator signal 101 should be defined (known) rather than random after a predetermined (fixed) time has passed since powering up frequency divider 180.

[0023] As described above, the PLL 170 can generate the PLL signal 171 based on the known reference oscillation signal 172. Therefore, after a period of time has passed since the LO signal generation circuit 190 was powered on, the PLL signal 171 is locked to the reference oscillation signal 172. This will be Figure 2 becomes more obvious.

[0024] Figure 2 FIG2 shows a timing diagram showing the time course of signals in the LO signal generating circuit 190. The uppermost signal course 210 shows the state of the PLL 170, that is, the signal course 210 shows whether the PLL 170 is on or off (a low signal is associated with the off state, and a high signal is associated with the on state). The PLL 170 is powered on synchronously with the reference oscillation signal 172 of the reference source. After a fixed time has passed since power-on, the controlled oscillator (e.g., a digitally controlled oscillator DCO or a voltage controlled oscillator VCO) of the PLL 170 is phase-locked to the reference oscillation signal 172 of the reference source. This is shown in FIG2 . Figure 2This is illustrated in FIG. 1 by signal progression 220, which represents the time course of PLL signal 171. After a fixed, known time t1 after PLL 170 is powered on, PLL signal 171 is locked. This can be achieved, for example, by always initializing a multi-stage noise shaper in PLL 170 with the same value. Alternatively, this can be achieved by connecting a running multi-stage noise shaper to a multi-modulus divider within PLL 170. As a result, PLL signal 171 has a specific, known phase.

[0025] In contrast, since the divider is designed at a very high frequency, the divider 180 has no static reset. Therefore, the phase of the LO signal 101 is random. Figure 2 In the timing diagram of FIG, for illustration purposes, it is assumed that the divider 180 divides the frequency of the PLL signal 171 by two. However, it should be noted that the divider 180 may alternatively divide the frequency of the PLL signal 171 by any other integer (e.g., three, four, eight, or sixteen). The resulting phase uncertainty is Figure 2 , which is represented by signal progressions 230 and 240 representing possible phase positions of LO signal 101. As is apparent from signal progressions 230 and 240, the frequency of LO signal 101 is half the frequency of PLL signal 171. However, signal progressions 230 and 240 are phase-shifted by 180° relative to each other. It should be noted that for a frequency divider that divides the frequency of an input oscillating signal by n, the phase of the resulting LO signal can be shifted by m*360° / n, where m and n are integers and m is less than n.

[0026] Due to the phase uncertainty, it is unknown whether a phase jump (e.g., 180°) of the LO signal 101 occurs after a power-down / power-up cycle of the LO signal generating circuit 190. In other words, it is unknown whether virtual phase continuity exists during the power-down / power-up cycle (virtual because no LO signal is generated during the power-down period of the LO signal generating circuit 190).

[0027] To determine the phase continuity of LO signal 101, LO signal generation circuit 190 further includes circuit 100 for determining the phase continuity of the LO signal generated using a frequency divider. For example, circuit 100 can be coupled to the output of PLL 170 and the output of frequency divider 180. Circuit 100 includes sampling circuit 110 configured to determine at least one sample of LO signal 101. Thus, sampling circuit 110 can be coupled to the output of frequency divider 180.

[0028] For example, sampling circuit 110 may sample LO signal 101 at a predetermined time after PLL 170 is turned on. The predetermined time may be greater than the time required for PLL 170 to lock the phase of PLL signal 171 to reference oscillation signal 172. For example, the predetermined time after PLL 170 is turned on may be defined relative to PLL signal 171. Sampling circuit 110 may, for example, sample LO signal 101 at a fixed predetermined time interval after a signal edge (rising edge or falling edge) of PLL signal 171 occurs. In this regard, the fixed predetermined time interval is shorter than the entire cycle time of PLL signal 171.

[0029] Furthermore, the circuit 100 comprises an evaluation circuit 120 configured to determine information about phase continuity using at least one sample. That is, the evaluation circuit 120 determines the phase continuity of the LO signal 101 based on at least one sample of the LO signal 101.

[0030] Thus, circuit 100 allows phase continuity to be determined based on one or more samples of LO signal 101. There is no phase relationship to be measured between LO signal 101 and reference oscillator signal 172 before and after a power-down / power-up cycle. Consequently, area-intensive circuitry for phase measurement (e.g., a time-to-digital converter (TDC)) can be avoided, thereby improving the area efficiency of LO signal generation circuit 190. Furthermore, because circuit 100 can be integrated without disrupting the frequency divider, redesign of the conventional frequency divider is not required.

[0031] For example, the evaluation circuit 120 can use at least one sample together with information about a reference sample. The reference sample can be related to a previous power-up of the PLL 170 and the frequency divider 180. That is, the reference sample can be determined in the same manner as the at least one sample of the currently powered-up LO signal 101. If the LO signal 101 is phase continuous, then the at least one sample is equal to the reference sample because no phase shift occurs, and therefore, the LO signal 101 is sampled at the same position after two power-ups (replacing the reference sample). Figure 4 A more detailed explanation is given.) Thus, if at least one sample is equal to the reference sample, evaluation circuit 120 can determine that LO signal 101 is phase continuous.

[0032] The evaluation circuit 120 may save the determined sample as information about another reference sample, which is used for subsequent phase continuity determination (ie, for determining phase continuity after a subsequent power-down / power-up cycle).

[0033] Furthermore, circuit 100 may include additional circuitry 130 for correcting the phase of LO signal 101 if LO signal 101 is not phase continuous. For example, if LO signal 101 is not phase continuous, circuit 130 may control PLL 170 to phase shift PLL signal 171 or control frequency divider 180 to phase shift LO signal 101. If frequency divider 180 divides the frequency of PLL signal 171 by two, circuit 130 may, for example, control frequency divider 180 to shift the phase of LO signal 101 by 180° to generate a corrected LO signal.

[0034] In some examples, additional samples of LO signal 101 may be used to determine the phase continuity of LO signal 101. For example, sampling circuitry may determine another sample of LO signal 101 after determining a full cycle of PLL signal 171 after determining the (at least one) first sample. Thus, evaluation circuitry may use this additional sample to further determine information regarding phase continuity. The number of samples used to determine the phase continuity of LO signal 101 may be based on the ratio of the frequency of PLL signal 171 to the frequency of LO signal 101. That is, the number of samples used to determine the phase continuity of LO signal 101 may be based on the integer n used for frequency division by frequency divider 180. For example, if frequency divider 180 divides the frequency of PLL signal 171 by n, then n-1 samples may be used to determine the phase continuity of LO signal 101.

[0035] Figure 3 shows a more detailed example of a circuit for determining phase continuity of an LO signal generated using a frequency divider, Figure 4 A timing diagram is shown.

[0036] like Figure 3 As shown, a DCO 370 of a PLL (not shown) provides a PLL signal (oscillation signal) 371 to a frequency divider 380. The frequency divider 380 divides the frequency of the PLL signal 371 by an integer n to generate an LO signal 301 of a desired frequency.

[0037] like Figure 4 As shown in the left figure, during the first power-down / power-up cycle, the PLL is turned on synchronously with the reference clock (i.e., synchronized with the reference oscillator signal input to the PLL) via signal progression 410. As described above, after a fixed time t1, the PLL (i.e., DCO 370) is phase-locked to the reference oscillator signal (see the left portion of signal progression 420 representing PLL signal 371), while the LO signal 301 has an unknown phase.

[0038] Once the PLL (i.e., DCO 370) is phase locked, a trigger signal 331 is generated synchronously with the signal edge of the PLL signal 371 a fixed time after the PLL is turned on. For example, the trigger signal 331 can be synchronized to the falling edge of the PLL signal 371, as shown in the left portion of the signal progression 430 representing the trigger signal 331. Alternatively, the trigger signal 331 can be synchronized to the rising edge of the PLL signal 371. Synchronizing with a different edge of the PLL signal 371 only changes the value of the sample obtained from the LO signal 301, without changing the phase continuity detection (because the same edge is used for each power-down / power-up cycle). The PLL signal 371 and the trigger signal 331 are generated with a fixed but arbitrary time offset relative to the time point when the PLL 370 is turned on to avoid phase ambiguity.

[0039] like Figure 3 As shown, trigger circuit 330 receives trigger signal 331 along with PLL signal 371. Trigger circuit 330 generates sampling signal 332 based on trigger signal 331 and PLL signal 371. For example, sampling signal 332 can be a delayed copy of PLL signal 371. Sampling signal 332 is used by sampling circuit 310 to sample LO signal 301. Figure 4 The time course of the sampling signal 332 is shown in FIG by the signal course 440. As can be clearly seen from the signal course 440, the initial signal edge 441 of the sampling signal 332 occurs at a fixed predetermined time interval after the signal edge 421 of the PLL signal 371. Figure 4 As shown by the signal progression 450 in FIG, the sampling circuit 310 samples the LO signal 331 at the occurrence of the signal edge 441 of the sampling signal 332. Therefore, the sampling circuit 310 samples the LO signal 301 at a predetermined time t2 after the PLL is turned on during the first power-down / power-up cycle. Specifically, after the signal edge of the PLL signal 371 occurs, the sampling circuit 310 samples the LO signal 301 at a fixed predetermined time interval. Figure 4 In the example of FIG, the value of LO signal 301 at the time of sampling is 1. The resulting sample 311 is used as a reference sample.

[0040] Similarly, in the subsequent second power-down / power-up cycle, the PLL is turned on synchronously with the reference clock (see the right side of the signal process 410). After the same fixed time t1, the PLL is locked to the reference oscillation signal again (see the right part of the signal process 420 representing the PLL signal 371). After a fixed time from the second time the PLL is turned on, the trigger signal 331 is generated again synchronously with the signal edge of the PLL signal 371. Moreover, the sampling signal 332 appears again at a fixed predetermined time interval after the signal edge 421' of the PLL signal 371. Therefore, the sampling circuit 310 samples the LO signal 301 again at a predetermined time t2 after the second time the PLL is turned on in the subsequent power-down / power-up cycle. However, since the divider 380 does not have a static reset, the phase of the LO signal 301 is random. For example, the phase of the LO signal 301 can be phase-shifted by 180° to perform a two-way frequency division, as shown in FIG. Figure 4 This is shown as the signal progression 450 and 460 in the right portion of FIG.

[0041] Evaluation circuit 320 detects phase continuity based on samples 311 and 311′. That is, evaluation circuit 320 uses sample 311′ along with information about reference sample 311 to determine the phase continuity of LO signal 301. If sample 311′ is equal to sample 311, evaluation circuit 320 determines that LO signal 301 is phase continuous. If sample 311′ is not equal to sample 311, evaluation circuit 320 determines that LO signal 301 is not phase continuous.

[0042] If LO signal 301 is not phase continuous, a required phase correction may be determined and used to correct the phase of LO signal 301. For example, the phase correction of LO signal 301 may be determined based on sample 311 and sample 311' (i.e., a current sample and a reference sample). For example, circuit 300 may include circuitry (not shown) for determining a corrected LO signal.

[0043] In the foregoing description, it is assumed that the frequency divider 380 divides the frequency of the PLL signal 371 by two. However, the frequency divider 380 can divide the frequency of the PLL signal 371 by any integer. Figure 5 3. Since the divider 380 divides the frequency of the PLL signal 371 by three, the phase of the LO signal 301 may be shifted by 120° or 240° after the second power-down / power-up cycle compared to the phase position of the LO signal 301 after the first power-down / power-up cycle. Figure 5 3 is shown by signal courses 530 , 540 and 550 , which show the time course of LO signal 301 with a phase shift of 0°, 120° and 240°.

[0044] In addition to the sampling for the frequency division by two described above, sampling circuit 310 determines another (second) sample of LO signal 301 after determining the first sample and after a full cycle time of PLL signal 371 (after the PLL is turned on). Figure 5 Signal progression 510 in FIG. 1 again illustrates the time progression of PLL signal 371. Signal progression 520 illustrates the time progression of sampling signal 332. As is apparent from signal progression 520, the initial rising edge 521 of sampling signal 332 occurs at a fixed, predetermined time interval after edge 511 of PLL signal 371. Because sampling signal 332 is a delayed copy of PLL signal 371, the next rising edge 522 of sampling signal 332 occurs exactly one full cycle of PLL signal 371. As shown in signal progressions 530, 540, and 550, sampling circuit 310 samples LO signal 301 at rising edges 521 and 522 of sampling signal 332. The resulting samples of LO signal 301 have different values depending on the phase of LO signal 301. For example, for a 0° phase shift, samples of LO signal 301 may have values of 1 and 0, for a 120° phase shift, they may have values of 0 and 1, and for a 240° phase shift, they may have values of 0 and 0.

[0045] Evaluation circuit 320 uses two samples, namely the first and second (another) samples of LO signal 301 after turning on the PLL, to determine information about phase continuity. By comparing these two values with reference values obtained from a previous power-down / power-up cycle, the phase continuity of LO signal 301 can be determined.

[0046] In the following, combined Figure 6 An exemplary embodiment of a circuit 600 that combines the functionality of a trigger circuit and a sampling circuit according to the proposed technology is described. Circuit 600 includes a shift register having N (high-speed) flip-flop circuits 610-1, 610-2, ..., 610-N. The number of flip-flop circuits N can be based on an integer n used by a frequency divider to divide the PLL signal. For example, N can be equal to n-1. N flip-flop circuits 610-1, 610-2, ..., 610-N hold consecutive samples taken from an LO signal 601 input to circuit 600. N flip-flop circuits 610-1, 610-2, ..., 610-N are clocked by a sampling signal 602. As described above, sampling signal 602 is a delayed copy of a PLL signal 603 input to circuit 600. Sampling signal 602 is generated by delaying PLL signal 603 using a delay line 620.

[0047] The delay line 620 is controlled based on an enable signal 631. The enable signal 631 is generated by an enable circuit 630 that receives the PLL signal 603 and the trigger signal 604. The enable circuit 630 synchronizes the trigger signal 604 with the PLL signal 603. For example, the enable circuit 630 can synchronize the trigger signal 604 with the (rising / falling) edge of the PLL signal 603. In addition, the enable circuit 630 is configured to determine the number of samples to be acquired. Therefore, the enable circuit 630 can be configured to count a certain type of edge (e.g., falling or rising) of the PLL signal 603 and set the enable signal 631 to a disable state, which disables the delay line 620 after a predetermined number (e.g., after N signal edges have been counted).

[0048] The synchronization circuit 640 synchronizes the PLL signal 603 with a signal 605 indicating a PLL state synchronized with a reference oscillation signal input to the PLL.

[0049] The outputs of the flip-flop circuits 610-1, 610-2, ..., 610-N are provided to a second group of N flip-flop circuits 650-1, ..., 650-N, which are clocked based on the output signal of the synchronization circuit 640. The synchronization circuit 640, together with the flip-flop circuits 610-1, 610-2, 610-N and the second group of flip-flop circuits 650-1, 650-N, can be understood as a sampling circuit 660 according to the proposed technology. The outputs of the flip-flop circuits 610-1, 610-2, 610-N are synchronized to the reference clock domain (i.e., the reference oscillation signal input to the PLL) via the output signal of the synchronization circuit 640.

[0050] This is the case for the frequency division of n=4. Figure 7 Here, N=n-1=3 flip-flop circuits are used to sample the LO signal.

[0051] Signal progression 710 again shows that during the power down / power up cycle, the PLL is turned on synchronously with the reference clock (ie, synchronously with the reference oscillating signal input to the PLL).

[0052] After a fixed period of time after the PLL is turned on (during which the PLL locks to the reference oscillator signal), a trigger signal is generated synchronously with the signal edge of the PLL signal. For example, the trigger signal can be synchronized to the falling edge of the PLL signal, as shown in signal progressions 720 and 730, where signal progression 720 represents the trigger signal and signal progression 730 represents the PLL signal. Thus, when the trigger signal is high, in response to the first falling edge of the PLL signal, the enable signal, represented by signal progression 740, goes high (indicating the active state of the delay line used to delay the PLL signal). Thus, when the enable signal is high, the enable circuit begins counting rising edges of the PLL signal, as shown in progression 750. When the count reaches its predetermined maximum value of N = n - 1 = 4 - 1 = 3 edges of the PLL signal, the count is reset to zero. When the count is reset to zero, the enable signal returns to a low level.

[0053] Therefore, when the enable circuit counts from 1 to 3, the delay line only delays the pulses of the PLL signal. Therefore, the sampled signal includes N = 3 pulses (see signal progression 760), allowing the flip-flop circuit to sample N = 3 samples of the LO signal (see signal progression 770). Processes 780, 790, and 795 show the sampled data of the LO signal for three samples. As is apparent from processes 780, 790, and 795, after the enable circuit counts N = 3 signal edges of the PLL signal, the three flip-flop circuits retain the sampled data. Process 799 shows the corresponding outputs of the second set of flip-flop circuits. As is apparent from processes 710 and 799, the outputs of the second set of flip-flop circuits are synchronized with the reference clock (because the PLL is turned on synchronously with the reference clock).

[0054] Figure 8 Shown Figure 6 Example timing for a variation of the enable circuit 630 is shown. Figure 8 In the example of , the enable circuit 630 exhibits a synchronization uncertainty of two (or multiples thereof) full clock cycles of the PLL signal relative to the synchronization of the trigger signal 604 with the PLL signal 603. Figure 8 In FIG, it is assumed that the frequency divider performs division by two to generate the LO signal from the PLL signal.

[0055] exist Figure 8 In the left part of FIG, the signal progression for the first power-down / power-up cycle is shown, while in Figure 8 In the right part of FIG, the corresponding signal progression for the second (subsequent) power-down / power-up cycle is shown.

[0056] For both cycles, as shown in signal progression 810, the PLL is phase locked after a fixed time t1 has passed since the PLL was powered on. For the first cycle, a fixed time after the PLL is turned on (see the left portion of signal progression 820), the trigger signal is again generated synchronously with the edge of the PLL signal. For the second power-down / power-up cycle, due to Figure 6 The illustrated enable circuit 630 exhibits a synchronization uncertainty of two (or multiples thereof) full clock cycles of the PLL signal relative to the synchronization of the trigger signal 604 and the PLL signal 603. Therefore, the position of the trigger signal pulse may vary according to two PLL clock cycles. Consequently, the pulses in the sampling signal used to control the flip-flop circuit may also vary according to two PLL clock cycles, as shown in the right portion of signal progression 830. In other words, the sampling time of the flip-flop circuit may vary according to two PLL clock cycles.

[0057] However, as is apparent from signal progressions 840 and 850 representing the LO signal with and without phase shift, varying the sampling time of the flip-flop circuit according to two PLL clock cycles does not change the sampling result of the frequency division by two, thereby enabling the phase shift of the LO signal to be correctly determined.

[0058] Typically, for frequency division by n, an uncertainty of n full clock cycles of the PLL signal can be tolerated in the enable circuit 630 (i.e., the synchronization stage) for correct LO signal phase change detection. This robustness against clock uncertainty can relax the design of the synchronization stage.

[0059] From the foregoing description, it is clear that the proposed technique can be implemented in an area-saving manner because it avoids area-wasting components such as the TDC. Alternatively, the proposed technique can be implemented using a few flip-flop circuits and gates for sampling and synchronization. Furthermore, the proposed technique can be easily scaled to any number of frequency dividers with minimal area impact.

[0060] As previously mentioned, in some examples, the divider input can be used to sample the divider output at each power-up. Sampling is performed at a fixed offset from the time the PLL is turned on, synchronized with the reference clock. Phase changes in the LO signal output by the divider can be detected by comparing the sample values between two consecutive power-ups. For a divide-by-n, n-1 samples can be used.

[0061] In general, some examples of the present disclosure relate to an apparatus for determining phase continuity of an LO signal generated using a frequency divider. The apparatus includes means for determining at least one sample of the LO signal and means for determining information regarding phase continuity using the at least one sample. As described above, the means for determining at least one sample of the LO signal can be configured to sample the LO signal at a predetermined time after a PLL (Pulse-Lock Loop) is turned on, the PLL generating the PLL signal input to the frequency divider.

[0062] exist Figure 9 An example of an implementation using a circuit for determining phase continuity of an LO signal according to one or more aspects of the proposed architecture or one or more examples described above is shown in FIG. Figure 9 An example of a mobile communication device 900 (eg, a mobile phone, smartphone, tablet, or laptop) comprising circuitry for determining phase continuity of an LO signal as described herein is schematically shown.

[0063] The mobile communication device 900 includes at least one of a transmitter 910 and a receiver 920. For example, the transceiver 930 may include the transmitter 910 and the receiver 920. At least one antenna element 940 of the mobile communication device 900 may be coupled to the transmitter 910, the receiver 920, or the transceiver 930.

[0064] Transmitter 910 includes mixer circuitry 950. Mixer circuitry 950 includes LO signal generation circuitry 951 according to one or more of the examples described above, and mixer 952 for generating an RF signal based on a baseband signal and an LO signal generated by LO signal generator circuitry 951. As described above, LO signal generation circuitry 951 includes circuitry 953 for determining phase continuity of the LO signal according to the examples described herein. A power amplifier 960 may be further coupled to the output of mixer circuitry 950 to amplify the generated RF signal before radiating the generated RF signal into the environment via at least one antenna element 940.

[0065] Similarly, receiver 920 includes another mixer circuit 970. Mixer circuit 970 includes LO signal generation circuit 972 according to one or more of the examples described above, and mixer 971 for generating a baseband signal based on the RF signal and the LO signal from LO signal generator circuit 972. As described above, according to the examples described herein, LO signal generation circuit 972 includes circuit 973 for determining phase continuity of the LO signal. A low-noise amplifier 980 may be further coupled to the input of mixer circuit 970 to amplify the RF signal received from the environment via at least one antenna element 940 before the RF signal is down-converted by mixer circuit 970.

[0066] To this end, a mobile communication device having a transmitter / receiver / transceiver with improved (reduced) power consumption and chip area consumption may be provided.

[0067] With the help of Figure 10 The flowchart in FIG. 1 shows an example of a method 1000 for determining phase continuity of an LO signal generated using a frequency divider. The method 1000 includes determining at least one sample of a local oscillator signal 1002. Furthermore, the method 1000 includes determining information about phase continuity using the at least one sample 1004.

[0068] In combination with the proposed technology or one or more of the above examples (e.g., Figure 1-9 ) mentions more details and aspects of the method. The method may include one or more additional optional features corresponding to one or more aspects of the proposed technology or one or more examples above.

[0069] Wireless communication circuitry using circuits, transmitters, or receivers according to the proposed technology or one or more of the above examples can be configured to operate according to one of the mobile communication networks or systems standardized by the Third Generation Partnership Project (3GPP). The mobile or wireless communication system can correspond to, for example, Long Term Evolution (LTE), Advanced LTE (LTE-A), High Speed Packet Access (HSPA), Universal Mobile Telecommunications System (UMTS) or UMTS Terrestrial Radio Access Network (UTRAN), Evolved UTRAN (e-UTRAN), Global System for Mobile Communications (GSM) or Enhanced Data Rates for GSM Evolution (EDGE) network, GSM / EDGE Radio Access Network (GERAN). Alternatively, the wireless communication circuitry may be configured to operate according to a mobile communication network having a different standard, such as the Worldwide Interoperability for Microwave Access (WIMAX) network IEEE 802.16 or the Wireless Local Area Network (WLAN) IEEE 802.11, typically an Orthogonal Frequency Division Multiple Access (OFDMA) network, a Time Division Multiple Access (TDMA) network, a Code Division Multiple Access (CDMA) network, a Wideband CDMA (WCDMA) network, a Frequency Division Multiple Access (FDMA) network, a Space Division Multiple Access (SDMA) network, and the like.

[0070] The examples described in this article can be summarized as follows:

[0071] Example 1 is a method for determining phase continuity of a local oscillator signal generated using a frequency divider, the method comprising: determining at least one sample of the local oscillator signal; and determining information about the phase continuity using the at least one sample.

[0072] In Example 2, the step of determining at least one sample of the local oscillator signal in the method of Example 1 includes sampling the local oscillator signal at a predetermined time after a phase-locked loop is turned on, the phase-locked loop generating a phase-locked loop signal input to the frequency divider.

[0073] In Example 3, the step of determining at least one sample of the local oscillator signal in the method of Example 2 includes sampling the local oscillator signal at a fixed predetermined time interval after a signal edge of the phase-locked loop signal.

[0074] In Example 4, the fixed predetermined time interval in the method of Example 3 is shorter than the entire cycle time of the phase-locked loop signal.

[0075] In Example 5, the step of determining the information about the phase continuity in the method of Example 1 includes using at least one sample together with the information about the reference sample.

[0076] In Example 6, in the method of Example 5, determining the information about phase continuity includes determining that the local oscillator signal is phase continuous if at least one sample is equal to a reference sample.

[0077] In Example 7, the step of determining whether the local oscillator signal is phase continuous in the method of Example 5 or Example 6 includes: saving the determined sample as information about another reference sample, the another reference sample information being used for subsequent phase continuity determination.

[0078] In Example 8, the method of any one of Examples 1 to 7 further includes correcting a phase of the local oscillator signal if the local oscillator signal is not phase continuous.

[0079] In Example 9, the method of any one of Examples 1 to 8 further includes: after determining the at least one sample, determining another sample of the local oscillator signal after a full cycle time of the phase-locked loop signal; and determining information about phase continuity using the another sample.

[0080] Example 10 is a circuit for determining phase continuity of a local oscillator signal generated using a frequency divider, the circuit comprising: a sampling circuit configured to determine at least one sample of the local oscillator signal; and an evaluation circuit configured to determine information about the phase continuity using the at least one sample.

[0081] In Example 11, the sampling circuit in the circuit of Example 10 is configured to sample the local oscillator signal at a predetermined time after a phase-locked loop is turned on, the phase-locked loop generating the phase-locked loop signal input to the frequency divider.

[0082] In Example 12, the sampling circuit in the circuit of Example 11 is configured to sample the local oscillator signal at a fixed predetermined time interval after a signal edge of the phase-locked loop signal.

[0083] In Example 13, the fixed predetermined time interval in the circuit of Example 12 is shorter than a whole cycle time of the phase-locked loop signal.

[0084] In Example 14, the evaluation circuit in the circuit of Example 10 is configured to use the at least one sample together with information about the reference sample.

[0085] In Example 15, the evaluation circuit in the circuit of Example 14 is configured to determine that the local oscillator signal is phase continuous if at least one sample is equal to the reference sample.

[0086] In Example 16, the evaluation circuit in the circuit of Example 14 or Example 15 is configured to save the determined sample as information about another reference sample for subsequent phase continuity determination.

[0087] In Example 17, the circuit of any one of Examples 10 to 16 further includes circuitry configured to correct a phase of the local oscillator signal if the local oscillator signal is not phase continuous.

[0088] In Example 18, the sampling circuit in the circuit of any one of Examples 10 to 17 is further configured to determine another sample of the local oscillator signal after determining at least one sample and after a full cycle time of the phase-locked loop signal, and wherein the evaluation circuit is further configured to use the another sample to determine information about phase continuity.

[0089] Example 19 is a local oscillator signal generating circuit, comprising: a phase-locked loop, configured to generate a phase-locked loop signal; a divider, configured to receive the phase-locked loop signal and divide the frequency of the phase-locked loop signal to generate a local oscillator signal; and a circuit for determining phase continuity according to any one of Examples 10 to 18.

[0090] In Example 20, the circuit for determining phase continuity in the local oscillator signal generating circuit of Example 19 is coupled to an output of the phase-locked loop and to an output of the frequency divider.

[0091] In Example 21, the sampling circuit in the local oscillator signal generating circuit of Example 20 is coupled to the output of the frequency divider.

[0092] Example 22 is a mixer circuit for a transmitter, comprising: a local oscillator signal generator circuit according to any one of Examples 19 to 21; and a mixer configured to generate a radio frequency signal based on a baseband signal and a local oscillator signal of the local oscillator signal generator circuit.

[0093] Example 23 is a transmitter comprising the mixer circuit according to Example 22.

[0094] In Example 24, the transmitter of Example 23 further includes a power amplifier coupled to the output of the mixer circuit.

[0095] Example 25 is a mixer circuit for a receiver, comprising: a local oscillator signal generator circuit according to any one of Examples 19 to 21; and a mixer configured to generate a baseband signal based on a radio frequency signal and a local oscillator signal of the local oscillator signal generator circuit.

[0096] Example 26 is a receiver comprising the mixer circuit according to Example 25.

[0097] In Example 27, the receiver of Example 26 further includes a low noise amplifier coupled to the input of the mixer circuit.

[0098] Example 28 is a transceiver comprising the transmitter according to any one of Examples 23 and 24 or the receiver according to any one of Examples 26 and 27.

[0099] Example 29 is a mobile communication device comprising the transmitter according to any one of Examples 23 and 24, the receiver according to any one of Examples 26 and 27, or the transceiver according to Example 28.

[0100] In Example 30, the mobile communication device of Example 29 further comprises at least one antenna element coupled to the transmitter, receiver, or transceiver.

[0101] Example 31 is a module for determining phase continuity of a local oscillator signal generated using a frequency divider, the module comprising: a module for determining at least one sample of the local oscillator signal; and a module for determining information about the phase continuity using the at least one sample.

[0102] In Example 32, the module for determining at least one sample of the local oscillator signal in the module of Example 31 is configured to sample the local oscillator signal at a predetermined time after the phase-locked loop is turned on, and the phase-locked loop generates a phase-locked loop signal that is input to the divider.

[0103] with one or more of the examples and appendices described in detail above. Figure 1 The aspects and features mentioned and described herein may also be combined with one or more other examples in order to replace similar features of the other examples, or to additionally introduce features into the other examples.

[0104] Examples may further be or relate to computer programs having program codes for performing one or more of the above methods when the computer program is executed on a computer or processor. The steps, operations or processes of various above methods may be performed by a programmed computer or processor. Examples may also include program storage devices such as digital data storage media, which are machine, processor or computer readable and encode the machine executable program, processor executable program or computer executable program of the instructions. The instructions execute or cause some or all of the actions of the above methods to be performed. The program storage device may include or may be, for example, a digital memory, a magnetic storage medium such as a disk and tape, a hard drive or an optically readable digital data storage medium. Other examples may also include computers, processors or control units programmed to perform the actions of the above methods, or (field) programmable logic arrays ((F) PLAs) or (field) programmable gate arrays ((F) PGAs) programmed to perform the actions of the above methods.

[0105] The description and drawings merely illustrate the principles of the present disclosure. Furthermore, all examples cited herein are expressly and in principle intended only for educational purposes to help the reader understand the principles of the present disclosure and the concepts proposed by the inventors to further advance the art. All statements herein citing principles, aspects, and examples of the present disclosure, as well as specific examples thereof, are intended to encompass their equivalents.

[0106] A functional block represented as a “module for ...” that performs a specific function may refer to a circuit configured to perform the specific function. Therefore, a “module for something” may be realized as “means configured to or suitable for something,” such as a device or circuit configured to or suitable for a respective task.

[0107] The functions of the various elements shown in the drawings, including any functional blocks labeled as "modules," "modules for providing signals," "modules for generating signals," etc., may be implemented in the form of dedicated hardware, such as "signal providers," "signal processing units," "processors," "controllers," etc., and may be implemented in the form of hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, a single shared processor, or multiple separate processors, some or all of which may be shared. However, the terms "processor" or "controller" are not limited to hardware specifically capable of executing software, but may also include digital signal processor (DSP) hardware, network processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), read-only memories (ROMs), random access memories (RAMs), and non-volatile memories for storing software. Other conventional and / or custom hardware may also be included.

[0108] A block diagram may, for example, illustrate a high-level circuit diagram that implements the principles of the present disclosure. Similarly, a flow chart, state transition diagram, pseudocode, or the like may represent various processes, operations, or steps, which, for example, may be substantially represented in a computer-readable medium and thus executed by a computer or processor, whether or not such computer or processor is explicitly shown. The methods disclosed in the specification or claims may be implemented by a device having modules for performing the various actions of these methods.

[0109] It should be understood that, unless otherwise expressly or implicitly stated, for example for technical reasons, the disclosure of multiple actions, processes, operations, steps or functions disclosed in the specification or claims may not be interpreted as being in a particular order. Therefore, the disclosure of multiple actions or functions will not limit them to a particular order unless these actions or functions are not interchangeable for technical reasons. In addition, in some examples, a single action, function, process, operation or step may include or be decomposed into multiple sub-actions, sub-functions, sub-processes, sub-operations or sub-steps, respectively. Unless expressly excluded, such sub-actions may be included in a portion of the disclosure of the single action.

[0110] Furthermore, the following claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. Although each claim may stand on its own as a separate example, it should be noted that—while dependent claims may refer to a specific combination with one or more other claims in a claim—other examples may include combinations of dependent claims with the subject matter of other dependent or independent claims. Unless it is indicated that a particular combination is not intended, such combinations are expressly contemplated herein. Furthermore, even if a claim is not directly dependent on an independent claim, it is intended that features of that claim be incorporated into any other independent claim.

Claims

1. A method for determining phase continuity of a local oscillator signal generated using a frequency divider, comprising: determining at least one sample of the local oscillator signal; as well as determining information about phase continuity using the at least one sample; Wherein, determining the at least one sample of the local oscillator signal comprises: sampling the local oscillator signal at a predetermined time after a phase-locked loop is turned on, the phase-locked loop generating a phase-locked loop signal input to the frequency divider; Wherein, determining the at least one sample of the local oscillator signal comprises: The local oscillator signal is sampled at a fixed predetermined time interval after a signal edge of the phase-locked loop signal, wherein the fixed predetermined time interval is shorter than a full cycle time of the phase-locked loop signal.

2. The method according to claim 1, wherein Determining information about the phase continuity includes: The at least one sample is used together with information about a reference sample.

3. The method according to claim 2, wherein: Determining information about the phase continuity includes: If the at least one sample is equal to the reference sample, then the local oscillator signal is determined to be phase continuous.

4. The method according to claim 3, wherein: Determining whether the local oscillator signal is phase continuous includes: The determined sample is saved as information about another reference sample, and the another reference sample information is used for subsequent phase continuity determination.

5. The method according to claim 1, further comprising: If the local oscillator signal is not phase continuous, the phase of the local oscillator signal is corrected.

6. The method according to claim 1, further comprising: After determining the at least one sample, determining another sample of the local oscillator signal after a full cycle time of the phase locked loop signal; as well as Information about phase continuity is determined using the further sample.

7. A circuit for determining phase continuity of a local oscillator signal generated using a frequency divider, comprising: a sampling circuit configured to determine at least one sample of the local oscillator signal; and an evaluation circuit configured to determine information about phase continuity using the at least one sample, wherein the sampling circuit is configured to sample the local oscillator signal at a predetermined time after a phase-locked loop is turned on, the phase-locked loop generating a phase-locked loop signal input to the frequency divider, The sampling circuit (110) is configured to sample the local oscillator signal at a fixed predetermined time interval after a signal edge of the phase-locked loop signal, wherein the fixed predetermined time interval is shorter than a full cycle time of the phase-locked loop signal.

8. The circuit according to claim 7, wherein The evaluation circuit is configured to use the at least one sample together with information about a reference sample.

9. The circuit according to claim 8, wherein The evaluation circuit is configured to determine that the local oscillator signal is phase continuous if the at least one sample is equal to the reference sample.

10. The circuit according to claim 7, wherein The evaluation circuit is configured to save the determined sample as information about a further reference sample, which is used for a subsequent phase continuity determination.

11. The circuit of claim 7, further comprising: Circuitry is configured to correct the phase of the local oscillator signal if the local oscillator signal is not phase continuous.

12. The circuit according to claim 7, wherein The sampling circuit is further configured to determine, after determining the at least one sample, a further sample of the local oscillator signal after a full cycle time of the phase-locked loop signal, and wherein the evaluation circuit is further configured to use the further sample to determine information about phase continuity.

13. A local oscillator signal generating circuit, comprising: a phase-locked loop configured to generate a phase-locked loop signal; a frequency divider configured to receive the phase-locked loop signal and divide the frequency of the phase-locked loop signal to generate a local oscillator signal; as well as A circuit for determining phase continuity according to claim 7.

14. The circuit according to claim 13, wherein Circuitry for determining phase continuity is coupled to the output of the phase-locked loop and to the output of the frequency divider.

15. The circuit of claim 14, wherein: The sampling circuit is coupled to the output of the frequency divider.

16. A mixer circuit for a transmitter, comprising: The local oscillator signal generator circuit according to claim 13; as well as The mixer is configured to generate a radio frequency signal based on the baseband signal and a local oscillator signal of the local oscillator signal generator circuit.

17. A transmitter comprising the mixer circuit according to claim 16.

18. A mixer circuit for a receiver, comprising: The local oscillator signal generator circuit according to claim 13; as well as The mixer is configured to generate a baseband signal based on the radio frequency signal and a local oscillator signal of the local oscillator signal generator circuit.

19. A receiver comprising the mixer circuit according to claim 18.

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