Scan driver and display device including the same

Abstract

The present invention discloses a scan driver and a display device including the scan driver. The scan driver includes: a substrate; a first transistor located on the substrate, the first transistor includes a first active pattern and a first gate electrode, the first active pattern includes a first area and a second area and a first channel area located between the first area and the second area; a second transistor located on the first transistor, the second transistor includes a second active pattern and a second gate electrode, the second active pattern includes a third area and a fourth area and a second channel area located between the third area and the fourth area; a first electrode and a second electrode located on the second transistor, the first electrode and the second electrode are electrically connected to the first area and the second area respectively; and a third electrode and a fourth electrode located on the second transistor, the third electrode and the fourth electrode are electrically connected to the third area and the fourth area respectively, wherein the first electrode and the third electrode are electrically connected.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a scan driver and a display device including the scan driver. Background Art

[0002] Recently, various flat panel display devices have been developed that have weight and size advantages over conventional display devices such as cathode ray tubes (CRTs). Examples of flat panel display devices include liquid crystal display (LCD) devices, field emission display (FED) devices, plasma display panels (PDPs), and organic light emitting display (OLED) devices.

[0003] Since the OLED device uses an organic light emitting diode that emits light based on the recombination of electrons and holes, the OLED device has advantages such as fast response and low power consumption. Summary of the invention

[0004] Embodiments of the present disclosure provide a scan driver occupying a small area, and also provide a display device having a reduced dead zone.

[0005] According to an embodiment, a scan driver may include: a substrate; a first transistor located on the substrate, the first transistor including a first active pattern and a first gate electrode, the first active pattern including a first region, a second region, and a first channel region located between the first region and the second region; a second transistor located on the first transistor, the second transistor including a second active pattern and a second gate electrode, the second active pattern including a third region, a fourth region, and a second channel region located between the third region and the fourth region; a first electrode and a second electrode located on the second transistor, the first electrode and the second electrode being electrically connected to the first region and the second region, respectively; and a third electrode and a fourth electrode located on the second transistor, the third electrode and the fourth electrode being electrically connected to the third region and the fourth region, respectively, wherein the first electrode is electrically connected to the third electrode.

[0006] The first active pattern may include a first overlapping portion, a first protruding portion protruding from the first overlapping portion in a first direction and connected to the first electrode, and a second protruding portion protruding from the first overlapping portion in a second direction and connected to the second electrode.

[0007] The second active pattern may include a second overlapping portion overlapping the first overlapping portion, a third protruding portion protruding from the second overlapping portion in the first direction and connected to the third electrode, and a fourth protruding portion protruding from the second overlapping portion in the second direction and connected to the fourth electrode.

[0008] The third protrusion portion may not overlap with the first protrusion portion, and the fourth protrusion portion may not overlap with the second protrusion portion.

[0009] The second direction may be opposite to the first direction.

[0010] The second electrode may be electrically connected to the fourth electrode.

[0011] The second gate electrode may overlap the first gate electrode.

[0012] The scan driver may further include a shielding electrode between the first transistor and the second transistor.

[0013] A width of the shielding electrode may be greater than a width of the first gate electrode.

[0014] A voltage for controlling a driving range of the second transistor may be applied to the shielding electrode.

[0015] When a negative voltage is applied to the shielding electrode, a driving range of the second transistor may be widened, and when a positive voltage is applied to the shielding electrode, the driving range of the second transistor may be narrowed.

[0016] The scan driver may further include multiple stages for respectively outputting multiple scan signals, wherein each of the multiple stages includes: a first input unit for transmitting the input signal to a set node in response to a second clock signal; a second input unit for transmitting the first clock signal to a reset node in response to the input signal and the second clock signal; a first output unit for outputting a third clock signal as a scan signal in response to a voltage of the set node; and a second output unit for outputting a concurrent drive signal as a scan signal in response to a voltage of the reset node.

[0017] The plurality of stages may include a first stage including a first transistor and a second stage including a second transistor.

[0018] The first output section of the first stage may include a first transistor, and the first output section of the second stage may include a second transistor.

[0019] The second output section of the first stage may include a first transistor, and the second output section of the second stage may include a second transistor.

[0020] The first output section may include a first transistor, and the second output section may include a second transistor.

[0021] According to an embodiment, a scan driver may include: a substrate; a first active pattern located on the substrate, the first active pattern including a first area, a second area, and a first channel area located between the first area and the second area; a first gate electrode located on the first active pattern; a second active pattern located on the first gate electrode, the second active pattern including a third area, a fourth area, and a second channel area located between the third area and the fourth area; a second gate electrode located on the second active pattern; a first electrode and a second electrode located on the second gate electrode, the first electrode and the second electrode being electrically connected to the first area and the second area, respectively; and a third electrode and a fourth electrode located on the same layer as the first electrode and the second electrode, the third electrode and the fourth electrode being electrically connected to the third area and the fourth area, respectively, wherein the first electrode is formed integrally with the third electrode.

[0022] The second electrode may be formed integrally with the fourth electrode.

[0023] The first active pattern may include a first overlapping portion, a first protruding portion protruding from the first overlapping portion in a first direction and connected to the first electrode, and a second protruding portion protruding from the first overlapping portion in a second direction and connected to the second electrode.

[0024] The second active pattern may include a second overlapping portion overlapping the first overlapping portion, a third protruding portion protruding from the second overlapping portion in the first direction and connected to the third electrode, and a fourth protruding portion protruding from the second overlapping portion in the second direction and connected to the fourth electrode.

[0025] The third protrusion portion may not overlap with the first protrusion portion, and the fourth protrusion portion may not overlap with the second protrusion portion.

[0026] The second gate electrode may overlap the first gate electrode.

[0027] The scan driver may further include a shielding electrode between the first gate electrode and the second active pattern.

[0028] A width of the shielding electrode may be greater than a width of the first gate electrode.

[0029] According to an embodiment, a display device may include: a display unit including: a driving transistor including a driving active pattern and a driving gate electrode; and a switching transistor located on the driving transistor, the switching transistor including a switching active pattern and a switching gate electrode; and a scan driver for supplying a scan signal to the display unit and including: a first transistor including a first active pattern and a first gate electrode, the first active pattern including a first region, a second region, and a first channel region located between the first region and the second region; and a second transistor located on the first transistor, the second transistor including a second active pattern and a second gate electrode, the second active pattern including a third region, a fourth region, and a second channel region located between the third region and the fourth region.

[0030] The first active pattern and the first gate electrode of the first transistor may be located on the same layer as the driving active pattern and the driving gate electrode of the driving transistor, respectively.

[0031] The second active pattern and the second gate electrode of the second transistor may be located on the same layer as the switching active pattern and the switching gate electrode of the switching transistor, respectively.

[0032] The display unit may further include a storage capacitor including a first storage electrode integrally formed with the driving gate electrode and a second storage electrode between the driving transistor and the switching transistor, and the scan driver may further include a shielding electrode between the first transistor and the second transistor.

[0033] The shielding electrode may be located on the same layer as the second storage electrode.

[0034] The display unit may further include: a programming capacitor, including a first programming electrode located on the switching transistor and a second programming electrode located on the first programming electrode, and the scan driver may further include a first electrode, a second electrode, a third electrode and a fourth electrode located on the second transistor, the first electrode, the second electrode, the third electrode and the fourth electrode being electrically connected to the first region, the second region, the third region and the fourth region, respectively.

[0035] The first electrode, the second electrode, the third electrode, and the fourth electrode may be located on the same layer as one of the first programming electrode and the second programming electrode.

[0036] The display device may further include a pixel electrode electrically connected to the second programming electrode, an organic light emitting layer on the pixel electrode, and a common electrode on the organic light emitting layer.

[0037] The scan driver according to some of the embodiments may include a first transistor and a second transistor, which overlap each other and are electrically connected to each other through electrodes located on the first transistor and the second transistor. Therefore, the scan driver may occupy a small area.

[0038] According to some embodiments of the present invention, the display device may include a scan driver and a display unit, the scan driver includes a first transistor and a second transistor overlapping each other, and the display unit includes a driving transistor and a switch transistor overlapping each other. Therefore, a high-definition display device can be implemented, and a dead zone of the display device can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0040] Figure 1 is a block diagram illustrating a display device according to an embodiment.

[0041] Figure 2 It is shown in Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0042] Figure 3 It is shown in Figure 1 A cross-sectional view of an example of a display unit included in a display device.

[0043] Figure 4 It is shown in Figure 1 A block diagram of an example of a scan driver included in a display device in FIG.

[0044] Figure 5 It is shown in Figure 4 A circuit diagram of an example of a stage included in a scan driver.

[0045] Figure 6 is a plan view illustrating a scan driver according to an embodiment.

[0046] Figure 7 It is shown in Figure 6 A plan view of a first active pattern included in a scan driver in FIG.

[0047] Figure 8 It is shown in Figure 6 A plan view of a second active pattern included in a scan driver in FIG.

[0048] Fig. 9 is along Figure 6 A cross-sectional view taken along line II' in FIG.

[0049] Fig.10 is a plan view illustrating a scan driver according to an embodiment.

[0050] Fig.11 is along Fig.10 A cross-sectional view taken along line II-II'.

[0051] Fig.12 is a block diagram illustrating a display device according to an embodiment.

[0052] Fig.13 is a block diagram illustrating an electronic device including a display device according to an embodiment.

[0053] Fig.14 It is a diagram of Fig.13 A diagram of an example in which an electronic device is implemented as a head-mounted display (HMD). DETAILED DESCRIPTION

[0054] By referring to the detailed description and drawings of the embodiments, the features of the inventive concept and its implementation method can be more easily understood. Hereinafter, the embodiments will be described in more detail with reference to the drawings. However, the described embodiments can be embodied in various different forms and should not be interpreted as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects and features of the inventive concept will be fully conveyed to those skilled in the art. Therefore, it may not be described that the processes, elements and techniques that are unnecessary for those of ordinary skill in the art to fully understand the aspects and features of the inventive concept. Unless otherwise stated, throughout the drawings and written descriptions, the same reference numerals represent the same elements, and therefore, their descriptions are not repeated. In addition, parts that are not related to the description of the embodiments may not be shown to make the description clear. In the drawings, for clarity, the relative sizes of elements, layers and regions may be magnified.

[0055] Various embodiments are described herein with reference to cross-sectional views, which are schematic diagrams of embodiments and / or intermediate structures. As such, variations from the illustrated shapes due to, for example, manufacturing techniques and / or deviations can be expected. In addition, the specific structural or functional descriptions disclosed herein are merely illustrative, for the purpose of describing embodiments according to the concepts of the present disclosure. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the specific regional shapes shown, but rather include deviations in shape caused by, for example, manufacturing. For example, an implanted region shown as a rectangle will typically have circular or arc-shaped features and / or a gradient of implant concentration at its edge, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device, and are not intended to be limiting. In addition, as will be appreciated by those skilled in the art, the described embodiments may be modified in a variety of different ways, all without departing from the spirit or scope of the present disclosure.

[0056] In the detailed description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various embodiments. However, it is apparent that various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessary obfuscation of various embodiments.

[0057] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part without departing from the spirit and scope of the present disclosure.

[0058] In addition, for the purpose of ease of explanation, spatial relative terms such as "below", "below", "down", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature relative to another element or feature as illustrated in the accompanying drawings. It should be understood that spatial relative terms are intended to include different orientations of the device in use or operation other than the orientation depicted in the accompanying drawings. For example, if the device is flipped in the accompanying drawings, the elements described as "below", "below" or "below" other elements or features will be oriented to be "above" other elements or features. Therefore, the exemplary terms "below" and "below" may include both above and below. The device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first component is described as being arranged "on" a second component, this indicates that the first component is arranged on the upper or lower side of the second component, and is not limited to the upper side of the second component based on the direction of gravity.

[0059] It should be understood that when an element, layer, region or component is referred to as being "on", "connected to" or "coupled to" another element, layer, region or component, it may be directly on, directly connected to or coupled to another element, layer, region or component, or one or more intermediate elements, layers, regions or components may exist. However, "directly connected / directly coupled" refers to a component directly connected or coupled to another component without the presence of intermediate components. At the same time, other expressions such as "between...", "close to..." or "adjacent to..." and "directly adjacent to..." that describe the relationship between components may be similarly interpreted. In addition, it should also be understood that when an element or layer is referred to as being "between" two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also exist.

[0060] For purposes of this disclosure, expressions such as "at least one of," when following a list of elements, modify the entire list of elements, and not the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. The same reference numerals refer to the same elements throughout. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0061] The terms used herein are only used to describe specific embodiments and are not intended to limit the present disclosure. As used herein, the singular form "a" is intended to also include the plural form, unless the context clearly states otherwise. It will be further understood that when used in this specification, the terms "include", "comprise" and "have" indicate the presence of stated features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0062] As used herein, the terms "substantially," "approximately," "approximately," and similar terms are used as terms of approximation rather than terms of degree, and are intended to encompass the inherent deviations in measured or calculated values ​​recognized by those of ordinary skill in the art. As used herein, "approximately" or "approximately" includes the stated value and refers to being within an acceptable range of deviations of a particular value as determined by one of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "approximately" may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Further, when describing the various embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0063] When a specific embodiment can be implemented in different ways, the specific process can be performed in a different order from the described order. For example, two processes described in succession can be performed substantially at the same time, or in a reverse order from the described order.

[0064] The electrical or electronic device and / or any other related device or component according to the various embodiments of the present disclosure described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or a separate IC chip. In addition, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. In addition, the various components of these devices can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform various functions described herein. Computer program instructions are stored in a memory that can be implemented in a computing device using a standard storage device, such as a random access memory (RAM). Computer program instructions can also be stored in other non-temporary computer-readable media, such as a CD-ROM, a flash drive, etc. In addition, those skilled in the art will recognize that the functions of each computing device can be combined or integrated into a single computing device, or the functions of a specific computing device can be distributed between one or more other computing devices without departing from the spirit and scope of the various embodiments of the present disclosure.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meanings as commonly understood by those of ordinary skill in the art to which the inventive concept belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such in this article.

[0066] Figure 1 is a block diagram illustrating a display apparatus 100 according to an embodiment.

[0067] refer to Figure 1 , the display device 100 may include a display unit 110, a data driver 130 that provides a data signal to the display unit 110, a scan driver 150 that provides a scan signal to the display unit 110, and a signal source 170 that provides a signal to the display unit 110. In an embodiment, the display device 100 may further include a controller (e.g., a timing controller) 190 that controls the data driver 130, the scan driver 150, and the signal source 170.

[0068] The display unit 110 may include a plurality of data lines DL1, ..., DLm, ..., DLM, a plurality of scan lines SL1, ..., SLn, ..., SLN, and a plurality of pixels PX connected to the data lines DL1, ..., DLm, ..., DLM and the scan lines SL1, ..., SLn, ..., SLN. In an embodiment, the display device 100 may be an organic light emitting display device in which each pixel PX includes an organic light emitting diode, but is not limited thereto. For example, the display device 100 may be a liquid crystal display (LCD) device, etc.

[0069] Figure 2 It is shown in Figure 1 1 is a circuit diagram of an example of a pixel PX included in the display device 100.

[0070] refer to Figure 2 In an embodiment, each pixel PX may have a 3T2C structure including three transistors TD, TS1 and TS2 and two capacitors Cst and Cpr. For example, each pixel PX may include a driving transistor TD, a first switching transistor TS1, a second switching transistor TS2, a storage capacitor Cst, a programming capacitor Cpr, and an organic light emitting diode OLED.

[0071] The storage capacitor Cst may have a first electrode receiving the first driving signal Vinit and a second electrode connected to the first node N1.

[0072] The driving transistor TD may have a gate connected to the first node N1 , a source receiving the first power signal ELVDD, and a drain connected to the organic light emitting diode OLED.

[0073] The first switching transistor TS1 may have a gate receiving the scan signal SCAN, a source connected to the second node N2 , and a drain connected to the first node N1 .

[0074] The second switching transistor TS2 may have a gate receiving the second driving signal GC, a source connected to the second node N2 , and a drain connected to the drain of the driving transistor TD.

[0075] The programming capacitor Cpr may have a first electrode receiving the data signal DATA and a second electrode connected to the second node N2.

[0076] The organic light emitting diode OLED may have an anode connected to the drain of the driving transistor TD and a cathode receiving the second power signal ELVSS.

[0077] although Figure 2 An example of a pixel PX having a 3T2C structure is illustrated, but the structure of the pixel PX of the display device 100 according to the embodiment is not limited to the 3T2C structure. For example, the pixel PX may have another 3T2C structure having the same Figure 2 Examples of the connections are different from those of the connections of the transistors 1 and 2, or the pixel PX may have any structure including two or more transistors and one or more capacitors.

[0078] In an embodiment, the display device 100 may be driven in a concurrent (eg, simultaneous or substantially simultaneous) driving manner in which each frame includes a concurrent compensation period, a data programming period, and a concurrent emission period.

[0079] In the concurrent compensation period, the plurality of pixels PX may concurrently (or simultaneously) perform a threshold voltage compensation operation. For example, in the concurrent compensation period, the plurality of scan signals SCAN and the second drive signal GC may be applied to the plurality of pixels PX, the first switch transistors TS1 and the second switch transistors TS2 of the plurality of pixels PX may be turned on in response to the plurality of scan signals SCAN and the second drive signal GC, and the drive transistors TD of the plurality of pixels PX may be diode-connected through the turned-on first switch transistors TS1 and the second switch transistors TS2 to store the threshold voltage of the drive transistor TD in the storage capacitor Cst.

[0080] In the data programming period, the data signal DATA is sequentially written to the plurality of pixels PX row by row. For example, in the data programming period, the plurality of scan signals SCAN may be sequentially applied to the plurality of pixels PX row by row, the first switch transistor TS1 of each pixel PX may be turned on in response to the scan signal SCAN, and the data signal DATA may be stored by charge sharing between the programming capacitor Cpr and the storage capacitor Cst in each pixel PX. Since the threshold voltage has been stored in the storage capacitor Cst of each pixel PX in the concurrent compensation period, the data signal DATA in which the threshold voltage is compensated may be stored in the storage capacitor Cst in the data programming period.

[0081] In the concurrent emission period, the plurality of pixels PX may emit light concurrently (or simultaneously). For example, in the concurrent emission period, the driving transistors TD of the plurality of pixels PX may generate a driving current based on the data signal DATA in which the threshold voltage is compensated and stored in the storage capacitor Cst, and the organic light emitting diodes OLED of the plurality of pixels PX may emit light concurrently (or simultaneously) based on the driving current.

[0082] Figure 3 It is shown in Figure 1 1 is a cross-sectional view of an example of a display unit 110 included in a display device 100. For example, Figure 3 Can be illustrated Figure 2 An example of a pixel PX shown in FIG.

[0083] refer to Figure 3 , the driving transistor TD, the first switching transistor TS1 , the second switching transistor TS2 , the storage capacitor Cst, the programming capacitor Cpr, and the organic light emitting diode OLED may be located on the substrate 310 in the display unit 110 .

[0084] The first insulating layer IL1 may be formed on the substrate 310. The substrate 310 may be an insulating substrate including one or more of glass, crystal, ceramic, plastic, etc. The first insulating layer IL1 may block impurities from the substrate 310 during a crystallization process for forming polysilicon to improve the characteristics of the polysilicon, and the first insulating layer IL1 may provide a planarized surface on the first insulating layer IL1.

[0085] A first active layer including a driving active pattern 320a may be formed on the first insulating layer IL1. The driving active pattern 320a may include a driving channel region 321a and driving source and drain regions 323a and 325a formed therebetween.

[0086] A second insulating layer IL2 covering the driving active pattern 320a may be formed on the driving active pattern 320a. A first conductive layer including a driving gate electrode 331a may be formed on the second insulating layer IL2. The driving gate electrode 331a may overlap the driving channel region 321a. The driving gate electrode 331a may form a driving transistor TD together with the driving active pattern 320a.

[0087] A third insulating layer IL3 covering the driving gate electrode 331a may be formed on the driving gate electrode 331a. A second conductive layer including a second storage electrode 341 may be formed on the third insulating layer IL3. The second storage electrode 341 may be wider than the first storage electrode 331a serving as the driving gate electrode. The second storage electrode 341 may form a storage capacitor Cst together with the first storage electrode 331a.

[0088] A fourth insulating layer IL4 covering the second storage electrode 341 may be formed on the second storage electrode 341. A fifth insulating layer IL5 may be formed on the fourth insulating layer IL4. The fifth insulating layer IL5 may block impurities during a crystallization process for forming polysilicon to improve characteristics of polysilicon, and the fifth insulating layer IL5 may provide a planarized surface on the fifth insulating layer IL5.

[0089] A second active layer including a first switch active pattern 350b and a second switch active pattern 350c may be formed on the fifth insulating layer IL5. The first switch active pattern 350b may include a first switch channel region 351b and a first switch source region 353b and a first switch drain region 355b, and the first switch channel region 351b is formed between the first switch source region 353b and the first switch drain region 355b. The second switch active pattern 350c may include a second switch channel region 351c and a second switch source region 353c and a second switch drain region 355c, and the second switch channel region 351c is formed between the second switch source region 353c and the second switch drain region 355c.

[0090] The driving active pattern 320a and the second active layer may be formed of polysilicon or an oxide semiconductor. The oxide semiconductor may include an oxide based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In).

[0091] A sixth insulating layer IL6 covering the second active layer may be formed on the second active layer. Contact holes CH1, CH2, CH3, and CH4 may be formed in the sixth insulating layer IL6. A third conductive layer including a first switch gate electrode 361b, a second switch gate electrode 361c, a first connection pattern 363, and a second connection pattern 365 may be formed on the sixth insulating layer IL6.

[0092] The first switch gate electrode 361b and the second switch gate electrode 361c may overlap the first switch channel region 351b and the second switch channel region 351c, respectively. The first switch gate electrode 361b may form a first switch transistor TS1 together with the first switch active pattern 350b. The second switch gate electrode 361c may form a second switch transistor TS2 together with the second switch active pattern 350c. The first connection pattern 363 may be connected to the first switch source region 353b through a first contact hole CH1 formed in the sixth insulating layer IL6, and may be connected to the second switch source region 353c through a second contact hole CH2 formed in the sixth insulating layer IL6. The second connection pattern 365 may be connected to the drive gate electrode 331a through a third contact hole CH3 formed in the third insulating layer IL3, the fourth insulating layer IL4, the fifth insulating layer IL5, and the sixth insulating layer IL6, and may be connected to the first switch drain region 355b through a fourth contact hole CH4 formed in the sixth insulating layer IL6.

[0093] The driving gate electrode 331a, the second storage electrode 341, and the third conductive layer may be formed of copper (Cu), a copper alloy, aluminum (Al), an aluminum alloy, molybdenum (Mo), and / or a molybdenum alloy.

[0094] The first switch transistor TS1 and / or the second switch transistor TS2 may overlap with the drive transistor TD. In an embodiment, both the first switch transistor TS1 and the second switch transistor TS2 may overlap with the drive transistor TD. However, the present embodiment is not limited thereto, and in other embodiments, only one of the first switch transistor TS1 and the second switch transistor TS2 may overlap with the drive transistor TD.

[0095] A seventh insulating layer IL7 covering the third conductive layer may be formed on the third conductive layer. A fourth conductive layer including the data line 371 may be formed on the seventh insulating layer IL7.

[0096] An eighth insulating layer IL8 covering the data line 371 may be formed on the data line 371. Contact holes CH5, CH6, CH7, and CH8 may be formed in the eighth insulating layer IL8. A fifth conductive layer including a first power signal line 381 and a second programming electrode 383 may be formed on the eighth insulating layer IL8.

[0097] The first power signal line 381 may be connected to the driving source region 323a through a fifth contact hole CH5 formed in the second insulating layer IL2, the third insulating layer IL3, the fourth insulating layer IL4, the fifth insulating layer IL5, the sixth insulating layer IL6, the seventh insulating layer IL7, and the eighth insulating layer IL8. The second programming electrode 383 may overlap with the first programming electrode 371 used as a data line. The second programming electrode 383 may form a programming capacitor Cpr together with the first programming electrode 371. The second programming electrode 383 may be connected to the second switching drain region 355c through a sixth contact hole CH6 formed in the sixth insulating layer IL6, the seventh insulating layer IL7, and the eighth insulating layer IL8, may be connected to the driving drain region 325a through a seventh contact hole CH7 formed in the second insulating layer IL2, the third insulating layer IL3, the fourth insulating layer IL4, the fifth insulating layer IL5, the sixth insulating layer IL6, the seventh insulating layer IL7, and the eighth insulating layer IL8, and may be connected to the first connection pattern 363 through an eighth contact hole CH8 formed in the seventh insulating layer IL7 and the eighth insulating layer IL8.

[0098] The first insulating layer IL1, the second insulating layer IL2, the third insulating layer IL3, the fourth insulating layer IL4, the fifth insulating layer IL5, the sixth insulating layer IL6, the seventh insulating layer IL7 and the eighth insulating layer IL8 may be formed of silicon nitride, silicon oxide, etc. The data line 371 and the fifth conductive layer may be formed of copper (Cu), copper alloy, aluminum (Al), aluminum alloy, molybdenum (Mo) and / or molybdenum alloy. For example, the data line 371 and the fifth conductive layer may be formed of a triple layer of titanium / aluminum / titanium (Ti / Al / Ti), a triple layer of molybdenum / aluminum / molybdenum (Mo / Al / Mo) or a triple layer of molybdenum / copper / molybdenum (Mo / Cu / Mo).

[0099] A ninth insulating layer IL9 covering the fifth conductive layer may be formed on the fifth conductive layer. The ninth insulating layer IL9 may cover the fifth conductive layer to perform planarization on the fifth conductive layer. The ninth insulating layer IL9 may be formed of a stacked layer of an organic material such as a polyacrylate resin, a polyimide resin, etc., or a stacked layer of an organic material and an inorganic material.

[0100] The pixel electrode 391 may be formed on the ninth insulating layer IL9. The pixel electrode 391 may be connected to the second programming electrode 383 through a contact hole formed in the ninth insulating layer IL9.

[0101] A tenth insulating layer IL10 covering an edge of the pixel electrode 391 may be formed on the edge of the pixel electrode 391. The tenth insulating layer IL10 may have an opening exposing the pixel electrode 391. The tenth insulating layer IL10 may be formed of an organic material such as polyacrylate resin, polyimide resin, etc., or a silicon dioxide-based inorganic material.

[0102] An organic light emitting layer 392 may be formed on the pixel electrode 391 exposed by the opening, and a common electrode 393 may be formed on the organic light emitting layer 392. The common electrode 393 may also be formed on the tenth insulating layer IL10 and may be formed across a plurality of pixels PX. The organic light emitting layer 392 and the common electrode 393 may form an organic light emitting diode OLED together with the pixel electrode 391.

[0103] In an embodiment, the pixel electrode 391 may be an anode of the organic light emitting diode OLED, and the common electrode 393 may be a cathode of the organic light emitting diode OLED. However, the present embodiment is not limited thereto, and in other embodiments, according to a driving method, the pixel electrode 391 may be a cathode of the organic light emitting diode OLED, and the common electrode 393 may be an anode of the organic light emitting diode OLED. When holes and electrons are injected into the organic light emitting layer 392 from the pixel electrode 391 and the common electrode 393, respectively, and the excitons obtained by combining the injected holes and electrons drop from an excited state to a ground state, light may be emitted.

[0104] The organic light emitting layer 392 may be formed of a low molecular weight organic material or a high molecular weight organic material such as poly-3,4-ethylenedioxythiophene (PEDOT). The organic light emitting layer 392 may be formed of a plurality of layers including at least one of an emission layer, a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0105] like Figure 3 As shown in , the driving active pattern 320a and the second active layer located in different layers from each other may be formed in the display unit 110. Therefore, the transistors TD, TS1, and TS2 included in the pixel PX may overlap with each other. Therefore, the area occupied by the transistors TD, TS1, and TS2 may be reduced, the area of ​​the pixel PX may be reduced, and the display device 100 with high resolution in which the display unit 110 includes more pixels PX in a unit area may be implemented.

[0106] Reference again Figure 1 , the data driver 130 may output the data signal DATA to the data lines DL1, ..., DLm, ..., DLM based on the data control signal and the image data from the controller 190. In an embodiment, the data driver 130 may provide the data signal DATA to the plurality of pixels PX through the data lines DL1, ..., DLm, ..., DLM in a data programming period.

[0107] The scan driver 150 may output the scan signal SCAN to the scan lines SL1, ..., SLn, ..., SLN based on the gate control signal from the controller 190. In an embodiment, the gate control signal may include a start signal FLM, an input clock signal ICK, and a concurrent drive signal GCK. In an embodiment, the scan driver 150 may provide the scan signal SCAN concurrently (or simultaneously) to a plurality of pixels PX through the scan lines SL1, ..., SLn, ..., SLN in response to the concurrent drive signal GCK during the concurrent compensation period, and may sequentially provide the scan signal SCAN to a plurality of pixels PX row by row through the scan lines SL1, ..., SLn, ..., SLN in response to the start signal FLM and the input clock signal ICK during the data programming period.

[0108] The signal source 170 may supply the first power signal ELVDD, the second power signal ELVSS, the first driving signal Vinit, and the second driving signal GC to the display unit 110 based on the signal supply control signal from the controller 190 .

[0109] Figure 4 It is shown in Figure 1 1 is a block diagram of an example of a scan driver 150 included in the display device 100 in FIG.

[0110] refer to Figure 4 , the scan driver 150 can receive the start signal FLM, the first to fourth input clock signals ICLK1, ICLK2, ICLK3 and ICLK4 and the concurrent driving signal GCK, and can include a plurality of stages 410, 420, 430, 440 and 450 that output a plurality of scan signals SCAN1, SCAN2, SCAN3, SCAN4 and SCAN5 to the scan lines SL1, ..., SLn, ..., SLN, respectively.

[0111] Each stage 410, 420, 430, 440, and 450 may receive a start signal FLM or a previous scan signal as an input signal IN. For example, the first stage 410 may receive the start signal FLM as the input signal IN, and the other stages 420, 430, 440, and 450 may receive scan signals SCAN1, SCAN2, SCAN3, and SCAN4 of their respective previous stages 410, 420, 430, and 440 as input signals IN.

[0112] Furthermore, four adjacent stages (eg, 410 , 420 , 430 , and 440 ) may receive different groups of three signals among the sequentially activated first to fourth input clock signals ICLK1 , ICLK2 , ICLK3 , and ICLK4 as first to third clock signals CLK1 , CLK2 , and CLK3 . For example, the first stage 410 can receive the first to third input clock signals ICLK1, ICLK2 and ICLK3 as the first to third clock signals CLK1, CLK2 and CLK3, respectively, the second stage 420 can receive the second to fourth input clock signals ICLK2, ICLK3 and ICLK4 as the first to third clock signals CLK1, CLK2 and CLK3, respectively, the third stage 430 can receive the third input clock signal ICLK3, the fourth input clock signal ICLK4 and the first input clock signal ICLK1 as the first to third clock signals CLK1, CLK2 and CLK3, respectively, and the fourth stage 440 can receive the fourth input clock signal ICLK4, the first input clock signal ICLK1 and the second input clock signal ICLK2 as the first to third clock signals CLK1, CLK2 and CLK3, respectively. Similar to the first stage 410 , the fifth stage 450 may receive the first to third input clock signals ICLK1 , ICLK2 , and ICLK3 as the first to third clock signals CLK1 , CLK2 , and CLK3 , respectively.

[0113] In an embodiment, in a data programming period, each stage 410, 420, 430, 440 and 450 may receive an input signal IN in response to a pulse of the second clock signal CLK2, and may output a next pulse of the third clock signal CLK3 as scan signals SCAN1, SCAN2, SCAN3, SCAN4 and SCAN5.

[0114] For example, the first stage 410 may output the next pulse of the third input clock signal ICLK3 as the first scan signal SCAN1, then the second stage 420 may output the next pulse of the fourth input clock signal ICLK4 as the second scan signal SCAN2, then the third stage 430 may output the next pulse of the first input clock signal ICLK1 as the third scan signal SCAN3, then the fourth stage 440 may output the next pulse of the second input clock signal ICLK2 as the fourth scan signal SCAN4, and then the fifth stage 450 may output the next pulse of the third input clock signal ICLK3 as the fifth scan signal SCAN5. In this manner, the plurality of stages 410, 420, 430, 440, and 450 may sequentially output the plurality of scan signals SCAN1, SCAN2, SCAN3, SCAN4, and SCAN5 in response to the sequentially activated input clock signals ICLK1, ICLK2, ICLK3, and ICLK4.

[0115] In an embodiment, in the concurrent compensation period, the plurality of stages 410 , 420 , 430 , 440 , and 450 may concurrently receive the concurrent driving signal GCK and may concurrently output the plurality of scan signals SCAN1 , SCAN2 , SCAN3 , SCAN4 , and SCAN5 in response to the concurrent driving signal GCK.

[0116] Figure 5 It is shown in Figure 4 1 is a circuit diagram of an example of stages included in the scan driver 150 in FIG.

[0117] refer to Figure 5 , each stage included in the scan driver 150 may include a first input section 510 , a second input section 520 , a first output section 530 , and a second output section 540 . In an embodiment, each stage may further include a holding section 550 , a concurrent driving control section 560 , and a stabilizing section 570 .

[0118] The first input section 510 may transmit the input signal IN to the set node NQ in response to the second clock signal CLK2. For example, the first input section 510 of the first stage 410 may receive the start signal FLM as the input signal IN, and the first input section 510 of each of the remaining stages may receive the previous scan signal PSCAN as the input signal IN. In an embodiment, the first input section 510 may include a first input transistor T510 including a gate receiving the second clock signal CLK2, a first terminal receiving the input signal IN, and a second terminal connected to the set node NQ.

[0119] The second input unit 520 can transmit the first clock signal CLK1 to the reset node NQB in response to the input signal IN and the second clock signal CLK2. For example, when the input signal IN and the second clock signal CLK2 have a valid level (or Figure 5 When the second input unit 520 has a non-effective level (or Figure 5 The first clock signal CLK1 (a high level in the example) is transmitted to the reset node NQB. In an embodiment, the second input unit 520 may include a second input transistor T521, which includes a gate receiving the input signal IN, a first terminal receiving the first clock signal CLK1, and a second terminal, and may also include a third input transistor T522, the second input transistor T521 includes a gate receiving the input signal IN, a first terminal receiving the first clock signal CLK1, and a second terminal, the third input transistor T522 includes a gate receiving the second clock signal CLK2, a first terminal connected to the second terminal of the second input transistor T521, and a second terminal connected to the reset node NQB.

[0120] The holding section 550 may hold the voltage of the reset node NQB in response to the first clock signal CLK1. For example, when the first clock signal CLK1 has a low level, the holding section 550 may hold the voltage of the reset node NQB at a low level. In an embodiment, the holding section 550 may include a holding transistor T550 including a gate receiving the first clock signal CLK1, a first terminal receiving the first clock signal CLK1, and a second terminal connected to the reset node NQB.

[0121] The concurrent drive control section 560 may deactivate the first output section 530 in response to the concurrent drive signal GCK. In an embodiment, the concurrent drive signal GCK may have a low level in the concurrent compensation period, and may have a high level in the remaining period (e.g., the data programming period and the concurrent emission period). In the concurrent compensation period, the concurrent drive control section 560 may transmit a gate-off voltage VGH (or a high gate voltage VGH) having a high level to the set node NQ in response to the concurrent drive signal GCK. The first output section 530 may be deactivated by the gate-off voltage VGH of the set node NQ. In an embodiment, the concurrent drive control section 560 may include a concurrent drive control transistor T560, which includes a gate receiving the concurrent drive signal GCK, a first terminal receiving the gate-off voltage VGH, and a second terminal connected to the set node NQ.

[0122] The stabilizing unit 570 may stabilize the scan signal SCAN in response to the voltage of the reset node NQB and the third clock signal CLK3. For example, when the voltage of the reset node NQB and the third clock signal CLK3 have a low level, the stabilizing unit 570 may stabilize the scan signal SCAN to a high level. In an embodiment, the stabilizing unit 570 may include a first stabilizing transistor T571, which includes a gate receiving the third clock signal CLK3, a first terminal connected to the set node NQ, and a second terminal, and the second stabilizing transistor T572 includes a gate connected to the reset node NQB, a first terminal connected to the second terminal of the first stabilizing transistor T571, and a second terminal connected to the output node NO.

[0123] The first output unit 530 may output the third clock signal CLK3 as the scan signal SCAN in response to the voltage of the set node NQ. For example, in the data programming period, the input signal IN having a low level may be transmitted to the set node NQ in response to the pulse of the second clock signal CLK2, and then the voltage of the set node NQ may be boosted to a level lower than the low level at the next pulse of the third clock signal CLK3 by the first output capacitor C530 of the first output unit 530. In an embodiment, the first output unit 530 may include a first output transistor T530, and may further include a first output capacitor C530, the first output transistor T530 including a gate connected to the set node NQ, a first terminal receiving the third clock signal CLK3, and a second terminal connected to the output node NO, and the first output capacitor C530 including a first electrode connected to the set node NQ and a second electrode connected to the output node NO.

[0124] The second output unit 540 may output the concurrent drive signal GCK as the scan signal SCAN in response to the voltage of the reset node NQB. For example, in the concurrent compensation period, when the concurrent drive signal GCK changes from a high level to a low level, the voltage of the reset node NQB may be boosted to a level lower than the low level by the second output capacitor C540 of the second output unit 540. The second output transistor T540 of the second output unit 540 may output the concurrent drive signal GCK having a low level as the scan signal SCAN in response to the boosted voltage of the reset node NQB. In an embodiment, the second output unit 540 may include a second output transistor T540, and may further include a second output capacitor C540, the second output transistor T540 including a gate connected to the reset node NQB, a first terminal receiving the concurrent drive signal GCK, and a second terminal connected to the output node NO, and the second output capacitor C540 including a first electrode connected to the reset node NQB and a second electrode receiving the concurrent drive signal GCK.

[0125] Figure 6 is a plan view illustrating a scan driver 150 according to an embodiment. Figure 7 It is shown in Figure 6 FIG. 1 is a plan view of a first active pattern included in a scan driver 150 in FIG. Figure 8 It is shown in Figure 6 1 is a plan view of a second active pattern included in the scan driver 150 in FIG. Fig. 9 is along Figure 6 A cross-sectional view taken along line II' in FIG.

[0126] refer to Figure 6 , Figure 7 , Figure 8 and Fig. 9, the scan driver 150 may include a first transistor T1 located on the substrate 310 and a second transistor T2 located on and overlapping the first transistor T1. In an embodiment, the scan driver 150 may further include a shielding electrode 343 located between the first transistor T1 and the second transistor T2.

[0127] like Fig. 9 As shown in FIG. 1 , a first active pattern 320d including a first channel region 321d and a first region 323d and a second region 325d (wherein the first channel region 321d is formed between the first region 323d and the second region 325d) may be formed on the first insulating layer IL1. The first active layer may include the first active pattern 320d and a driving active pattern 320a formed in the display unit 110. For example, the first region 323d and the second region 325d may be a source region and a drain region of the first active pattern 320d, respectively.

[0128] like Figure 7 As shown in , the first active pattern 320d may include a first overlapping portion OP1, a first protruding portion PP1, and a second protruding portion PP2. The first protruding portion PP1 and the second protruding portion PP2 may protrude from the first overlapping portion OP1. For example, the first protruding portion PP1 may protrude from the first overlapping portion OP1 in a first direction D1, and the second protruding portion PP2 may protrude from the first overlapping portion OP1 in a second direction D2 opposite to the first direction D1. The first protruding portion PP1 may be formed in the first region 323d, and the second protruding portion PP2 may be formed in the second region 325d.

[0129] like Fig. 9 As shown in FIG. 1 , a first gate electrode 331d overlapping the first channel region 321d may be formed on the second insulating layer IL2. The first conductive layer may include the first gate electrode 331d and the driving gate electrode 331a formed in the display unit 110. The first gate electrode 331d may form a first transistor T1 together with the first active pattern 320d. The first transistor T1 may have a dual gate structure, such as Figure 6 and Fig. 9 However, the present embodiment is not limited thereto, and the first transistor T1 may have a single gate structure.

[0130] A shielding electrode 343 overlapping the first gate electrode 331d may be formed on the third insulating layer IL3. The second conductive layer may include the shielding electrode 343 and the second storage electrode 341 formed in the display unit 110. The shielding electrode 343 may be located between the stacked first transistor T1 and the second transistor T2. Therefore, the shielding electrode 343 may minimize or reduce the effects such as parasitic capacitance, kick back, etc. between the first transistor T1 and the second transistor T2.

[0131] In an embodiment, the width of the shielding electrode 343 may be greater than the width of the first gate electrode 331d. For example, the width of the shielding electrode 343 may be greater than the sum of the widths of the two regions of the first gate electrode 331d having a double-gate structure. Therefore, the shielding electrode 343 may completely cover the first gate electrode 331d. The width of the shielding electrode 343 may be greater than the width of the first gate electrode 331d, and therefore, the influence between the first transistor T1 and the second transistor T2 may be further reduced.

[0132] In an embodiment, a voltage for controlling the characteristics of the second transistor T2 may be applied to the shielding electrode 343. For example, the driving range, s factor, etc. of the second transistor T2 may be controlled by the voltage applied to the shielding electrode 343. When the characteristics of the first transistor T1 and the characteristics of the second transistor T2 are substantially the same or similar, the influence between the first transistor T1 and the second transistor T2 may be reduced or minimized. Therefore, the characteristics of the second transistor T2 may be controlled by applying a voltage to the shielding electrode 343, and therefore, the influence between the first transistor T1 and the second transistor T2 may be controlled.

[0133] In an embodiment, when a negative voltage is applied to the shielding electrode 343, the driving range of the second transistor T2 may be widened, and when a positive voltage is applied to the shielding electrode 343, the driving range of the second transistor T2 may be narrowed. Therefore, when the driving range of the second transistor T2 is narrower than the driving range of the first transistor T1, a negative voltage may be applied to the shielding electrode 343, and when the driving range of the second transistor T2 is wider than the driving range of the first transistor T1, a positive voltage may be applied to the shielding electrode 343, thereby reducing the influence between the first transistor T1 and the second transistor T2.

[0134] A second active pattern 350e including a second channel region 351e and third and fourth regions 353e and 355e (wherein the second channel region 351e is formed between the third and fourth regions 353e and 355e) may be formed on the fifth insulating layer IL5. The second active layer may include the second active pattern 350e and the first and second switching active patterns 350b and 350c formed in the display unit 110. For example, the third and fourth regions 353e and 355e may be the source and drain regions of the second active pattern 350e, respectively.

[0135] like Fig. 9 As shown in , the second active pattern 350e may overlap the first active pattern 320d. Figure 8 As shown in , the second active pattern 350e may include a second overlapping portion OP2, a third protruding portion PP3, and a fourth protruding portion PP4. The second overlapping portion OP2 of the second active pattern 350e may overlap the first overlapping portion OP1 of the first active pattern 320d. The third protruding portion PP3 and the fourth protruding portion PP4 may protrude from the second overlapping portion OP2. For example, the third protruding portion PP3 may protrude from the second overlapping portion OP2 in the first direction D1, and the fourth protruding portion PP4 may protrude from the second overlapping portion OP2 in the second direction D2. The third protruding portion PP3 may be formed in the third region 353e, and the fourth protruding portion PP4 may be formed in the fourth region 355e. The third protruding portion PP3 may not overlap with the first protruding portion PP1, and the fourth protruding portion PP4 may not overlap with the second protruding portion PP2.

[0136] like Fig. 9 As shown in , a second gate electrode 361e overlapping the second channel region 351e may be formed on the sixth insulating layer IL6. The third conductive layer may include the second gate electrode 361e and the first switch gate electrode 361b, the second switch gate electrode 361c, the first connection pattern 363, and the second connection pattern 365 formed in the display unit 110. The second gate electrode 361e may form a second transistor T2 together with the second active pattern 350e. The second transistor T2 may have a dual gate structure, such as Figure 6 and Fig. 9 However, the present embodiment is not limited thereto, and the second transistor T2 may have a single gate structure.

[0137] The contact holes CH9, CH10, CH11, and CH12 may be formed in the seventh insulating layer IL7. The first electrode 373, the second electrode 375, the third electrode 377, and the fourth electrode 379 may be formed on the seventh insulating layer IL7. The fourth conductive layer may include the first electrode 373, the second electrode 375, the third electrode 377, and the fourth electrode 379, and the first programming electrode 371 formed in the display unit 110. However, the present embodiment is not limited thereto, and the first electrode 373, the second electrode 375, the third electrode 377, and the fourth electrode 379 may be formed on the eighth insulating layer IL8. For example, the fifth conductive layer may include the first electrode 373, the second electrode 375, the third electrode 377, and the fourth electrode 379, and the first power signal line 381 and the second programming electrode 383 formed in the display unit 110.

[0138] The first electrode 373 may be connected to the first region 323d through a ninth contact hole CH9 formed in the second, third, fourth, fifth, sixth, and seventh insulating layers IL2, IL3, IL4, IL5, IL6, and IL7. The ninth contact hole CH9 may expose the first protrusion PP1 of the first active pattern 320d, and the first electrode 373 may contact the first protrusion PP1 through the ninth contact hole CH9.

[0139] The second electrode 375 may be connected to the second region 325d through an eleventh contact hole CH11 formed in the second, third, fourth, fifth, sixth, and seventh insulating layers IL2, IL3, IL4, IL5, IL6, and IL7. The eleventh contact hole CH11 may expose the second protrusion portion PP2 of the first active pattern 320d, and the second electrode 375 may contact the second protrusion portion PP2 through the eleventh contact hole CH11.

[0140] The third electrode 377 may be connected to the third region 353e through a tenth contact hole CH10 formed in the sixth and seventh insulating layers IL6 and IL7. The tenth contact hole CH10 may expose and contact the third protrusion portion PP3 of the second active pattern 350e.

[0141] The fourth electrode 379 may be connected to the fourth region 355e through a twelfth contact hole CH12 formed in the sixth and seventh insulating layers IL6 and IL7. The twelfth contact hole CH12 may expose and contact the fourth protrusion portion PP4 of the second active pattern 350e.

[0142] The second transistor T2 overlapping the first transistor T1 may be located on the first transistor T1. The first electrode 373 and the second electrode 375 connected to the first transistor T1 and the third electrode 377 and the fourth electrode 379 connected to the second transistor T2 may be located on the second transistor T2. The first active pattern 320d may include protrusions PP1 and PP2 that do not overlap with the protrusions PP3 and PP4 of the second active pattern 350e, and thus may be connected to the first electrode 373 and the second electrode 375 located above the second active pattern 350e even if the first active pattern 320d overlaps the second active pattern 350e.

[0143] In an embodiment, the first electrode 373 may be integrally formed with the third electrode 377. In this case, the first region 323d may be electrically connected to the third region 353e, and a terminal of the first transistor T1 may be electrically connected to a terminal of the second transistor T2.

[0144] In an embodiment, the first transistor T1 and the second transistor T2 may be included in different stages. For example, the first transistor T1 may be a transistor included in the first stage, and the second transistor T2 may be a transistor included in the second stage. In an embodiment, the first transistor T1 may be a first output transistor T530 of the first stage, and the second transistor T2 may be a first output transistor T530 of the second stage. In an embodiment, the first transistor T1 may be a second output transistor T540 of the first stage, and the second transistor T2 may be a second output transistor T540 of the second stage. However, the present embodiment is not limited thereto, and the first transistor T1 may be any transistor other than the first output transistor T530 and the second output transistor T540 of the first stage, and the second transistor T2 may be any transistor other than the first output transistor T530 and the second output transistor T540 of the second stage.

[0145] In an embodiment, the first transistor T1 and the second transistor T2 may be included in the same level. For example, the first transistor T1 and the second transistor T2 may be transistors included in the first level. In an embodiment, the first transistor T1 may be a first output transistor T530 of the first level, and the second transistor T2 may be a second output transistor T540 of the first level. However, the present embodiment is not limited thereto, and the first transistor T1 may be any transistor other than the first output transistor T530 and the second output transistor T540 of the first level, and the second transistor T2 may be any transistor other than the first output transistor T530 and the second output transistor T540 of the first level.

[0146] like Figure 6 and Fig. 9As shown in FIG. 1 , the first active pattern 320d and the second active pattern 350e located at different layers may be formed in the scan driver 150. Therefore, the transistors T1 and T2 included in the scan driver 150 may overlap each other. Therefore, the area occupied by the transistors T1 and T2 may be reduced, the area of ​​the scan driver 150 may be reduced, and the display device 100 having a narrower dead zone may be formed.

[0147] Fig.10 is a plan view illustrating a scan driver 150 a according to an embodiment. Fig.11 is along Fig.10 A cross-sectional view taken along line II-II'.

[0148] For reference Fig.10 and Fig.11 The scan driver 150a described in reference Figures 6 to 9 Detailed descriptions of elements that are substantially the same as or similar to the elements described for the scan driver 150 may not be repeated.

[0149] refer to Fig.10 and Fig.11 In an embodiment, the first electrode 373 may be integrally formed with the third electrode 377, and the second electrode 375 may be integrally formed with the fourth electrode 379. In this case, the first region 323d may be electrically connected to the third region 353e, and the second region 325d may be electrically connected to the fourth region 355e. Therefore, one terminal of the first transistor T1 may be electrically connected to one terminal of the second transistor T2, and the other terminal of the first transistor T1 may be electrically connected to the other terminal of the second transistor T2.

[0150] Fig.12 is a block diagram illustrating a display device 101 according to an embodiment.

[0151] refer to Fig.12 , the display device 101 may include a display unit 110, a data driver 130 that provides a data signal to the display unit 110, a first scan driver 151 and a second scan driver 152 that provide a scan signal to the display unit 110, and a signal source 170 that provides a signal to the display unit 110. In an embodiment, the display device 101 may further include a controller (e.g., a timing controller) 190 that controls the data driver 130, the first scan driver 151, the second scan driver 152, and the signal source 170. Fig.12 The display device 101 described in reference Figure 1 Detailed descriptions of elements that are substantially the same as or similar to the elements of the described display device 100 may not be repeated.

[0152] The display unit 110 may include: a plurality of data lines DL1, ..., DLm, DLm+1, ..., DLM, a plurality of first scan lines SL11, ..., SL1n, ..., SL1N, a plurality of second scan lines SL21, ..., SL2n, ..., SL2N, and a plurality of pixels PX connected to the data lines DL1, ..., DLm, DLm+1, ..., DLM and the first scan lines SL11, ..., SL1n, ..., SL1N or connected to the data lines DL1, ..., DLm, DLm+1, ..., DLM and the second scan lines SL21, ..., SL2n, ..., SL2N.

[0153] The first scan driver 151 may output scan signals SCAN to the first scan lines SL11, ..., SL1n, ..., SL1N based on gate control signals from the controller 190. The pixels PX receiving the scan signals SCAN from the first scan lines SL11, ..., SL1n, ..., SL1N may receive data signals DATA from some of the data lines DL1, ..., DLm, DLm+1, ..., DLM.

[0154] The second scan driver 152 may output scan signals SCAN to the second scan lines SL21, ..., SL2n, ..., SL2N based on the gate control signal from the controller 190. The pixels PX receiving the scan signals SCAN from the second scan lines SL21, ..., SL2n, ..., SL2N may receive data signals DATA from some of the data lines DLm+1, ..., DLM among the data lines DL1, ..., DLm, DLm+1, ..., DLM.

[0155] The first scan driver 151 and the second scan driver 152 may be disposed opposite to each other, with the display unit 110 located between the first scan driver 151 and the second scan driver 152. For example, the first scan driver 151 may be located at a first side (e.g., left side) of the display unit 110, and the second scan driver 152 may be located at a second side (e.g., right side) opposite to the first side of the display unit 110. For example, the first scan driver 151 may be connected to the pixels PX located on one side of the center of the display unit 110 among the pixels PX of the display unit 110, and the second scan driver 152 may be connected to the pixels PX located on the other side of the center of the display unit 110 among the pixels PX of the display unit 110.

[0156] When the display device 101 is a high-resolution display device including a relatively large number of pixels PX, a relatively large number of pixels PX may be connected to each scan line. In this case, the resistance of the scan line may increase, and thus the transmission of the scan signal SCAN through the scan line may be delayed. However, the display device 101 according to the present embodiment may include a first scan driver 151 and a second scan driver 152, some of the pixels PX may be connected to the first scan driver 151, and other pixels of the pixels PX may be connected to the second scan driver 152. Therefore, the transmission delay of the scan signal SCAN through the scan lines SL11, ..., SL1n, ..., SL1N, SL21, ..., SL2n, ..., SL2N may be reduced or substantially prevented.

[0157] Fig.13 is a block diagram illustrating an electronic device 1300 including a display device 1360 according to an embodiment. Fig.14 It is a diagram of Fig.13 FIG. 1 is a diagram of an example in which the electronic device 1300 is implemented as a head mounted display (HMD) 1400 .

[0158] refer to Fig.13 , the electronic device 1300 may include: a processor 1310, a memory device 1320, a storage device 1330, an input / output (I / O) device 1340, a power supply 1350, and a display device 1360. The electronic device 1300 may further include a plurality of ports for communicating with a video card, a sound card, a memory card, a universal serial bus (USB) device, other electronic devices, and the like.

[0159] The processor 1310 may perform various computing functions or tasks. The processor 1310 may be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1310 may be coupled to other components via an address bus, a control bus, a data bus, etc. In addition, in an embodiment, the processor 1310 may be further coupled to an expansion bus such as a peripheral component interconnect (PCI) bus.

[0160] The storage device 1320 may store data used for the operation of the electronic device 1300. For example, the storage device 1320 may include at least one non-volatile storage device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistive random access memory (RRAM) device, a nano-floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and / or at least one volatile storage device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.

[0161] The storage device 1330 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I / O device 1340 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc. and / or an output device such as a printer, a speaker, etc. The power supply 1350 may supply power for the operation of the electronic device 1300.

[0162] The display device 1360 may include a display unit, a data driver that outputs a data signal to the display unit, and a scan driver that outputs a plurality of scan signals to the display unit. The scan driver may include a plurality of transistors that overlap each other. Therefore, the area occupied by the scan driver may be reduced, and the dead zone of the display device 1360 may be reduced.

[0163] In an embodiment, Fig.14 As shown in , the electronic device 1300 may be implemented as a head mounted display (HMD) 1400. However, the electronic device 1300 according to an embodiment may not be limited to the HMD 1400. For example, the electronic device 1300 may be any electronic device including a display device 1360, such as a virtual reality (VR) device, a cellular phone, a smart phone, a tablet computer, a wearable device, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation system, a digital television, a 3D television, a personal computer (PC), a home appliance, a laptop computer, etc.

[0164] The present invention can be applied to a display device and an electronic device including the display device. For example, the display device can be included in an HMD, a VR device, a cellular phone, a smart phone, a tablet computer, a digital TV, a 3D TV, a PC, a home appliance, a laptop computer, a PDA, a PMP, a digital camera, a music player, a portable game console, a navigation system, etc.

[0165] Although a scan driver according to an embodiment and a display device including the scan driver have been described with reference to the accompanying drawings, the illustrated embodiments are examples and may be modified and changed by a person having ordinary knowledge in the relevant technical field without departing from the technical spirit described in the attached claims and the functional equivalents of the claims included herein.

Claims

1. A scanning driver, comprising: substrate; a first transistor located on the substrate, the first transistor comprising a first active pattern and a first gate electrode, the first active pattern comprising a first region, a second region, and a first channel region located between the first region and the second region; a second transistor located on the first transistor and overlapping the first transistor in a thickness direction of the substrate, the second transistor comprising a second active pattern and a second gate electrode, the second active pattern comprising a third region, a fourth region, and a second channel region located between the third region and the fourth region; a first electrode and a second electrode located on the second transistor, the first electrode and the second electrode being directly connected to the first region and the second region respectively; a third electrode and a fourth electrode located on the second transistor, the third electrode and the fourth electrode being directly connected to the third region and the fourth region respectively; as well as a shielding electrode located between the first transistor and the second transistor, wherein a voltage for controlling a driving range of the second transistor is applied to the shielding electrode, and The first electrode is electrically connected to the third electrode.

2. The scan driver according to claim 1, wherein: The second electrode is electrically connected to the fourth electrode.

3. The scan driver according to claim 1, wherein: The first active pattern includes a first overlap portion, a first protrusion portion protruding from the first overlap portion in a first direction and connected to the first electrode, and a second protrusion portion protruding from the first overlap portion in a second direction and connected to the second electrode.

4. The scan driver according to claim 3, wherein: The second active pattern includes a second overlapping portion overlapping the first overlapping portion, a third protruding portion protruding from the second overlapping portion in the first direction and connected to the third electrode, and a fourth protruding portion protruding from the second overlapping portion in the second direction and connected to the fourth electrode.

5. The scan driver according to claim 4, wherein: The second direction is opposite to the first direction.

6. The scan driver according to claim 4, wherein: The third protruding portion does not overlap with the first protruding portion, and the fourth protruding portion does not overlap with the second protruding portion.

7. The scan driver according to claim 1, wherein: The second gate electrode overlaps with the first gate electrode.

8. The scan driver according to claim 1, wherein: The shielding electrode has a width greater than that of the first gate electrode.

9. The scan driver according to claim 1, wherein: When a negative voltage is applied to the shielding electrode, the driving range of the second transistor becomes wider, and when a positive voltage is applied to the shielding electrode, the driving range of the second transistor becomes narrower.

10. The scan driver according to claim 1, further comprising a plurality of stages for respectively outputting a plurality of scan signals, wherein each of the plurality of stages comprises: a first input section for transmitting an input signal to a set node in response to a second clock signal; a second input section for transmitting the first clock signal to a reset node in response to the input signal and the second clock signal; a first output section, configured to output a third clock signal as the scan signal in response to a voltage of the set node; as well as The second output unit is used to output a concurrent driving signal as the scanning signal in response to the voltage of the reset node.

11. The scan driver according to claim 10, wherein: The plurality of stages include a first stage including the first transistor and a second stage including the second transistor.

12. The scan driver according to claim 11, wherein: The first output section of the first stage includes the first transistor, and the first output section of the second stage includes the second transistor.

13. The scan driver according to claim 11, wherein: The second output section of the first stage includes the first transistor, and the second output section of the second stage includes the second transistor.

14. The scan driver according to claim 10, wherein: The first output section includes the first transistor, and the second output section includes the second transistor.

15. A scanning driver, comprising: substrate; a first active pattern located on the substrate, the first active pattern comprising a first region, a second region, and a first channel region located between the first region and the second region; a first gate electrode located on the first active pattern; a second active pattern located on the first gate electrode and overlapping the first active pattern in a thickness direction of the substrate, the second active pattern comprising a third region, a fourth region, and a second channel region located between the third region and the fourth region; a second gate electrode located on the second active pattern; a first electrode and a second electrode located on the second gate electrode, the first electrode and the second electrode being directly connected to the first region and the second region respectively; A third electrode and a fourth electrode located on the same layer as the first electrode and the second electrode, the third electrode and the fourth electrode being directly connected to the third region and the fourth region respectively; as well as a shielding electrode located between the first gate electrode and the second active pattern, wherein a voltage for controlling a driving range of a transistor formed by the second active pattern and the second gate electrode is applied to the shielding electrode, and The first electrode and the third electrode are formed integrally.

16. The scan driver according to claim 15, wherein: The second electrode is formed integrally with the fourth electrode.

17. The scan driver according to claim 15, wherein: The first active pattern includes a first overlap portion, a first protrusion portion protruding from the first overlap portion in a first direction and connected to the first electrode, and a second protrusion portion protruding from the first overlap portion in a second direction and connected to the second electrode.

18. The scan driver according to claim 17, wherein: The second active pattern includes a second overlapping portion overlapping the first overlapping portion, a third protruding portion protruding from the second overlapping portion in the first direction and connected to the third electrode, and a fourth protruding portion protruding from the second overlapping portion in the second direction and connected to the fourth electrode.

19. The scan driver according to claim 18, wherein: The third protruding portion does not overlap with the first protruding portion, and the fourth protruding portion does not overlap with the second protruding portion.

20. The scan driver according to claim 15, wherein: The second gate electrode overlaps with the first gate electrode.

21. The scan driver according to claim 15, wherein: The shielding electrode has a width greater than that of the first gate electrode.

22. A display device comprising: Display unit, comprising: a driving transistor including a driving active pattern and a driving gate electrode; and a switching transistor located on the driving transistor and overlapping the driving transistor in a thickness direction of the display unit, the switching transistor including a switching active pattern and a switching gate electrode; and a scan driver for supplying a scan signal to the display unit and including: a first transistor including a first active pattern and a first gate electrode, wherein the first active pattern includes a first region, a second region, and a first channel region between the first region and the second region; a second transistor located on the first transistor and overlapping the first transistor in the thickness direction of the display unit, the second transistor comprising a second active pattern and a second gate electrode, the second active pattern comprising a third region, a fourth region, and a second channel region located between the third region and the fourth region; a first electrode, a second electrode, a third electrode, and a fourth electrode located on the second transistor, the first electrode, the second electrode, the third electrode, and the fourth electrode being directly connected to the first region, the second region, the third region, and the fourth region, respectively; and a shielding electrode located between the first transistor and the second transistor, A voltage for controlling a driving range of the second transistor is applied to the shielding electrode.

23. The display device according to claim 22, wherein: The first active pattern and the first gate electrode of the first transistor are located on the same layer as the driving active pattern and the driving gate electrode of the driving transistor, respectively.

24. The display device according to claim 22, wherein: The second active pattern and the second gate electrode of the second transistor are located on the same layer as the switch active pattern and the switch gate electrode of the switch transistor, respectively.

25. The display device according to claim 22, wherein the display unit further comprises: A storage capacitor includes a first storage electrode integrally formed with the driving gate electrode and a second storage electrode located between the driving transistor and the switching transistor.

26. The display device according to claim 25, wherein: The shielding electrode and the second storage electrode are located on the same layer.

27. The display device according to claim 22, wherein the display unit further comprises: A programming capacitor includes a first programming electrode located on the switch transistor and a second programming electrode located on the first programming electrode.

28. The display device according to claim 27, wherein: The first electrode, the second electrode, the third electrode, and the fourth electrode are located on a same layer as one of the first programming electrode and the second programming electrode.

29. The display device according to claim 27, further comprising: a pixel electrode electrically connected to the second programming electrode; an organic light-emitting layer located on the pixel electrode; as well as A common electrode is located on the organic light emitting layer.

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