Semiconductor package including test pads and method of forming the same

Abstract

A semiconductor package including a test pad and a method of forming the same are provided. The semiconductor package includes a substrate including a first bonding structure and a first semiconductor chip including a second bonding structure coupled to the first bonding structure of the substrate, wherein the first bonding structure includes a test pad, a first pad electrically connected to the test pad, and a first insulating layer, wherein the second bonding structure includes a second pad electrically connected to the first pad, and a second insulating layer contacting the first insulating layer, and wherein at least a portion of the test pad contacts the second insulating layer.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This application claims priority to Korean Patent Application No. 10-2018-0129137, filed on October 26, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety. TECHNICAL FIELD

[0003] An apparatus according to exemplary embodiments relates to a semiconductor package, and more particularly, to a semiconductor package including a test pad. BACKGROUND

[0004] Recently, as demand for high-performance electronic products and demand for miniaturization of such high-performance electronic products have been increasing, various types of semiconductor packages have been developed. To this end, semiconductor packages including a plurality of semiconductor chips in which individual chips are mounted or stacked on a substrate or another chip to reduce the thickness of the semiconductor package are being developed.

[0005] When mounting or stacking individual chips, if a normal chip is mounted or stacked on a defective chip, not only the defective chip but also the normal chip stacked on the defective chip can not function normally in the semiconductor package. SUMMARY

[0006] One or more exemplary embodiments provide a semiconductor package including a test pad capable of checking defects of a semiconductor chip.

[0007] According to an aspect of an exemplary embodiment, there is provided a semiconductor package including a substrate including a first bonding structure, and a first semiconductor chip including a second bonding structure coupled to the first bonding structure of the substrate, wherein the first bonding structure includes a test pad, a first pad electrically connected to the test pad, and a first insulating layer, wherein the second bonding structure includes a second pad electrically connected to the first pad, and a second insulating layer contacting the first insulating layer, and wherein at least a portion of the test pad contacts the second insulating layer.

[0008] According to an aspect of another exemplary embodiment, there is provided a semiconductor package including a substrate; and a plurality of semiconductor chips disposed on the substrate, wherein the plurality of semiconductor chips includes a first semiconductor chip and a second semiconductor chip, the first semiconductor chip and the second semiconductor chip being sequentially stacked on and coupled to the substrate. The first semiconductor chip includes a first surface and a second surface opposite to the first surface. The second semiconductor chip includes a third surface and a fourth surface opposite to the third surface. The first semiconductor chip includes a first internal circuit layout disposed on the first surface of the first semiconductor chip. The second semiconductor chip includes a second internal circuit layout disposed on the third surface of the second semiconductor chip. The second surface of the first semiconductor chip includes a first pad, a test pad, and a first insulating layer. The third surface of the second semiconductor chip includes a second pad contacting and bonded to the first pad, and a second insulating layer contacting and bonded to the first insulating layer.

[0009] According to an aspect of another exemplary embodiment, there is provided a semiconductor package including a substrate having a first surface and a second surface opposite to the first surface, a lower semiconductor chip disposed on the substrate and having a third surface and a fourth surface opposite to the third surface, and an upper semiconductor chip disposed on the lower semiconductor chip and having a fifth surface and a sixth surface opposite to the fifth surface. Each of the second surface of the substrate and the fourth surface of the lower semiconductor chip includes a first bonding structure. Each of the third surface of the lower semiconductor chip and the fifth surface of the upper semiconductor chip includes a second bonding structure. The first bonding structure includes a first pad, a test pad, and a first insulating layer, and the second bonding structure includes a second pad and a second insulating layer. The first bonding structure of the substrate and the second bonding structure of the lower semiconductor chip are bonded while contacting each other. The first bonding structure of the lower semiconductor chip and the second bonding structure of the upper semiconductor chip are bonded while contacting each other. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and / or other aspects, features, and advantages of the present disclosure will be more apparent from the following detailed description, taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1A is a cross-sectional view illustrating a semiconductor package according to an exemplary embodiment.

[0012] Figure 1Bis a cross-sectional view of a first bonding structure and a second bonding structure of a semiconductor chip shown in Figure 1A

[0013] Figure 2A is a perspective view of a first bonding structure and a second bonding structure of a semiconductor chip shown in Figure 1A

[0014] Figure 2B is a perspective view of a first bonding structure and a second bonding structure of a semiconductor chip shown in Figure 1A

[0015] Figure 3 is a cross-sectional view of a modified example of a semiconductor package according to an example embodiment.

[0016] Figure 4 is a cross-sectional view of a first bonding structure and a second bonding structure of a semiconductor chip shown in Figure 3

[0017] Figure 5 is a cross-sectional view of a modified example of a semiconductor package according to an example embodiment.

[0018] Figure 6 is a cross-sectional view of a first bonding structure and a second bonding structure of a semiconductor chip shown in Figure 5

[0019] Figure 7 is a cross-sectional view of a modified example of a semiconductor package according to an example embodiment.

[0020] Figure 8 is a cross-sectional view of a modified example of a semiconductor package according to an example embodiment.

[0021] Figure 9 is a cross-sectional view of a first bonding structure and a second bonding structure of a semiconductor chip shown in Figure 8

[0022] Figure 10 is a cross-sectional view of a modified example of a semiconductor package according to an example embodiment.

[0023] Figure 11 is a cross-sectional view of a modified example of a semiconductor package according to an example embodiment.

[0024] Figure 12 ​​​​​​is a cross-sectional view showing a modified example of a semiconductor package according to an exemplary embodiment.

[0025] Figure 13 is a cross-sectional view showing a modified example of a semiconductor package according to an exemplary embodiment.

[0026] Figures 14A to 14D is a view showing a method of manufacturing a semiconductor package according to an exemplary embodiment.

[0027] [Explanation of symbols]

[0028] 1a, 1b, 1c, 1d, 1e, 1f, 1g, 1h, 1i: semiconductor package

[0029] 10, 10a: lower structure

[0030] 20: connection structure

[0031] 100, 100', 100a, 100a': substrate

[0032] 100W: wafer

[0033] 105: substrate body

[0034] 110: substrate through-electrode structure

[0035] 128: substrate internal circuit

[0036] 130: lower insulating layer

[0037] 130': substrate lower insulating layer / substrate internal circuit structure

[0038] 135: substrate lower pad

[0039] 135': substrate lower pad / substrate internal circuit structure

[0040] 160: substrate wiring structure / substrate backside structure

[0041] 160': substrate backside structure

[0042] 160a: lower connection structure

[0043] 165: substrate backside insulating layer / substrate backside structure

[0044] 175 (INS1), 275 (INS1), INS1: first insulating layer

[0045] 180a (P1a), 182 (P1b), 280a (P1a), 282 (P1b): first pad

[0046] 180b (TP), 280b (TP), TP: test pad

[0047] 180c (IPa), 280c (IPa), IPa: pad connection

[0048] 200: first semiconductor chip / lower semiconductor chip / semiconductor chip

[0049] 200a, 200b, 200c: lower semiconductor chip / semiconductor chip

[0050] 205: first semiconductor body

[0051] 210: first through-electrode structure

[0052] 215: first internal circuit wiring / first internal circuit structure / internal circuit structure

[0053] 220: first lower insulating layer / first internal circuit structure / internal circuit structure

[0054] 230 (INS2), 330 (INS2), INS2: second insulating layer

[0055] 265: upper insulating layer

[0056] 300: second semiconductor chip / semiconductor chip / upper semiconductor chip

[0057] 305: second semiconductor body

[0058] 315: second internal circuit wiring / second internal circuit structure / internal circuit structure

[0059] 320: second lower insulating layer / second internal circuit structure / internal circuit structure

[0060] 235 (P2a), 235 (P2b), 335 (P2a), 335 (P2b), P2a, P2b: second pad

[0061] 400: third semiconductor chip / semiconductor chip

[0062] 405: third semiconductor body

[0063] 415: third internal circuit wiring / internal circuit wiring / third internal circuit structure

[0064] 420: lower insulating layer / third internal circuit structure

[0065] 450: molding layer

[0066] 460: heat dissipation structure

[0067] 462: Insulating thermal conduction layer / thermal conduction layer

[0068] 464: Heat dissipation plate

[0069] 510a: Carrier substrate

[0070] 520a: Adhesive layer

[0071] 600: Sawing process

[0072] 1000: Test equipment

[0073] 1010a, 1010b: Probe

[0074] BS: Back side

[0075] DA: Dummy area

[0076] DP: Dummy pad area

[0077] IPb: Dummy connection portion

[0078] FS: Front side

[0079] P1a: First portion / pad / first pad

[0080] P1b: Second portion / first pad

[0081] PA: Test area

[0082] ST1: First bonding structure

[0083] ST2: Second bonding structure

[0084] W b , W c1 , W c2 , W TP , W P : Width DETAILED DESCRIPTION

[0085] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0086] First, exemplary embodiments of a semiconductor package 1a according to exemplary embodiments will be described with reference to Figure 1A , Figure 1B and Figure 2A . Figure 1A is a cross-sectional view illustrating a semiconductor package according to exemplary embodiments. Figure 1B is a cross-sectional view illustrating a substrate 100, a first semiconductor chip 200, and a second semiconductor chip 300 of the semiconductor package 1a shown in Figure 1A in an exploded manner according to exemplary embodiments. Figure 2A is a cross-sectional view illustratingFigure 1A and Figure 1B perspective views of the first and second joint structures ST1 and ST2.

[0087] Referring to Figure 1A and Figure 1B According to an exemplary embodiment, a semiconductor package 1a can include a substrate 100 and one or more semiconductor chips on the substrate 100.

[0088] In an exemplary embodiment, the substrate 100 can be an interposer. However, exemplary embodiments are not limited thereto. For example, the substrate 100 can be a semiconductor chip.

[0089] The semiconductor package 1a according to an exemplary embodiment can further include a lower structure 10 disposed under the substrate 100 and coupled to the substrate 100 by a connection structure 20. The lower structure 10 can be a printed circuit board. The connection structure 20 can be a bump or a solder ball.

[0090] In an exemplary embodiment, the semiconductor package 1a can include a first semiconductor chip 200 and a second semiconductor chip 300 stacked in sequence on the substrate 100, and a third semiconductor chip 400 disposed adjacent to the first semiconductor chip 200 on the substrate 100, as shown in Figure 1A .

[0091] In an exemplary embodiment, the first semiconductor chip 200, the second semiconductor chip 300, and the third semiconductor chip 400 can include a logic semiconductor chip and / or a memory semiconductor chip. For example, the first semiconductor chip 200 and the second semiconductor chip 300 can be memory semiconductor chips, and the third semiconductor chip 400 can be a logic semiconductor chip. The memory semiconductor chip can be a volatile memory chip (e.g., a dynamic random access memory (DRAM) or a static random access memory (SRAM)) or a non-volatile memory chip (e.g., a phase-change random access memory (PRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), a resistive random access memory (RRAM), or a flash memory). The logic semiconductor chip can be a microprocessor, an analog device, or a digital signal processor.

[0092] The substrate 100 and the first semiconductor chip 200, second semiconductor chip 300, and third semiconductor chip 400 may be coupled by including a first bonding structure ST1 and a second bonding structure ST2. For example, the substrate 100 and the first semiconductor chip 200 may include a first bonding structure ST1 located on the top surface of each of the substrate 100 and the first semiconductor chip 200, and the first semiconductor chip 200, the second semiconductor chip 300, and the third semiconductor chip 400 may include a second bonding structure ST2 located on the bottom surface of each of the first semiconductor chip 200, the second semiconductor chip 300, and the third semiconductor chip 400. Figure 1B As shown, the first bonding structure ST1 of the substrate 100 is coupled to the second bonding structure ST2 of the first semiconductor chip 200, and the first bonding structure ST1 of the first semiconductor chip 200 is coupled to the second bonding structure ST2 of the second semiconductor chip 300. Additionally, the width W of the substrate 100... b The width W is greater than the width of each of the first, second, and third semiconductor chips. c1 W c2 .

[0093] The first bonding structure ST1 may include first pads P1a and P1b, a test pad TP, and a first insulating layer INS1. The second bonding structure ST2 may include second pads P2a and P2b, and a second insulating layer INS2.

[0094] In an exemplary embodiment, the first portion P1a of the first pads P1a and P1b can be electrically connected to the test pad TP via the pad connection portion IPa, and the second portion P1b of the first pads P1a and P1b can be spaced apart from the test pad TP, such as... Figure 2A As shown in the diagram. Additionally, the width W of each of the test pads TP is also measured. TP The width W is greater than the width of each of the first pads P1a and P1b. P .

[0095] When the first bonding structure ST1 and the second bonding structure ST2 are coupled to each other, the first pads P1a and P1b and the second pads P2a and P2b can be in direct contact with each other. The first pads P1a and P1b and the second pads P2a and P2b can contain the same conductive material, such as copper (Cu). The first pads P1a and P1b and the second pads P2a and P2b, which are in direct contact with each other while facing each other, can be coupled through the mutual diffusion of copper.

[0096] In exemplary embodiments, the conductive material capable of forming the first pads P1a and P1b and the second pads P2a and P2b can not be limited to copper only, but can include any material capable of coupling to each other. For example, the conductive material capable of forming the first pads P1a and P1b and the second pads P2a and P2b can include gold (Au).

[0097] When the first bonding structure ST1 and the second bonding structure ST2 are coupled to each other, the first insulating layer INS1 of the first bonding structure ST1 and the second insulating layer INS2 of the second bonding structure ST2 can be in direct contact with each other while facing each other. The first insulating layer INS1 and the second insulating layer INS2 can be formed of the same material. For example, the first insulating layer INS1 and the second insulating layer INS2 can be formed of silicon oxide (SiO2). The first insulating layer INS1 and the second insulating layer INS2 can be coupled to each other while being in direct contact with each other.

[0098] In exemplary embodiments, the first insulating layer INS1 and the second insulating layer INS2 can not be limited to silicon oxide (SiO2) only, and can include all materials capable of coupling to each other. For example, the first insulating layer INS1 and the second insulating layer INS2 can be formed of silicon carbon nitride (SiCN).

[0099] Referring back to Figure 1A and Figure 1B , the substrate 100 can include a substrate body 105, a lower insulating layer 130 and a substrate lower pad 135 disposed below the substrate body 105, substrate backside structures 165 and 160 disposed on the substrate body 105, a first bonding structure ST1 disposed on the substrate backside structures 160 and 165, and a substrate through electrode structure 110 penetrating through the substrate body 105. The substrate body 105 can be a semiconductor substrate. For example, the substrate body 105 can be a silicon substrate.

[0100] The first bonding structure ST1 of the substrate 100 can include first pads 180a (P1a) and 182 (P1b), a pad connection portion 180c (IPa), a test pad 180b (TP), and a first insulating layer 175 (INS1).

[0101] The substrate backside structures 160 and 165 can include a substrate backside insulating layer 165 and a substrate wiring structure 160 disposed in the substrate backside insulating layer 165 and electrically connecting the substrate through electrode structure 110 of the substrate 100 with the first pads 180a (Pla) and 182 (Plb). The substrate through electrode structure 110 can be electrically connected to the substrate lower pads 135. Thus, the first pads 180a (Pla) and 182 (Plb) of the substrate 100 can be electrically connected to the substrate lower pads 135 through the substrate through electrode structure 110. The substrate through electrode structure 110 can be a through-silicon via (TSV) structure. The substrate wiring structure 160 can be electrically connected to the test pad 180b (TP). For example, the substrate wiring structure 160 can be electrically connected to the test pad 180b (TP) through the first pad Plb and the connection IPa.

[0102] The first semiconductor chip 200 can include a first semiconductor body 205, an upper insulating layer 265 disposed on the first semiconductor body 205, a first bonding structure ST1 disposed on the upper insulating layer 265, first internal circuit structures 215 and 220 disposed below the first semiconductor body 205, a second bonding structure ST2 disposed below the first internal circuit structures 215 and 220, and a first through electrode structure 210 penetrating through the first semiconductor body 205. The first through electrode structure 210 can be a through-silicon via (TSV) structure. The first semiconductor body 205 can be a semiconductor substrate, such as a silicon substrate.

[0103] The first bonding structure ST1 of the first semiconductor chip 200 can include first pads 280a (Pla) and 282 (Plb), a pad connection 280c (IPa), a test pad 280b (TP), and a first insulating layer 275 (INS1). The first pads 280a (Pla) and 282 (Plb) of the first semiconductor chip 200 can be electrically connected to the first through electrode structure 210. The second bonding structure ST2 of the first semiconductor chip 200 can include second pads 235 (P2a and P2b) and a second insulating layer 230 (INS2).

[0104] The first internal circuit structures 215 and 220 of the first semiconductor chip 200 can include first internal circuitry wiring 215 disposed in the first lower insulating layer 220 and electrically connected to the first through electrode structure 210 and the first pads 280a (Pla) and 282 (Plb) of the first semiconductor chip 200. The first internal circuit structures 215 and 220 can be disposed between the second bonding structure ST2 and the first semiconductor body 205 of the first semiconductor chip 200.

[0105] The second semiconductor chip 300 can include a second semiconductor body 305, second internal circuit structures 315 and 320 disposed below the second semiconductor body 305, and a second bonding structure ST2 disposed below the second internal circuit structures 315 and 320. The second semiconductor body 305 can be a semiconductor substrate, such as a silicon substrate. The second bonding structure ST2 of the second semiconductor chip 300 can include second pads 335 (P2a and P2b) and a second insulating layer 330 (INS2).

[0106] The second internal circuit structures 315 and 320 of the second semiconductor chip 300 can include a second lower insulating layer 320 and second internal circuit wiring 315 disposed in the second lower insulating layer 320 and electrically connected to the second pads 335 (P2a and P2b) of the second semiconductor chip 300. The second internal circuit structures 315 and 320 can be disposed between the second bonding structure ST2 and the second semiconductor body 305 of the second semiconductor chip 300.

[0107] The third semiconductor chip 400 can include a third semiconductor body 405, third internal circuit structures 415 and 420 disposed below the third semiconductor body 405, a second pad P2b disposed below the third internal circuit structures 415 and 420 and constituting the second bonding structure ST2 as described above, and a second insulating layer INS2. The third internal circuit structures 415 and 420 can include a lower insulating layer 420 and third internal circuit wiring 415 located in the lower insulating layer 420. The third internal circuit structures 415 and 420 can be disposed between the second bonding structure ST2 and the third semiconductor body 405 of the third semiconductor chip 400.

[0108] The substrate 100 and the first semiconductor chip 200 can be coupled by bonding the first bonding structure ST1 of the substrate 100 and the second bonding structure ST2 of the first semiconductor chip 200. For example, the first pads 180a (P1a) and 182 (P1b) of the substrate 100 and the second pads 235 (P2a and P2b) of the first semiconductor chip 200 can be bonded and coupled while being in contact with each other, and the first insulating layer 175 (INS1) of the substrate 100 and the second insulating layer 230 (INS2) of the first semiconductor chip 200 can be bonded and coupled while being in contact with each other.

[0109] The substrate 100 and the third semiconductor chip 400 can be bonded and coupled while the first pad 182 (P1b) of the substrate 100 and the second pad P2b of the third semiconductor chip 400 are in contact with each other, and can be bonded and coupled while the first insulating layer 175 (INS1) of the substrate 100 and the second insulating layer INS2 of the third semiconductor chip 400 are in contact with each other.

[0110] The first semiconductor chip 200 and the second semiconductor chip 300 can be coupled while the first bonding structure ST1 of the first semiconductor chip 200 and the second bonding structure ST2 of the second semiconductor chip 300 are bonded. For example, the first pads 280a (P1a) and 282 (P1b) of the first semiconductor chip 200 and the second pads 335 (P2a and P2b) of the second semiconductor chip 300 can be bonded and coupled while being in contact with each other, and the first insulating layer 275 (INS1) of the first semiconductor chip 200 and the second insulating layer 330 (INS2) of the second semiconductor chip 300 can be bonded and coupled while being in contact with each other.

[0111] Each of the first semiconductor chip 200 and the second semiconductor chip 300 can have a front side FS and a back side BS opposite to each other. The front side FS of the first semiconductor chip 200 can contact and be bonded to the substrate 100, and the back side BS of the first semiconductor chip 200 can contact and be bonded to the front side FS of the second semiconductor chip 300.

[0112] In some embodiments, the front side FS of the first semiconductor chip 200 can be referred to as a first surface, the back side BS of the first semiconductor chip 200 can be referred to as a second surface, the front side FS of the second semiconductor chip 300 can be referred to as a third surface, and the back side BS of the second semiconductor chip 300 can be referred to as a fourth surface.

[0113] In some embodiments, the substrate 100a can include a first surface and a second surface opposite to the first surface, the front side FS of the first semiconductor chip 200 can be referred to as a third surface, the back side BS of the first semiconductor chip 200 can be referred to as a fourth surface, the front side FS of the second semiconductor chip 300 can be referred to as a fifth surface, and the back side BS of the second semiconductor chip 300 can be referred to as a sixth surface.

[0114] In some embodiments, the first bonding structure ST1 of the first semiconductor chip 200 can be referred to as a third bonding structure, and the second bonding structure ST2 of the second semiconductor chip 200 can be referred to as a fourth bonding structure.

[0115] Each of the first pads P1a and P1b can be smaller than each of the test pads TP.

[0116] In exemplary embodiments, each of the first and second pads P1a, P1b, P2a, and P2b can have a polygonal shape when viewed in a plan view. For example, each of the first and second pads P1a, P1b, P2a, and P2b can have a rectangular shape when viewed in a plan view.

[0117] In a modified example, reference is made to Figure 2BEach of the first and second pads P1a, P1b, P2a, and P2b can have a circular shape when viewed in a plan view.

[0118] Next, referring to Figures 3 to 10 Various modified examples of the semiconductor package 1b, 1c, 1d, 1e, and 1f will be explained. Figure 3 and Figure 4 is a view showing a modified example of the semiconductor package 1b according to an exemplary embodiment. Figure 5 and Figure 6 is a view showing another modified example of the semiconductor package 1c according to an exemplary embodiment. Figure 7 is a view showing another modified example of the semiconductor package 1d according to an exemplary embodiment. Figure 8 and Figure 9 is a view showing another modified example of the semiconductor package 1e according to an exemplary embodiment, and Figure 10 is a view showing another modified example of the semiconductor package 1f according to an exemplary embodiment.

[0119] Referring to Figure 3 and Figure 4 , the second bonding structure ST2 can further include a dummy connection portion IPb provided at a position corresponding to the pad connection portion IPa of the first bonding structure ST1 and contacting and bonded to the first bonding structure ST1. The dummy connection portion IPb can be formed of the same material as the pad connection portion IPa. The dummy connection portion IPb can extend from a portion of the second pad P2a of the second pads P2a and P2b. The first semiconductor chip 200 can include the dummy connection portion IPb contacting and bonded to the pad connection portion IPa of the substrate 100, and the second semiconductor chip 300 can include the dummy connection portion IPb contacting and bonded to the pad connection portion IPa of the first semiconductor chip 200. Thus, a semiconductor package 1b further including the dummy connection portion IPb contacting and bonded to the pad connection portion IPa can be provided.

[0120] In a modified example, referring to Figure 5 and Figure 6 , the test pad TP of the first bonding structure ST1 can include a test region PA directly contacting Figure 14A , Figure 14B and Figure 14Cprobes 1010a and 1010b for inspecting defects; and a dummy area DA surrounding the test area PA. The second bonding structure ST2 can be disposed at a position corresponding to the pad connection portion IPa of the first bonding structure ST1, and can further include: a dummy connection portion IPb contacting the pad connection portion IPa of the first bonding structure ST1 and bonded to the pad connection portion IPa of the first bonding structure ST1; and a dummy pad area DP contacting the dummy area DA of the test pad TP of the first bonding structure ST1 and bonded to the dummy area DA of the test pad TP of the first bonding structure ST1. The test area PA can contact the second insulating layer INS2 of the second bonding structure ST2.

[0121] The dummy connection portion IPb and the dummy pad area DP can be formed of the same material as the pad connection portion IPa and the test pad TP. The dummy connection portion IPb can extend from a portion of the second pad P2a among the second pads P2a and P2b, and the dummy pad area DP can extend from the dummy connection portion IPb.

[0122] The first semiconductor chip 200 can further include: a dummy connection portion IPb contacting the pad connection portion IPa of the substrate 100 and bonded to the pad connection portion IPa of the substrate 100; and a dummy pad area DP contacting a portion of the test pad TP of the substrate 100 (i.e., the dummy area DA) and bonded to the portion of the test pad TP of the substrate 100 (i.e., the dummy area DA), and the second semiconductor chip 300 can further include: a dummy connection portion IPb contacting the pad connection portion IPa of the first semiconductor chip 200 and bonded to the pad connection portion IPa of the first semiconductor chip 200; and a dummy pad area DP contacting a portion of the test pad TP of the first semiconductor chip 200 (i.e., the dummy area DA) and bonded to the portion of the test pad TP of the first semiconductor chip 200 (i.e., the dummy area DA). Accordingly, a semiconductor package 1c further including the dummy connection portion IPb and the dummy pad area DP can be provided.

[0123] In the modified example, referring to Figure 7 In the same plane, the test pad TP of the substrate 100 can be spaced apart from the first pads P1a and P1b of the substrate 100. Some of the first pads P1a can be electrically connected to the test pad TP of the substrate 100 through the lower connection structure 160a of the substrate wiring structure 160. The lower connection structure 160a can be disposed under the test pad TP and the first pads P1a and P1b of the substrate 100. Accordingly, a semiconductor package 1d including the test pad TP of the substrate 100 and the first pads P1a and P1b of the substrate 100 spaced apart from each other in the same plane can be provided.

[0124] In the modified example, referring to Figure 8 andFigure 9 Some of the first pads P1a in the first pads P1a and P1b of the base 100 can be electrically connected to the test pads TP through the lower connection structure 160a, as shown in Figure 7 . The test pads TP of the first bonding structure ST1 can include a dummy area DA and a test area PA, as described with reference to Figure 6 . The second bonding structure ST2 of each of the first semiconductor chip 200 and the second semiconductor chip 300 can include a dummy pad area DP spaced apart from the second pads P2a and P2b, contacting the dummy area DA of the test pads TP of the first bonding structure ST1 and bonded to the dummy area DA of the test pads TP of the first bonding structure ST1. Accordingly, the semiconductor package 1e including the dummy pad area DP can be provided.

[0125] In a modified example, with reference to Figure 10 , the semiconductor package 1f can include a base 100', which can be a semiconductor chip. For example, the base 100' can include a base body 105, a base internal circuit 128 disposed below the base body 105, and a base lower pad 135' disposed below the base internal circuit 128. The base internal circuit 128 can be disposed in a base lower insulating layer 130' disposed below the base body 105.

[0126] The first semiconductor chip 200, the second semiconductor chip 300, and the third semiconductor chip 400 as described above can be disposed on the base 100'. The base 100' and the first semiconductor chip 200, the second semiconductor chip 300, and the third semiconductor chip 400 can be coupled via the first bonding structure ST1 and the second bonding structure ST2 contacting and bonded to each other as described above. Since the first bonding structure ST1 and the second bonding structure ST2 have been set forth above, detailed descriptions thereof will be omitted here.

[0127] Next, another modified example of a semiconductor package according to exemplary embodiments will be set forth with reference to Figure 11 . Figure 11 is a cross-sectional view illustrating a modified example of a semiconductor package 1g according to exemplary embodiments.

[0128] With reference to Figure 11 , the semiconductor chip 1g can include a lower structure 10a, a base 100a disposed on the lower structure 10a, and a plurality of semiconductor chips 200a, 200b, 200c, and 300 stacked on the base 100a. The semiconductor package 1g can further include a molding layer 450 formed on the base 100a and surrounding the plurality of semiconductor chips 200 (200a, 200b, and 200c) and 300.

[0129] The plurality of semiconductor chips 200 (200a, 200b, and 200c) and 300 can include lower semiconductor chips 200 (200a, 200b, and 200c) stacked in sequence and an upper semiconductor chip 300 disposed on the lower semiconductor chips 200.

[0130] In an exemplary embodiment, the lower structure 10a can be a printed circuit board or a semiconductor chip.

[0131] In an exemplary embodiment, the base 100a can be a semiconductor chip or an intermediate layer. The lower structure 10a and the base 100a can be electrically connected to each other via a connection structure 20 extending between the lower structure 10a and the base 100a.

[0132] Each of the lower semiconductor chips 200 (200a, 200b, and 200c) can include first and second bonding structures ST1 and ST2, which are substantially the same as the first and second bonding structures ST1 and ST2 described above.

[0133] Each of the lower semiconductor chips 200 (200a, 200b, and 200c) can have the same structure as the structure of the first semiconductor chip 200 set forth in Figure 1A and Figure 1B Each of the lower semiconductor chips 200 (200a, 200b, and 200c) can be the first semiconductor chip 200 set forth in Figure 1A and Figure 1B For example, as the first semiconductor chip 200 set forth in Figure 1A and Figure 1B Each of the lower semiconductor chips 200 (200a, 200b, and 200c) can include a first semiconductor body 205, a second bonding structure ST2 disposed below the first semiconductor body 205, internal circuit structures 215 and 220 disposed between the second bonding structure ST2 and the first semiconductor body 205, a first bonding structure ST1 disposed on the first semiconductor body 205, an upper insulating layer 265 disposed between the first bonding structure ST1 and the first semiconductor body 205, and a first through-electrode structure 210 penetrating through the first semiconductor body 205, as the first semiconductor chip 200 set forth in

[0134] In an exemplary embodiment, the upper semiconductor chip 300 can be the same as the second semiconductor chip 300 set forth in Figure 1A and Figure 1B The upper semiconductor chip 300 can include a second semiconductor body 305, such as a semiconductor substrate 305, an upper bonding structure ST3 disposed on the second semiconductor body 305, internal circuit structures 315 and 320 disposed between the upper bonding structure ST3 and the second semiconductor body 305, a lower bonding structure ST2 disposed below the second semiconductor body 305, and a second through-electrode structure 310 penetrating through the second semiconductor body 305, as the second semiconductor chip 300 set forth in Figure 1A and Figure 1BThe second semiconductor chip 300; the internal circuit structures 315 and 320 disposed below the second semiconductor body 305; and the second bonding structure ST2 disposed below the internal circuit structures 315 and 320 are described in

[0135] The substrate 100a can include a substrate body 105a; a lower insulating layer 130a and a substrate lower pad 135a disposed below the substrate body 105a; a substrate backside structure 160' and 165 disposed on the substrate body 105a; a first bonding structure ST1 disposed on the substrate backside structure 160' and 165; and a substrate through electrode structure 110 penetrating through the substrate body 105a, similar to the substrate 100 described in Figure 1A and Figure 1B The substrate 100a can include a substrate body 105a; a lower insulating layer 130a and a substrate lower pad 135a disposed below the substrate body 105a; a substrate backside structure 160' and 165 disposed on the substrate body 105a; a first bonding structure ST1 disposed on the substrate backside structure 160' and 165; and a substrate through electrode structure 110 penetrating through the substrate body 105a, similar to the substrate 100 described in

[0136] Since the first bonding structure ST1 and the second bonding structure ST2 in contact with and bonded to each other are described with reference to Figure 1A and Figure 1B The description of the first bonding structure ST1 and the second bonding structure ST2 will be omitted.

[0137] Next, a modified example of the semiconductor package 1h according to an exemplary embodiment will be described with reference to Figure 12 is a cross-sectional view illustrating a modified example of the semiconductor package 1h according to an exemplary embodiment. Figure 12

[0138] In the modified example, the semiconductor package 1h can include a lower structure 10a as described in Figure 12 Figure 11 The semiconductor package 1h can further include a molding layer 450 formed on the substrate 100a and surrounding side surfaces of the plurality of semiconductor chips 200 and 300.

[0139] The semiconductor package 1h can further include a heat dissipation structure 460 covering upper portions of the plurality of semiconductor chips 200 and 300. The heat dissipation structure 460 can include an insulating thermal conduction layer 462 and a heat sink 464 on the thermal conduction layer 462.

[0140] Next, a modified example of the semiconductor package 1i according to an exemplary embodiment will be described with reference to Figure 13 is a cross-sectional view illustrating a modified example of the semiconductor package 1i according to an exemplary embodiment. Figure 13

[0141] In the modified example, the semiconductor package 1i can include a lower structure 10a as described in Figure 13 ​​​The semiconductor package 1i can include a substrate 100a' including substrate internal circuitry 130' and 135'. Similar to the substrate 100' described in Figure 10 the substrate 100a' can include a substrate body 105, substrate internal circuitry 128 disposed below the substrate body 105, and a substrate lower pad 135' disposed below the substrate internal circuitry 128. The substrate internal circuitry 128 can be disposed in a substrate lower insulating layer 130' below the substrate body 105.

[0142] As described above, the substrate 100a' can include substrate backside structures 160' and 165 disposed on the substrate body 105, first bonding structures ST1 disposed on the substrate backside structures 160' and 165, and a substrate through electrode structure 110 penetrating through the substrate body 105. Thus, the substrate 100a' can be a semiconductor chip including the substrate internal circuitry 128.

[0143] The semiconductor package 1i can be understood as a similar structure to the semiconductor package 1g and the semiconductor package 1h with reference to Figure 11 and Figure 12 except for the substrate 100a described in Figure 11 and Figure 12 .

[0144] Next, exemplary embodiments of a method of manufacturing a semiconductor package according to exemplary embodiments will be described with reference to Figures 14A to 14D .

[0145] With reference to Figure 14A , a wafer 100W can be attached to a carrier substrate 510a. The wafer 100W can be attached to the carrier substrate 510a by an adhesive layer 520a disposed on the carrier substrate 510a.

[0146] The wafer 100W can include a substrate body 105, a lower insulating layer 130 and a substrate lower pad 135 disposed below the substrate body 105, substrate backside structures 165 and 160 on the substrate body 105, first bonding structures on the substrate backside structures 160 and 165, and a substrate through electrode structure 110 penetrating through the substrate body 105. The substrate backside structures 160 and 165 can include substrate backside wiring structures 160 disposed in a substrate backside insulating layer 165. The substrate body 105 can be a semiconductor wafer, such as a silicon wafer. That is, the substrate body 105 can be a semiconductor substrate, such as a silicon substrate.

[0147] As described with reference to Figure 1A and Figure 1B , the first bonding structures can include first pads P1a and P1b, a pad connection IPa, a test pad TP, and a first insulating layer INS1. Since the first bonding structures have been described with reference toFigure 1A and Figure 1B The first pads P1a and P1b, the pad connection portion IPa, the test pad TP, and the first insulating layer INS1 are described, and thus detailed descriptions thereof will be omitted here.

[0148] The connection structure 20 can be formed under the base lower pad 135 of the wafer 100W. The connection structure 20 can be embedded in the adhesive layer 520a.

[0149] The test equipment 1000 can be used to inspect the wafer 100W for defects. For example, by contacting the probes 1010a and 1010b of the test equipment 1000 to different test pads TP, the wafer 100W can be inspected by measuring electrical shorts of the base wiring structure 160 or leakage current of the base wiring structure 160.

[0150] Referring to Figure 14B As described above, when the wafer 100W is determined to be in a normal state (i.e., free of any defects) as a result of inspection of the wafer 100W for defects, the semiconductor chip 400 can be coupled to a portion of the wafer 100W. The semiconductor chip 400 can be the semiconductor chip 400 described with reference to Figure 1A and Figure 1B The third semiconductor chip 400 is described. Thus, the third semiconductor chip 400 can include a third semiconductor body 405, internal circuit structures 415 and 420 disposed under the third semiconductor body 405, a second pad P2b disposed under the internal circuit structures 415 and 420, and a second insulating layer INS2. The internal circuit structures 415 and 420 can include a lower insulating layer 420 and internal circuit wiring 415 disposed in the lower insulating layer 420.

[0151] The third semiconductor chip 400 can be placed on the wafer 100W, and pressure can be applied to the third semiconductor chip 400 in a thermal atmosphere (e.g., about 200°C to about 300°C) higher than room temperature. Thus, the first pad P1b of the wafer 100W and the second pad P2b of the third semiconductor chip 400 can be engaged and coupled to each other, and the first insulating layer INS1 of the wafer 100W and the second insulating layer INS2 of the third semiconductor chip 400 can be engaged and coupled to each other. Here, the temperature of the thermal atmosphere can not be limited to about 200°C to about 300°C, but can vary according to design intent. When the connection structure 20 embedded in the adhesive layer 520a is a solder ball, the adhesive layer 520a can prevent the connection structure 20 from being deformed due to the thermal atmosphere.

[0152] The test equipment 1000 can be used to inspect the wafer 100W for defects as described above with reference to Figure 14AThe same method described above is used to inspect the third semiconductor chip 400 for defects. For example, by contacting the probes 1010a and 1010b of the test equipment 1000 with different test pads TP of the wafer 100W, the electrical short circuit or leakage current of the internal circuit wiring of the third semiconductor chip 400 can be measured, thereby inspecting the third semiconductor chip 400.

[0153] Reference Figure 14C When the third semiconductor chip 400 is operating normally, as a result of defect inspection of the third semiconductor chip 400, the first semiconductor chip 200 (e.g., ...) can then be replaced. Figure 1A and Figure 1B (As described in the text) is coupled to the chip 100W.

[0154] The first semiconductor chip 200 may include a first bonding structure ( Figure 1B ST1) and the second joint structure ( Figure 1B ST2), for example Figure 1A and Figure 1B The first bonding structure and the second bonding structure described herein. The first semiconductor chip 200 Figure 1B The first bonding structure ST1 shown can be bonded simultaneously with the contact wafer 100W. The second bonding structure of the first semiconductor chip 200 ( Figure 1B ST2 may include second pads P2a and P2b and a second insulating layer INS2, as shown in reference. Figure 1A , Figure 1B , Figure 2A and Figure 2B The first bonding structure of the first semiconductor chip 200 (described). Figure 1B ST1 may include first pads P1a and P1b, test pad TP, and first insulating layer INS1, as shown in reference. Figure 1A , Figure 1B , Figure 2A and Figure 2B As stated above.

[0155] The first semiconductor chip 200 can be placed on the wafer 100W, and pressure can be applied to the first semiconductor chip 200 in a hot atmosphere with a temperature higher than room temperature. Therefore, the first pads P1a and P1b of the wafer 100W and the second pads P2a and P2b of the first semiconductor chip 200 can be bonded and coupled to each other, and the first insulating layer INS1 of the wafer 100W and the second insulating layer INS2 of the first semiconductor chip 200 can be bonded and coupled to each other. Here, the temperature of the hot atmosphere is not limited to about 200°C to about 300°C, but can be varied. When the connection structure 20 embedded in the adhesive layer 520a is a solder ball, the adhesive layer 520a can prevent the connection structure 20 from deforming due to the hot atmosphere.

[0156] Then, the first semiconductor chip 200 can be inspected for defects using the test equipment 1000 in the same manner as described above. For example, by contacting the test pads TP of the first semiconductor chip 200 with the probes 1010a and 1010b of the test equipment 1000, the internal circuit wiring of the first semiconductor chip 200 can be measured. Figure 1B The short circuit or leakage current of the 215) can be checked, thereby allowing the first semiconductor chip 200 to be inspected.

[0157] Reference Figure 14D When the first semiconductor chip 200 is operating normally, as a result of defect inspection of the first semiconductor chip 200, the second semiconductor chip 300 (e.g., ...) can be... Figure 1A and Figure 1B (as described in the text) is coupled to the first semiconductor chip 200. The coupling of the second semiconductor chip 300 to the first semiconductor chip 200 can be substantially the same as the coupling of the first semiconductor chip 200 to the wafer 100W.

[0158] Then, the wafer 100W can be cut using a sawing process 600, and the cut wafer 100W can then be separated from the adhesive layer 520a. Therefore, it is possible to... Figure 1A and Figure 1B The semiconductor package 1a is formed as described above. When the semiconductor package 1a further includes, for example... Figure 1A and Figure 1B When using the lower structure 10 as described above, the method may further include, after separating the cut wafer 100W from the adhesive layer 520a, mounting the separated wafer 100W onto the lower structure 10.

[0159] In another instance, in order to form Figure 11 The 1g semiconductor package described in the text can perform actions such as Figure 14A The defect inspection performed on the 100W wafer shown is then as follows: Figure 14C The formation of the first semiconductor chip 200 and the defect inspection of the first semiconductor chip 200 can be repeatedly performed as shown, and then a chip can be formed as shown. Figure 14D The second semiconductor chip 300 is described in the text. Then, it can be formed as follows: Figure 11 The molding layer described in the text ( Figure 11 (450), and can perform operations on the molding layer ( Figure 11 The sawing process 600 is used to cut the 450) and the 100W wafer.

[0160] According to an exemplary embodiment, a semiconductor package can be provided, which includes first pads P1a and P1b of a first bonding structure ST1 and second pads P2a and P2b of a second bonding structure ST2 which are in contact with and bonded to each other, and a first insulating layer INS1 of the first bonding structure ST1 and a second insulating layer INS2 of the second bonding structure ST2 which are in contact with and coupled to each other. The thickness of the semiconductor package can be miniaturized. Such a semiconductor package can more efficiently release heat in the chip outward through the first pads P1a and P1b and the second pads P2a and P2b which are in contact with and coupled to each other. A semiconductor package having improved heat dissipation characteristics can be provided.

[0161] According to an exemplary embodiment, a semiconductor package including a test pad TP can be provided. Since whether a chip in the semiconductor package is defective or not can be checked through the test pad TP before the semiconductor package is finally formed, the productivity of the semiconductor package can be improved.

[0162] As described above, according to an exemplary embodiment, a semiconductor package can be provided, which includes pads bonded to each other while being in contact with each other, and a chip including insulating layers coupled to each other while being in contact with each other. The thickness of the semiconductor package can be reduced, so that the semiconductor package can be miniaturized. Such a semiconductor package can efficiently release heat in the chip outward through the pads which are coupled to each other while being in contact with each other. Accordingly, a semiconductor package having improved heat dissipation characteristics can be provided.

[0163] According to an exemplary embodiment, a semiconductor package including a test pad TP can be provided. Since whether a chip in the semiconductor package is defective or not can be checked through the test pad TP before the semiconductor package is finally formed, the productivity of the semiconductor package can be improved.

[0164] While the above has shown and described in detail certain exemplary embodiments, it will be obvious to those skilled in the art that various changes and modifications can be made therein without departing from the scope of the inventive concepts as defined by the appended claims.

Claims

1. A semiconductor package comprising: a substrate comprising a first bonding structure; and a first semiconductor chip comprising a second bonding structure coupled to the first bonding structure of the substrate, wherein the first bonding structure comprises: a test pad; a first pad electrically connected to the test pad; a pad connection electrically connecting the first pad and the test pad to each other; and a first insulating layer, wherein the second bonding structure comprises: a second pad electrically connected to the first pad; a dummy connection contacting the pad connection; and a second insulating layer contacting the first insulating layer, wherein at least a portion of the test pad contacts the second insulating layer.

2. The semiconductor package of claim 1, wherein at least a portion of the pad connection contacts the second insulating layer.

3. The semiconductor package of claim 1, wherein the substrate comprises: a substrate body; a through-electrode structure penetrating through the substrate body; and a substrate backside structure disposed on the substrate body, wherein the first bonding structure of the substrate is disposed on the substrate backside structure, and wherein the substrate backside structure comprises a substrate wiring structure electrically connected to the test pad.

4. The semiconductor package of claim 3, wherein the substrate body comprises a silicon substrate.

5. The semiconductor package of claim 1, wherein the substrate comprises an interposer.

6. The semiconductor package of claim 1, wherein the substrate comprises a different semiconductor chip than the first semiconductor chip.

7. The semiconductor package of claim 1, wherein the test pad has a width greater than a width of the first pad.

8. The semiconductor package of claim 1, further comprising: a lower structure disposed below the substrate; and a connection structure disposed between the substrate and the lower structure.

9. A semiconductor package comprising: a substrate comprising a first bonding structure; and a first semiconductor chip comprising a second bonding structure coupled to the first bonding structure of the substrate, wherein the first bonding structure comprises: a test pad; a first pad electrically connected to the test pad; a pad connection electrically connecting the first pad and the test pad to each other; and a first insulating layer, wherein the second bonding structure comprises: a dummy pad portion; a second pad electrically connected to the first pad; and a second insulating layer contacting the first insulating layer, wherein at least a portion of the test pad contacts the second insulating layer, wherein the test pad of the substrate comprises: a test region; and a dummy region surrounding the test region, and wherein the dummy pad portion of the second bonding structure contacts the dummy region of the test pad.

10. The semiconductor package of claim 9, wherein the test region contacts the second insulating layer of the first semiconductor chip.

11. A semiconductor package comprising: a substrate comprising a substrate bonding structure and located on a lower structure; a connection structure between the substrate and the lower structure; ​ ​ ​ ​ a first semiconductor chip on a first region of the base, a second semiconductor chip on a second region of the base and spaced apart from the first semiconductor chip in a first direction parallel to an upper surface of the lower structure, wherein the base bonding structure of the base includes a base insulating layer, a first base pad, a base test pad, and a second base pad, wherein the first semiconductor chip includes a first semiconductor substrate, a first bonding structure, and a first internal circuit structure between the first semiconductor substrate and the first bonding structure, wherein the first bonding structure includes a first insulating layer bonded to the base insulating layer and a first front side pad bonded to the first base pad along a plane at which the first front side pad and the first base pad face each other, wherein the second semiconductor chip includes a second semiconductor substrate, a second bonding structure, and a second internal circuit structure between the second semiconductor substrate and the second bonding structure, wherein the second bonding structure includes a second insulating layer bonded to the base insulating layer and a second front side pad bonded to the second base pad along a plane at which the second front side pad and the second base pad face each other, wherein the base test pad does not overlap the second semiconductor chip in a vertical direction perpendicular to the upper surface of the lower structure, wherein the base test pad does not overlap the first front side pad of the first semiconductor chip in the vertical direction and overlaps a lower surface of the first insulating layer of the first semiconductor chip in the vertical direction, wherein the lower surface of the first insulating layer and a lower surface of the first front side pad are coplanar with each other, and wherein a center of an upper surface of the base test pad is in contact with the lower surface of the first insulating layer.

12. The semiconductor package of claim 11, wherein the base has a first width that is greater than a second width of each of the first semiconductor chip and the second semiconductor chip.

13. A semiconductor package, comprising: a base; a first semiconductor chip disposed on the base and including a first front side bonding structure, a first internal circuit structure on the first front side bonding structure, a first semiconductor substrate on the first internal circuit structure, and a first back side bonding structure on the first semiconductor substrate, wherein the first semiconductor substrate is between the first back side bonding structure and the first internal circuit structure; and a second semiconductor chip disposed on the first semiconductor chip and including a second front side bonding structure, a second internal circuit structure on the second front side bonding structure, a second semiconductor substrate on the second internal circuit structure, and a second back side bonding structure on the second semiconductor substrate, wherein the first front side bonding structure includes a first front side insulating layer and a first front side pad, wherein the first back side bonding structure includes a first back side insulating layer, a first back side pad, and a first back side test pad, wherein the first back side test pad does not overlap the second semiconductor chip in a vertical direction perpendicular to an upper surface of the lower structure, wherein the first back side test pad does not overlap the second front side pad of the second semiconductor chip in the vertical direction and overlaps a lower surface of the second insulating layer of the second semiconductor chip in the vertical direction, wherein the lower surface of the second insulating layer and a lower surface of the second front side pad are coplanar with each other, and wherein a center of an upper surface of the first back side test pad is in contact with the lower surface of the second insulating layer. wherein the second front side bonding structure includes a second front side insulating layer bonded to the first back side insulating layer and a second front side pad bonded to the first back side pad along a plane where the first back side pad and the second front side pad face each other, wherein the second back side bonding structure includes a second back side insulating layer, a second back side pad, and a second back side test pad, wherein a width of the first back side test pad is greater than a width of the first back side pad, wherein a width of the second back side test pad is greater than a width of the second back side pad, wherein the first back side test pad does not overlap the second front side pad, wherein the second front side bonding structure and the second internal circuit structure are located between the second semiconductor substrate of the second semiconductor chip and the first back side bonding structure of the first semiconductor chip, and wherein a center of an upper surface of the first back side test pad is in contact with a lower surface of the second front side insulating layer.

14. The semiconductor package of claim 13, wherein each of the first front side pad, the second front side pad, the first back side pad, and the second back side pad comprises a conductive material.

15. A method of forming a semiconductor package, comprising: forming a wafer including a first pad, a substrate test pad, and a first insulating layer; inspecting the wafer for defects through the substrate test pad of the wafer; coupling a first semiconductor chip including a first test pad to the wafer; performing a defect inspection of the first semiconductor chip through the first test pad of the first semiconductor chip; coupling a second semiconductor chip to the first semiconductor chip; and dicing the wafer to form a semiconductor package, wherein the semiconductor package includes: a substrate including a first bonding structure; a first semiconductor chip including a second bonding structure coupled to the first bonding structure of the substrate; and a second semiconductor chip on the first semiconductor chip, wherein the first bonding structure includes: the substrate test pad; the first pad electrically connected to the substrate test pad; a pad connection electrically connecting the first pad and the substrate test pad to each other; and the first insulating layer, wherein the second bonding structure includes: the first test pad; a second pad electrically connected to the first pad; a dummy connection contacting the pad connection; and a second insulating layer contacting the first insulating layer, and wherein at least a portion of the substrate test pad is in contact with the second insulating layer. ​

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