Integrated Circuit Package

Abstract

An integrated circuit package integrating a photonic die (oDie) and an electronic die (eDie). More specifically, the integrated circuit package may include a plurality of redistribution layers communicatively coupled to at least one of the photonic die and / or the electronic die, wherein a molding material at least partially surrounds at least one of the photonic die and / or the electronic die.

Description

Technical Field

[0001] The embodiment of the present invention relates to an integrated circuit package and a manufacturing method thereof. Background Art

[0002] Conventional packaging techniques generally involve segmenting the wafer and then packaging the individual dies on the cut wafer. Since the individual dies are packaged after the wafer has been cut, the package size tends to be significantly larger than the die size. In contrast, in standard wafer-level packaging techniques, the integrated circuits are packaged while portions of the wafer are stationary, and the wafer is then cut. Therefore, the resulting package is typically the same size as the die itself. However, due to the limited number of external contacts that can be accommodated in the limited package footprint, there are both advantages and disadvantages to having a smaller package. In some cases, this can become a significant limitation when considering complex semiconductor devices that require a large number of contacts. Summary of the invention

[0003] In one embodiment, an integrated circuit package includes: a photonic die (oDie) containing at least one optical component; an electronic die (eDie); a substrate, a plurality of redistribution layers, the plurality of redistribution layers being communicatively coupled to at least one of the photonic die and / or the electronic die, wherein the substrate includes a molding portion, the molding portion at least partially surrounding the at least one of the photonic die and / or the electronic die; and a connection portion, electrically coupling the at least one of the photonic die and / or the electronic die to at least one redistribution layer, the at least one redistribution layer being positioned adjacent to the topmost layer of the integrated circuit package. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] When read in conjunction with the accompanying drawings, various aspects of the present disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, the size of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0005] Figure 1 A cross-sectional view of a first example of a photonic package is depicted in accordance with some embodiments.

[0006] Figure 2A to Figure 2B A cross-sectional view of a second example of a photonic package is depicted in accordance with some embodiments.

[0007] FIG. 3A to FIG. 3B A cross-sectional view of a third example of a photonic package is depicted in accordance with some embodiments.

[0008] FIG. 4A to FIG. 4B A cross-sectional view of a fourth example of a photonic package is depicted in accordance with some embodiments.

[0009] FIG. 5A to FIG. 5B Depicted is a cross-sectional view of a fifth example of a photonic package in accordance with some embodiments.

[0010] Figure 6 A system incorporating a photonic package according to some embodiments is depicted.

[0011] Figure 7 A flow chart depicts a method for forming a photonic package according to some embodiments.

[0012] Figures 8A to 8P Steps of a process for fabricating a photonic package according to some embodiments are described. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are just examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include an embodiment in which the first feature and the second feature are directly contacted, and may also include an embodiment in which an additional feature may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat figure numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description herein, spatially relative terms such as "below," "beneath," "lower," "above," "upper," and the like may be used to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0015] When optical components such as lasers, optical modulators, optical detectors, and optical switches are incorporated into packaged electronic modules, conventional packaging techniques and standard wafer level packaging techniques can generally result in low-density pin counts, larger form factors, and higher costs. For example, an integrated circuit can be attached to an insert such as a silicon insert via microbumps and then connected to a printed circuit board via a conductive glue. When the optical fiber array is located on the insert, connections, power, and / or data from the integrated circuit interfaced with the optical fiber array are routed from the microbumps to external pads located at the PCB through one or more tracks within the insert and wire bonding connections. While wire bonding can be cost-effective and flexible, wire bonding techniques can suffer from safety issues and generally result in larger package sizes.

[0016] A multi-chip module including one or more optical modules may include an integrated circuit that communicates with the optical module. In some cases, a flip-chip packaging technique may be used so that the integrated circuit and the optical module are coupled to each other in a communicative manner and attached to the substrate using one or more bumps. In some cases, an insert may reside between the integrated circuit and the optical module so that connections (e.g., connections coupled to the integrated circuit and / or the optical module and coupled to the substrate) may be spread to a wider spacing and / or the connections may be rewired to different connections. In some cases, the insert may utilize through-silicon vias (TSVs) to connect the insert to the substrate, while the integrated circuit and the optical module may be attached to the insert using existing connection methods (e.g., bump connections). In some cases, the insert may be a photonic insert for directing and / or guiding light from a light source such as a laser to another location in the package. Such multi-chip modules typically have a larger form factor, a higher cost, and typically have a lower density and pin count.

[0017] The embodiments described herein disclose advanced packaging technologies that integrate photonic die (oDie) and electronic die (eDie) into one package. In some cases, components other than oDie and eDie may also be included in the package. For example, the package may include oDie, eDie, and a switch ASIC that forms an internal wiring package. The components of the eDie may include, but are not limited to, at least one of the following: one or more serializers / parallels (serial parallelizers (serde)), one or more transceivers, clock circuits, and control logic and circuits. The integration of the eDie with the switch ASIC can shorten the distance between the serial parallelizer and the switch logic, which in turn can reduce the size and power consumption of the serial parallelizer. In some cases, silicon vias can be used in the substrate to electrically connect various components. In other embodiments described herein, the oDie may be integrated with one or more additional photonic components in a single integrated circuit package. The eDie can then be attached to the integrated circuit package via one or more bumps.

[0018] As described herein, a package may utilize Integrated Fan-Out (InFO) technology to integrate multiple dies that may include photonic integrated circuit applications into an integrated circuit package (also known as a wafer-level package). Thus, an advanced package that can handle high pin counts (e.g., high pin and component density) while having a small form factor may be obtained. Since InFO technology may be utilized, such a package may be highly integrated and may be manufactured at a lower cost than conventional packaging technology. Advanced packages may be suitable for high-speed circuits.

[0019] InFO packaging technology is different from other packaging technologies at least because fan-out packaging utilizes individual dies and buries them in materials such as epoxy molding compound or other materials and allocates space between each die for additional I / O connection points. Therefore, the use of silicon substrate real estate to accommodate higher pin counts can be avoided. In addition, redistribution layers can be used to route / reroute some I / O connections to edge areas, further adding to higher package pin count density and contact utilization.

[0020] Figure 1Depicts a cross-sectional view of a first package 104 according to some embodiments of the present disclosure. More specifically, the first package may utilize integrated circuit packaging technology (such as InFO packaging technology) and provide an optical fiber 112 coupled to an optical interconnect 117, wherein the optical interconnect 117 may be specifically configured to receive light and provide the received light to an oDie 116 for further processing. That is, when light is received at the first package 104 via an optical fiber, the first package 104 is configured to convert the light into an electrical signal. One or more optical interconnects 117 may receive light and direct or guide the light to one or more detectors positioned at the oDie 116 via an optical waveguide. One or more detectors of the oDie 116 may detect the light and subsequently convert the light into one or more corresponding electrical signals. The one or more electrical signals may flow through a redistribution layer 120 to, for example, an eDie 108, wherein the eDie 108 may further process the received one or more electrical signals. The oDie 116 may be coupled to the eDie 108 via a redistribution layer 120 and one or more bumps, such as microbumps 124 of the oDie 116 and microbumps 128 of the eDie 108. The eDie 108 may process one or more electrical signals and provide the one or more processed electrical signals to the bumps 132 via the redistribution layer 120 and the through silicon vias 136 for connection to a printed circuit board of another die.

[0021] The first package 104 may include one or more parts. For example, the first package 104 may include an eDie 108, an optical fiber 112, and an oDie packaging portion 140. The oDie packaging portion 140 may include a first connection portion 144, one or more redistribution layers 120, one or more oDies 116, one or more silicon layers 148, one or more silicon through-vias 136, and one or more second connection portions 152. The one or more first connection portions 144 may include one or more bumps 124 as previously discussed; the one or more second connection portions 152 may include one or more bumps 132. The eDie 108, the oDie packaging portion 140, and the optical fiber 112 may be encapsulated in a protective material 156, wherein one or more bumps 132 in the one or more second connection portions 152 may be exposed for connection to a printed circuit board, other dies, and / or external connections. For example, the first package 104 may be coupled to a log and / or a memory.

[0022] Figure 2A Depicted is a cross-sectional view of a second package 200 according to an embodiment of the present disclosure. Figure 2B Depiction Figure 2A. Similar to the first package 104, the second package 200 may utilize integrated circuit packaging technology, such as InFO packaging technology. The second package may include a substrate 204. The substrate 204 may include a mold material, a silicon material, and / or other substantially insulating or semiconductor materials. The package 200 may include a protective layer 212 formed on top of the substrate 204, directly contacting the substrate 204, and / or arranged on the substrate 204. The protective layer 212 may include a polyimide and / or polybenzoxazole material. The protective layer 212 may be a stress relief coating used as a protective layer or "buffer coating" or as a redistribution layer 252 before packaging. Before forming the protective layer 212, one or more redistribution layers 208 may be formed on top of the substrate 204, directly contacting the substrate 204, and / or arranged on at least a portion of the substrate 204. Another protective layer 216 may be formed on at least a portion of the protective layer 212 and the redistribution layer 252. In some embodiments, one or more through-holes 218 may be formed within protective layer 216 and / or protective layer 212. In some cases, the first through-hole may be formed after forming the first protective layer 212, and the second through-hole may be formed after forming the second protective layer 216. Alternatively or additionally, the first through-hole and / or the second through-hole may be formed after protective layer 212 and protective layer 216 have been formed. For example, one or more portions of protective layer 216 may be removed; for example, the one or more portions may be etched, drilled, and / or exposed to light to form a first hole in protective layer 212 and / or protective layer 216. An insulating material may then be placed within the first hole to line the sides of the hole. Finally, a conductive material may be placed in the hole, thereby forming one or more through-holes 218.

[0023] The package 200 may include one or more redistribution layers 220 formed on, on top of, in direct contact with, or otherwise disposed on the protective layer 216. In one embodiment, a protective layer 224 may be formed on, on top of, in direct contact with, or otherwise disposed on the protective layer 216. One or more portions of the protective layer 224 may be removed. For example, the one or more portions may be etched, drilled, exposed to light, etc., and thereby form holes in the protective layer 224. Subsequently, the redistribution layer 220 may be formed within the one or more holes in the redistribution layer 220. Finally, one or more under bump metallization layers 228 may be formed on the redistribution layer 220 ; the one or more under bump metallization layers 228 may be configured to receive solder balls and / or connectors 232A to 232C to form, for example, a ball grid array.

[0024] As previously discussed, the package 200 may include a redistribution layer 208; the redistribution layer 208 may provide a signal path from the optical die (oDie) 240 and / or one or more of the one or more eDies 236 to one or more of the connectors 232A to 232C via the interface portion 276. The connection portion 244 may include a redistribution layer 286A and / or a redistribution layer 286B, one or more pads 284A and 284B, one or more conductive portions 270, and one or more insulating portions 282. A through integrated circuit package via (through integrated circuit package via) or through insulator via (TIV) 272 may be formed in the substrate 204. For example, the TIV 272 may couple the redistribution layer 208 to the backside redistribution layer 246. For example, the backside redistribution layer 246 may couple the redistribution layer 208 to one or more redistribution layers 252. Thus, a via 248 may be formed that couples the redistribution layer 252 to one or more copper redistribution layers 286A and / or copper redistribution layers 286B. The redistribution layer 268A and / or the redistribution layer 286B may be formed directly above or otherwise disposed on the liner 284A and / or the liner 284B. The liner 284A and / or the liner 284B may be disposed within an insulating portion 282 comprising an insulating material; thus, one or more of the liner 284A and / or the liner 284B may be coupled to the oDie and / or the eDie 236 via the conductive portion 270.

[0025] As previously discussed, oDie 240 can be coupled to an optical interconnect 264, which can be configured to receive light from optical fiber 260 and / or transmit the light to a detector portion of oDie 240. Thus, an opening can exist on the fiber array receiving side of package 200. oDie 240 can convert the light into one or more electrical signals and transmit or otherwise provide the one or more electrical signals to eDie 236 and / or external connections, such as one or more of connectors 232A to 232C. The one or more electrical signals can be transmitted through package 200 via a redistribution layer, one or more through-vias, one or more TIVs, one or more pads 284A and / or pads 284B, and one or more of the one or more conductive portions 270.

[0026] According to some embodiments of the present disclosure, oDie 240 and eDie 236 may reside within package 200. For example, a cavity, hole, or other portion may be formed or otherwise present in substrate 204. Each of one or more oDies 240 and / or one or more eDies 236 may reside, for example, between TIVs on both sides in a cross-sectional view. In addition, substrate material 204 may include epoxy or otherwise be epoxy. In some embodiments, oDie 240 and / or eDie 236 may be directly connected to one or more of conductive portions 270 or otherwise disposed on one or more of the conductive portions.

[0027] Figure 3A Depicted is a cross-sectional view of a third package 300 according to an embodiment of the present disclosure. Figure 3B Depiction Figure 3A . An enlarged portion of the third package 300 depicted in FIG. . Similar to the first package 104 and the second package 200, the third package 300 may utilize integrated circuit packaging technology. The third package may include a substrate 304. The substrate 304 may include a mold material, a silicon material, and / or other substantially insulating or semiconductor materials. The package 300 may include a protective layer 312 formed on top of the substrate 304, directly contacting the substrate 304, and / or arranged on the substrate 304. The protective layer 312 may include a polyimide and / or polybenzoxazole material. The protective layer 312 may be a stress relief coating used as a protective layer or "buffer coating" or as a redistribution layer 352 before packaging. Before forming the protective layer 312, one or more redistribution layers 308 may be formed on top of the substrate 304, directly contacting the substrate 304, and / or arranged on at least a portion of the substrate 304. Another protective layer 316 may be formed on at least a portion of the protective layer 312 and the redistribution layer 352. In some embodiments, one or more through-holes 318 may be formed within protective layer 316 and / or protective layer 312. In some cases, the first through-hole may be formed after forming the first protective layer 312, and the second through-hole may be formed after forming the second protective layer 316. Alternatively or additionally, the first through-hole and / or the second through-hole may be formed after protective layer 312 and protective layer 316 have been formed. For example, one or more portions of protective layer 316 may be removed; for example, the one or more portions may be etched, drilled, and / or exposed to light to form a first hole in protective layer 312 and / or protective layer 316. An insulating material may then be placed within the first hole to line the sides of the hole. Finally, a conductive material may be placed in the hole, thereby forming one or more through-holes 318.

[0028] Package 300 may include one or more redistribution layers 320 formed on, on top of, in direct contact with, or otherwise disposed on protective layer 316. In one embodiment, protective layer 324 may be formed on, on top of, in direct contact with, or otherwise disposed on protective layer 316. One or more portions of protective layer 324 may be removed. For example, the one or more portions may be etched, drilled, exposed to light, etc., and thereby form holes in protective layer 324. Subsequently, redistribution layer 320 may be formed within the one or more holes in redistribution layer 320. Finally, one or more under bump metallization layers 328 may be formed on the redistribution layer 320 ; the one or more under bump metallization layers 328 may be configured to receive solder balls and / or connectors 332A to 332C to form, for example, a ball grid array.

[0029] As previously discussed, the package 300 may include a redistribution layer 308; the redistribution layer 308 may provide a signal path from the photonic die (oDie) 340 and / or one or more of the one or more eDies 336 to one or more of the connectors 332A to 332C via the interface portion 376. The connection portion 344 may include one or more of the redistribution layers 386A and / or 386B, one or more pads 384A and 384B, one or more conductive portions 370, and one or more insulating portions 382. A through integrated circuit package via (TIV) or through insulator via 372 may be formed in the substrate 304. For example, the TIV 372 may couple the redistribution layer 308 to the backside redistribution layer 346. For example, the backside redistribution layer 346 may couple the redistribution layer 308 to the one or more redistribution layers 352. Thus, a via 348 may be formed that couples the redistribution layer 352 to one or more redistribution layers 386A and / or redistribution layers 386B. The redistribution layer 368A and / or the redistribution layer 386B may be formed directly above or otherwise disposed on the liner 384A and / or the liner 384B. The liner 384A and / or the liner 384B may be disposed within an insulating portion 382 comprising an insulating material; thus, one or more of the liner 384A and / or the liner 384B may be coupled to the eDie 336 via the conductive portion 370.

[0030] The oDie 340 may be coupled to an optical interconnect 364, which may be configured to receive light from the optical fiber 360 and / or transmit the light to a detector portion of the oDie 340. Thus, an opening may exist on the fiber array receiving side of the package 300. The oDie 340 may convert the light into one or more electrical signals and transmit or otherwise provide the one or more electrical signals to the eDie 336 and / or external connections, such as one or more of the connectors 332A to 332C. The one or more electrical signals may be transmitted through the package 300 via a redistribution layer, one or more through-vias, one or more TIVs, one or more pads 384A and / or pads 384B, and one or more of the conductive portions 370.

[0031] According to some embodiments of the present disclosure, oDie 340 and eDie 336 may reside within package 300. For example, a cavity, hole, or other portion may be formed or otherwise present in substrate 304. Each of one or more oDies 340 and / or one or more eDies 336 may reside, for example, between TIVs on both sides in the cross-sectional view. In addition, substrate material 304 may include epoxy or otherwise be epoxy such that the substrate material may be between eDie 336, oDie 340, and one or more of the one or more TIVs. In some embodiments, eDie 336 may be directly connected to or otherwise disposed on one or more of conductive portion 370 and insulating portion 382.

[0032] like FIG. 3A to FIG. 3B As further depicted in FIG. 3 , eDie 336 can be positioned between oDie 340 and insulating portion 382. Thus, oDie 340 can be coupled to eDie 336 via one or more through-holes 388 and one or more bumps 390. According to at least one example, oDie 340 can be flip-chip bonded to eDie 346, while package 300 employs integrated circuit packaging technology.

[0033] Figure 4A Depicted is a cross-sectional view of a fourth package 400 according to an embodiment of the present disclosure. Figure 4B Depiction Figure 4A. Similar to the first package 104, the second package 200, and the third package 300, the fourth package 400 may utilize integrated circuit packaging technology. The fourth package may include a substrate 404. The substrate 404 may include a mold material, a silicon material, and / or other substantially insulating or semiconductor materials. The package 400 may include a protective layer 412 formed on top of the substrate 404, directly contacting the substrate 404, and / or arranged on the substrate 404. The protective layer 412 may include a polyimide and / or polybenzoxazole material. The protective layer 412 may be a stress relief coating used as a protective layer or "buffer coating" or as a redistribution layer 452 before packaging. Before forming the protective layer 412, one or more redistribution layers 408 may be formed on top of the substrate 404, directly contacting the substrate 404, and / or arranged on at least a portion of the substrate 404. Another protective layer 416 may be formed over at least a portion of the protective layer 412 and the redistribution layer 452. In some embodiments, one or more through-holes 418 may be formed in the protective layer 416 and / or the protective layer 412. In some cases, the first through-hole may be formed after the first protective layer 412 is formed, and the second through-hole may be formed after the second protective layer 416 is formed. Alternatively or additionally, the first through-hole and / or the second through-hole may be formed after the protective layer 412 and the protective layer 416 have been formed. For example, one or more portions of the protective layer 416 may be removed; for example, the one or more portions may be etched, drilled, and / or exposed to light to form a first hole in the protective layer 412 and / or the protective layer 416. An insulating material may then be placed in the first hole to line the sides of the hole. Finally, a conductive material may be placed in the hole, thereby forming the one or more through-holes 418.

[0034] The package 400 may include one or more redistribution layers 420 formed on, on top of, in direct contact with, or otherwise disposed on the protective layer 416. In one embodiment, a protective layer 424 may be formed on, on top of, in direct contact with, or otherwise disposed on the protective layer 416. One or more portions of the protective layer 424 may be removed. For example, the one or more portions may be etched, drilled, exposed to light, etc., and thereby form holes in the protective layer 424. Subsequently, the redistribution layer 420 may be formed within the one or more holes in the redistribution layer 420. Finally, one or more under bump metallization layers 428 may be formed on the redistribution layer 420; the one or more under bump metallization layers 428 may be configured to receive solder balls and / or connectors 432A to 432C to form, for example, a ball grid array.

[0035] As previously discussed, the package 400 may include a redistribution layer 408; the redistribution layer 408 may provide a signal path from the photonic die (oDie) 440 and / or one or more of the one or more eDies 436 to one or more of the connectors 432A to 432C via the interface portion 476. The connection portion may include one or more of the redistribution layers 486A and / or 486B, one or more pads 484A and 484B, one or more conductive portions 470, and one or more insulating portions 482. A through insulator via (TIV) 472 (or integrated circuit package through via) may be formed in the substrate 404. For example, the TIV 472 may couple the redistribution layer 408 to the backside redistribution layer 446. For example, the backside redistribution layer 446 may couple the redistribution layer 408 to the one or more redistribution layers 452. Thus, a via 448 may be formed that couples the redistribution layer 452 to one or more redistribution layers 486A and / or redistribution layers 486B. The redistribution layer 468A and / or the redistribution layer 486B may be formed directly above or otherwise disposed on the liner 484A and / or the liner 484B. The liner 484A and / or the liner 484B may be disposed within an insulating portion 482 comprising an insulating material; thus, one or more of the liner 484A and / or the liner 484B may be coupled to the oDie 440 via the conductive portion 470.

[0036] The oDie 440 may be coupled to an optical interconnect 464, which may be configured to receive light from the optical fiber 460 and / or transmit the light to a detector portion of the oDie 440. Thus, an opening may be present on the fiber array receiving side of the package 400. The oDie 440 may convert the light into one or more electrical signals and transmit or otherwise provide the one or more electrical signals to the eDie 436 and / or external connections, such as one or more of the connectors 432A to 432C. The one or more electrical signals may be transmitted through the package 400 via a redistribution layer, one or more through-vias, one or more TIVs, one or more pads 484A and / or pads 484B, and one or more of the conductive portions 470.

[0037] According to some embodiments of the present disclosure, oDie 440 and eDie 436 may reside within package 400. For example, a cavity, hole, or other portion may be formed or otherwise present in substrate 404. Each of one or more oDies 440 and / or one or more eDies 436 may reside, for example, between TIVs on both sides in the cross-sectional view. In addition, substrate material 404 may include epoxy or otherwise be epoxy such that the substrate material may be between eDie 436, oDie 440, and one or more of the one or more TIVs. In some embodiments, oDie 440 may be directly connected to or otherwise disposed on one or more of conductive portion 470 and insulating portion 482.

[0038] like FIG. 4A to FIG. 4B As further depicted in FIG. 4 , oDie 440 can be positioned between eDie 436 and insulating portion 482. Thus, eDie 436 can be coupled to oDie 440 using one or more bumps 490. One or more through-holes 488 can facilitate connection of oDie 440 to conductive portion 470 and / or eDie 436. According to at least one example, eDie 436 can be flip-chip bonded to oDie 440, while package 400 employs integrated circuit packaging technology.

[0039] Figure 5A Depicted is a cross-sectional view of a fifth package 500 according to an embodiment of the present disclosure. Figure 5B Depiction Figure 5A. Similar to the first package 104, the second package 200, the third package 300, and the fourth package 400, the fifth package 500 may utilize integrated circuit packaging technology. The fifth package may include a substrate 504. The substrate 504 may include a mold material, a silicon material, and / or other substantially insulating or semiconductor materials. The package 500 may include a protective layer 512 formed on top of the substrate 504, directly contacting the substrate 504, and / or arranged on the substrate 504. The protective layer 512 may include a polyimide and / or polybenzoxazole material. The protective layer 512 may be a stress relief coating used as a protective layer or "buffer coating" or as a redistribution layer 552 before packaging. Before forming the protective layer 512, one or more redistribution layers 508 may be formed on top of the substrate 504, directly contacting the substrate 504, and / or arranged on at least a portion of the substrate 504. Another protective layer 516 may be formed on at least a portion of the protective layer 512 and the redistribution layer 552. In some embodiments, one or more through-holes 518 may be formed in the protective layer 516 and / or the protective layer 512. In some cases, the first through-hole may be formed after the first protective layer 512 is formed, and the second through-hole may be formed after the second protective layer 516 is formed. Alternatively or additionally, the first through-hole and / or the second through-hole may be formed after the protective layer 512 and the protective layer 516 have been formed. For example, one or more portions of the protective layer 516 may be removed; for example, the one or more portions may be etched, drilled, and / or exposed to light to form a first hole in the protective layer 512 and / or the protective layer 516. An insulating material may then be placed in the first hole to line the sides of the hole. Finally, a conductive material may be placed in the hole, thereby forming one or more through-holes 518.

[0040] The package 500 may include one or more redistribution layers 520 formed on, on top of, in direct contact with, or otherwise disposed on the protective layer 516. In one embodiment, a protective layer 524 may be formed on, on top of, in direct contact with, or otherwise disposed on the protective layer 516. One or more portions of the protective layer 524 may be removed. For example, the one or more portions may be etched, drilled, exposed to light, etc., and thereby form holes in the protective layer 524. Subsequently, the redistribution layer 520 may be formed within the one or more holes in the redistribution layer 520. Finally, one or more under bump metallization layers 528 may be formed on the redistribution layer 520; the one or more under bump metallization layers 528 may be configured to receive solder balls and / or connectors 532A to 532C to form, for example, a ball grid array.

[0041] As previously discussed, the package 500 may include a redistribution layer 508; the redistribution layer 508 may provide a signal path from the photonic die (oDie) 540 and / or one or more of the one or more eDies 536 to one or more of the connectors 532A to 532C via the interface portion 576. The connection portion may include one or more of the redistribution layers 586A and / or 586B, one or more pads 584A and 584B, one or more conductive portions 570, and one or more insulating portions 582. Through insulator vias (TIVs) 572 may be formed in the substrate 504. For example, the TIVs 572 may couple the redistribution layer 508 to the backside redistribution layer 546. For example, the backside redistribution layer 546 may couple the redistribution layer 508 to the one or more redistribution layers 552. Thus, a via 548 may be formed that couples the redistribution layer 552 to one or more redistribution layers 586A and / or redistribution layers 586B. The redistribution layer 568A and / or the redistribution layer 586B may be formed directly above or otherwise disposed on the liner 584A and / or the liner 584B. The liner 584A and / or the liner 584B may be disposed within an insulating portion 582 comprising an insulating material; thus, one or more of the liner 584A and / or the liner 584B may couple an insert 588 that may couple the oDie 540 and the eDie 536 to the conductive portion 570.

[0042] The oDie 540 may be coupled to an optical interconnect 564, which may be configured to receive light from the optical fiber 560 and / or transmit the light to a detector portion of the oDie 540. Thus, an opening may be present on the fiber array receiving side of the package 500. The oDie 540 may convert the light into one or more electrical signals and transmit or otherwise provide the one or more electrical signals to the eDie 536 and / or external connections, such as one or more of the connectors 532A to 532C. The one or more electrical signals may be transmitted through the package 500 via a redistribution layer, one or more through-holes, one or more TIVs, one or more pads 584A and / or pads 584B, and one or more of the conductive portions 570.

[0043] According to some embodiments of the present disclosure, oDie 540 and eDie 536 may reside within package 500 along with insert 588. For example, a cavity, hole, or other portion may be formed or otherwise present in substrate 504. Each of one or more oDies 540, one or more eDies 536, and insert 588 may reside, for example, between TIVs on both sides in a cross-sectional view. In addition, substrate material 504 may include an epoxy group or be otherwise epoxy-based, so that the substrate material may be between eDie 536, oDie 540, and one or more of the one or more TIVs. In some embodiments, oDie 540 and eDie 536 may be connected to insert 588 using one or more bumps 590 and bumps 592, while insert 588 is directly connected to one or more of the conductive portion 570 and the insulating portion 582 or is otherwise arranged on the conductive portion and one or more of the insulating portion. As shown in FIG. FIG. 5A to FIG. 5B As further depicted in FIG. 5 , eDie 588 can be positioned between oDie 540 and / or eDie 536 and insulating portion 582. According to at least one example, eDie 536 and / or oDie 540 can be flip-chip bonded to interposer 588 in package 500 that employs integrated circuit packaging technology.

[0044] Figures 1 to 5B One or more of the foregoing embodiments of the package shown in can be included in a system or device. More specifically, Figure 6 System 600 is shown including a photonic package 604. System 600 also includes a processing subsystem 608 (having one or more processors) and a memory subsystem 612 (having memory).

[0045] In general, the system 600 may be implemented using a combination of hardware and / or software. Thus, the system 600 may include one or more program modules or instruction sets stored in a memory subsystem 612 (e.g., DRAM or another type of volatile computer-readable memory or non-volatile computer-readable memory) that may be executed by the processing subsystem 608 during operation.

[0046] System 600 may include: a switch, a hub, a bridge, a router, a communication system (e.g., a wavelength division multiplexing communication system), a storage area network, a data center, a network (e.g., a regional network), and / or a computer system (e.g., a multi-core processor computer system). In addition, the computer system may include, but is not limited to: a server (e.g., a multi-socket, multi-rack server), a laptop, a communication device or system, a personal computer, a workstation, a mainframe computer, a blade, an enterprise computer, a data center, a tablet computer, a supercomputer, a network-attached-storage (NAS) system, a storage-area network (SAN) system, a media player (e.g., an MP3 player), an appliance, a sub-notebook / netbook, a tablet computer, a smart phone, a cellular phone, a network appliance, a set-top box, a personal digital assistant (PDA), a toy, a controller, a digital signal processor, a game console, a device controller, a computing engine within an appliance, a consumer electronic device, a portable computing device or a portable electronic device, a personal assistant, and / or another electronic device.

[0047] In addition, the photonic package 604 can be used in a wide variety of applications, such as: communications (e.g., in transceivers, optical interconnects or optical links, such as for intra-chip communication or inter-chip communication), RF filters, biosensors, medicine (e.g., diagnostic techniques or surgical operations), bar code scanners, metrology (e.g., precise measurement of distances), manufacturing (cutting or welding), photolithography, data storage devices (e.g., optical storage devices or systems) and / or entertainment (laser displays).

[0048] Figure 7 A flowchart depicting a first example method for forming a photonic package according to some embodiments. In one embodiment, Figure 7 The process can be used to build Figures 1 to 5B First, one or more oDie 116, eDie 108 and / or insert 588 are bonded together in step 704 so that the resulting orientation results in the active surface facing downward. For example, one or more oDie, eDie and / or insert as shown in FIG. Figures 1 to 5B. The flip chip bonding technique may be applied to bond one or more oDie, eDie and / or insert. The resulting bonded die and / or insert are fixed to a temporary carrier wafer using a temporary adhesive, and the temporary carrier wafer may include one or more connection sections. An intermediate package is formed by dispensing a molding compound in step 708 to encapsulate the oDie, eDie and / or insert, and a compression and curing operation may be performed on the dispensed molding compound to produce an intermediate package in step 712. A reverse grinding operation may be performed on the intermediate package in step 716 to reveal the back side of the oDie, eDie and / or insert. In step 720, a through insulator via (TIV) is formed in the intermediate package. In step 724, a redistribution layer (RDL) 220 is formed on one or more portions of the surface exposed by the reverse grinding operation, wherein the RDL helps to route signals from the vias to the solder balls. In some embodiments, one or more pads, additional RDLs, and more protective layers may be formed. The temporary carrier wafer is removed in step 728, and the resulting intermediate package is flipped to expose the active surface of the oDie and / or eDie. In step 732, one or more optical connectors containing optical waveguides may be mounted to the intermediate package so that the optical waveguides are optically coupled to the oDie.

[0049] Figures 8A to 8P An example manufacturing process for manufacturing a photonic package according to some embodiments is described. When steps 8A to 8P are depicted as separate steps, it should be understood that one or more steps may be combined with another step and / or separated into multiple additional steps. The manufacturing process may begin at Fig. 8A , wherein a film 802 (e.g., a PBO film) may be applied to a carrier substrate, such as a glass carrier substrate 804. As an example, the film 802 may be applied via a light transfer heat conversion process. According to an embodiment of the present disclosure, the film 802 is applied to the back side of the glass carrier substrate 804, as will be apparent from the fabricated photonic package. Figure 8B At 804, a seed layer such as Ti / Cu may be applied to the film 804, followed by a conductive layer and photo patterning and wet acid etching to form redistribution layers (RDL) 806, RDL 808, and RDL 810. For example, the seed layer Ti / Cu may be 1K / 5KA thick, and the conductive layer may be 7 microns thick. Of course, other thicknesses of the Ti / Cu layer are contemplated. Figure 8CAt 802, a photoresist layer 812 may be applied to the film 802 and / or the RDL 806, RDL 808, and RDL 810. For example, the photoresist layer 812 may be 180 microns to 250 microns thick. Of course, other thicknesses of the photoresist layer 812 are contemplated. After the photoresist layer 812 is applied, one or more through insulator vias (TIVs) 814, TIV 816, TIV 818, TIV 820, and TIV 822 may be produced in the photoresist layer 812. TIV 814, TIV 816, TIV 818, TIV 820, and TIV 822 are examples of TIVs that may be produced; more or fewer TIVs are contemplated herein as are location, orientation, and sizing. For example, a TIV may include a 12 micron diameter hole. Each of the holes may or may not include an insulating portion lining the interior of the hole. In some cases, the insulating portion may only line a portion of the hole. In some cases, the insulating portion may not exist.

[0050] exist Fig.8D At , the hole may be filled with a conductive material 824. The conductive material 824 may include copper or other conductive materials. In some cases, the conductive material 824 may be formed using an electrochemical plating process such as, but not limited to, Cu-ECP. Fig. 8E At , excess copper can be removed to expose the photoresist layer 812. For example, a chemical mechanical planarization (Cu-CMP) process can be used to remove excess copper. Of course, other removal processes are contemplated. Figure 8F At , the photoresist layer 812 can be stripped away, leaving the TIV. In addition, a die attach film (DAF) 828 can be used to secure optical interconnects 832, O-Die 830, and E-Die 834. O-Die 830, E-Die 834, and optical interconnects 832 can be the same or similar to the previously described O-Die, E-Die, and optical interconnects previously described herein. In some cases, the DAF 828 can be pre-glued to a known good die and placed using a pick-and-place unit. In some instances, the DAF 828 can be picked and placed 10 times using a known good die. In some instances, the DAF 828 can be less than or greater than 10 microns thick. In Figure 8G At the locations, an overmolding compound (MC) 836 may be applied; MC 836 may be 50 microns thick; in some examples, MC 836 may be less than or greater than 50 microns thick. Figure 8H As depicted in , excess MC 836 may be removed; for example, excess MC 836 may be removed via grinding and / or chemical mechanical planarization.

[0051] According to an embodiment, conductive material 838 may be applied to the surface of MC 836. In some examples, conductive material 838 may be the same as or similar to conductive material 824. In some examples, an electrochemical plating process such as, but not limited to, Cu-ECP may be utilized. Conductive material 824 may be electrically coupled to conductive material 824, and in some cases electrically coupled to one or more of RDL 806, RDL 808, and RDL 810. Figure 8J , one or more portions of the conductive material 838 may be removed and a protective layer 840 may be formed on top of the MC 836 and on one or more portions of the conductive material 838. In some examples, the conductive material 838 may be 7 microns thick. In some examples, the protective layer 840 may be 4.5 microns thick; in other examples, the thickness of the protective layer 840 may be less than or greater than 4.5 microns thick. The protective layer may be the same or similar to a protective layer such as, but not limited to, the protective layer 412 previously described. In some examples, the protective layer 840 may include a PBO material.

[0052] like Figure 8J As depicted in , some examples may include RDL 842, RDL 844, RDL 846, RDL 848, and RDL 850. RDL 842, RDL 844, RDL 845, RDL 846, RDL 848, and RDL 850 may include a conductive material such as copper and may utilize a process such as, but not limited to, a Cu-ECP patterning process. Figure 8K As depicted in , protective layer 841 may be applied to protective layer 840 and one or more portions of RDL 842, RDL 844, RDL 846, RDL 848, and RDL 850. According to some examples, the conductive material forming RDL 852, RDL 854, and RDL 856 may be patterned onto protective layer 841. Figure 8L , another protective layer 858 may be disposed on protective layer 840 and RDL 852, RDL 854, and RDL 856. Protective layer 858 may be a PBO layer. RDL 852, RDL 854, and RDL 856 may be applied using a photomask and patterning process followed by an etching process such as a wet acid etch. In some examples, protective layer 858 may be applied via spin coating. Figure 8MUnderbump mounts (UBM) 860, UBM 862, and UBM 864 are depicted. UBM 860, UBM 862, and UBM 864 may be applied using a photomask patterning process followed by an etching process such as, but not limited to, a wet acid etch. UBM 860, UBM 862, and UBM 864 may then be deposited; in some examples, UBM 860, UBM 862, and UBM 864 may be copper and may be deposited using a Cu-ECP process. Figure 8N As depicted in , bumps 866 , 868 , and 870 may be formed on top of corresponding UBMs 860 , 862 , and 864 .

[0053] like Fig.8O As depicted in FIG. 8 , the glass carrier 804 can be removed after UV exposure to the LTHC, with the protective layer 802 serving as the final protective layer for the assembled package. Figure 8P As depicted in , a portion 872 of the backside region may be removed to accommodate an optical fiber array 874. Although the manufacturing process has been depicted using a number of steps, these steps and / or the order of these steps should not be considered limiting.

[0054] In one embodiment, an integrated fan-out (InFO) package is provided as an integrated circuit package, which may include: a photonic die (oDie) including at least one optical component; an electronic die (eDie); and a molded portion, wherein the molded portion includes a plurality of redistribution layers communicatively coupled to at least one of the oDie and / or the eDie, and wherein the molded portion at least partially surrounds at least one of the oDie and / or the eDie.

[0055] In one embodiment, an integrated circuit package includes: a photonic die (oDie) comprising at least one optical component; an electronic die (eDie); a substrate comprising a plurality of redistribution layers, the plurality of redistribution layers being communicatively coupled to at least one of the photonic die and / or the electronic die, wherein the substrate includes a molding portion, the molding portion at least partially surrounding the at least one of the photonic die and / or the electronic die; and a connection portion, electrically coupling the at least one of the photonic die and / or the electronic die to at least one redistribution layer, the at least one redistribution layer being positioned adjacent to the topmost layer of the integrated circuit package.

[0056] In one embodiment, the photonic die is optically coupled to at least one optical fiber. In one embodiment, the photonic die is disposed between the electronic die and the connection portion. In one embodiment, the electronic die is disposed between the photonic die and the connection portion. In one embodiment, a first side of the integrated circuit package includes one or more under bump metallization layers, and a second side of the integrated circuit package opposite to the first side of the integrated circuit package includes an exposed surface of at least one of the photonic die and / or the electronic die. In one embodiment, further includes at least one redistribution layer between the first side and at least one through package via (TIV), the package through via coupling the redistribution layer to the connection portion. In one embodiment, the connection portion includes one or more redistribution layers and one or more through vias, the one or more redistribution layers and the one or more through vias coupling solder bumps positioned at the first side of the integrated circuit package to the one or more of the photonic die and / or the electronic die. In one embodiment, the at least one of the photonic die and / or the electronic die is directly coupled to the connection portion. In one embodiment, an insert is further included between the at least one of the photonic die and / or the electronic die and the connection portion. In one embodiment, the photonic die is coupled to the electronic die via one or more solder bumps.

[0057] In an embodiment, a device includes at least one of a logic and / or a memory component electrically coupled to the integrated circuit package.

[0058] In another embodiment, a package including a photonic die (oDie) and an electronic die (eDie) is provided, the oDie including at least one optical component. The package may include a molded portion having a first side and a second side, wherein the molded portion includes one or more redistribution layers, the one or more redistribution layers coupling at least one of the oDie and / or the eDie positioned at the first side of the package together with the molded portion to a conductive portion positioned at the second side of the package.

[0059] In another embodiment, a package includes: a photonic die (oDie) comprising at least one optical component; an electronic die (eDie); and a molded portion having a first side and a second side, the molded portion including one or more redistribution layers, the one or more redistribution layers coupling at least one of the photonic die and / or the electronic die in the molded portion positioned at the first side of the package to a conductive portion positioned at the second side of the package.

[0060] In another embodiment, the molded portion at least partially surrounds the at least one of the photonic die and / or the electronic die. In another embodiment, further comprising electrically coupling the at least one of the photonic die and / or the electronic die to a connection portion of at least one redistribution layer, the at least one redistribution layer being positioned adjacent to the second side of the package. In another embodiment, the photonic die is disposed between the electronic die and the connection portion. In another embodiment, the electronic die is disposed between the photonic die and the connection portion. In another embodiment, further comprising an insert disposed between the at least one of the photonic die and / or the electronic die and the connection portion.

[0061] In another embodiment, a device includes at least one of a logic and / or memory component electrically coupled to an integrated circuit package as described above.

[0062] In some embodiments, a method of making an integrated circuit package, such as an integrated circuit (InFO) package, is provided. The method may include: electrically coupling at least one photonic die (oDie) to an electronic die (eDie); forming an intermediate package including a molding portion around a portion of the oDie and a portion of the eDie; and removing at least a portion of the molding portion. Subsequently, at least one redistribution layer may be formed at a position of the molding portion corresponding to the removed portion, and at least one protective layer may be formed on the at least one redistribution layer, wherein the at least one redistribution layer positioned between the molding portion and a first side of the integrated circuit package couples at least one of the oDie and / or the eDie to a conductive portion positioned at the first side of the integrated circuit package.

[0063] In some embodiments, it further includes: forming a plurality of packaging through holes, wherein the packaging through holes are positioned in a portion of the molded portion so that the at least one of the photonic die and / or the electronic die is positioned between two of the plurality of packaging through holes in the cross-sectional view.

[0064] The foregoing summarizes the features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art will appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit package, comprising: a photonic die comprising at least one optical component; Electronic tube die; a substrate including a plurality of redistribution layers electrically coupled to the photonic die and the electronic die, wherein the substrate includes a molding portion at least partially surrounding the photonic die and the electronic die, the molding portion including an opening at a back side of the integrated circuit package, the opening exposing the back side of the photonic die; as well as Following on from this, the photonic die and the electronic die are electrically coupled to at least one of the plurality of redistribution layers.

2. The integrated circuit package of claim 1, wherein the photonic die is optically coupled to at least one optical fiber.

3. The integrated circuit package of claim 1, wherein a front side of the integrated circuit package includes one or more under bump metallization layers, and a back side of the integrated circuit package opposite the front side of the integrated circuit package includes an exposed surface of the photonic die.

4. The integrated circuit package according to claim 1, further comprising: a backside redistribution layer at the backside of the molded portion; as well as At least one insulator through-via is located within the molded portion and couples the plurality of redistribution layers to the backside redistribution layer. 5 . The integrated circuit package of claim 4 , wherein the at least one through-insulator via is comprised of copper. 6 . The integrated circuit package of claim 1 , wherein the continuation portion comprises one or more redistribution layers and one or more pads. 7 . The integrated circuit package of claim 1 , wherein the connecting portion further comprises one or more conductive portions and one or more insulating portions. 8 . The integrated circuit package of claim 1 , further comprising a protection layer at the back side of the integrated circuit package. 9 . The integrated circuit package of claim 8 , wherein the protection layer exposes the opening.

10. The integrated circuit package of claim 1, wherein the molding portion comprises a molding compound.

11. A package comprising: a photonic die comprising at least one optical component; Electronic tube die; as well as a molded portion having a front side and a back side, the photonic die and the electronic die being located within the molded portion, the molded portion comprising an opening at the back side of the molded portion, the opening exposing the back side of the photonic die; a connecting portion located within the molded portion and at a front side of the molded portion, the photonic die and the electronic die being electrically coupled to the connecting portion; as well as One or more redistribution layers are located at the front side of the molded portion and are electrically coupled to the connection portion. 12 . The package of claim 11 , wherein the molding portion at least partially surrounds the photonic die and the electronic die.

13. The package of claim 12, wherein the continuation portion comprises one or more redistribution layers and one or more pads.

14. The package of claim 11, wherein the photonic die is optically coupled to at least one optical fiber. The package of claim 11 , wherein the molding portion comprises a molding compound.

16. An integrated circuit package, comprising: a molded portion having a front side and a back side; a photonic die configured to be optically coupled to an optical fiber, the photonic die being located within the molded portion; an electronic die located in the molded portion; a connecting portion located within the molded portion and at the front side of the molded portion, wherein the photonic die and the electronic die are electrically coupled to the connecting portion; as well as one or more redistribution layers located at the front side of the molded portion and electrically coupled to the connection portion, Wherein the molding portion includes an opening at the back side of the molding portion, the opening exposing a back side of the photonic die. The integrated circuit package of claim 16 , wherein the molding portion comprises a molding compound.

18. The integrated circuit package of claim 16, further comprising: a backside redistribution layer at the backside of the molded portion; as well as At least one insulator through-via is located within the molded portion and couples the plurality of redistribution layers to the backside redistribution layer.

19. A method for manufacturing an integrated circuit package, the method comprising: electrically coupling at least one photonic die to the electronic die; forming a molding portion around a portion of the photonic die and a portion of the electronic die; removing at least a portion of the molded portion; forming at least one redistribution layer at a position of the molded portion corresponding to the removed portion; as well as At least one protective layer is formed on the at least one redistribution layer, wherein the at least one redistribution layer positioned between the molded portion and the first side of the integrated circuit package couples at least one of the photonic die and / or the electronic die to a conductive portion positioned at the first side of the integrated circuit package.

20. The method for manufacturing an integrated circuit package according to claim 19, further comprising: A plurality of packaging through vias are formed, wherein the packaging through vias are positioned in a portion of the molding portion such that the at least one of the photonic die and / or the electronic die is positioned between two of the plurality of packaging through vias in a cross-sectional view.

Images