Display device

Abstract

A display device is disclosed. The display device includes a substrate, a first pixel on the substrate, a first data line to apply a first data signal to the first pixel, a second pixel on the substrate and adjacent to the first pixel, a second data line to apply a second data signal to the second pixel, and a shield layer between the first data line and the second data line. The first data line and the second data line are parallel to each other and disposed at different heights, and the shield layer includes a metal layer.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2018-0132556 filed on October 31, 2018, and all the benefits accruing therefrom, the contents of which are incorporated herein in their entirety. TECHNICAL FIELD

[0002] One or more exemplary embodiments relate to a display apparatus. BACKGROUND

[0003] As the field of display representing various electrical signal information visually has been rapidly developed, various flat panel display apparatuses having excellent characteristics such as slimness, light weight, and low power consumption have been introduced, and the resolution thereof is also increasing.

[0004] The increase in resolution of a display apparatus means an increase in the number of pixels per unit area in the display apparatus. Accordingly, as the resolution of the display apparatus is increasing, the number of wirings for applying electrical signals to the pixels in the display apparatus is also increasing. As a result, the distance between the wirings is reduced, signal interference between the wirings occurs, and the quality of an image of the display apparatus can be degraded. SUMMARY

[0005] One or more exemplary embodiments include a display apparatus that can prevent signal interference between wirings from occurring.

[0006] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the description or can be learned by practice of the presented exemplary embodiments.

[0007] According to one or more exemplary embodiments, a display apparatus includes a substrate, a first pixel on the substrate, a first data line applying a first data signal to the first pixel, a second pixel on the substrate and adjacent to the first pixel, a second data line applying a second data signal to the second pixel, and a shield layer between the first data line and the second data line. The first data line and the second data line are parallel to each other and are located at different heights, and the shield layer includes a metal layer.

[0008] The shield layer can further include a metal oxide layer on the metal layer.

[0009] The metal oxide in the metal oxide layer can be an oxide of the metal in the metal layer.

[0010] The concentration of oxygen included in the metal oxide layer can gradually increase from a lower portion to an upper portion of the metal oxide layer.

[0011] The display apparatus can further include first and second insulating layers between the first and second data lines and disposed at lower and upper portions of the shield layer, respectively.

[0012] Each of the first and second pixels can include an organic light emitting diode ("OLED") including a pixel electrode and a circuit unit for driving the OLED, and the circuit unit can include a thin film transistor ("TFT") having a drain electrode electrically connected to the pixel electrode, the first data line can be on the same layer as the drain electrode, and an organic insulating layer can be between the second data line and the pixel electrode.

[0013] The pixel electrode can be electrically connected to the drain electrode via a contact hole in the organic insulating layer, the second insulating layer, the shield layer, and the first insulating layer, and the second insulating layer can cover side surfaces of the shield layer and the first insulating layer at an inner side surface of the contact hole.

[0014] The shield layer can be commonly formed in one body to correspond to the first and second pixels.

[0015] The shield layer can be in a floating state.

[0016] A width of the second data line located on the shield layer can be greater than a width of the first data line located under the shield layer.

[0017] According to one or more example embodiments, a display apparatus includes: a pixel unit including a plurality of pixels and a plurality of data lines applying data signals to the plurality of pixels and arranged in parallel to each other; a data driving unit generating the data signals and connected to the plurality of data lines; and a shield layer blocking signal interference between two adjacent data lines among the plurality of data lines, located between the two adjacent data lines, and commonly disposed in one body to correspond to the plurality of pixels. The two adjacent data lines are at different heights.

[0018] The shield layer can include a metal layer and a metal oxide layer on the metal layer.

[0019] The metal oxide in the metal oxide layer can be an oxide of the metal in the metal layer

[0020] A concentration of oxygen in the metal oxide layer can gradually increase from a lower portion to an upper portion of the metal oxide layer.

[0021] The shield layer can be in a floating state.

[0022] A first data line among the plurality of data lines located at a lower portion of the shield layer and a second data line among the plurality of data lines located at an upper portion of the shield layer can be alternately arranged in a first direction.

[0023] The display device may further include a first insulating layer and a second insulating layer located between the first data line and the second data line, respectively, at the lower and upper parts of the shielding layer.

[0024] Each of the plurality of pixels may include an organic light-emitting diode (OLED) (including a pixel electrode) and a circuit unit for driving the OLED, and the circuit unit may include a thin-film transistor (TFT) having a drain electrode electrically connected to the pixel electrode, and a first data line may be located on the same layer as the drain electrode, and an organic insulating layer may be located on the second data line, and the pixel electrode may be located on the organic insulating layer.

[0025] The pixel electrode can be electrically connected to the drain electrode via a contact hole located in the organic insulating layer, the second insulating layer, the shielding layer, and the first insulating layer, and the second insulating layer can cover the side surface of the shielding layer and the side surface of the first insulating layer at the inner surface of the contact hole.

[0026] The width of the second data cable can be larger than the width of the first data cable. Attached Figure Description

[0027] These and / or other aspects will become apparent and more readily understood from the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0028] Figure 1 This is a schematic plan view of a display device according to an exemplary embodiment;

[0029] Figure 2 yes Figure 1 An exemplary equivalent circuit diagram of the pixels of a display device;

[0030] Figure 3 It is shown schematically in Figure 1 An exemplary arrangement diagram of the positions of thin-film transistors (“TFTs”) and capacitors arranged in the pixels of a display device;

[0031] Figures 4 to 8 It is shown schematically according to layers. Figure 3 A layout diagram of components such as multiple TFTs and capacitors;

[0032] Figure 9 It is shown schematically. Figure 1 A cross-sectional view of a portion of a display device;

[0033] Figure 10 It is shown schematically. Figure 9 A cross-sectional view of an example of a shielding layer;

[0034] Figure 11 It is shown schematically. Figure 9 A cross-sectional view of another example of a shielding layer; and

[0035] Figure 12 is a cross-sectional view schematically illustrating a method of manufacturing a display apparatus. Figure 1 DETAILED DESCRIPTION

[0036] Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the present exemplary embodiments can have different forms and should not be construed as being limited to the descriptions set forth herein. Accordingly, the exemplary embodiments are merely described below, by referring to the drawings, to explain aspects of the present description. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] Since the present disclosure allows various changes and numerous exemplary embodiments, specific exemplary embodiments will be illustrated in the drawings and described in detail in the written description. By referring to the exemplary embodiments that will be described in detail later with reference to the accompanying drawings, the effects and features of the present disclosure and the means for achieving them will become apparent. However, the invention is not limited to the following exemplary embodiments, but can be implemented in various forms.

[0038] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another.

[0039] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0040] It will be further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used herein, specify the presence of stated features, integers, components or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, components or combinations thereof.

[0041] It will be understood that when a layer, region or component is referred to as being "on" or "under" another layer, region or component, it can be directly on or under the other layer, region or component, or intervening layers, regions or components can also be present. That is, for example, one layer, region or component can intervene between one layer, region or component that is "on" or "under" another layer, region or component.

[0042] For ease of explanation, the sizes of the elements in the drawings can be exaggerated. In other words, the size and thickness of the components in the drawings are arbitrarily shown for ease of explanation, and the invention is not limited thereto.

[0043] ​When some of the example embodiments can be implemented differently, a specific process sequence can be performed differently from the described sequence. For example, two consecutively described processes can be performed substantially simultaneously, or can be performed in an order opposite to the described sequence.

[0044] Hereinafter, example embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. The same reference numerals are used for the same or corresponding components, and detailed descriptions thereof will be omitted.

[0045] Figure 1 is a plan view schematically showing a display apparatus according to an example embodiment.

[0046] Referring to Figure 1 The display apparatus 10 according to an example embodiment can include a pixel unit 11, a data driving unit 13, a scan driving unit 15, and a controller 17.

[0047] The pixel unit 11 can include a plurality of scan lines SL1 to SLn, a plurality of data lines DL11 to DL2m, a plurality of emission control lines EL1 to ELn, and a plurality of pixels PX. Each of the plurality of pixels PX can include a light emitting device and a circuit unit for driving the light emitting device. In an example embodiment, the light emitting device can be an organic light emitting device, and the circuit unit can include a plurality of transistors and one capacitor.

[0048] The plurality of scan lines SL1 to SLn can be arranged in rows. For example, the scan lines SL1 to SLn can be connected to the scan driving unit 15, and can transmit a scan signal generated by the scan driving unit 15 to the pixels PX.

[0049] The scan driving unit 15 generates a scan signal in response to a control signal of the controller 17, and supplies the scan signal to the scan lines SL1 to SLn. Also, the scan driving unit 15 can be connected to the plurality of emission control lines EL1 to ELn, can generate an emission control signal in response to a control signal of the controller 17, and can supply the emission control signal to the emission control lines EL1 to ELn. Each of the plurality of emission control lines EL1 to ELn transmits the emission control signal to the pixel unit 11. In another example embodiment, the emission control signal can be generated through a separate emission control driving unit, and can also be applied to the pixel unit 11. A driving voltage ELVDD and a common voltage ELVSS are applied to each of the pixels PX of the pixel unit 11. The common voltage ELVSS can be a voltage lower than the driving voltage ELVDD.

[0050] A plurality of data lines DL11 to DL2m are arranged, for example, in columns, and transmit data signals to the pixels PX. Each pixel PX can be located in a portion in which the plurality of scan lines SL1 to SLn and the plurality of data lines DL11 to DL2m intersect each other.

[0051] The data driving unit 13 is connected to the plurality of data lines DL11 to DL2m. The data driving unit 13 converts a video signal into a data signal in the form of a voltage or a current in response to a control signal of the controller 17. The data driving unit 13 applies the data signal to the plurality of data lines DL11 to DL2m.

[0052] The controller 17 generates a plurality of control signals in response to a synchronization signal supplied from the outside. The controller 17 outputs a control signal for controlling the data driving unit 13 to the data driving unit 13, and outputs a control signal for controlling the scan driving unit 15 to the scan driving unit 15.

[0053] As the resolution of the display device 10 increases, the number of pixels PX increases, and thus the size of each pixel PX in the pixel unit 11 decreases. Therefore, the number of the scan lines SL1 to SLn, the data lines DL11 to DL2m, and the emission control lines EL1 to ELn for applying an electric signal to the pixels increases. As a result, the distance therebetween decreases. In particular, since the distance between the plurality of data lines DL11 to DL2m (for example, the distance between two adjacent data lines) decreases, electrical interference occurs between the plurality of data lines DL11 to DL2m (for example, electrical interference occurs between two adjacent data lines), and due to crosstalk, an unintended data signal can be applied to the pixels PX (for example, a pixel PX that receives a distorted data signal). However, as will be described later, according to an exemplary embodiment, two adjacent data lines among the data lines DL11 to DL2m can be at different heights, and a shield layer for cutting off the transmission of an electric signal is located between the two adjacent data lines, so that interference between the two adjacent data lines can be effectively prevented. This will be described later with reference to FIGS. 6A and 6B. Figures 3 to 11 This is described.

[0054] Figure 2 is Figure 1 an exemplary equivalent circuit diagram of a pixel of the display device 10.

[0055] As Figure 2As shown in the middle, one pixel PX can include a plurality of TFTs (e.g., a driving TFT T1, a switching TFT T2, a compensation TFT T3, an initialization TFT T4, an operation control TFT T5, an emission control TFT T6, and a bypass TFT T7), a capacitor Cst, and an organic light emitting diode ("OLED"). It will be understood that the driving TFT T1, the switching TFT T2, the compensation TFT T3, the initialization TFT T4, the operation control TFT T5, the emission control TFT T6, and the bypass TFT T7, or the capacitor Cst can be components in a pixel circuit of the pixel PX. The circuit units are electrically connected to a plurality of signal lines, e.g., a scan line 121, a previous scan line 122, an emission control line 123, an initialization voltage line 124, a data line 171, and power lines 172 and 178.

[0056] The scan line 121 can transmit a scan signal Sn, and the previous scan line 122 can transmit a previous scan signal Sn-1 to the initialization TFT T4 and the bypass TFT T7. The emission control line 123 can transmit an emission control signal En to the operation control TFT T5 and the emission control TFT T6. The data line 171 intersecting the scan line 121 can transmit a data signal Dm. The initialization voltage line 124 can transmit an initialization voltage Vint to the driving TFT T1 to initialize the driving TFT T1.

[0057] The driving TFT T1 receives the data signal Dm according to the switching operation of the switching TFT T2, and supplies a driving current I OLED to the OLED. The gate electrode G1 of the driving TFT T1 is connected to the lower electrode Cst1 of the capacitor Cst, the source electrode S1 of the driving TFT T1 is connected to the power line 172 via the operation control TFT T5, and the drain electrode D1 of the driving TFT T1 is electrically connected to the pixel electrode of the OLED via the emission control TFT T6.

[0058] The gate electrode G2 of the switching TFT T2 is connected to the scan line 121, and the source electrode S2 of the switching TFT T2 is connected to the data line 171. The drain electrode D2 of the switching TFT T2 is connected to the source electrode S1 of the driving TFT T1, and is connected to the power line 172 via the operation control TFT T5. The switching TFT T2 is turned on according to the scan signal Sn transmitted through the scan line 121, and performs a switching operation of transmitting the data signal Dm transmitted via the data line 171 to the source electrode S1 of the driving TFT T1.

[0059] The gate electrode G3 of the compensation TFT T3 is connected to the scan line 121, the source electrode S3 of the compensation TFT T3 is connected to the drain electrode D1 of the driving TFT T1, and is connected to the pixel electrode of the OLED via the emission control TFT T6. The drain electrode D3 of the compensation TFT T3 is connected to the lower electrode Cst1 of the capacitor Cst, the drain electrode D4 of the initialization TFT T4, and the gate electrode G1 of the driving TFT T1. The compensation TFT T3 is turned on according to the scan signal Sn transmitted through the scan line 121, and electrically connects the gate electrode G1 and the drain electrode D1 of the driving TFT T1 to each other to diode-connect the driving TFT T1.

[0060] The gate electrode G4 of the initialization TFT T4 is connected to the previous scan line 122, the source electrode S4 of the initialization TFT T4 is connected to the drain electrode D7 of the bypass TFT T7 and the initialization voltage line 124. The drain electrode D4 of the initialization TFT T4 is connected to the lower electrode Cst1 of the capacitor Cst, the drain electrode D3 of the compensation TFT T3, and the gate electrode G1 of the driving TFT T1. The initialization TFT T4 is turned on according to the previous scan signal Sn-1 transmitted through the previous scan line 122, transmits the initialization voltage Vint to the gate electrode G1 of the driving TFT T1 to perform the initialization operation for initializing the voltage of the gate electrode G1 of the driving TFT T1.

[0061] The gate electrode G5 of the operation control TFT T5 is connected to the emission control line 123, the source electrode S5 of the operation control TFT T5 is connected to the power supply line 172, and the drain electrode D5 of the operation control TFT T5 is connected to the source electrode S1 of the driving TFT T1 and the drain electrode D2 of the switching TFT T2.

[0062] The gate electrode G6 of the emission control TFT T6 is connected to the emission control line 123, the source electrode S6 of the emission control TFT T6 is connected to the drain electrode D1 of the driving TFT T1 and the source electrode S3 of the compensation TFT T3. The drain electrode D6 of the emission control TFT T6 is electrically connected to the source electrode S7 of the bypass TFT T7 and the pixel electrode of the OLED. The operation control TFT T5 and the emission control TFT T6 are simultaneously turned on according to the emission control signal En transmitted through the emission control line 123. The driving voltage ELVDD is transmitted to the OLED, so that the driving current I OLED may flow through the OLED.

[0063] The gate electrode G7 of the bypass TFT T7 is connected to the previous scan line 122. The source electrode S7 of the bypass TFT T7 is connected to the drain electrode D6 of the emission control TFT T6 and the pixel electrode of the OLED. The drain electrode D7 of the bypass TFT T7 is connected to the source electrode S4 of the initialization TFT T4 and the initialization voltage line 124. The gate electrode G7 of the bypass TFT T7 receives the previous scan signal Sn-1 transmitted via the previous scan line 122. When an electrical signal of a voltage at a predetermined level that allows the bypass TFT T7 to be turned off is applied from the previous scan line 122, the bypass TFT T7 is turned off, causing the drive current I... d Part of it (i.e., bypass current I) bp It can escape through the bypass TFT T7.

[0064] If the OLED emits light even when the minimum current flowing through the driving TFT T1 for displaying a black image is used as the driving current, then the black image is not displayed correctly. Here, the minimum current flowing through the driving TFT T1 refers to the gate-source voltage V of the driving TFT T1. GS The current is less than the threshold voltage Vth and the driving TFT T1 is turned off. Therefore, to prevent the OLED from emitting light when the minimum current flows as the driving current, the bypass TFT T7 can control the current I flowing from the driving TFT T1. d Part of it (i.e., bypass current I) bp The current is dispersed into different current paths besides the current path toward the OLED. Because of this feature, when the driving TFT T1 is off, a current smaller than the minimum driving current (e.g., a current equal to or less than 10 picoamps (pA)) is transmitted to the OLED, so the OLED does not emit light, or the emission level is minimized, thus enabling a black image.

[0065] exist Figure 2 In this embodiment, the initialization TFT T4 and the bypass TFT T7 are connected to the previous scan line 122. However, the invention is not limited thereto. In another exemplary embodiment, the initialization TFT T4 is connected to the previous scan line 122 and is driven according to the previous scan signal Sn-1, and the bypass TFT T7 can be connected to a separate wiring and can be driven according to the signal transmitted to that wiring.

[0066] The upper electrode Cst2 of capacitor Cst is connected to power line 172, and the counter electrode of the OLED is connected to the common voltage ELVSS. Therefore, the OLED can receive a driving current I from the driving TFT T1. OLED It shines.

[0067] exist Figure 2In this embodiment, the compensation TFT T3 and the initialization TFT T4 have a dual-gate electrode. However, the invention is not limited thereto. In another exemplary embodiment, for example, the compensation TFT T3 and the initialization TFT T4 may have a single gate electrode. Furthermore, various modifications are possible. In another exemplary embodiment, in addition to the compensation TFT T3 and the initialization TFT T4, at least one of TFTs T1, T2, T5, T6, and T7 may have a dual-gate electrode.

[0068] In the following text, reference will be made to Figures 3 to 9 describe Figure 1 The detailed structure of the display device 10.

[0069] Figure 3 The exemplary locations of the TFTs and capacitors of two adjacent pixels PX1 and PX2 are shown. Figures 4 to 8 The following diagram illustrates components such as TFTs and capacitors in the two pixels PX1 and PX2. In the following text, if portions of the first pixel PX1 and the second pixel PX2 have the same shape, those portions will not be described separately.

[0070] also, Figure 9 It is shown schematically. Figure 1 A cross-sectional view of a portion of the display device 10, wherein, for convenience, the cross-sections of several portions of two pixels PX1 and PX2 are shown as connected to each other. That is, Figure 9 The parts shown do not necessarily have to be adjacent to each other. For example, unlike Figure 9 The portions showing the emission control TFT T6 and OLED 190a of the first pixel PX1, the portion showing the capacitor Cst, and the portion showing the first data line 171n may not be adjacent to each other. Of course, their relative positions do not have to be... Figure 9 The order shown in the figure. That is, in another exemplary embodiment, the first data line 171n may be disposed in the portion other than the portion in which the emission control TFT T6 and OLED 190a in the first pixel PX1 are shown and the portion in which the capacitor Cst is shown.

[0071] like Figure 9As illustrated in FIG. 1, the display device 10 includes a substrate 110. The substrate 110 can include various materials such as a glass material, a metal material, or a plastic material. A plurality of pixels PX including a first pixel PX1 and a second pixel PX2 can be disposed on the substrate 110. A buffer layer 111 can be located on the substrate 110. The buffer layer 111 can planarize a surface of the substrate 110, or can prevent impurities from penetrating into a semiconductor layer on the buffer layer 111. In an exemplary embodiment, the buffer layer 111 can have a single / multi-layer structure including an inorganic insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0072] A semiconductor layer can be located on the buffer layer 111. As illustrated in FIG. 1, the semiconductor layer can have various non-uniform shapes, and the first pixel PX1 and the second pixel PX2 can include semiconductor layers having the same shape. Hereinafter, in the case where layers of the first pixel PX1 and the second pixel PX2 have the same shape, these layers will not be described separately. Figure 4

[0073] The semiconductor layer can include a driving channel region 131a corresponding to the driving TFT T1, a switching channel region 131b corresponding to the switching TFT T2, compensation channel regions 131c1, 131c2, and 131c3 corresponding to the compensation TFT T3, initialization channel regions 131d1, 131d2, and 131d3 corresponding to the initialization TFT T4, an operation control channel region 131e corresponding to the operation control TFT T5, an emission control channel region 131f corresponding to the emission control TFT T6, and a bypass channel region 131g corresponding to the bypass TFT T7 (see FIG. 1). Figure 4 That is, it will be understood that the driving channel region 131a, the switching channel region 131b, the compensation channel regions 131c1, 131c2, and 131c3, the initialization channel regions 131d1, 131d2, and 131d3, the operation control channel region 131e, the emission control channel region 131f, and the bypass channel region 131g can be partial regions of the semiconductor layer illustrated in FIG. 1. Figure 4

[0074] The semiconductor layer can include polysilicon. The semiconductor layer can include, for example, the above-described channel region in which no impurity is doped, and source and drain regions in which impurities are doped at both sides of the channel region. Here, the impurity can vary depending on the type of the TFT, and can include an N-type impurity or a P-type impurity. The channel region, the source region at one side of the channel region, and the drain region at the other side of the channel region can be referred to as an active layer. That is, it will be understood that the TFT has the active layer, and the active layer includes the channel region, the source region, and the drain region.

[0075] ​​Depending on the context, the doped source and drain regions can be interpreted as the source and drain electrodes of the TFT, respectively. That is, for example, the driving source electrode can be... Figure 4 The driving source region 176a, which is doped with impurities, is located near the driving channel region 131a in the semiconductor layer shown in the figure. The driving drain electrode can be associated with... Figure 4 The impurity-doped drive drain region 177a is located near the drive channel region 131a in the semiconductor layer shown in the figure.

[0076] In an exemplary embodiment, a first gate insulating layer 141 comprising an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride may be located on top of the semiconductor layer (see [example description]). Figure 9 ).

[0077] Conductive layers, such as gate electrode 125f and lower electrode 125a, are located on the first gate insulating layer 141. Of course, various conductive layers can be located on the first gate insulating layer 141. These various conductive layers, including gate electrode 125f and lower electrode 125a, located on the first gate insulating layer 141 can be referred to as the first gate wiring. Figure 5 As shown, the first gate wiring may include a scan line 121, a previous scan line 122, an emission control line 123, and a lower electrode 125a.

[0078] like Figure 5 As shown, it will be understood that the switching gate electrode 125b and the compensation gate electrodes 125c1 and 125c2 may be portions of the scan line 121 or portions protruding from the scan line 121; the initialization gate electrodes 125d1 and 125d2 and the bypass gate electrode 125g may be portions of the previous scan line 122 or portions protruding from the previous scan line 122; and the operation control gate electrode 125e and gate electrode 125f may be portions of the emission control line 123 or portions protruding from the emission control line 123. The scan line 121, the previous scan line 122, and the emission control line 123 intersect with the semiconductor layer.

[0079] The second gate insulating layer 142 may cover the first gate wiring. In an exemplary embodiment, the second gate insulating layer 142 may include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0080] The upper electrode 127 of capacitor Cst can be located on the second gate insulating layer 142. Of course, as... Figure 6 As shown, the initialization voltage line 124 can be located on the second gate insulating layer 142, that is, on the same layer as the upper electrode 127. The various conductive layers located on the second gate insulating layer 142 can be referred to as the second gate wiring.

[0081] like Figure 6As shown in FIG. 12, the opening 27 can be defined in the upper electrode 127. The lower electrode 125a and the compensation drain region 177c of the compensation TFT T3 can be electrically connected to each other by the connection member 174. The connection member 174 can pass through the opening 27, which will be described later.

[0082] The interlayer insulating layer 143 is located on the second gate wire (see Figure 9 ). In an exemplary embodiment, the interlayer insulating layer 143 can include an inorganic insulating material such as silicon nitride, silicon oxide, or silicon oxynitride.

[0083] The drain electrode 175 connected to the semiconductor layer via the contact hole defined in the first gate insulating layer 141 and the second gate insulating layer 142 can be located on the interlayer insulating layer 143. Here, the drain electrode 175 can be referred to as an intermediate connection layer. The drain electrode 175 as the intermediate connection layer can be connected to the drain region 177f via the contact hole 163. Of course, in addition to including the drain electrode 175, various conductive layers including a source electrode can be located on the interlayer insulating layer 143. In an exemplary embodiment, for example, as shown in FIG. 13, the source electrode 175a can be located on the interlayer insulating layer 143. Figure 7 As shown in FIG. 12, the power supply line 172, the initialization connection line 173, and the connection member 174 can be disposed on the interlayer insulating layer 143.

[0084] The power supply line 172 can be connected to the upper electrode 127 via the contact hole 168 defined in the interlayer insulating layer 143, and can be connected to the lower semiconductor layer via the contact holes 165 and 169 defined in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143 (see Figure 3 ).

[0085] One end of the initialization connection line 173 can be connected to the initialization voltage line 124 via the contact hole 161 defined in the second gate insulating layer 142 and the interlayer insulating layer 143, and the other end of the initialization connection line 173 can be connected to the initialization source region 176d via the contact hole 162 defined in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143 (see Figure 3 ). The initialization drain region 177d is a portion of the semiconductor layer in which an impurity is doped, and is a side portion opposite to the initialization source region 176d with respect to the initialization channel region 131d (see Figure 4 ).

[0086] One end of the connection member 174 is connected to the compensation drain region 177c and the initialization drain region 177d via the contact hole 166 defined in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143, and the other end of the connection member 174 is connected to the lower electrode 125a via the contact hole 167 defined in the second gate insulating layer 142 and the interlayer insulating layer 143. In this case, the other end of the connection member 174 is connected to the lower electrode 125a via the opening 27 defined in the upper electrode 127 (see Figure 3 ).

[0087] The first pixel PX1 includes the first data line 171n directly on the interlayer insulating layer 143. The first data line 171n can be connected to the switch source region 176b via the contact hole 164 defined in the first gate insulating layer 141, the second gate insulating layer 142, and the interlayer insulating layer 143. On the other hand, the second data line 171n+1 of the second pixel PX2 is not directly disposed on the interlayer insulating layer 143 (see Figure 9 ).

[0088] As shown in Figure 9 , the first insulating layer 151, the shield layer 152, and the second insulating layer 153 are sequentially located on the drain electrode 175 and the first data line 171n, and the second data line 171n+1 of the second pixel PX2 is located on the second insulating layer 153. That is, the first data line 171n of the first pixel PX1 and the second data line 171n+1 of the second pixel PX2 are at different heights. The second data line 171n+1 can be connected to the switch source region 176b of the second pixel PX2 via the contact hole 164 defined in the first gate insulating layer 141, the second gate insulating layer 142, the interlayer insulating layer 143, the first insulating layer 151, the shield layer 152, and the second insulating layer 153. In this case, even though not shown in Figure 9 , the second insulating layer 153 is disposed to cover the inner side surface of the contact hole 164 and prevent the side surface of the metal layer included in the shield layer 152 from being exposed, so that the second data line 171n+1 can be prevented from being electrically connected to the metal layer included in the shield layer 152.

[0089] In an exemplary embodiment, the first insulating layer 151 and the second insulating layer 153 can include silicon nitride, silicon oxide, or silicon oxynitride. The shield layer 152 includes a metal layer, so that interference can be effectively prevented from occurring between the first data line 171n and the second data line 171n+1.

[0090] As described above, as the resolution of the display device 10 increases, the distance between the first data line 171n and the second data line 171n+1 for applying data signals to the first pixel PX1 and the second pixel PX2 decreases. Therefore, the possibility that electrical interference occurs between the first data line 171n and the second data line 171n+1 increases. In this case, if the first data line 171n and the second data line 171n+1 are located at opposite sides of the shield layer 152 (for example, one data line is on the shield layer 152 and the other data line is under the shield layer 152), one of the first data line 171n and the second data line 171n+1 can be prevented from being interfered with by a data signal applied to the other of the first data line 171n and the second data line 171n+1 due to the metal layer included in the shield layer 152. In addition, since the first data line 171n and the second data line 171n+1 are located on different layers, the width W1 of the first data line 171n and the width W2 of the second data line 171n+1 can increase. Therefore, the resistance of the first data line 171n and the second data line 171n+1 can decrease. Thus, the display device 10 can provide a high-quality image because the RC delay can be reduced while achieving high resolution. In an alternative exemplary embodiment, since the number of components located in the same layer as the second data line 171n+1 on the shield layer 152 is smaller than the number of components located in the same layer as the first data line 171n, the width W2 of the second data line 171n+1 can be greater than the width W1 of the first data line 171n.

[0091] Figure 9 Only two pixels PX1 and PX2 are shown, and a case in which the first data line 171n of the first pixel PX1 and the second data line 171n+1 of the second pixel PX2 are at different heights is shown. However, this should be interpreted as the data lines included in two adjacent pixels among a plurality of pixels being at different heights. That is, a third data line included in a third pixel adjacent to the second pixel PX2 can be located directly on the interlayer insulating layer 143 as with the first data line 171n, and thus can be located at a height different from that of the second data line 171n+1. That is, even if two adjacent data lines in the first direction (x direction) have different heights, the data lines located at the same height can be alternately arranged in the first direction (x direction).

[0092] Referring back to Figure 9The first organic insulating layer 154 is located at the upper portion of the emission control TFT T6. The first organic insulating layer 154 includes an organic material, and a top surface of the first organic insulating layer 154 can have an approximately flat shape regardless of the shape of the top surface of the structure located at the lower portion of the emission control TFT T6. Accordingly, the first organic insulating layer 154 can also be referred to as a planarization layer. In an exemplary embodiment, the first organic insulating layer 154 can include an organic material such as acryl, benzocyclobutene (“BCB”), polyimide, or hexamethyldisiloxane (“HMDSO”).

[0093] The pixel electrode 191 (e.g., the pixel electrode 191a of the first pixel PX1 and the pixel electrode 191b of the second pixel PX2) can be located on the first organic insulating layer 154 and can be connected to the drain electrode 175 below the first organic insulating layer 154. In detail, the pixel electrode 191 and the drain electrode 175 can be connected to each other via a contact hole defined in the first organic insulating layer 154, the first insulating layer 151, the shield layer 152, and the second insulating layer 153. In this case, because the shield layer 152 includes a metal layer, in order to prevent a short circuit between the metal layer exposed to the side surface of the contact hole and the pixel electrode 191, the second insulating layer 153 is provided to cover the side surface of the shield layer 152 and the side surface of the first insulating layer 151 at the inner side surface of the contact hole. Accordingly, it is possible to prevent the pixel electrode 191 from being electrically connected to another component such as the second data line 171n+1 via the metal layer.

[0094] The pixel electrode 191 can be a (semi-)transparent electrode or a reflective electrode. In the case where the pixel electrode 191 is a (semi-)transparent electrode, for example, the pixel electrode 191 can include ITO, IZO, ZnO, In2O3, IGO, or AZO. In the case where the pixel electrode 191 is a reflective electrode, for example, the pixel electrode 191 can have a reflective layer including Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and compounds thereof and a layer formed of ITO, IZO, ZnO, In2O3, IGO, or AZO. Of course, the present application is not limited thereto. Various modifications can be made, for example, the pixel electrode 191 can include various materials other than the above-described materials, and can have a single layer or a multi-layer structure.

[0095] A second organic insulating layer 192, which is a pixel-defining layer including an organic material, can be located at an upper portion of the first organic insulating layer 154. The second organic insulating layer 192 defines an opening corresponding to a sub-pixel, i.e., an opening through which at least a center of the pixel electrode 191 is exposed, thereby the second organic insulating layer 192 defines a pixel. Further, the second organic insulating layer 192 increases a vertical distance between an edge of the pixel electrode 191 and an edge of the counter electrode 195 at an upper portion of the pixel electrode 191, thereby an electric arc can be prevented from occurring in the edge of the pixel electrode 191. In an exemplary embodiment, the second organic insulating layer 192 can include an organic material such as polyimide.

[0096] The intermediate layer 193 of the OLED 190 (e.g., the intermediate layer 193a of the first pixel PX1 and the intermediate layer 193b of the second pixel PX2) can include a small molecular weight material or a polymer material. In the case where the intermediate layer 193 includes the small molecular weight material, the intermediate layer 193 can have a structure in which a hole injection layer ("HIL"), a hole transport layer ("HTL"), an emission layer ("EML"), an electron transport layer ("ETL"), and an electron injection layer ("EIL") are stacked in a single layer or a multi-layer structure. In the case where the intermediate layer 193 includes the polymer material, the intermediate layer 193 can include an HTL and an EML. Of course, the intermediate layer 193 according to the present application is not limited thereto. Of course, the intermediate layer 193 according to the present application is not limited thereto, but can have various structures.

[0097] The counter electrode 195 (e.g., the counter electrode 195a of the first pixel PX1 and the counter electrode 195b of the second pixel PX2) can be located at an upper portion of the display area to cover the display area. Here, the display area refers to an area in which an image is displayed in the display device. That is, the counter electrode 195 can be commonly provided as one body in a plurality of OLEDs 190 (e.g., the OLED 190a of the first pixel PX1 and the OLED 190b of the second pixel PX2), and can correspond to a plurality of pixel electrodes 191. The counter electrode 195 can be a (semi-)transparent electrode or a reflective electrode. In the case where the counter electrode 195 is a (semi-)transparent electrode, for example, the counter electrode 195 can have a layer including a metal having a small work function, i.e., Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and a compound thereof, and a (semi-)transparent conductive layer such as ITO, IZO, ZnO, or In2O3. In the case where the counter electrode 195 is a reflective electrode, for example, the counter electrode 195 can have a layer including Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and a compound thereof. Of course, the configuration and material of the counter electrode 195 according to the present application are not limited thereto, but can be variously modified.

[0098] Figure 10 andFigure 11 An example of a shield layer is shown, Figure 9 Figure 12 is a cross-sectional view schematically showing a method of manufacturing a display apparatus 10, which shows a method of schematically forming a shield layer. Figure 1

[0099] First, referring to Figure 10 The shield layer 152 can have a stacked structure of a metal layer 152a and a metal oxide layer 152b. In this case, the metal oxide layer 152b is located on the metal layer 152a. That is, according to an exemplary embodiment, a stacked order of the first insulating layer 151, the metal layer 152a, the metal oxide layer 152b, and the second insulating layer 153 is provided.

[0100] As described above, the metal layer 152a can prevent crosstalk between two data lines respectively arranged at the upper side and the lower side of the shield layer 152. The metal layer 152a can be in a floating state.

[0101] If the metal layer 152a blocks electromagnetic waves, the type of the metal layer 152a according to the invention is not limited. In an exemplary embodiment, the metal layer 152a can include Fe, Cu, Cr, Mn, Ni, Ti, Mo, Al, or W. However, in order to prevent crosstalk between data lines, the thickness T1 of the metal layer 152a can be or more.

[0102] The metal layer 152a can be provided as one body to correspond to a plurality of pixels PX. Therefore, in order to prevent components such as a pixel electrode arranged on the metal layer 152a from being short-circuited due to the metal layer 152a, the second insulating layer 153 is provided on the metal layer 152a. The second insulating layer 153 can be formed by chemical vapor deposition ("CVD"). When the second insulating layer 153 is formed by CVD, an arc can occur due to the metal layer 152a being exposed to a deposition process. Therefore, damage such as a crack can occur in the second insulating layer 153. In order to prevent this problem, the metal oxide layer 152b can be further provided on the metal layer 152a. The metal oxide layer 152b can prevent the metal layer 152a from being exposed after a process of forming the metal layer 152a, and thus can prevent the above-described arc problem.

[0103] The metal oxide layer 152b can include an oxide of a metal material included in the metal layer 152a. Further, the metal oxide layer 152b can be formed continuously with the metal layer 152a when the metal layer 152a is formed.

[0104] In another example, Figure 12 A method of schematically forming the metal layer 152a using sputtering is shown. First, Figure 12 ​​The sputtering apparatus 200 can include a chamber 201, a stage 203 located in the chamber 201 and on which a substrate S is placed, and a sputtering part 220 for forming a thin layer on the substrate S.

[0105] The inside of the chamber 201 can be maintained in a vacuum state, and a shielding layer 152 can be formed on the substrate S placed on the stage 203 by sputtering of the sputtering part 220.

[0106] In an example, the sputtering part 220 can include a first target part 221 and a second target part 222 facing each other. A pair of targets 232 and 234 are mounted on the first target part 221 and the second target part 222 to face each other, and the pair of targets 232 and 234, the first target part 221 and the second target part 222 are electrically connected to a power supply unit (not shown) such as a direct current ("DC") power supply via a power supply line. An inert gas such as argon (Ar) gas can be supplied between the first target part 221 and the second target part 222 via a pipe 240.

[0107] When power is supplied between the pair of targets 232 and 234 and between the first target part 221 and the second target part 222, discharge occurs in a space between the pair of targets 232 and 234, and electrons generated by the discharge collide with the Ar gas, so that the Ar gas is ionized, and thus plasma can be generated. Ar ions collide with the pair of targets 232 and 234 including a material for forming a metal layer 152a. Accordingly, atoms or molecules of the material for forming the metal layer 152a are ejected from the pair of targets 232 and 234, and are deposited on the substrate S, so that the metal layer 152a can be formed.

[0108] When the metal layer 152a is formed to a predetermined thickness or more, oxygen (O2) is injected into the chamber 201 via a pipe 250, so that a metal oxide layer 152b can be formed on the metal layer 152a, as shown in FIG. 2B. Figure 10

[0109] The metal oxide layer 152b can have a thickness T2 of or more. Accordingly, when a second insulating layer 153 is formed on the shielding layer 152, an arc can be effectively prevented from occurring due to the metal oxide layer 152b.

[0110] When the metal oxide layer 152b is formed by injecting oxygen (O2) into the chamber 201, as described above, the content of the injected oxygen (O2) gradually increases, so that the concentration of oxygen in the metal oxide layer 152b can gradually increase from a lower portion to an upper portion of the metal oxide layer 152b, as shown in FIG. 2B. Figure 11

[0111] ​​The metal oxide layer 152b is a layer formed by implanting oxygen (O2) at the same time as the metal layer 152a is formed, and unoxidized metal material can be included in the metal oxide layer 152b, and this can serve as a path over which current can flow. Thus, when the metal oxide layer 152b is formed, the concentration of the implanted oxygen (O2) gradually increases, so that unoxidized metal material can not be included in the upper portion of the metal oxide layer 152b. Thus, it is possible to more effectively prevent arcing due to the metal layer 152a in subsequent processes.

[0112] As described above, in the display apparatus according to one or more exemplary embodiments, since two adjacent wires among the wires for applying an electric signal to a pixel are at different heights, and a shield layer is located between the two adjacent wires, it is possible to prevent a crosstalk phenomenon from occurring between the wires. Further, since the width of the wires can be increased, the resistance of the wires is reduced, and thus high resolution can be achieved and a high quality image can be provided due to a reduction in RC delay. Of course, the invention is not limited by these effects.

[0113] It should be understood that the exemplary embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each exemplary embodiment should be considered as available for other similar features or aspects in other exemplary embodiments.

[0114] While one or more exemplary embodiments have been described with reference to the attached drawings, it will be understood by those of ordinary skill in the art that various changes in form and details can be made therein without departing from the spirit and scope of the claims.

Claims

1. A display device comprising: a substrate; a first pixel on the substrate; a first data line extending in a first direction and applying a first data signal to the first pixel; a second pixel on the substrate and adjacent to the first pixel in a second direction crossing the first direction; a second data line applying a second data signal to the second pixel and adjacent to the first data line in the second direction; and a shield layer between the first data line and the second data line, the shield layer including a metal layer, wherein one of the first data line and the second data line is disposed above the shield layer and the other of the first data line and the second data line is disposed below the shield layer. The shield layer further includes a metal oxide layer on the metal layer.

2. The display device of claim 1, wherein, The metal oxide in the metal oxide layer is an oxide of the metal in the metal layer.

3. The display device of claim 2, wherein, A concentration of oxygen in the metal oxide layer gradually increases from a lower portion to an upper portion of the metal oxide layer.

4. The display device of claim 2, wherein, 5.The display device of claim 1, further comprising first and second insulating layers between the first and second data lines and disposed at lower and upper portions of the shield layer, respectively. Each of the first and second pixels includes an organic light emitting diode including a pixel electrode and a circuit unit for driving the organic light emitting diode, 6. The display device of claim 5, wherein, The circuit unit includes a thin film transistor having a drain electrode electrically connected to the pixel electrode, The first data line is on the same layer as the drain electrode, and An organic insulating layer is between the second data line and the pixel electrode. The pixel electrode is electrically connected to the drain electrode via a contact hole in the organic insulating layer, the second insulating layer, the shield layer, and the first insulating layer, and the second insulating layer covers a side surface of the shield layer and a side surface of the first insulating layer at an inner side surface of the contact hole.

7. The display device of claim 6, wherein, The shield layer is commonly disposed in one piece to correspond to the first and second pixels.

8. The display device of claim 1, wherein, The shield layer is in a floating state.

9. The display device of claim 1, wherein, A width of the second data line on the shield layer is greater than a width of the first data line under the shield layer.

10. The display device of claim 1, wherein, 11.A display device comprising: a pixel unit including a plurality of pixels and a plurality of data lines extending in a first direction, each of the plurality of data lines applying a data signal to a pixel adjacent to the data line among the plurality of pixels in a second direction crossing the first direction; a data driving unit generating the data signal and connected to the plurality of data lines; and a shield layer blocking signal interference between two adjacent data lines among the plurality of data lines, between the two adjacent data lines, and commonly disposed in one piece to correspond to the plurality of pixels. ​ ​ The two adjacent data lines apply data signals to respective corresponding pixels, one of the two adjacent data lines is disposed above the shield layer, and the other of the two adjacent data lines is disposed below the shield layer.

12. The display device of claim 11, wherein, The shield layer includes a metal layer and a metal oxide layer disposed on the metal layer.

13. The display device of claim 12, wherein, The metal oxide in the metal oxide layer is an oxide of the metal in the metal layer.

14. The display device of claim 12, wherein, The concentration of oxygen in the metal oxide layer gradually increases from a lower portion to an upper portion of the metal oxide layer.

15. The display device of claim 11, wherein, The shield layer is in a floating state.

16. The display device of claim 11, wherein, First data lines among the plurality of data lines at a lower portion of the shield layer and second data lines among the plurality of data lines at an upper portion of the shield layer are alternately arranged in a first direction.

17. The display device of claim 16, further comprising first and second insulating layers between the first and second data lines and at the lower and upper portions of the shield layer, respectively.

18. The display device of claim 17, wherein, Each of the plurality of pixels includes an organic light emitting diode including a pixel electrode and a circuit unit for driving the organic light emitting diode, and The circuit unit includes a thin film transistor having a drain electrode electrically connected to the pixel electrode, and The first data line and the drain electrode are on the same layer, and An organic insulating layer is on the second data line, and The pixel electrode is on the organic insulating layer.

19. The display device of claim 18, wherein, The pixel electrode is electrically connected to the drain electrode via a contact hole in the organic insulating layer, the second insulating layer, the shield layer, and the first insulating layer, and the second insulating layer covers a side surface of the shield layer and a side surface of the first insulating layer at an inner side surface of the contact hole.

20. The display device of claim 16, wherein, The second data line has a greater width than the first data line.

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