Lossless pixel compression based on inferred control information

Abstract

The lossless pixel compressor may include techniques for detecting a format of a pixel memory region and compressing the pixel memory region with embedded control information indicating the format of the detected pixel memory region.Other embodiments are disclosed and claimed.

Description

Technical Field

[0001] Embodiments relate generally to graphics systems. More particularly, embodiments relate to lossless pixel compression based on inferred control information. Background Art

[0002] Lossless compression may refer to data compression that allows perfect recovery of the original data from the compressed data. On the other hand, lossy compression may only allow approximate recovery of the original data. Lossy compression may increase the compression ratio and reduce the size of the data. Lossless data compression may be used by various applications, such as ZIP (.zip files) and GZIP (.gz files). Lossless compression may be more suitable for situations where the original data and the decompressed data need to be the same, such as executable programs, text documents, source code, etc. Lossy compression may be more suitable for situations where an approximation of the original data is acceptable, such as audio files / formats (e.g., WMA, MP3), picture files / formats (e.g., JPEG, PNG), video files / formats (e.g., WMV, MP4), etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Various advantages of the embodiments will become apparent to those skilled in the art upon reading the following specification and appended claims, and upon reference to the following drawings, in which:

[0004] Figure 1 is a block diagram of an example of an electronic processing system according to an embodiment;

[0005] Figure 2 is a block diagram of an example of a semiconductor packaging device according to an embodiment;

[0006] FIG. 3A to FIG. 3D is a flow chart of an example of a method of compressing pixels according to an embodiment;

[0007] Figure 4 is a block diagram of an example of a lossless pixel compressor according to an embodiment;

[0008] Figure 5 is an illustrative diagram of an example of a residual format for compressing cache lines according to an embodiment;

[0009] Figure 6 is an illustrative diagram of an example of a multi-stage application compression table according to an embodiment;

[0010] Figure 7 is an illustrative diagram of a starting point calculation for a compressed cache line according to an embodiment;

[0011] Figure 8 is an illustrative diagram of a compressed cache line layout according to an embodiment;

[0012] Fig. 9is a block diagram of another example of a lossless pixel compressor according to an embodiment;

[0013] Fig.10 is a block diagram of an example of a format and depth detector according to an embodiment;

[0014] Fig.11 is a block diagram of an example of a bit cost calculator according to an embodiment;

[0015] Fig.12 is a block diagram of an example of a system with a navigation controller according to an embodiment; and

[0016] Fig.13 is a block diagram of an example of a system with a small form factor according to an embodiment. DETAILED DESCRIPTION

[0017] Now go to Figure 1 , an embodiment of the electronic processing system 10 may include a processor 11, a memory 12 communicatively coupled to the processor 11, and a logic 13 communicatively coupled to the processor 11, the logic 13 being configured to detect a format of a pixel memory region and compress the pixel memory region together with embedded control information indicating the format of the detected pixel memory region. In some embodiments, the logic 13 may be further configured to determine a compression result of two or more compression techniques, select one of the two or more compression techniques based on the determined compression result, and compress the pixel memory region together with the embedded control information using the selected compression technique. For example, the logic 13 may be configured to compress a portion of the pixel memory region using one of the two or more compression techniques, and estimate a compression result for the entire pixel memory region based on the compression result for the compressed portion of the pixel memory region. Additionally or alternatively, the logic 13 may also be configured to compare the compression result for one of the two or more compression techniques with a threshold value, and select one of the two or more compression techniques based on the threshold value comparison. In some embodiments, the logic 13 may also be configured to subdivide cache lines into independently compressible sub-regions, and / or to subdivide cache lines into independently decompressible sub-regions. In some embodiments, the logic 13 may also be configured to rearrange bytes of a pixel memory region into sub-regions based on a detected pixel format (e.g., sub-regions may be more uniform or more compressible when appropriately rearranged). For example, the logic 13 may also be configured to detect the depth of a pixel memory region. In some embodiments, the embedded control information may include an index to a compression table for multiple levels of application (e.g., as described in more detail herein).

[0018] Embodiments of each of the processor 11, memory 12, logic 13, and other system components described above may be implemented in hardware, software, or any suitable combination thereof. For example, hardware implementations may include configurable logic, such as a programmable logic array (PLA), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or fixed-function logic hardware using circuit technology such as an application specific integrated circuit (ASIC), a complementary metal oxide semiconductor (CMOS), or a transistor-transistor logic (TTL) technology, or any combination thereof.

[0019] Alternatively or additionally, all or part of these components may be implemented in one or more modules as a set of logical instructions stored in a machine or computer readable storage medium (e.g., random access memory (RAM), read-only memory (ROM), programmable ROM (PROM), firmware, flash memory, etc.) and executed by a processor or computing device. For example, the computer program code that performs the operation of the components may be written in any combination of one or more operating system (OS) applicable / appropriate programming languages ​​(including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, and conventional procedural programming languages ​​such as "C" programming language or similar programming languages). For example, the memory 12, persistent storage medium, or other system memory may store a set of instructions that, when executed by the processor 11, causes the system 10 to implement one or more components, features, or aspects of the system 10 (e.g., logic 13, detecting the format of a pixel memory region, compressing the pixel memory region with embedded control information indicating the format of the detected pixel memory region, etc.).

[0020] Now turn Figure 2, an embodiment of the semiconductor package device 20 may include a substrate 21 and a logic 22 coupled to the substrate, wherein the logic 22 is at least partially implemented in one or more of a configurable logic and a fixed-function hardware logic. The logic 22 coupled to the substrate 21 may be configured to detect a format of a pixel memory region and compress the pixel memory region together with embedded control information, the embedded control information indicating the format of the detected pixel memory region. In some embodiments, the logic 22 may be further configured to determine a compression result of two or more compression techniques, select one of the two or more compression techniques based on the determined compression result, and compress the pixel memory region together with the embedded control information using the selected compression technique. For example, the logic 22 may be configured to compress a portion of the pixel memory region using one of the two or more compression techniques, and estimate the compression result for the entire pixel memory region based on the compression result for the compressed portion of the pixel memory region. Additionally or alternatively, the logic 22 may also be configured to compare the compression result for one of the two or more compression techniques with a threshold value, and select one of the two or more compression techniques based on the threshold value comparison. In some embodiments, the logic 22 may be further configured to subdivide cache lines into independently compressible sub-regions, and / or to subdivide cache lines into independently decompressible sub-regions. In some embodiments, the logic 22 may also be configured to rearrange bytes of a pixel memory region into sub-regions based on a detected pixel format (e.g., sub-regions may be more uniform or more compressible when properly rearranged). For example, the logic 22 may also be configured to detect the depth of a pixel memory region. In some embodiments, the embedded control information may include an index to a compression table for multiple levels of application.

[0021] Embodiments of logic 22 and other components of device 20 may be implemented in hardware, software, or any combination thereof, including at least partially in hardware. For example, hardware implementations may include configurable logic, such as PLA, FPGA, CPLD, or fixed-function logic hardware using circuit technology such as ASIC, CMOS, or TTL technology, or any combination thereof. In addition, portions of these components may be implemented in one or more modules as a set of logic instructions stored in a machine or computer readable storage medium (e.g., RAM, ROM, PROM, firmware, flash memory, etc.) and executed by a processor or computing device. For example, a computer program code for the operation of the execution component may be written in any combination of one or more OS-appropriate / appropriate programming languages ​​(including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, and conventional process programming languages ​​such as "C" programming language or similar programming languages).

[0022] Now go to FIG. 3A to FIG. 3D , an embodiment of the method 25 for compressing pixels may include: detecting a format of a pixel memory region at box 26; and compressing the pixel memory region together with embedded control information at box 27, the embedded control information indicating the format of the detected pixel memory region. Some embodiments of the present invention may further include: determining compression results of two or more compression techniques at box 28; selecting one of the two or more compression techniques based on the determined compression results at box 29; and compressing the pixel memory region together with the embedded control information using the selected compression technique at box 30. For example, the method 25 may include compressing a portion of the pixel memory region using one of the two or more compression techniques at box 31, and estimating a compression result for the entire pixel memory region based on the compression result for the compressed portion of the pixel memory region at box 32. Additionally or alternatively, the method 25 may include comparing a compression result for one of the two or more compression techniques with a threshold at box 33, and selecting one of the two or more compression techniques based on the threshold comparison at box 34. For example, the method 25 may also include detecting a depth of the pixel memory region at box 35. In some embodiments, at block 36, the embedded control information may include an index to a compression table for the multi-stage application. Some embodiments of method 25 may further include subdividing the cache line into independently compressible sub-regions at block 37, and / or subdividing the cache line into independently decompressible sub-regions at block 38. For example, method 25 may further include rearranging bytes of the pixel memory region into sub-regions based on the detected pixel format at block 39 (e.g., the sub-regions may be more uniform or more compressible when appropriately rearranged).

[0023] Embodiments of method 25 may be implemented in, for example, systems, devices, computers, equipment, etc. described herein. More specifically, hardware implementations of method 25 may include configurable logic, such as PLA, FPGA, CPLD, or fixed-function logic hardware using circuit technology such as ASIC, CMOS, or TTL technology, or any combination thereof, or any combination thereof. Alternatively or in addition, method 25 may be implemented in one or more modules as a set of logic instructions stored in a machine or computer readable storage medium (e.g., RAM, ROM, PROM, firmware, flash memory, etc.) and executed by a processor or computing device. For example, computer program code for the operation of the execution component may be written in any combination of one or more OS-appropriate / appropriate programming languages ​​(including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, and conventional procedural programming languages ​​such as "C" programming language or similar programming languages).

[0024] For example, method 25 may be implemented on a computer readable medium as described below in conjunction with Examples 19 to 27. Embodiments of method 25, or portions thereof, may be implemented in firmware, an application (e.g., via an application programming interface (API)), or in driver software running on an operating system (OS).

[0025] Now go to Figure 4 , an embodiment of the lossless pixel compressor 44 may include a format detector 45, which is communicatively coupled to the compression selector 46 and the compressor 47. The format detector 45 may include a technique for detecting the format of the pixel memory region, and the compressor 47 may include a technique for compressing the pixel memory region together with embedded control information, the embedded control information indicating the format of the detected pixel memory region. In some embodiments, the compression selector 46 may include a technique for determining compression results of two or more lossless pixel compression techniques, and selecting one of the two or more lossless pixel compression techniques based on the determined compression results. The compressor 47 may compress the pixel memory region together with the embedded control information using the selected lossless pixel compression technique. For example, the compression selector 46 may cooperate with the compressor 47 to compress a portion of the pixel memory region using one of the two or more lossless pixel compression techniques, and estimate the compression result for the entire pixel memory region based on the compression result for the compressed portion of the pixel memory region. Additionally or alternatively, the compression selector 46 may also include a technique for the following operations: comparing the compression result of one of two or more lossless pixel compression techniques with a threshold, and selecting one of the two or more lossless pixel compression techniques based on the threshold comparison. For example, the format detector 45 may also include a technique for detecting the depth of the pixel memory region. In some embodiments, the embedded control information may include an index to a compression table for multi-level applications. In some embodiments, the compressor 47 may be further configured to subdivide the cache line into independently compressible sub-regions, and / or to subdivide the cache line into independently decompressible sub-regions. In some embodiments, the compressor 47 may also be configured to rearrange the bytes of the pixel memory region into sub-regions based on the detected pixel format (e.g., to increase compression). For example, ARGBARGB may be reformatted into AARRGGBB so that each sub-region may be more uniform and may be better compressed. Similarly, rearranging ARGBARGB into ARARGBGB may not necessarily be more uniform, but in some cases the compression effect of ARARGBGB may still be better than ARGBARGB.

[0026] Embodiments of the format detector 45, compression selector 46, compressor 47, and other components of the lossless pixel compressor 44 may be implemented in hardware, software, or any combination thereof, including at least partially in hardware. For example, hardware implementations may include configurable logic, such as PLA, FPGA, CPLD, or fixed function logic hardware using circuit technology such as ASIC, CMOS, or TTL technology, or any combination thereof. In addition, portions of these components may be implemented in one or more modules as a set of logic instructions stored in a machine or computer readable storage medium (e.g., RAM, ROM, PROM, firmware, flash memory, etc.) and executed by a processor or computing device. For example, computer program code that performs the operation of the components may be written in any combination of one or more OS-appropriate / suitable programming languages ​​(including object-oriented programming languages ​​such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages).

[0027] Some embodiments may advantageously use inferred control information for lossless pixel memory compression. For example, in lossless memory compression for 2D graphics applications, various memory packaging structures are common. Some embodiments may advantageously automatically detect common formats and embed the detected formats into compressed cache lines. Some embodiments may advantageously reduce or eliminate the need to send sideband information and may not require the sender to explicitly encode the memory layout to be used by the compressor.

[0028] Some embodiments may additionally or alternatively improve compression in situations where certain pixel patterns may achieve higher compression in a format different from the originally declared format. For example, when a pair (or more) of cache lines are provided to an embodiment of a compressor block rather than explicitly signaling what the layout is (e.g., 8-8-8-8, 10-10-10-2, 16-16 (using only 10 bits), etc.), the compressor may detect the format by trying various combinations of byte groupings. The best compression technique may then be selected, and control information may be embedded in the compressed cache line(s) for use by the decompressor.

[0029] Some embodiments may advantageously provide improved power and performance for video and pixel based memory applications without degrading image quality over a larger set of pixel formats and layouts than would be possible if all types were managed throughout the internal process of compression and decompression. For example, the P010 format may utilize a word (16 bits) per pixel value even though the allowable range for any pixel is limited to 1023, requiring only 10 bits. The upper six (6) bits are always zero (0), and embodiments of the compressor may detect this pattern and signal the presence of 192 zeros with one (1) bit (e.g., providing lossless compression of approximately 192 to 1).

[0030] In some other systems, in addition to the seed, each pixel may be variable length encoded, and various details about how the data is compressed may be handled by sideband information. Rather than treating each pixel strictly as a byte or word and calculating deltas between each pixel one by one, some embodiments may analyze entire cache lines to detect key patterns, which may be signaled within the cache line as embedded information to be used by the decompressor. Some embodiments may simplify control information handling (e.g., by software), and may also improve compression when mixed formats are used within the same memory area.

[0031] Now go to Figure 5 , embodiments of the residual format of the compressed cache line 50 may include embedded control information. For example, the cache line 50 may include a format index 51 indicating the format of the entire cache line 50, a table index 52, a bitmap portion 53, and residual data 54. For example, the cache line may include 512 bits, which may be organized as sixty-four (64) eight (8) bit bytes representing sixteen (16) bytes or four (4) 4×4 pixel blocks. In some embodiments, the format index 51 may include five (5) bits to index up to 32 different formats, the table index 52 may include three (3) bits for each of the four 4×4 blocks to index up to 8 entries in the compression table for multiple levels of application (e.g., 12 bits total for the table index 52), and the bitmap portion 53 may include fifteen (15) bits for each encoded 4×4 block (e.g., up to 60 bits total for the bitmap portion 53). The residual data 54 may include an adaptive two-length residual for each pixel within each encoded 4×4 block. Depending on the data in cache line 50, bitmap portion 53 and / or residual data 54 may not be encoded for one or more of the 4x4 blocks.

[0032] Now go to Figure 6, an embodiment of a compression table 60 for a multi-level application may include eight (8) table entries. Each entry zero (0) to seven (7) may include a level 0 (L0) value, a level 1 (LI) value, a bitmap value, a minimum (Min) value, and a maximum (Max) value. Table 60 may be considered a compression table for a two-level application. Other embodiments may include more levels and / or more or fewer table entries. Table 60 may be used to determine what compression technique has been applied to a cache line. For example, the information in table 60 may be used to generate information that may have previously been transmitted as sideband information that is marked along with each set of compressed data. Advantageously, because the Min and Max values ​​are not included in the sideband information, a wider range of Min and Max residual values ​​may be supported, and some embodiments may provide improved or more optimized compression.

[0033] For some embodiments of Table 60, for table entry zero (0), there may be no bitmap and residual to encode (e.g., the seed may always be explicitly encoded). For table entries one (1) and two (2), there may be no bitmap to encode. For table entries three (3) through seven (7), there may be both a bitmap and a residual to encode. For table entry seven (7), if 8 bits are required, some embodiments may encode the original data instead of the residual.

[0034] In Table 60, the L0 value may correspond to the number of bits used to represent the residual value if the corresponding bitmap value is 0. The LI value may correspond to the number of bits used to represent the residual value if the corresponding bitmap value is 1. The bitmap value provides one bit per pixel for a 4x4 block, except for the seed (e.g., 15 bits per 4x4 block). If the bitmap is encoded, each bit represents either L0 or LI being used to encode the corresponding residual. The Min value may represent the minimum residual value for an entry, while the Max value may represent the maximum residual value for an entry.

[0035] Now go to Figure 7 , an embodiment of the calculation 70 of the starting point for decoding a cache line may include the following calculation:

[0036] starting_point = k + L0*#bitmap0 + L1*#bitmap1 [Equation 1]

[0037] Where k corresponds to the number of bits representing the first pixel value in each 4×4 block (e.g., k=8), #bitmap0 corresponds to a bitmap value of 0 at a specified position in the 4×4 block, and #bitmap1 corresponds to a bitmap value of 1 at a specified position in the 4×4 block. Using Table 60, residual decoding can be performed on each pixel as follows. If the pixel is a seed pixel, 8 bits can be used to decode the pixel value (e.g., the seed can be pulled out into a separate segment). If the cache line bitmap value of the pixel is 0, L0 can be used to decode the pixel value. Otherwise, LI can be used to decode the pixel value.

[0038] The prediction on the compressor side may be the same as in the decompressor. In addition to performing the prediction and encoding the residual, the compressor may also pick up the correct length (corresponding to the table index) to encode the residual. To determine the table index selection, some embodiments may determine the minimum and maximum residuals for each 4×4 block in the cache line. The compressor may then select an entry in the compression table of the multi-level application that specifies the range that most closely covers the determined minimum / maximum residual. For example, in Table 60, the entries may be arranged with increasing ranges of minimum / maximum residual pairs (e.g., decreasing Min and increasing Max). The compressor may start with entry 0 and then select the entry with the lowest number that covers the minimum / maximum residual value for the determined cache line.

[0039] Now go to Figure 8 , can be combined as above Figure 7 A set of illustrative compressed cache lines (CL) are decoded as described. The value of UC may correspond to an uncompressed seed value. The value of 1D may correspond to a compression error based on one of the up / left / down / right predictions. The value of 2D may correspond to a compression error based on up / down and left / right predictions. There may be 4 critical paths with 4 predictions to complete the 512 bits. Some other compressed cache line layouts may take 18 levels to decompress the entire block. Some embodiments may improve latency by subdividing the 16×4 cache line into 4 4×4 sub-cache lines. Each sub-cache line may have its own uncompressed seed value, allowing the 4 sub-cache lines to be decompressed in parallel. The UC may be placed towards the center to allow decompression to be performed from the center outward (e.g., the radius may be smaller than the diameter). Some embodiments may advantageously require only 4 levels that can be completed in parallel.

[0040] The bit size of each 4x4 may vary based on the complexity of each block. Advantageously, by knowing the number of bits of each 4x4, an offset to the start of each 4x4 may be calculated to enable parallel decompression. Rather than including three (3) 9-bit offset values ​​inside the cache line header, some embodiments of the decoder may calculate the offset based on other information provided by the header.

[0041] Figure 8The illustration shown in can correspond to the monochrome case. In the case where the pixels are detected as ARGBARGBARGB, etc., the compressor can make 4×4 of A, 4×4 of R, 4×4 of G, and 4×4 of B. Within each 4×4, compression / decompression can be handled in the same manner as the monochrome case, and then the decompressor can shuffle the bytes back to ARGBARGBARGB. For the similar case of YUYV (YUY2), two (2) 4×4 blocks will be Y, one (1) 4×4 will be U, and one (1) 4×4 will be V. These cases can all include 8-bit values ​​per component. In the case of higher bit depths, some embodiments can utilize 4×2 blocks of 16-bit data types, which can still have 16 pixels per 4×4 data group.

[0042] In some embodiments, the detection logic may be performed on only one of the subdivided regions. The analysis of one subdivided region may then be applied to the entire block to reduce the amount of redundant analysis. Advantageously, the offset of the starting bit position within the compressed cache line may be inferred (e.g., not explicitly signaled) by inspecting the header. Some embodiments may provide one or more uncompressed seeds. For example, some embodiments may provide only one seed for the first sub-region and then compress the other three pseudo-seeds as increments from a unique originally encoded seed. Providing four original seeds may further reduce latency, but only one seed (e.g., an uncompressed pixel value) may be required.

[0043] Now go to Fig. 9, an embodiment of the compressor 80 may include a format and depth detector (FDD) 81 that is communicatively coupled to a cache line buffer 82. For example, the cache line buffer 82 may store two or more cache lines of pixel data. The FDD 81 may include two or more detectors 81a to 81n. Each of the detectors may include techniques for detecting a specific pixel packing format and / or pixel depth. Example pixel depths may include eight (8) bit depths (e.g., byte depths), sixteen (16) bit depths (e.g., word depths), ten (10) bit depths (e.g., 16 bits, 6 of which are always zero), twelve (12) bit depths (e.g., 16 bits, 4 of which are always zero), etc. For example, detector 81a may be configured to detect a Y21 (dist=2) format (e.g., where “dist” corresponds to the distance of pixels of the same channel in a pixel memory area), detector 81b may be configured to detect a UV21 (dist=2) format, detector 81c may be configured to detect a YUYV (dis=2, 4) format, detector 81d may be configured to detect an RGBA (dist=4) format, detector 81e may be configured to detect an RGBA (dist=4) format after a Y410 converter 83, detector 81f may be configured to detect a Y216 (dist=4, 8 format), detector 81g may be configured to detect a Y416 (dist=8) format, detector 81n may be configured to detect a Y416 format after an FP16 converter 84, and so on (e.g., other converters and / or format detectors may be included).

[0044] The detectors 81a to 81n may be coupled in parallel to improve performance, and the FDD 81 may provide the result of the format detection to a compression selector 85. The compression selector 85 may analyze the data in the cache line buffer 82 and / or the detected format information to select an optimal compression technique for the data in the cache line buffer 82. For example, the compression selector 85 may apply one or more compression techniques to a portion of the data in the cache line buffer 82 to determine whether any available compression techniques are able to achieve a target compression ratio (e.g., 2:1 compression, 3:2 compression, 4:3 compression, 3:1 compression, etc.). In some embodiments, the compression selector 85 may apply all available compression techniques and select the compression technique that provides the best compression. Alternatively, in some embodiments, the compression selector 85 may select the first applied compression technique that provides sufficiently good compression (e.g., compared to a threshold or range of acceptable compression).

[0045] The pseudo code for the multi-format, multi-depth detection structure can be expressed as follows:

[0046]

[0047]

[0048] Now go to Fig.10 , an embodiment of the format and depth detector 90 may include a predictor 91 for determining a prediction based on cache line data, format class information (e.g., including prediction dist), etc., and providing residual data based on the prediction. The detector 90 may further include a bit cost estimator 92 to estimate the bit cost of various depth values ​​and provide an estimated bit cost for the best depth value. For example, the bit cost estimator 92 may include a first estimator 93 for 4×4 block 0 and a second estimator 94 for 4×4 block 3 to determine different bit cost estimates for various depths. The bit cost estimator 93 may include logic for counting the number of 2-bit, 3-bit, and 4-bit residual shift zero operations for 4×4 block 0 (e.g., numRes_shift0 (2 bits, 3 bits, 4 bits)), and if depth detection is enabled, performing similar operations for shift two, shift three, and shift four operations (e.g., numRes_shift2 (2 bits, 3 bits, 4 bits), etc.). For example, numRes_shiftx (2 bits) may refer to the number of residues that can be represented by 2 bits after shifting the residue by x bits within a 4×4 group. Logic 93b may calculate the bit cost of the shift-by-zero operation (e.g., see Fig.11 ). When shift detection is required, logic 93c may encode the bit cost of a shift of two operations as 16*6=96, logic 93d may encode the bit cost of a shift of three operations as 16*4=64, and logic 93e may encode the bit cost of a shift of four operations as 16*2=32.

[0049] Similarly, the bit cost estimator 94 may include logic to count the number of 2-bit, 3-bit, and 4-bit residual shift-zero operations for 4×4 block 3 (e.g., numRes_shift0 (2 bits, 3 bits, 4 bits)), and if depth detection is enabled, perform similar operations for shift-two, shift-three, and shift-four operations (e.g., numRes_shift2 (2 bits, 3 bits, 4 bits), etc.). The same operation may also be applied to 4×4 block 1 and 4×4 block 2. The logic 94b may calculate the bit cost of the shift-zero operation (e.g., see below). Fig.11 ). When shift detection is required, logic 94c may encode the bit cost of a shift by two operation as 16*6=96, logic 94d may encode the bit cost of a shift by three operation as 16*4=64, and logic 94e may encode the bit cost of a shift by four operation as 16*2=32. Optimal depth selector 95 may be configured to determine an optimal depth value based on the estimated bit cost.

[0050] Now go to Fig.11 , an embodiment of the method 100 for calculating the bit cost may include: finding the best code at block 101; and determining whether LI=0 at block 102. If so, the bit cost may be calculated at block 103 as the number of bits used for the bitmap (e.g., 15) plus L0 plus the number of bits used for the seed in the 4×4 block (e.g., 8) plus the number of bits used for the table index (e.g., 3). Otherwise, the bit cost may be calculated at block 104 as follows:

[0051] bitcost = numRes_shift(L0)*L0 [Equation 2]

[0052] +(bitmap_size-numRes_shift0(L0))*L1

[0053] +bitmap_size+seed_size_in_bits+table_index_size

[0054] Where bitmap_size corresponds to the number of bits in the bitmap, seed_size_in_bits corresponds to the number of bits representing the seed in a 4×4 block, and table_index_size corresponds to the number of bits used for the table index. In some embodiments, the calculations may be all or primarily integer calculations. Some embodiments may additionally or alternatively utilize floating point calculations.

[0055] Advantageously, some embodiments may utilize compression tables for multi-level applications together with embedded control information to simplify the compression / decompression process without sideband information. Some embodiments may additionally or alternatively improve the capabilities and performance of video and pixel-based memory applications without degrading image quality.

[0056] Fig.12 An embodiment of a system 700 is illustrated. In an embodiment, the system 700 may be a media system, but the system 700 is not limited to this context. For example, the system 700 may be incorporated into a personal computer (PC), a laptop computer, an ultra-laptop computer, a tablet computer, a touchpad, a portable computer, a handheld computer, a palmtop computer, a personal digital assistant (PDA), a cellular phone, a combination cellular phone / PDA, a television, a smart device (e.g., a smart phone, a smart tablet computer, or a smart TV), a mobile Internet device (MID), a messaging device, a data communication device, etc.

[0057] In embodiments, system 700 includes platform 702 coupled to display 720 that presents visual content. Platform 702 may receive video bitstream content from a content device such as content service device(s) 730 or content delivery device(s) 740 or other similar content sources. Navigation controller 750 including one or more navigation features may be used to interact with, for example, platform 702 and / or display 720. Each of these components is described in greater detail below.

[0058] In an embodiment, the platform 702 may include any combination of a chipset 705, a processor 710, a memory 712, a storage device 714, a graphics subsystem 715, an application 716, and / or a radio device 718 (e.g., a network controller). The chipset 705 may provide intercommunication between the processor 710, the memory 712, the storage device 714, the graphics subsystem 715, the application 716, and / or the radio device 718. For example, the chipset 705 may include a storage adapter (not shown) capable of providing intercommunication with the storage device 714.

[0059] Processor 710 may be implemented as a complex instruction set computer (CISC) or reduced instruction set computer (RISC) processor, an x86 instruction set compatible processor, a multi-core, or any other microprocessor or central processing unit (CPU). In an embodiment, processor 710 may include (one or more) dual-core processors, (one or more) dual-core mobile processors, and the like.

[0060] Memory 712 may be implemented as a volatile storage device such as, but not limited to, a random access memory (RAM), a dynamic random access memory (DRAM), or a static RAM (SRAM).

[0061] The storage device 714 may be implemented as a non-volatile storage device, such as, but not limited to, a magnetic disk drive, an optical disk drive, a tape drive, an internal storage device, an attached storage device, flash memory, battery-backed SDRAM (synchronous DRAM), and / or a network accessible storage device. In an embodiment, the storage device 714 may include technology for increasing storage performance enhancement protection for valuable digital media when, for example, multiple hard drives are included.

[0062] The graphics subsystem 715 can process images such as stills or videos for display. The graphics subsystem 715 can be, for example, a graphics processing unit (GPU) or a visual processing unit (VPU). An analog or digital interface can be used to communicatively couple the graphics subsystem 715 and the display 720. For example, the interface can be any of a high-definition multimedia interface (HDMI), a display port (DisplayPort), wireless HDMI, and / or a wireless HD compatible technology. The graphics subsystem 715 can be integrated into the processor 710 or the chipset 705. The graphics subsystem 715 can be a stand-alone card communicatively coupled to the chipset 705. In one example, the graphics subsystem 715 includes a noise reduction subsystem as described herein.

[0063] The graphics and / or video processing techniques described herein may be implemented in a variety of hardware architectures. For example, graphics and / or video functions may be integrated into a chipset. Alternatively, a discrete graphics and / or video processor may be used. As another embodiment, graphics and / or video functions may be implemented by a general purpose processor including a multi-core processor. In another embodiment, these functions may be implemented in a consumer electronic device.

[0064] Radio 718 may be a network controller that includes one or more radios capable of sending and receiving signals using a variety of suitable wireless communication technologies. Such technologies may involve communications across one or more wireless networks. Exemplary wireless networks include, but are not limited to, wireless local area networks (WLANs), wireless personal area networks (WPANs), wireless metropolitan area networks (WMANs), cellular networks, and satellite networks. When communicating across such networks, radio 718 may operate in accordance with one or more applicable standards in any version.

[0065] In an embodiment, the display 720 may include a monitor or display of any television type. The display 720 may include, for example, a computer display screen, a touch screen display, a video monitor, a television-like device, and / or a television. The display 720 may be digital and / or analog. In an embodiment, the display 720 may be a holographic display. Moreover, the display 720 may be a transparent surface that can receive a visual projection. Such a projection may convey information, images, and / or objects in various forms. For example, such a projection may be a visual overlay for a mobile augmented reality (MAR) application. Under the control of one or more software applications 716, the platform 702 may display a user interface 722 on the display 720.

[0066] In embodiments, content services device(s) 730 may be hosted by any national, international, and / or independent service and thus accessible by platform 702, e.g., via the Internet. Content services device(s) 730 may be coupled to platform 702 and / or display 720. Platform 702 and / or content services device(s) 730 may be coupled to network 760 to communicate (e.g., send and / or receive) media information to and from network 760. Content delivery device(s) 740 may also be coupled to platform 702 and / or display 720.

[0067] In embodiments, content services device(s) 730 may include a cable box, a personal computer, a network, a telephone, an Internet-enabled device or appliance capable of delivering digital information and / or content, and any other similar device capable of delivering content unidirectionally or bidirectionally between content providers and platform 702 and / or display 720, either directly or via network 760. It will be appreciated that content may be delivered unidirectionally and / or bidirectionally to and from any one of the components in system 700 and content providers via network 760. Examples of content may include any media information, including, for example, video, music, medical and gaming information, and the like.

[0068] (One or more) content service device 730 receives content such as cable television programs including media information, digital information and / or other content. Examples of content providers may include any cable or satellite television or radio or Internet content providers. The examples provided are not meant to limit the embodiments.

[0069] In embodiments, platform 702 may receive control signals from a navigation controller 750 having one or more navigation features. For example, the navigation features of controller 750 may be used to interact with user interface 722. In embodiments, navigation controller 750 may be a pointing device that may be a computer hardware component (specifically a human interface device) that allows a user to input spatial (e.g., continuous and multi-dimensional) data into a computer. Many systems such as graphical user interfaces (GUIs), televisions, and monitors allow a user to control and provide data to a computer or television using physical gestures.

[0070] Movements of the navigation features of controller 750 may be replicated on a display (e.g., display 720) by movements of a pointer, cursor, focus ring, or other visual indicator displayed on the display. For example, under the control of software applications 716, for example, the navigation features located on navigation controller 750 may be mapped to virtual navigation features displayed, for example, on user interface 722. In embodiments, controller 750 may not be a separate component, but may be integrated into platform 702 and / or display 720. Embodiments, however, are not limited to the elements or in the context shown or described herein.

[0071] In embodiments, for example, when enabled, drivers (not shown) may include technology that enables a user to instantly turn platform 702 on and off with the touch of a button after initial boot-up, like a television. When the platform is "off," program logic may allow platform 702 to stream content to a media adapter or other content service device(s) 730 or content delivery device(s) 740. Additionally, chipset 705 may include hardware and / or software support for, for example, 5.1 surround sound audio and / or high definition 7.1 surround sound audio. Drivers may include a graphics driver for an integrated graphics platform. In embodiments, the graphics driver may include a high-speed peripheral component interconnect (PCI) graphics card.

[0072] In various embodiments, any one or more of the components shown in system 700 may be integrated. For example, platform 702 and (one or more) content service device 730 may be integrated, or platform 702 and (one or more) content delivery device 740 may be integrated, or platform 702, (one or more) content service device 730, and (one or more) content delivery device 740 may be integrated. In various embodiments, platform 702 and display 720 may be an integrated unit. For example, display 720 and (one or more) content service device 730 may be integrated, or display 720 and (one or more) content delivery device 740 may be integrated. These examples are not meant to limit the embodiments.

[0073] In various embodiments, the system 700 may be implemented as a wireless system, a wired system, or a combination of the two. When implemented as a wireless system, the system 700 may include components and interfaces suitable for communicating via a wireless shared medium, such as one or more antennas, transmitters, receivers, transceivers, amplifiers, filters, control logic, etc. Examples of wireless shared media may include a portion of a wireless spectrum, such as an RF spectrum, etc. When implemented as a wired system, the system 700 may include components and interfaces suitable for communicating on a wired communication medium, such as an input / output (I / O) adapter, a physical connector for connecting an I / O adapter to a corresponding wired communication medium, a network interface card (NIC), a disk controller, a video controller, an audio controller, etc. Examples of wired communication media may include wires, cables, metal leads, printed circuit boards (PCBs), backplanes, switch fabrics, semiconductor materials, twisted pairs, coaxial cables, optical fibers, etc.

[0074] Platform 702 may establish one or more logical or physical channels to transmit information. Information may include media information and control information. Media information may refer to any data representing content intended for a user. Examples of content may include, for example, data from a voice conversation, a video conference, a streaming video, an electronic mail ("email") message, a voice mail message, alphanumeric symbols, graphics, images, video, text, and the like. Data from a voice conversation may be, for example, voice information, periods of silence, background noise, comfort noise, tones, and the like. Control information may refer to any data representing commands, instructions, or control words intended for an automated system. For example, control information may be used to route media information through a system, or to instruct a node to process media information in a predetermined manner. However, embodiments are not limited to the embodiments described herein. Fig.12 The elements or situations shown or described in FIG.

[0075] As discussed above, system 700 may be embodied in different physical styles or form factors. Fig.13 An embodiment of a small form factor device 800 in which the system 700 may be embodied is illustrated. In an embodiment, for example, the device 800 may be implemented as a mobile computing device with wireless capabilities. A mobile computing device may refer to, for example, any device having a processing system and a mobile power source or supply (e.g., one or more batteries).

[0076] As described above, examples of mobile computing devices may include a personal computer (PC), a laptop computer, an ultralaptop computer, a tablet computer, a touchpad, a portable computer, a handheld computer, a palmtop computer, a personal digital assistant (PDA), a cellular phone, a combination cellular phone / PDA, a television, a smart device (e.g., a smart phone, a smart tablet, or a smart TV), a mobile Internet device (MID), a messaging device, a data communications device, and the like.

[0077] Examples of mobile computing devices may also include computers that are arranged to be worn by a person, such as a wrist computer, a finger computer, a ring computer, an eyeglass computer, a belt-clip computer, an arm-band computer, a shoe computer, a clothing computer, and other wearable computers. In an embodiment, for example, a mobile computing device may be implemented as a smart phone capable of executing computer applications as well as voice communications and / or data communications. Although some embodiments may be described with a mobile computing device implemented as a smart phone by way of example, it will be appreciated that other embodiments may also be implemented using other wireless mobile computing devices. The embodiments are not limited to this context.

[0078] like Fig.13 As shown, device 800 may include housing 802, display 804, input / output (I / O) device 806 and antenna 808. Device 800 may also include navigation features 812. Display 804 may include any suitable display unit for displaying information suitable for mobile computing devices. I / O device 806 may include any suitable I / O device for inputting information into mobile computing devices. Examples of I / O device 806 may include alphanumeric keyboards, numeric keypads, touch pads, input keys, buttons, switches, rocker switches, microphones, speakers, voice recognition devices and software, etc. Information may also be input into device 800 via a microphone. Such information may be digitized by a voice recognition device. Embodiments are not limited to this context.

[0079] According to some embodiments, the system 700 and / or device 800 may be advantageously configured with one or more features of the lossless pixel compressor / decompressor described herein (e.g., including multi-depth and / or multi-format detection). For example, the system 700 and / or device 800 may include one or more of the features described in the following additional description and examples.

[0080] Additional notes and examples:

[0081] Example 1 may include a semiconductor package device including a substrate and logic coupled to the substrate, wherein the logic is at least partially implemented in one or more of configurable logic and fixed-function hardware logic, and the logic coupled to the substrate is used to: detect a format of a pixel memory region and compress the pixel memory region together with embedded control information, the embedded control information indicating the format of the detected pixel memory region.

[0082] Example 2 may include the apparatus of Example 1, wherein the logic is further used to: determine a compression result of two or more compression techniques, select one of the two or more compression techniques based on the determined compression result, and compress the pixel memory area together with the embedded control information using the selected compression technique.

[0083] Example 3 may include the apparatus of Example 2, wherein the logic is further used to: compress a portion of the pixel memory area using one of two or more compression techniques, and estimate a compression result for the entire pixel memory area based on the compression result for the compressed portion of the pixel memory area.

[0084] Example 4 may include the apparatus of Example 2, wherein the logic is further used to: compare a compression result for one of the two or more compression techniques with a threshold, and select the one of the two or more compression techniques based on the threshold comparison.

[0085] Example 5 may include the apparatus of Example 1, wherein the logic is further to: subdivide the cache line into independently compressible sub-regions.

[0086] Example 6 may include the apparatus of Example 1, wherein the logic is further to: subdivide the cache line into independently decompressible sub-regions.

[0087] Example 7 may include the apparatus of Example 1, wherein the logic is further to: rearrange bytes of the pixel memory region into sub-regions based on the detected pixel format.

[0088] Example 8 may include the apparatus of any of Examples 1-7, wherein the logic is further for: detecting a depth of the pixel memory region.

[0089] Example 9 may include the apparatus of any of Examples 1 to 7, wherein the embedded control information comprises an index to a compression table of the multi-stage application.

[0090] Example 10 may include a method of compressing pixels, comprising: detecting a format of a pixel memory region; and compressing the pixel memory region together with embedded control information indicating the detected format of the pixel memory region.

[0091] Example 11 may include the method of Example 10, further comprising: determining compression results of two or more compression techniques; selecting one compression technique from the two or more compression techniques based on the determined compression results; and compressing the pixel memory area together with the embedded control information using the selected compression technique.

[0092] Example 12 may include the method of Example 11, further comprising: compressing a portion of the pixel memory area using one of two or more compression techniques, and estimating a compression result for the entire pixel memory area based on the compression result for the compressed portion of the pixel memory area.

[0093] Example 13 may include the method of Example 11, further comprising: comparing a compression result for one of the two or more compression techniques with a threshold, and selecting one of the two or more compression techniques based on the threshold comparison.

[0094] Example 14 may include the method of Example 10, further comprising subdividing the cache line into independently compressible sub-regions.

[0095] Example 15 may include the method of Example 10, further comprising subdividing the cache line into independently decompressible sub-regions.

[0096] Example 16 may include the method of Example 10, further comprising rearranging bytes of the pixel memory region into sub-regions based on the detected pixel format.

[0097] Example 17 may include the method of any of Examples 10 to 16, further comprising detecting a depth of the pixel memory region.

[0098] Example 18 may include the method of any one of Examples 10 to 16, wherein the embedded control information may include an index to a compression table of the multi-stage application.

[0099] Example 19 may include at least one computer-readable medium comprising a set of instructions that, when executed by a computing device, cause the computing device to: detect a format of a pixel memory region, and compress the pixel memory region together with embedded control information indicating the format of the detected pixel memory region.

[0100] Example 20 may include at least one computer-readable medium of Example 19, comprising another set of instructions, which, when executed by a computing device, causes the computing device to: determine a compression result of two or more compression techniques, select one of the two or more compression techniques based on the determined compression result, and compress the pixel memory region together with the embedded control information using the selected compression technique.

[0101] Example 21 may include at least one computer-readable medium of Example 20, comprising another set of instructions, which, when executed by a computing device, causes the computing device to: compress a portion of a pixel memory area using one of two or more compression techniques, and estimate a compression result for the entire pixel memory area based on the compression result for the portion of the compressed pixel memory area.

[0102] Example 22 may include at least one computer-readable medium of Example 20, comprising another set of instructions, which, when executed by a computing device, causes the computing device to: compare a compression result for one of the two or more compression techniques with a threshold, and select one of the two or more compression techniques based on the threshold comparison.

[0103] Example 23 may include the at least one computer-readable medium of Example 19, comprising another set of instructions that, when executed by a computing device, cause the computing device to: subdivide a cache line into independently compressible sub-regions.

[0104] Example 24 may include the at least one computer-readable medium of Example 19, comprising another set of instructions that, when executed by a computing device, cause the computing device to: subdivide a cache line into independently decompressible sub-regions.

[0105] Example 25 may include at least one computer-readable medium of Example 19, comprising another set of instructions that, when executed by a computing device, cause the computing device to: rearrange bytes of a pixel memory region into sub-regions based on a detected pixel format.

[0106] Example 26 may include the at least one computer readable medium of any of Examples 19 to 25, comprising a further set of instructions that, when executed by a computing device, cause the computing device to: detect a depth of a pixel memory region.

[0107] Example 27 may include the at least one computer readable medium of any one of Examples 19 to 25, wherein the embedded control information comprises an index to a compression table of the multi-stage application.

[0108] Example 28 may include an electronic processing system comprising a processor, a memory communicatively coupled to the processor, and logic communicatively coupled to the processor for detecting a format of a pixel memory region and compressing the pixel memory region with embedded control information indicating the format of the detected pixel memory region.

[0109] Example 29 may include the system of Example 28, wherein the logic is further used to: determine a compression result of two or more compression techniques, select one of the two or more compression techniques based on the determined compression result, and compress the pixel memory area together with the embedded control information using the selected compression technique.

[0110] Example 30 may include the system of Example 29, wherein the logic is further used to: compress a portion of the pixel memory area using one of two or more compression techniques, and estimate a compression result for the entire pixel memory area based on the compression result for the compressed portion of the pixel memory area.

[0111] Example 31 may include the system of Example 29, wherein the logic is further for comparing a compression result for one of the two or more compression techniques with a threshold, and selecting the one of the two or more compression techniques based on the threshold comparison.

[0112] Example 32 may include the system of Example 28, wherein the logic is further for: subdividing the cache line into independently compressible sub-regions.

[0113] Example 33 may include the system of Example 28, wherein the logic is further for: subdividing the cache line into independently decompressible sub-regions.

[0114] Example 34 may include the system of Example 28, wherein the logic is further for: rearranging bytes of the pixel memory region into sub-regions based on the detected pixel format.

[0115] Example 35 may include the system of any of Examples 28 to 34, wherein the logic is further for: detecting a depth of the pixel memory region.

[0116] Example 36 may include the system of any of Examples 28 to 34, wherein the embedded control information comprises an index to a compression table of the multi-stage application.

[0117] Example 37 may include a pixel compressor device comprising: a device for detecting a format of a pixel memory region, and a device for compressing the pixel memory region together with embedded control information, the embedded control information indicating the format of the detected pixel memory region.

[0118] Example 38 may include the apparatus of Example 37, further comprising: a device for determining compression results of two or more compression techniques, a device for selecting one of the two or more compression techniques based on the determined compression results, and a device for compressing a pixel memory area together with embedded control information using the selected compression technique.

[0119] Example 39 may include the apparatus of Example 38, further comprising: a device for compressing a portion of a pixel memory area using one of two or more compression techniques, and a device for estimating a compression result for the entire pixel memory area based on the compression result for the compressed portion of the pixel memory area.

[0120] Example 40 may include the apparatus of Example 38, further comprising: a device for comparing a compression result for one of the two or more compression techniques with a threshold, and a device for selecting one of the two or more compression techniques based on the threshold comparison.

[0121] Example 41 may include the apparatus of Example 37, further comprising: means for subdividing the cache line into independently compressible sub-regions.

[0122] Example 42 may include the apparatus of Example 37, further comprising: means for subdividing the cache line into independently decompressible sub-regions.

[0123] Example 43 may include the apparatus of Example 37, further comprising: means for rearranging bytes of the pixel memory region into sub-regions based on the detected pixel format.

[0124] Example 44 may include the apparatus of any of Examples 37 to 43, further comprising: means for detecting a depth of the pixel memory region.

[0125] Example 45 may include the apparatus of any one of Examples 37 to 43, wherein the embedded control information comprises an index to a compression table of the multi-stage application.

[0126] Embodiments are applicable to use with all types of semiconductor integrated circuit ("IC") chips. Examples of these IC chips include, but are not limited to, processors, controllers, chipset components, programmable logic arrays (PLA), memory chips, network chips, systems on chips (SoC), SSD / NAND controller ASICs, and the like. In addition, in some of these figures, signal conductor lines are represented by lines. Some lines may be different to indicate more constituent signal paths; may have numbered labels to indicate the numbering of constituent signal paths; and / or have arrows at one or more ends to indicate the main information flow. However, this should not be interpreted in a limiting manner. Rather, such added details may be used in conjunction with one or more exemplary embodiments to facilitate easier understanding of the circuit. Any signal line represented, whether or not it has additional information, may actually include one or more signals that can travel in multiple directions and may be implemented with any suitable type of signal scheme, for example, digital or analog lines implemented with differential pairs, fiber optic lines, and / or single-ended lines.

[0127] Example size / model / value / range can be given, but the embodiment is not limited thereto. As manufacturing technology (e.g., photolithography) matures over time, it is expected that devices of smaller size can be manufactured. In addition, in order to simplify the illustration and discussion, so as not to confuse certain aspects of the embodiment, the well-known power supply / ground connection with the IC chip and other components may be shown or not shown in the figure. In addition, in order to avoid confusing the embodiment, and also in view of the fact that the details of the implementation mode of such a block diagram arrangement are highly dependent on the platform in which the embodiment is implemented (that is, such details should be fully within the scope of vision of those skilled in the art), the arrangement can be shown in the form of a block diagram. In the case of elaborating specific details (e.g., circuit) for describing the example embodiment, it should be clear to those skilled in the art that the embodiment can be practiced without these specific details or with changes to these specific details. Therefore, the description should be considered illustrative rather than restrictive.

[0128] The term "coupled" may be used herein to refer to any type of direct or indirect relationship between the components being discussed, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. Additionally, unless otherwise noted, the terms "first," "second," etc. may be used herein only to facilitate discussion and do not have a specific time or timing meaning.

[0129] As used in this application and in the claims, a list of items connected by the term "one or more of" may mean any combination of the listed items. For example, the phrase "one or more of A, B, and C" and the phrase "one or more of A, B, or C" may both mean A; B; C; A and B; A and C; B and C; or A, B, and C.

[0130] From the foregoing description, those skilled in the art will appreciate that the broad techniques of the embodiments can be implemented in various forms. Therefore, although the embodiments have been described in conjunction with specific examples of the embodiments, the true scope of the embodiments should not be limited thereby, as other modifications will become apparent to those skilled in the art after studying the drawings, the specification, and the appended claims.

Claims

1. A semiconductor packaging device, comprising: substrate; and Logic coupled to the substrate, wherein the logic is implemented at least in part in one or more of configurable logic and fixed function hardware logic, the logic coupled to the substrate to: detect the format of the pixel memory region, and The pixel memory region is compressed together with embedded control information indicating a format of the detected pixel memory region.

2. The device according to claim 1, wherein: The logic is also used to: determining compression results of two or more compression techniques; selecting one of the two or more compression techniques based on the determined compression result; as well as The pixel memory region is compressed along with the embedded control information using the selected compression technique.

3. The device according to claim 2, wherein: The logic is also used to: compressing a portion of the pixel memory region using one of the two or more compression techniques; as well as A compression result for the entire pixel memory area is estimated based on a compression result for a compressed portion of the pixel memory area.

4. The device according to claim 2, wherein: The logic is also used to: comparing a compression result for one of the two or more compression techniques to a threshold value; as well as One of the two or more compression techniques is selected based on a threshold comparison.

5. The device according to claim 1, wherein: The logic is also used to: Subdivide cache lines into sub-regions that can be compressed independently.

6. The device according to claim 1, wherein: The logic is also used to: Subdivide cache lines into sub-regions that can be decompressed independently.

7. The device according to claim 1, wherein: The logic is also used to: The bytes of the pixel memory region are rearranged into sub-regions based on the detected pixel format.

8. The device according to any one of claims 1 to 7, wherein: The logic is further configured to detect a depth of the pixel memory region.

9. The device according to any one of claims 1 to 7, wherein: The embedded control information includes an index to a compression table for a multi-level application.

10. A method for compressing pixels, comprising: Detecting the format of a pixel memory region; as well as The pixel memory region is compressed together with embedded control information indicating a format of the detected pixel memory region.

11. The method according to claim 10, further comprising: determining compression results of two or more compression techniques; selecting one of the two or more compression techniques based on the determined compression result; as well as The pixel memory region is compressed along with the embedded control information using the selected compression technique.

12. The method according to claim 11, further comprising: compressing a portion of the pixel memory region using one of the two or more compression techniques; as well as A compression result for the entire pixel memory area is estimated based on a compression result for a compressed portion of the pixel memory area.

13. The method according to claim 11, further comprising: comparing a compression result for one of the two or more compression techniques to a threshold value; as well as One of the two or more compression techniques is selected based on a threshold comparison.

14. The method according to claim 10, further comprising: Subdivide cache lines into sub-regions that can be compressed independently.

15. The method according to claim 10, further comprising: Subdivide cache lines into sub-regions that can be decompressed independently.

16. The method according to claim 10, further comprising: The bytes of the pixel memory region are rearranged into sub-regions based on the detected pixel format.

17. The method according to any one of claims 10 to 16, further comprising: The depth of the pixel memory region is detected.

18. The method according to any one of claims 10 to 16, wherein: The embedded control information includes an index to a compression table for a multi-level application.

19. An electronic processing system comprising: processor; a memory communicatively coupled to the processor; as well as Logic communicatively coupled to the processor, the logic to: detect the format of the pixel memory region, and The pixel memory region is compressed together with embedded control information indicating a format of the detected pixel memory region.

20. The system of claim 19, wherein: The logic is also used to: determining compression results of two or more compression techniques; selecting one of the two or more compression techniques based on the determined compression result; as well as The pixel memory region is compressed along with the embedded control information using the selected compression technique.

21. The system of claim 20, wherein: The logic is also used to: compressing a portion of the pixel memory region using one of the two or more compression techniques; as well as A compression result for the entire pixel memory area is estimated based on a compression result for a compressed portion of the pixel memory area.

22. The system of claim 20, wherein: The logic is also used to: comparing a compression result for one of the two or more compression techniques to a threshold value; as well as One of the two or more compression techniques is selected based on a threshold comparison.

23. The system of claim 19, wherein: The logic is also used to: Subdivide cache lines into sub-regions that can be compressed independently.

24. The system of claim 19, wherein: The logic is also used to: Subdivide cache lines into sub-regions that can be decompressed independently.

25. A system according to any one of claims 19 to 24, wherein: The embedded control information includes an index to a compression table for a multi-level application.

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