Through-Silicon Via Detection Circuit, Detection Method Thereof, and Integrated Circuit

Abstract

The present disclosure relates to a through-silicon via detection circuit, a detection method thereof, and an integrated circuit. The through-silicon via detection circuit includes a first detection module and a second detection module. The first detection module includes: a first comparison unit, a first input unit, and a first switching unit. The first input unit is configured to transmit an input signal to a first input terminal of the first comparison unit under the control of a first clock signal; the first switching unit is configured to transmit a signal of a first node to a second input terminal of the first comparison unit under the control of a first detection control signal, and the first node is connected to a first end of the through-silicon via. The second detection module includes: a second input unit and a second switching unit. The second input unit is configured to transmit the input signal to a second node under the control of a second clock signal; the second switching unit is configured to transmit a signal of the second node to a second end of the through-silicon via under the control of a second detection control signal.

Description

Background Art

[0002] With the development and progress of technology, the use of 3D chips is becoming more and more widespread. 3D chips achieve the connection of multiple silicon wafers through TSV (Through-Silicon Vias). TSV is prone to failures during the manufacturing and bonding processes, and TSV failures will inevitably affect the performance of 3D chips.

[0003] Currently, for TSV failures, usually, fault detection is first performed, and the control signal of the programming multiplexer is used to shield the faulty TSV through the TSV redundancy mechanism. However, due to the high cost of the TSV redundancy mechanism and the corresponding detection circuit, it is not suitable for application in mass-produced 3D chips.

[0004] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0005] The purpose of the present disclosure is to provide a through-silicon via detection device, its detection method, and an integrated circuit, so as to at least to a certain extent overcome the problem that the TSV redundancy mechanism and the corresponding detection circuit have a high cost and are not suitable for application in mass-produced 3D chips due to the limitations and defects of the related technology.

[0006] According to the first aspect of the present disclosure, a through-silicon via detection circuit is provided, including:

[0007] A first detection module, including:

[0008] A first comparison unit;

[0009] A first input unit, configured to transmit an input signal to a first input terminal of the first comparison unit under the control of a first clock signal;

[0010] A first switch unit, configured to transmit the signal of a first node to a second input terminal of the first comparison unit under the control of a first detection control signal, and the first node is connected to a first end of the through-silicon via;

[0011] A second detection module, including:

[0012] A second input unit, configured to transmit the input signal to a second node under the control of a second clock signal;

[0013] A second switch unit, configured to transmit the signal of the second node to a second end of the through-silicon via under the control of a second detection control signal.

[0014] According to an embodiment of the present disclosure, the first input unit includes:

[0015] A first trigger, with its input terminal connected to an input signal, its output terminal connected to a first input terminal of a first comparison unit, and its clock terminal connected to a first clock signal.

[0016] According to an embodiment of the present disclosure, the first input unit further includes:

[0017] A first selector, with its first input terminal connected to the input signal, its second input terminal connected to the output terminal of the first comparison unit, its control terminal connected to a first selection control signal, and its output terminal connected to the input terminal of the first trigger.

[0018] According to an embodiment of the present disclosure, the first detection module further includes:

[0019] A third switch unit, with its first end connected to the output terminal of the first trigger and its second end connected to the first node, and its control terminal connected to a first detection control signal.

[0020] According to an embodiment of the present disclosure, the second input unit includes:

[0021] A second trigger, with its input terminal connected to the input signal, its output terminal connected to a second node, and its clock terminal connected to a second clock signal.

[0022] According to an embodiment of the present disclosure, the second input unit further includes:

[0023] A second selector, with its first input terminal connected to the input signal, its control terminal connected to a second selection control signal, and its output terminal connected to the input terminal of the second trigger.

[0024] According to an embodiment of the present disclosure, the second detection module further includes:

[0025] A fourth switch unit, with its first end connected to the second end of the through-silicon via, and its control terminal connected to the second detection control signal;

[0026] A second comparison unit, with its first input terminal connected to the second end of the fourth switch unit, its second input terminal connected to the second node, and its output terminal connected to the second input terminal of the second selector.

[0027] According to an embodiment of the present disclosure, the first detection module is disposed on a first chip layer, the second detection module is disposed on a second chip layer, and the first chip layer and the second chip layer are connected by a through-silicon via.

[0028] According to an embodiment of the present disclosure, a plurality of first detection modules are sequentially disposed on the first chip layer, wherein the output terminal of the first trigger in the previous first detection module is connected to the input terminal of the next first detection module;

[0029] A plurality of second detection modules are sequentially arranged on the second chip layer, wherein the output end of the second flip-flop in the previous second detection module is connected to the input end of the next second detection module.

[0030] According to an embodiment of the present disclosure, the through-silicon via detection circuit further includes:

[0031] A third comparison unit, and the output ends of the plurality of first comparison units are respectively connected to the input end of the third comparison unit.

[0032] According to an embodiment of the present disclosure, each comparison unit is an exclusive-OR gate.

[0033] According to an embodiment of the present disclosure, the first switch unit is an N-type metal oxide semiconductor transistor, and the second switch unit is a P-type metal oxide semiconductor transistor;

[0034] Alternatively, the first switch unit is a P-type metal oxide semiconductor transistor, and the second switch unit is an N-type metal oxide semiconductor transistor.

[0035] According to an embodiment of the present disclosure, both the first switch unit and the second switch unit are CMOS (Complementary Metal Oxide Semiconductor) transmission gates.

[0036] According to a second aspect of the present disclosure, a through-silicon via detection method is provided, including:

[0037] Input an input signal into the second input unit through a second clock signal and transmit it to a second node;

[0038] Input the input signal into the first input unit through a first clock signal and transmit it to a first input end of the first comparison unit;

[0039] Turn on the first switch unit through a first detection control signal, turn on the second switch unit through a second detection control signal, and the input signal is transmitted to a second input end of the first comparison unit through the second switch unit, the through-silicon via, and the first switch unit;

[0040] Compare the signals input to the first input end and the second input end of the first comparison unit, and output a comparison result.

[0041] According to an embodiment of the present disclosure, the method includes:

[0042] Input the input signal into the second input unit sequentially through the second clock signal and transmit it to the corresponding second node;

[0043] The input signal is sequentially input into the first input unit through the first clock signal and transmitted to the first input end of the corresponding first comparison unit;

[0044] Multiple first switch units are turned on through the first detection control signal, and multiple second switch units are turned on through the second detection control signal. The input signal is transmitted to the second input end of the second comparison unit through the second switch unit connected to a through-silicon via, the through-silicon via, and the first switch unit respectively;

[0045] Multiple second comparison units respectively compare the signals input to their first input end and second input end and output comparison results.

[0046] According to an embodiment of the present disclosure, the method for detecting a through-silicon via further includes:

[0047] The output signals of multiple first comparison units are respectively input into the third comparison unit. The third comparison unit compares the output signals of multiple first comparison units and outputs a comparison result.

[0048] According to a third aspect of the present disclosure, an integrated circuit is provided, which is the above-mentioned through-silicon via detection circuit.

[0049] The through-silicon via detection circuit provided by the present disclosure transmits the input signal to the first end of the first comparison unit through the first input unit, transmits the input signal to the second node through the second input unit, the second detection control signal controls the second switch unit to turn on, and the first detection control signal controls the first switch unit to turn on. The input signal at the second node is transmitted to the second end of the first comparison unit through the second switch unit, the through-silicon via, and the first switch unit. That is, the original input signal is input to the first input end of the first comparison unit, and the input signal passing through the through-silicon via is input to the second end. By comparing these two signals, if there is a difference between the two signals, the through-silicon via has a fault; if there is no difference between the two signals, the through-silicon via has no fault. Since the through-silicon via detection circuit provided by the present disclosure has a simple structure and is easy to manufacture, it is suitable for use in mass-produced 3D chips and can reduce production costs.

[0050] It should be understood that the above general description and the following detailed description are only exemplary and explanatory and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] By referring to the accompanying drawings to describe its exemplary embodiments in detail, the above and other features and advantages of the present disclosure will become more obvious.

[0052] Figure 1a Schematic diagram of a fault-free TSV;

[0053] Figure 1b Schematic diagram of a TSV with a hole fault;

[0054] Figure 1c Schematic diagram of a TSV with leakage fault

[0055] Figure 2 Schematic diagram of a through - silicon via (TSV) detection circuit provided by an exemplary embodiment of the present disclosure

[0056] Figure 3 Schematic diagram of a first detection module provided by an exemplary embodiment of the present disclosure

[0057] Figure 4 Schematic diagram of a second detection module provided by an exemplary embodiment of the present disclosure

[0058] Figure 5 Schematic diagram of the connection of multiple detection modules provided by an exemplary embodiment of the present disclosure

[0059] Figure 6 Another schematic diagram of the connection of multiple detection modules provided by an exemplary embodiment of the present disclosure

[0060] Figure 7 Flowchart of a through - silicon via detection method provided by an exemplary embodiment of the present disclosure

[0061] Figure 8 Another flowchart of a through - silicon via detection method provided by an exemplary embodiment of the present disclosure

[0062] In the figure: 100, the first detection module; 110, the first input unit; 111, the first flip - flop; 112, the first selector; 120, the first switch unit; 130, the first comparison unit; 200, the second detection module; 210, the second input unit; 211, the second flip - flop; 212, the second selector; 220, the second switch unit; 230, the second comparison unit; 300, the third comparison unit Detailed implementation manners

[0063] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar parts, and thus their repeated description will be omitted

[0064] In addition, the described features, structures, or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will recognize that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, materials, devices, steps, etc. may be employed. In other cases, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the present disclosure.

[0065] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or these functional entities or a part of the functional entities may be implemented in one or more software-hardened modules, or these functional entities may be implemented in different networks and / or processor devices and / or microcontroller devices.

[0066] In the related art, for a fault-free TSV as Figure 1a shown, generally, a TSV may have a hole fault as Figure 1b shown, or a leakage fault as Figure 1c shown. When there is a hole or leakage fault in the TSV, the signal passing through the TSV will change.

[0067] In an exemplary embodiment of the present disclosure, a through-silicon via detection circuit is first provided, as Figure 2 shown, the through-silicon via detection circuit includes: a first detection module 100 and a second detection module 200

[0068] The first detection module 100 includes: a first comparison unit 130, a first input unit 110, and a first switch unit 120;

[0069] The first input unit 110 is configured to transmit an input signal to a first input terminal of the first comparison unit 130 under the control of a first clock signal CLK1;

[0070] The first switch unit 120 is configured to transmit the signal of a first node P1 to a second input terminal of the first comparison unit 130 under the control of a first detection control signal CT1, and the first node P1 is connected to a first end of the through-silicon via;

[0071] The second detection module 200 includes: a second input unit 210 and a second switch unit 220;

[0072] The second input unit 210 is configured to transmit the input signal to a second node P2 under the control of a second clock signal CLK2;

[0073] The second switch unit 220 is configured to transmit the signal of the second node P2 to the second end of the through-silicon via under the control of the second detection control signal CT2.

[0074] The first comparison unit 130 receives the signal output by the first input unit 110 and the signal output by the first switch unit 120. Since the signal output by the first switch unit 120 is the signal that passes through the second input unit 210, the second switch unit 220 and the through-silicon via, the signals input to the two input terminals of the first comparison unit 130 are compared. If there is a difference between the signals input to the two input terminals of the first comparison unit 130, it indicates that the through-silicon via has a fault. If there is no difference between the signals input to the two input terminals of the first comparison unit 130, it indicates that the through-silicon via has no fault.

[0075] It should be noted that in the case where there is a difference between the signals at the two input terminals of the first comparison unit 130 described in the embodiments of the present disclosure, this difference can be a range value. That is, when the difference between the signals input to the first input terminal and the second input terminal of the first comparison unit 130 is within a preset range, it can be considered that there is no difference between the signals input to the two input terminals of the first comparison unit 130.

[0076] The through-silicon via detection circuit provided by the embodiments of the present disclosure transmits the input signal to the first input terminal of the first comparison unit 130 through the first input unit 110, transmits the input signal to the second node P2 through the second input unit 210. The second detection control signal CT2 controls the second switch unit 220 to conduct, and the first detection control signal CT1 controls the first switch unit 120 to conduct, and transmits the input signal at the second node P2 to the second end of the first comparison unit 130 through the second switch unit 220, the through-silicon via and the first switch unit 120. That is, the original input signal is input to the first input terminal of the first comparison unit 130, and the input signal that passes through the through-silicon via is input to the second end. By comparing these two signals, if there is a difference between the two signals, it indicates that the through-silicon via has a fault. If there is no difference between the two signals, it indicates that the through-silicon via has no fault. Since the through-silicon via detection circuit provided by the present disclosure has a simple structure and is easy to manufacture, it is suitable for use in mass-produced 3D chips and can reduce production costs.

[0077] Next, each module and unit in the through-silicon via detection circuit provided by the embodiments of the present disclosure will be described in detail.

[0078] As Figure 3 shown, the first input unit 110 may include: a first flip-flop 111, whose input terminal is connected to the input signal, the output terminal is connected to the first input terminal of the first comparison unit 130, and the clock terminal is connected to the first clock signal CLK1 terminal. The first flip-flop 111 responds to the control of the first clock signal CLK1 and outputs the signal at the input terminal to the first end of the first comparison unit 130.

[0079] As Figure 4As shown, the second input unit 210 may include: a second flip-flop 211, with its input terminal connected to the input signal, its output terminal connected to the second node P2, and its clock terminal connected to the second clock signal CLK2 terminal.

[0080] During detection, the second flip-flop 211 responds to the second clock signal CLK2 to transmit the input signal to the second node P2. The first switch unit 120 conducts in response to the first detection control signal CT1, and the second switch unit 220 conducts in response to the second detection control signal CT2, transmitting the signal of the second node P2 to the second input terminal of the first comparison unit 130 via the second switch unit 220, the through-silicon via, and the first switch unit 120. The first flip-flop 111 responds to the second clock signal CLK2 to transmit the input signal to the first input terminal of the first comparator, and determines whether there is a fault in the through-silicon via by comparing the signals at the two input terminals of the first comparison unit 130.

[0081] Wherein, the first detection control signal CT1 and the second detection control signal CT2 may be the same detection control signal or different detection control signals, and the first clock signal CLK1 and the second clock signal CLK2 may be the same clock signal or different clock signals. The embodiments of the present disclosure do not make specific limitations on this.

[0082] The first input unit 110 may further include: a first selector 112, with its first input terminal connected to the input signal, its second input terminal connected to the output terminal of the first comparison unit 130, its control terminal connected to the first selection control signal MUX1 terminal, and its output terminal connected to the input terminal of the first flip-flop 111. The first selector 112 responds to the first selection control signal MUX1 to select to conduct from the first input terminal to the output terminal to transmit the input signal to the input terminal of the first flip-flop 111, or to conduct from the second input terminal to the output terminal to transmit the signal output by the first comparison unit 130 to the input terminal of the first flip-flop 111.

[0083] The first detection module 100 may further include: a third switch unit, with its first end connected to the output terminal of the first flip-flop 111, its second end connected to the first node P1, and its control terminal connected to the first detection control signal. The third switch unit conducts in response to the first detection control signal CT1, transmitting the signal at the output terminal of the first flip-flop 111 to the first node P1.

[0084] The second input unit 210 may further include: a second selector 212, with its first input terminal connected to the input signal, its control terminal connected to the second selection control signal MUX2 terminal, and its output terminal connected to the input terminal of the second flip-flop 211.

[0085] The second selector 212 responds to the second selection control signal MUX2 to select the first input terminal to the output terminal to conduct and transmit the input signal to the input terminal of the second flip-flop 211, or select the second input terminal to the output terminal to conduct and transmit the signal output by the first comparison unit 130 to the input terminal of the second flip-flop 211.

[0086] The second detection module 200 further includes: a fourth switch unit, the first end of which is connected to the second end of the through-silicon via, and the control end of which is connected to the second detection control signal; the fourth switch unit conducts in response to the second detection control signal CT2, and transmits the signal at the second end of the through-silicon via to the first input terminal of the second comparison unit 230.

[0087] The second comparison unit 230, the first input terminal of which is connected to the second end of the fourth switch unit, the second input terminal of which is connected to the second node P2, and the output terminal of which is connected to the second input terminal of the second selector 212.

[0088] In order to detect the through-silicon vias connecting different chip layers, the first detection module 100 can be disposed on the first chip layer, the second detection module 200 can be disposed on the second chip layer, and the first chip layer and the second chip layer are connected by through-silicon vias.

[0089] It should be noted that the first chip layer and the second chip layer described in the embodiments of the present disclosure can be adjacent chip layers to each other, or non-adjacent chip layers. When the first chip layer and the second chip layer are adjacent chip layers, the first detection module 100 and the second detection module 200 are used to detect the TSVs connecting adjacent chip layers. When the first chip layer and the second chip layer are non-adjacent chip layers, at this time, multiple chip layers can be connected by a plurality of TSVs connected end to end, and the first detection module 100 and the second detection module 200 are used to detect the plurality of TSVs connected end to end.

[0090] Preferably, for the convenience of detection, the structures of the first detection module 100 and the second detection module 200 can be the same, and they are both referred to as detection modules, and detection modules can be provided in each chip layer. That is, the detection module includes an input unit, two switch units and a comparison unit. When detecting, the detection combination can be selected according to the detection requirements to detect any one TSV, or any plurality of TSVs connected end to end.

[0091] As Figure 5 shown, a plurality of first detection modules 100 are sequentially provided on the first chip layer, wherein the output terminal of the first flip-flop in the previous first detection module 100 is connected to the input terminal of the next first detection module 100; a plurality of second detection modules 200 are sequentially provided on the second chip layer, wherein the output terminal of the second flip-flop in the previous second detection module 200 is connected to the input terminal of the next second detection module 200.

[0092] Since in practical applications, multiple TSVs are often provided in a chip layer, multiple first detection modules 100 can be provided in the first chip layer, and multiple second detection modules 200 can be provided in the second chip layer. Usually, the number of the first detection modules 100, the number of the second detection modules 200, and the number of the TSVs correspond to each other.

[0093] Preferably, for the convenience of fabrication and control, the structures of the first detection module 100 and the second detection module 200 can be the same. At this time, the first detection module 100 and the second detection module 200 can be collectively referred to as detection modules. Multiple detection modules can be provided in the same chip layer. The multiple detection modules are arranged in sequence, and the output end of the input unit of the previous detection module is connected to the input end of the next detection module. Multiple detection modules are respectively provided in multiple chip layers, and the multiple detection modules are respectively connected to the corresponding TSVs. A third comparison unit is provided in each chip layer, and the output ends of the multiple first comparison units in this chip layer are respectively connected to the input end of the third comparison unit. That is to say, the same circuit as shown in Figure 5 or Figure 6 is provided in each chip layer, and all or part of the circuit is retrieved for detection according to actual needs during detection.

[0094] During detection, under the control of the second clock signal CLK2, the input signal is sequentially input into multiple second input units 210 provided on the second chip layer, and then multiple second switch units 220 are turned on through the second detection control signal CT2. Multiple first switch units 120 are turned on through the first detection control signal CT1, and the input signal is respectively transmitted to the second ends of multiple first comparison units 130 via the second switch units 220, the TSVs, and the first switch units 120. After the input signal is sequentially input into multiple first input units 110 under the control of the first clock signal CLK1, it is transmitted to the first ends of multiple first comparison units 130.

[0095] Multiple first flip-flops 111 are sequentially connected to form a scan chain. When multiple first units output comparison results, the comparison results are input into the corresponding flip-flops through the first selection control signal MUX1. The first clock signal CLK1 controls the multiple flip-flops to sequentially transfer the comparison results to the next flip-flop, and finally the comparison results are sequentially output through the flip-flop at the end of the scan chain. Whether multiple TSVs are faulty is judged based on the comparison results and the order of the comparison results.

[0096] Further, in order to quickly determine whether there is a faulty TSV among multiple TSVs, the through-silicon via detection circuit may further include: a third comparison unit 300, and the output ends of the multiple first comparison units 130 are respectively connected to the input end of the third comparison unit 300. If there are differences in the results output by the third comparison unit 300 when comparing the outputs of the multiple first comparison units 130, there is a faulty TSV among the multiple TSVs.

[0097] Among them, each comparison unit in the embodiments of the present disclosure may be an exclusive OR gate. For example, the first comparison unit 130 and the second comparison unit 230 may be two-input exclusive OR gates, and the third comparison unit 300 may be a multi-input exclusive OR gate, and the number of its input ends is determined by the number of TSVs. When the two-input exclusive OR gate of the first comparison unit 130 outputs 1, the corresponding TSV is faulty. If the two-input exclusive OR gate of the first comparison unit 130 outputs 0, the corresponding TSV is faultless. If the multi-input AND gate of the third comparison unit 300 outputs 1, there is a faulty TSV among the multiple TSVs. If its output is 0, in one case, there is no faulty TSV among the multiple TSVs, and in another case, all the multiple TSVs are faulty TSVs. At this time, it can be judged by the data output from the output end of the scan chain. When its output is 0, all the multiple TSVs are faultless, and vice versa, all the multiple TSVs are faulty TSVs. However, in practical applications, the probability that all the multiple TSVs are faulty TSVs is extremely small.

[0098] In a feasible implementation manner provided by the present disclosure, the first switch unit 120 includes a first transistor T1, and T1 may be an NMOS (N-type metal oxide semiconductor transistor). The second switch unit 220 includes a second transistor T2, and T2 may be a PMOS (P-type metal oxide semiconductor transistor). When the through-silicon via detection circuit further includes a third switch unit and a fourth switch unit, the third switch unit includes a third transistor T3, and T3 may be an NMOS, and the fourth switch unit includes a fourth transistor T4, and T4 may be a PMOS. At this time, the first switch unit 120 and the third switch unit can be controlled to conduct at different times through the first detection control signal CT1. The second switch unit 220 and the fourth switch unit are controlled to conduct at different times through the second detection control signal CT2.

[0099] Alternatively, T1 may be a PMOS, T2 may be an NMOS, T3 may be a PMOS, and T4 may be an NMOS. At this time, T1 and T3 can be controlled to conduct at different times through the first detection control signal CT1. T2 and T4 are controlled to conduct at different times through the second detection control signal CT2.

[0100] Among them, for each transistor, the control terminal can be the gate of the transistor, the first terminal can be the source of the transistor, and the second terminal can be the drain of the transistor; or the first terminal can be the drain of the transistor and the second terminal can be the source of the transistor. The embodiments of the present disclosure do not make specific limitations on this.

[0101] In another feasible embodiment provided by the present disclosure, as Figure 6 shown, both the first switch unit 120 and the second switch unit 220 are CMOS transmission gates TG. When the through-silicon via detection circuit further includes a third switch unit and a fourth switch unit, the third switch unit and the fourth switch unit can also be CMOS transmission gates TG.

[0102] The through-silicon via detection circuit provided by the embodiments of the present disclosure can set the first detection module 100 and the second detection module 200 to have the same structure in application, and determine the number of detection modules according to the number of TSVs in multiple chip layers. Since the structures of the detection modules are the same, it is convenient to manufacture, which is beneficial to the application in large-scale integrated circuits, and can call the detection modules of different layers according to the detection control signal to implement the detection of one or more TSVs.

[0103] In practical applications, the TSV redundancy mechanism can be combined to set spare TSVs in each chip layer. If the through-silicon via detection circuit detects a faulty TSV, the spare TSV can be enabled to replace the faulty TSV.

[0104] The exemplary embodiment of the present disclosure further provides a through-silicon via detection method for the above-mentioned through-silicon via detection circuit, including the following steps:

[0105] Step S710: Input the input signal into the second input unit 210 through the second clock signal CLK2 and transmit it to the second node P2;

[0106] Step S720: Input the input signal into the first input unit 110 through the first clock signal CLK1 and transmit it to the first input terminal of the first comparison unit 130;

[0107] Step S730: Turn on the first switch unit 120 through the first detection control signal CT1, and turn on the second switch unit 220 through the second detection control signal CT2. The input signal is transmitted to the second input terminal of the first comparison unit 130 through the second switch unit 220, the through-silicon via, and the first switch unit 120;

[0108] Step S740: Compare the signals input to the first input terminal and the second input terminal of the first comparison unit 130 and output a comparison result.

[0109] Further, when multiple first detection modules 100 are sequentially arranged on the first chip layer, wherein the output end of the previous first detection module 100 is connected to the input end of the next first detection module 100; and multiple second detection modules 200 are sequentially arranged on the second chip layer, wherein the output end of the previous second detection module 200 is connected to the input end of the next second detection module 200, the silicon through-hole detection method includes:

[0110] Step S810: Sequentially input the input signal into multiple second input units 210 through the second clock signal CLK2, and transmit it to the corresponding second node P2;

[0111] Step S820: Sequentially input the input signal into multiple first input units 110 through the first clock signal CLK1, and transmit it to the first input end of the corresponding first comparison unit 130;

[0112] Step S830: Turn on multiple first switch units 120 through the first detection control signal CT1, and turn on multiple second switch units 220 through the second detection control signal CT2. The input signal is respectively transmitted to the second input end of the second comparison unit 230 through the second switch unit 220 connected to a silicon through-hole, the silicon through-hole, and the first switch unit 120;

[0113] Step S840: Multiple second comparison units 230 respectively compare the signals input to their first input end and second input end, and output comparison results.

[0114] Further, when the silicon through-hole detection circuit further includes a third comparison unit 300, the silicon through-hole detection method further includes:

[0115] Step S850: The output signals of multiple first comparison units 130 are respectively input to the third comparison unit 300. The third comparison unit 300 compares the output signals of multiple first comparison units 130, and outputs comparison results.

[0116] Details of the silicon through-hole detection method have been described in detail in the above silicon through-hole detection circuit, and will not be elaborated here.

[0117] The exemplary embodiment of the present disclosure further provides an integrated circuit, particularly a 3D integrated circuit, including the above silicon through-hole detection circuit. Of course, in this integrated circuit, components such as a PCB board, a capacitor, or a resistor may also be included. Since they are all prior arts, they will not be elaborated in the embodiments of the present disclosure.

[0118] It should be noted that although the steps of the methods in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0119] Those skilled in the art can understand that various aspects of the present invention can be implemented as a system, a method, or a program product. Therefore, various aspects of the present invention can be specifically implemented in the following forms, namely: a complete hardware embodiment, a complete software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects, which can be collectively referred to as "circuits", "modules", or "systems" here.

[0120] In addition, the above-mentioned accompanying drawings are only schematic illustrations of the processes included in the methods according to the exemplary embodiments of the present invention, rather than for the purpose of limitation. It is easy to understand that the processes shown in the above-mentioned accompanying drawings do not indicate or limit the time sequence of these processes. Additionally, it is also easy to understand that these processes can be executed synchronously or asynchronously, for example, in multiple modules.

[0121] After considering the specification and practicing the invention disclosed herein, those skilled in the art will readily conceive of other embodiments of the present disclosure. This application is intended to cover any variations, uses, or adaptations of the present disclosure, which follow the general principles of the present disclosure and include well-known knowledge or conventional technical means in the technical field not disclosed in the present disclosure. The specification and the embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the claims.

[0122] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

Claims

1. A through - silicon via detection circuit, characterized in that, it includes a first detection module and a second detection module with the same structure, where: The first detection module includes: A first comparison unit; A first input unit, configured to transmit an input signal to a first input terminal of the first comparison unit under the control of a first clock signal; A first switch unit, configured to transmit a signal of a first node to a second input terminal of the first comparison unit under the control of a first detection control signal, and the first node is connected to a first end of the through - silicon via; The second detection module includes: A second input unit, configured to transmit the input signal to a second node under the control of a second clock signal; A second switch unit, configured to transmit a signal of the second node to a second end of the through - silicon via under the control of a second detection control signal.

2. The through - silicon via detection circuit according to claim 1, characterized in that, the first input unit includes: A first flip - flop, with an input terminal connected to the input signal, an output terminal connected to the first input terminal of the first comparison unit, and a clock terminal connected to the first clock signal.

3. The through - silicon via detection circuit according to claim 2, characterized in that, the first input unit further includes: A first selector, with a first input terminal connected to the input signal, a second input terminal connected to the output terminal of the first comparison unit, a control terminal connected to a first selection control signal, and an output terminal connected to the input terminal of the first flip - flop.

4. The through - silicon via detection circuit according to claim 3, characterized in that, the first detection module further includes: A third switch unit, with a first end connected to the output terminal of the first flip - flop, a second end connected to the first node, and a control terminal connected to the first detection control signal.

5. The through - silicon via detection circuit according to claim 1, characterized in that, the second input unit includes: A second flip - flop, with an input terminal connected to the input signal, an output terminal connected to the second node, and a clock terminal connected to the second clock signal.

6. The through - silicon via detection circuit according to claim 5, characterized in that, the second input unit further includes: A second selector, with a first input terminal connected to the input signal, a control terminal connected to a second selection control signal, and an output terminal connected to the input terminal of the second flip - flop.

7. The through - silicon via detection circuit according to claim 6, characterized in that, the second detection module further includes: A fourth switch unit, with a first end connected to the second end of the through - silicon via and a control terminal connected to the second detection control signal; A second comparison unit, with a first input terminal connected to a second end of the fourth switch unit, a second input terminal connected to the second node, and an output terminal connected to a second input terminal of the second selector.

8. The through - silicon via detection circuit according to claim 7, characterized in that, the first detection module is disposed on a first chip layer, the second detection module is disposed on a second chip layer, and the first chip layer and the second chip layer are connected through the through - silicon via.

9. The through - silicon via detection circuit according to claim 8, characterized in that, a plurality of first detection modules are sequentially disposed on the first chip layer, where the output terminal of the first flip - flop in the previous first detection module is connected to the input terminal of the next first detection module; A plurality of second detection modules are sequentially arranged on the second chip layer, wherein the output end of the second flip-flop in the previous second detection module is connected to the input end of the next second detection module.

10. The silicon via detection circuit according to claim 9, wherein, the silicon via detection circuit further includes: a third comparison unit, and the output ends of the plurality of first comparison units are respectively connected to the input end of the third comparison unit.

11. The silicon via detection circuit according to claim 8, wherein, the first chip layer and the second chip layer are non-adjacent chip layers, and a multi-layer chip layer including the first chip layer and the second chip layer and the chip layers therebetween is connected by a plurality of silicon vias connected end to end, and the first detection module and the second detection module are used to detect the plurality of silicon vias connected end to end.

12. The silicon via detection circuit according to claim 11, wherein, detection modules having the same structure as the first detection module and the second detection module are provided in each chip layer of the multi-layer chip layer.

13. The silicon via detection circuit according to any one of claims 1-12, wherein, each comparison unit is an exclusive OR gate.

14. The silicon via detection circuit according to claim 1, wherein: the first switch unit is an N-type metal oxide semiconductor transistor, and the second switch unit is a P-type metal oxide semiconductor transistor; alternatively, the first switch unit is a P-type metal oxide semiconductor transistor, and the second switch unit is an N-type metal oxide semiconductor transistor.

15. The silicon via detection circuit according to claim 1, wherein, the first switch unit and the second switch unit are both complementary metal oxide semiconductor transmission gates.

16. A silicon via detection method for the silicon via detection circuit according to any one of claims 1-15, wherein, it includes: inputting an input signal into a second input unit through a second clock signal and transmitting it to a second node; inputting the input signal into a first input unit through a first clock signal and transmitting it to a first input end of a first comparison unit; conducting the first switch unit through a first detection control signal and conducting the second switch unit through a second detection control signal, and the input signal is transmitted to a second input end of the first comparison unit through the second switch unit, the silicon via and the first switch unit; comparing the signals input to the first input end and the second input end of the first comparison unit and outputting a comparison result.

17. The silicon via detection method according to claim 16, for the silicon via detection circuit according to claim 9, wherein, it includes: sequentially inputting the input signal into the second input unit through the second clock signal and transmitting it to the corresponding second node; sequentially inputting the input signal into the first input unit through the first clock signal and transmitting it to the first input end of the corresponding first comparison unit; A plurality of first switch units are turned on by a first detection control signal, and a plurality of second switch units are turned on by a second detection control signal. An input signal is transmitted to a second input terminal of a first comparison unit through a second switch unit connected to a through-silicon via, the through-silicon via, and a first switch unit respectively. A plurality of first comparison units respectively compare signals input to their first input terminals and second input terminals, and output comparison results.

18. The through-silicon via detection method according to claim 17, characterized in that the through-silicon via detection circuit further includes a third comparison unit, and the through-silicon via detection method further includes: Output signals of a plurality of first comparison units are respectively input to the third comparison unit, and the third comparison unit compares the output signals of the plurality of first comparison units and outputs a comparison result.

19. An integrated circuit, characterized in that it includes the through-silicon via detection circuit according to any one of claims 1-15.

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