Vertical memory device with improved electrical characteristics and method of operating the same

Abstract

The present disclosure provides a vertical memory device with improved electrical characteristics and an operating method thereof. A method for operating a memory device, wherein the memory device comprises: a substrate; at least one dummy word line located above the substrate; a plurality of word lines located above the dummy word line; and a plurality of vertical holes, the plurality of vertical holes extending through the at least one dummy word line and the plurality of word lines in a direction perpendicular to the substrate and being classified into channel holes and dummy holes, each of the channel holes being connected to a bit line; the method comprises: performing an erase operation on a dummy cell formed as the dummy word line and the dummy hole; verifying the erase operation; and performing a programming operation on at least one dummy cell among the plurality of dummy cells, so that the at least one dummy cell has a higher threshold voltage than a main cell formed as the dummy word line and the channel hole.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2018-0139408, filed on November 13, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] Example embodiments of the inventive concepts relate to a vertical memory device and / or a method of operating the same. For example, at least some example embodiments relate to a vertical memory device having improved electrical characteristics and / or a method of operating the same. Background Art

[0004] Recently, as information communication devices become multifunctional, memory devices with larger capacity and higher integration are required. However, as the size of memory cells for higher integration decreases, the operation circuits and / or wiring structures included in the memory devices for operation and electrical connection of the memory devices may become more complicated. Therefore, there is a demand for memory devices having excellent electrical characteristics and data reliability while exhibiting increased integration. Summary of the invention

[0005] Example embodiments of the inventive concept provide a vertical memory device with improved electrical characteristics and / or a method of operating the vertical memory device. For example, example embodiments of the inventive concept provide a memory device in which a dummy hole is electrically isolated from a substrate by programming a dummy cell, and / or a method of operating the memory device.

[0006] At least some example embodiments of the present inventive concept relate to a method of operating a memory device. The memory device includes a substrate; at least one dummy word line located above the substrate; a plurality of word lines located above the at least one dummy word line; and a plurality of vertical holes extending through the at least one dummy word line and the plurality of word lines in a direction perpendicular to the substrate, the plurality of vertical holes including channel holes and dummy holes, the channel holes being vertical holes connected to bit lines among the plurality of vertical holes. The method includes: performing an erase operation on a plurality of dummy cells, each of the plurality of dummy cells including one of the at least one dummy word line and one of the dummy holes; verifying the erase operation; and performing a programming operation on at least one of the plurality of dummy cells so that the threshold voltage of the plurality of dummy cells is higher than the threshold voltage of the main cell, each of the main cells including one of the at least one dummy word line and one of the channel holes.

[0007] Other example embodiments of the present inventive concept relate to a method of operating a memory device. The memory device includes a substrate, a first pseudo word line located above the substrate, a second pseudo word line located above the first pseudo word line, a plurality of word lines located above the second pseudo word line, and a plurality of vertical holes extending through the first pseudo word line, the second pseudo word line, and the plurality of word lines in a direction perpendicular to the substrate, each of the plurality of vertical holes including one of the first vertical hole and the second vertical hole. The method includes: performing an erase operation on a first pseudo cell and a second pseudo cell, the first pseudo cell including one of the first vertical holes and the first pseudo word line, and the second pseudo cell including one of the second vertical holes and the second pseudo word line; verifying the erase operation; in response to verifying that the erase operation is complete, controlling a threshold voltage of each of the first pseudo cell and a main cell, the main cells each including one of the second vertical holes and the first pseudo word line; and programming the second pseudo cell.

[0008] Other example embodiments of the present inventive concept relate to a nonvolatile memory device, comprising: a substrate; a plurality of gate conductive layers, comprising at least one dummy word line located above the substrate and a plurality of word lines located above the at least one dummy word line; a plurality of bit lines located above the plurality of gate conductive layers, the plurality of bit lines being spaced apart from each other in a first direction and extending in a second direction, the second direction being perpendicular to the first direction; a plurality of vertical holes extending through the plurality of gate conductive layers in a direction perpendicular to the substrate, the plurality of vertical holes comprising channel holes and dummy holes, the channel holes being vertical holes in the plurality of vertical holes connected to corresponding bit lines in the plurality of bit lines; dummy cells, each of the dummy cells comprising one of the at least one dummy word line and one of the dummy holes; a main cell, each of the main cells comprising one of the plurality of word lines and one of the channel holes; and a row decoder configured to apply a voltage to each of the plurality of gate conductive layers so that when a turn-on voltage associated with the main cell is applied to the at least one dummy word line, the dummy cell is configured to be turned off. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the inventive concept will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a block diagram illustrating a memory system according to an example embodiment;

[0011] Figure 2 is a block diagram illustrating in detail a memory device according to an example embodiment;

[0012] Figure 3 Yes Description Figure 2A perspective view of an implementation example of a first memory block in the memory blocks;

[0013] Figure 4 It is shown Figure 2 a circuit diagram of an equivalent circuit of a first memory block in the memory blocks;

[0014] Figure 5A shows a top view of a first memory block according to an example embodiment, and Figure 5B Shown along Figure 5A The cross-sectional structure taken along the line V-V';

[0015] FIG. 6A to FIG. 6C is a diagram illustrating a method of operating a memory device;

[0016] Figure 7 is a flowchart illustrating a method of operating a memory device according to an example embodiment;

[0017] FIG. 8A to FIG. 8C is a diagram illustrating a method of operating a memory device according to another example embodiment;

[0018] Fig. 9 shows a distribution of a threshold voltage for each of a main cell and a dummy cell after performing a method of operating a memory device according to example embodiments; and

[0019] Fig.10 is a block diagram illustrating an example in which a memory device according to example embodiments is applied to a solid state drive (SSD) system. DETAILED DESCRIPTION

[0020] Hereinafter, example embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0021] Figure 1 is a block diagram illustrating a memory system according to example embodiments.

[0022] refer to Figure 1 , the memory system 1 may include a memory controller 10 and a memory device 100 , and the memory device 100 may include a memory cell array 110 and a control logic 120 .

[0023] The memory device 100 may include a non-volatile memory device. In some example embodiments, the memory system 1 may be implemented as an internal memory embedded in an electronic device, and may include, for example, a universal flash memory (UFS) memory device, an embedded multimedia card (eMMC), or a solid-state drive (SSD). In other example embodiments, the memory system 1 may be implemented as an external memory detachably attached to an electronic device, and may include, for example, a UFS memory card, a compact flash memory (CF), a secure digital card (SD), a micro secure digital card (Micro-SD), a mini secure digital card (Mini-SD), an extreme digital card (xD), or a memory stick.

[0024] The memory controller 10 may control the memory device 100 so that data stored in the memory device 100 is read in response to a read request from the host, or data is programmed into the memory device 100 in response to a write request from the host. For example, the memory controller 10 may control a program operation, a read operation, and / or an erase operation of the memory device 100 by providing an address ADDR, a command CMD, and a control signal CTRL to the memory device 100. In addition, data DATA to be programmed and / or read data DATA may be transmitted and received between the memory controller 10 and the memory device 100.

[0025] For example, the memory device 100 may include a single memory chip. As another example, the memory device 100 may include multiple memory chips. One memory chip may include a single die or multiple die. One die may include a single plane or multiple planes. One plane may include multiple memory blocks, each memory block may include multiple pages, and each page may include multiple sectors.

[0026] In addition, the memory cell array 110 may include a plurality of pseudo cells and a plurality of main cells. For example, the memory cell array 110 may include: at least one pseudo word line and a plurality of word lines, which are arranged on the semiconductor substrate in the order listed; and a plurality of vertical holes, which extend through the pseudo word lines and the word lines in a direction perpendicular to the semiconductor substrate. The plurality of vertical holes may be classified into channel holes connected to the bit lines and pseudo holes other than the channel holes. For example, each pseudo cell may be formed as a pseudo word line and each pseudo hole. In addition, each main cell may be formed as a pseudo word line and a channel hole.

[0027] The control logic 120 may receive a command CMD and an address ADDR from the memory controller 10, and may control an erase operation and / or a program operation for the dummy cell based on the command CMD and the address ADDR. In an example embodiment, the control logic 120 may control an erase operation and an erase verification operation for the dummy cell based on the command CMD and the address ADDR. In addition, the control logic 120 may control a program operation to be performed on at least one of the dummy cells so that the at least one dummy cell has a threshold voltage higher than the threshold voltage of the main cell. This will be described in detail below.

[0028] According to an example embodiment of the inventive concept, the control logic 120 can program the dummy cell so as to electrically isolate the semiconductor substrate from the dummy hole that is not connected to the bit line. Therefore, the memory device 100 can reduce the load caused by the dummy hole during the memory operation (e.g., data reading) and thus have improved electrical characteristics.

[0029] Figure 2 is a block diagram illustrating in detail a memory device according to an example embodiment. For example, Figure 2 Can explain Figure 1 An implementation example of a memory device 100 is shown.

[0030] refer to Figure 2 , the memory device 100 may include a memory cell array 110, a control logic 120, a voltage generator 130, a row decoder 140, and a page buffer 150. Figure 2 Although not shown in the figure, the memory device 100 may further include other various components related to memory operations, such as a data input / output circuit or an input / output interface.

[0031] The memory cell array 110 may include a plurality of memory cells and may be connected to a word line WL, a dummy word line DWL, a string selection line SSL, a ground selection line GSL, a common source line CSL (eg, Figure 3 The memory cell array 110 may be connected to the row decoder 140 via word lines WL, dummy word lines DWL, string selection lines SSL, and ground selection lines GSL, and may be connected to the page buffer 150 via bit lines BL.

[0032] For example, each of the plurality of memory cells included in the memory cell array 110 may include a nonvolatile memory cell that maintains stored data even if power supplied to the memory cell is turned off. Specifically, when each memory cell is a nonvolatile memory cell, the memory device 100 may include an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), a ferroelectric random access memory (FRAM), and the like. Hereinafter, although an example embodiment of the inventive concept will be described with reference to a case where the plurality of memory cells are NAND flash memory cells, it should be understood that the example embodiments of the inventive concept are not limited thereto.

[0033] The memory cell array 110 may include a plurality of memory blocks BLK1 to BLKz, and each of the memory blocks BLK1 to BLKz may have a planar structure or a three-dimensional structure. The memory cell array 110 may include at least one of a single-level cell block including a single-level cell (SLC), a multi-level cell block including a multi-level cell (MLC), a three-level cell block including a three-level cell (TLC), and a four-level cell block including a quad-level cell (QLC). For example, some of the plurality of memory blocks BLK1 to BLKz may be single-level cell blocks, while others may be multi-level cell blocks, three-level cell blocks, or four-level cell blocks.

[0034] The control logic 120 may output various internal control signals for programming data into or reading data from the memory cell array 110 based on the command CMD, the address ADDR, and the control signal CTRL received from the memory controller 10. For example, the control logic 120 may output a voltage control signal CTRL_vol for controlling the levels of various voltages generated by the voltage generator 130. The control logic 120 may provide a row address X-ADDR to the row decoder 140 and a column address Y-ADDR to the page buffer 150.

[0035] The voltage generator 130 may generate various voltages used in the memory device 100. For example, the voltage generator 130 may generate a word line voltage VWL, a string selection line voltage VSSL, and a ground selection line voltage VGSL. In addition, the voltage generator 130 may also generate a dummy word line voltage VWL.

[0036] The row decoder 140 may select at least one of the word lines of the memory block selected in response to the row address X-ADDR. During a programming operation, the row decoder 140 may provide a program voltage as a word line voltage VWL to the word line of the memory cell selected in response to the row address X-ADDR, and may provide a pass voltage as the word line voltage VWL to the word line of the non-selected memory cell.

[0037] The page buffer 150 may operate as a write driver or a sense amplifier. During a program operation, the page buffer 150 may operate as a write driver and thus apply a voltage to the bit line BL according to the data DATA stored in the memory cell array 110. During a read operation, the page buffer 150 may operate as a sense amplifier and thus read out the data DATA stored in the memory cell array 110.

[0038] The control logic 120 may control the voltage generator 130, the row decoder 140, and the page buffer 150 to perform an erase operation or a program operation on the dummy cell. For example, during a program operation for the dummy cell, the control logic 120 may control the voltage generator 130 and the row decoder 140 so that a program voltage is applied to the dummy word line DWL for (i.e., for) a desired (or alternatively, a preset) period of time.

[0039] In an example embodiment, the control logic 120 may control the programming operation of the dummy cells so that the threshold voltage of each dummy cell has a higher level than the threshold voltage of each main cell. In other words, the control logic 120 may control the programming operation of the dummy cells so that the threshold voltage of each dummy cell has a higher level than the turn-on voltage of each main cell. This will be described in detail below.

[0040] Figure 3 Yes Description Figure 2 A perspective view of an implementation example of a first memory block among memory blocks.

[0041] refer to Figure 3 , the first memory block BLK1 may be formed in a direction perpendicular to the substrate SUB. Figure 3 1 and 2 , the first memory block BLK1 is shown to include two selection lines GSL and SSL, one dummy word line DWL, seven word lines WL1 to WL7 , and three bit lines BL1 to BL3 , but the number of each component included in the first memory block BLK1 may be actually greater or less than the above number.

[0042] The substrate SUB may include a polysilicon layer doped to a first conductivity type (e.g., p-type). The substrate SUB may include a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, a germanium substrate, a germanium-on-insulator (GOI) substrate, a silicon-germanium substrate, or a substrate of an epitaxial thin film obtained by selective epitaxial growth (SEG). The substrate SUB may include a semiconductor material, such as at least one selected from the group consisting of silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium gallium arsenide (InGaAs), and aluminum gallium arsenide (AlGaAs).

[0043] In the substrate SUB, a common source line CSL extending in the first direction on the substrate SUB and doped with a second conductive type (e.g., n-type) impurity may be provided. Over a region of the substrate SUB between two adjacent common source lines CSL, a plurality of insulating films IL extending in the first direction may be sequentially arranged along a third direction, and the plurality of insulating films IL may be spaced apart from each other by a specific distance in the third direction. For example, each of the plurality of insulating films IL may include an insulating material such as silicon oxide.

[0044] On the region of the substrate SUB between two adjacent common source lines CSL, a plurality of vertical holes H each passing through a plurality of insulating films IL in the third direction may be sequentially arranged in the first direction. For example, the plurality of vertical holes H may contact the substrate SUB through the plurality of insulating films IL. Specifically, the surface layer S of each vertical hole H may include a silicon material doped with a first conductivity type and may serve as a channel region. In addition, the inner layer I of each vertical hole H may include an insulating material (e.g., silicon oxide or an air gap).

[0045] In the region between two adjacent common source lines CSL, the charge storage layer CS may be arranged along the exposed surfaces of the insulating film IL, the vertical hole H, and the substrate SUB. The charge storage layer CS may include a gate insulating layer (also referred to as the term "tunnel insulating layer"), a charge trapping layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In addition, in the region between two adjacent common source lines CSL, gate electrodes GE such as selection lines GSL and SSL, dummy word lines DWL, and word lines WL1 to WL7 may be arranged on the exposed surface of the charge storage layer CS.

[0046] The drain or drain contact DR may be respectively arranged on the vertical hole H. For example, the drain or drain contact DR may include a silicon material doped with impurities of the second conductivity type. The bit lines BL1 to BL3 extending in the second direction may be arranged on the drain contact DR to be spaced apart from each other by a certain distance in the first direction.

[0047] Figure 4 It is shown Figure 2 A circuit diagram of an equivalent circuit of a first memory block among memory blocks.

[0048] refer to Figure 4 , the first memory block BLK1 may be a vertical structure NAND flash memory, and Figure 2 Each of the memory blocks BLK1 to BLKz shown in FIG. Figure 4 The first memory block BLK1 may include a plurality of NAND cell strings NS11 to NS33, a pseudo word line DWL1, a plurality of word lines WL1 to WL7, a plurality of bit lines BL1 to BL3, a plurality of ground selection lines GSL1 to GSL3, a plurality of string selection lines SSL1 to SSL3, and a common source line CSL. Here, the number of NAND cell strings, the number of pseudo word lines, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may vary differently with each example embodiment.

[0049] NAND cell string NS11, NAND cell string NS21 and NAND cell string NS31 are arranged between the first bit line BL1 and the common source line CSL, NAND cell string NS12, NAND cell string NS22 and NAND cell string NS32 are arranged between the second bit line BL2 and the common source line CSL, and NAND cell string NS13, NAND cell string NS23 and NAND cell string NS33 are arranged between the third bit line BL3 and the common source line CSL. Each NAND cell string (e.g., NS11) may include a string selection transistor SST, a plurality of memory cells MC1 to MC8 and a ground selection transistor GST, which are connected in series in the order listed. For example, the first memory cell MC1 may be connected to the pseudo word line DWL1 and may be referred to as a "master cell".

[0050] Each NAND cell string connected to one bit line in common may constitute a column. For example, NAND cell string NS11, NAND cell string NS21, and NAND cell string NS31 connected to the first bit line BL1 in common may correspond to the first column, NAND cell string NS12, NAND cell string NS22, and NAND cell string NS32 connected to the second bit line BL2 in common may correspond to the second column, and NAND cell string NS13, NAND cell string NS23, and NAND cell string NS33 connected to the third bit line BL3 in common may correspond to the third column.

[0051] The NAND cell strings connected to one string selection line may constitute a row. For example, NAND cell strings NS11, NS12, and NS13 connected to the first string selection line SSL1 may correspond to the first row, NAND cell strings NS21, NS22, and NS23 connected to the second string selection line SSL2 may correspond to the second row, and NAND cell strings NS31, NS32, and NS33 connected to the third string selection line SSL3 may correspond to the third row.

[0052] The string selection transistor SST may be connected to a corresponding string selection line (e.g., one of SSL1 to SSL3). Each of the plurality of memory cells MC1 to MC8 may be connected to a corresponding word line (e.g., one of WL1 to WL8). The ground selection transistor GST may be connected to a corresponding ground selection line (e.g., one of GSL1 to GSL3), and the string selection transistor SST may be connected to a corresponding bit line (e.g., one of BL1 to BL3). The ground selection transistor GST may be connected to a common source line CSL.

[0053] In the present example embodiment, word lines (e.g., WL1) at the same height are generally connected to each other, string selection lines SSL1 to SSL3 are isolated from each other, and ground selection lines GSL1 to GSL3 are also isolated from each other. For example, when memory cells connected to the first word line WL1 and included in NAND cell strings NS11, NAND cell strings NS12, and NAND cell strings NS13 corresponding to the first column are programmed, the first word line WL1 and the first string selection line SSL1 are selected. However, example embodiments of the inventive concept are not limited thereto, and in another example embodiment, the ground selection lines GSL1 to GSL3 may be commonly connected to each other.

[0054] Figure 5A shows a top view of a first memory block according to an example embodiment, and Figure 5B Shown along Figure 5A The cross-sectional structure is taken along the line V-V'.

[0055] refer to Figure 5A and Figure 5B, the memory block BLK1 may include word line cutting regions WLC spaced apart from each other in the first direction and extending in the second direction. In addition, the memory block BLK1 may include: a plurality of vertical holes (e.g., H11, H31, DH1, H61, and H81) arranged between the word line cutting regions WLC in the first direction and the second direction; and bit lines BL1 to BL8 extending in the second direction and spaced apart from each other in the first direction.

[0056] In example embodiments, the vertical holes may be classified into channel holes connected to the bit lines and pseudo holes DH other than the channel holes. As an example, each vertical hole connected to the first bit line BL1 is a channel hole (e.g., H11), and a memory cell formed as the channel hole H11 may perform a data storage function. On the other hand, unlike the channel holes, the pseudo holes DH are vertical holes that are not connected to the bit lines BL1 to BL8, and a memory cell formed as the pseudo holes DH may not perform a data storage function.

[0057] refer to Figure 5B , a ground selection line GSL, a first dummy word line DWL1, and a plurality of word lines WL1 to WL6 may be disposed over the substrate SUB. An insulating film IL may be sequentially disposed between the substrate SUB, the ground selection line GSL, the first dummy word line DWL1, and the word lines WL1 to WL6. In addition, the channel holes H11, H31, H61, and H81 and the dummy holes DH1 may extend in a third direction to pass through the insulating film IL, the first dummy word line DWL1, the word lines WL1 to WL6, and the string selection line SSL.

[0058] Each of the channel hole H11, the channel hole H31, the channel hole H61, and the channel hole H81 and the first dummy word line DWL1 may form a main cell. For example, the first channel hole H11 and the first dummy word line DWL1 may form the first main cell MC11 and the first main cell MC12, the third channel hole H31 and the first dummy word line DWL1 may form the second main cell MC21 and the second main cell MC22, the sixth channel hole H61 and the first dummy word line DWL1 may form the sixth main cell MC61 and the sixth main cell MC62, and the eighth channel hole H81 and the first dummy word line DWL1 may form the eighth main cell MC81 and the eighth main cell MC82. In addition, the dummy hole DH1 and the first dummy word line DWL1 may form the dummy cell DC11 and the dummy cell DC12.

[0059] In an example embodiment, each of the dummy cells DC11 and DC12 may be programmed to have a higher threshold voltage than the main cells MC11 to MC82. Alternatively, each of the dummy cells DC11 and DC12 may be programmed to have a threshold voltage having a higher level than the turn-on voltage of the main cells MC11 to MC82. As an example, for a desired (or alternatively, preset) time period for performing a programming operation for the dummy cells DC11 and DC12, a prohibition voltage may be applied to the bit lines BL1, BL3, BL6, and BL8 and a voltage having a level sufficient to cause Fowler-Nordheim (FN) tunneling from the surface layer DS1 may be applied to the first dummy word line DWL1. Therefore, during a memory operation such as a read of the memory device 100, when the dummy cells DC11 and DC12 are turned off, the dummy hole DH1 may be electrically isolated from the substrate SUB.

[0060] FIG. 6A to FIG. 6C is a diagram showing a method of operating a memory device. Specifically, Fig. 6A To illustrate a flow chart of a method of operating a memory device, Figure 6B Shown in Fig. 6A A table of voltage conditions used during an erase operation, and Figure 6C A timing diagram showing the voltage applied to each line during dummy cell programming. Figure 5B About FIG. 6A to FIG. 6C Description.

[0061] refer to Fig. 6A In operation S10, the memory device 100 may perform an erase operation on the dummy cells DC11 and DC12. Figure 6B During the erase operation for the dummy cells DC11 and DC12, the string selection line SSL may be floated and the word line erase voltage Vwe may be applied to the first dummy word line DWL1. The ground selection line GSL may be floated and the erase voltage V_ERS may be applied to the substrate SUB.

[0062] The substrate SUB and the surface layer DS1 may include silicon materials having the same conductivity. Therefore, the erase voltage V_ERS applied to the substrate SUB may be transferred to the surface layer DS1. For example, the erase voltage V_ERS may be higher than the word line erase voltage Vwe. Since the ground selection line GSL and the string selection line SSL are in a floating state, when the voltage of the surface layer DS1 changes, the ground selection line GSL and the string selection line SSL may be affected by coupling. That is, when the voltage of the surface layer DS1 increases to the erase voltage V_ERS, the voltages of the ground selection line GSL and the string selection line SSL may also increase. Therefore, the ground selection transistor and the string selection transistor may be prevented from being erased.

[0063] For example, the word line erase voltage Vwe applied to the first dummy word line DWL1 may be lower than the erase voltage V_ERS and may be a ground voltage. Due to the voltage difference between the surface layer DS1 and the first dummy word line DWL1, FN tunneling may occur in the dummy cells DC11 and DC12, and thus, the dummy cells DC11 and DC12 may be erased.

[0064] Next, in operation S20, the memory device 100 may perform erase verification on the dummy cells DC11 and DC12, and determine whether the erase verification passes. For example, when the memory device 100 determines that the erase of the dummy cells DC11 and DC12 is not completed, the memory device 100 may perform an erase operation on the dummy cells DC11 and DC12 again.

[0065] In operation S30, the memory device 100 may program the dummy cells DC11 and DC12 based on determining that the erase operations for the dummy cells DC11 and DC12 are completed. Figure 6C , the turn-on voltage V_TN_G may be applied to the ground selection line GSL for a preset time period earlier than the first time point t1. The turn-on voltage V_TN_G may be the turn-on voltage of the ground selection transistor GST. In addition, at the first time point t1, the pass voltage V_PASS may be applied to the word line WL and the pseudo word line DWL. The turn-on voltage V_TN_G may be applied to the ground selection line GSL before the word line WL and the pseudo word line DWL, thereby isolating the timing to prevent the boosting of the channel. Therefore, hot carrier injection (HCI) may be prevented. Since the ground voltage GND is applied to the common source line CSL from the first time point t1 to the fourth time point t4, the voltage of the channel formed in each of the pseudo hole and the channel hole may be the ground voltage in the period between the first time point t1 and the second time point t2.

[0066] Next, at the second time point t2, the off voltage may be applied (or restored) to the ground selection line GSL. In addition, the inhibition voltage V_INH may be applied to the bit line BL, and a voltage having a level equal to or higher than the sum of the levels of the turn-on voltage V_TN_S and the pass voltage V_PASS may be applied to the string selection line SSL.

[0067] Next, at a third time point t3, a programming voltage V_PGM may be applied to the pseudo word line DWL. The programming voltage V_PGM may be set so that the threshold voltages of the pseudo cells DC11 and DC12 are higher in level than the level of the turn-on voltage of the main cells MC11 to MC82. That is, the programming voltage V_PGM may be set so that the threshold voltages of the pseudo cells DC11 and DC12 are higher in level than the level of the threshold voltages of the main cells MC11 to MC82. For example, according to the programming voltage V_PGM, the pseudo cells DC11 and DC12 may be programmed based on the FN stress method. After the programming operations of the pseudo cells DC11 and DC12 are completed, at a fourth time point t4, the voltage of each line may be restored.

[0068] Figure 7 is a flowchart illustrating a method of operating a memory device according to an example embodiment. Figure 5B About Figure 7 Description.

[0069] refer to Figure 7 In order to set a target threshold voltage for the dummy cells DC11 and DC12 , the memory device 100 may search for a program voltage to be applied to the dummy cells DC11 and DC12 in operation S100 .

[0070] For example, after performing a programming operation on the main cells MC11 to MC82, the memory device 100 may search for a programming voltage for programming the pseudo word line DWL by comparing the target threshold voltage with the threshold voltage formed by the execution of the programming operation. Figure 6C The same method as described for programming the dummy cells DC11 and DC12 is used to program the main cells MC11 to MC82.

[0071] Next, in operation S110 , the memory device 100 may perform an erase operation on the dummy cells DC11 and DC12 , and in operation S120 , erase verification may be performed.

[0072] When the erase operation is completed, in operation S130 , the memory device 100 may perform a program operation on the dummy cells DC11 and DC12 based on the program voltage found in operation S100 .

[0073] FIG. 8A to FIG. 8C is a diagram illustrating a method of operating a memory device according to another example embodiment. Specifically, Fig. 8A To illustrate a flow chart of a method of operating a memory device, Figure 8B A cross-sectional view showing a memory device, and Figure 8C A timing diagram showing the voltage applied to each line when the second dummy cell is programmed. FIG. 8A to FIG. 8C In the description, for the convenience of description, the description already given above will be omitted.

[0074] refer to Fig. 8A and Figure 8B In operation S210, the memory device 100 may perform an erase operation on the first dummy cell DC11_1 and the first dummy cell DC12_1 and the second dummy cell DC11_2 and the second dummy cell DC12_2. For example, the first dummy cell DC11_1 and the first dummy cell DC12_1 may be formed as a dummy hole DH1 and a first dummy word line DWL1, and the second dummy cell DC11_2 and the second dummy cell DC12_2 may be formed as a dummy hole DH1 and a second dummy word line DWL2 disposed above the first dummy word line DWL1. In other words, the second dummy cell DC11_2 and the second dummy cell DC12_2 may be disposed above the first dummy cell DC11_1 and the first dummy cell DC12_1, respectively.

[0075] Next, in operation S220 , the memory device 100 may perform erasure verification on the first dummy cell DC11_1 , the first dummy cell DC12_1 , the second dummy cell DC11_2 , and the second dummy cell DC12_2 , and may determine whether the erasure verification is passed.

[0076] In operation S230 , the memory device 100 may perform a threshold voltage control operation on each of the first and second dummy cells DC11_1 and DC12_1 and the main cells MC11 to MC82 based on determining completion of the erase operation of the first and second dummy cells DC11_1 , DC12_1 , and DC12_2 .

[0077] In example embodiments, the memory device 100 may perform a threshold voltage control operation on each of the first dummy cell DC11_1 and the first dummy cell DC12_1 and the main cells MC11 to MC82 by applying a word line programming voltage to the first dummy word line DWL1 and applying a driving voltage to the bit lines BL1, BL3, BL6, and BL8. Therefore, when the dummy hole DH1 not connected to the bit line is boosted, the first dummy cell DC11_1 and the first dummy cell DC12_1 may not be programmed, and each of the main cells MC11 to MC82 may be programmed. In other words, through operation S230, the level of the threshold voltage of the main cells MC11 to MC82 may be higher than the level of the threshold voltage of the dummy cell DC11 and the dummy cell DC12.

[0078] Next, in operation S240, the memory device 100 may program the second dummy cell DC11_2 and the second dummy cell DC12_2. Figure 8C , at the first time point t1, a turn-on voltage V_TN_S may be applied to the string selection line SSL. The turn-on voltage V_TN_S may be a turn-on voltage of the string selection transistor SST.

[0079] Therefore, the string selection transistor SST may be turned on, and then the inhibition voltage V_INH may be applied to each of the bit lines BL1 , BL3 , BL6 , and BL8 at the second time point t2 .

[0080] Next, at the third time point t3, the pass voltage V_PASS may be applied to the word lines WL1 to 4, and a voltage having a desired (or alternatively, a preset) level may be applied to the second dummy word line DWL2. For example, at the third time point t3, a voltage having a level lower than that of the program voltage V_PGM to be applied subsequently may be applied to the second dummy word line DWL2.

[0081] Next, at a fourth time point t4, a programming voltage V_PGM may be applied to the second pseudo word line DWL2, and at a fifth time point t5, a turn-on voltage V_TN_G may be applied to the ground selection line GSL. For example, the turn-on voltage V_TN_G may be a turn-on voltage of the ground selection transistor GST. In addition, at the fifth time point t5, a turn-on voltage V_TN_D may be applied to the first pseudo word line DWL1. In an example embodiment, the turn-on voltage V_TN_D may be a voltage having a level lower than that of the threshold voltage of the main cells MC11 to MC82 and a level higher than that of the threshold voltage of the first pseudo cells DC11_1 and the first pseudo cells DC12_1. In other words, when the turn-on voltage V_TN_D is applied, the first pseudo cells DC11_1 and the first pseudo cells DC12_1 may be turned on, and the main cells MC11 to MC82 may be turned off. Therefore, at the fifth time point t5, the ground selection transistor GST can be turned on, and the programming operation can be performed on the second dummy cell DC11_2 and the second dummy cell DC12_2. For example, at the fifth time point t5, since the dummy hole DH1 is connected to the common source line CSL to which the ground voltage GND is applied, the programming operation of the HCI mode can be performed on the second dummy cell DC11_2 and the second dummy cell DC12_2. After the programming operation of the second dummy cell DC11_2 and the second dummy cell DC12_2 is completed, at the sixth time point t6, the voltage of each line can be restored.

[0082] In another example embodiment, in order to set the target threshold voltage of the second dummy cell DC11_2 and the second dummy cell DC12_2, the memory device 100 may also search for a programming voltage to be applied to the second dummy cell DC11_2 and the second dummy cell DC12_2. For example, before performing the erase operation in operation S210, the memory device 100 may perform a programming operation on the main cells MC11 to MC82, and may search for a programming voltage for setting the target threshold voltage by reading out a threshold voltage caused by the execution of the programming operation. In an example embodiment, the memory device 100 may perform a programming operation on the main cells MC11 to MC82 in the same manner as the programming operation performed in operation S240, and may search for a programming voltage for setting the target threshold voltage by reading out a threshold voltage caused by the execution of the programming operation.

[0083] Fig. 9 Threshold voltage distributions for each of a main cell and a dummy cell after performing a method of operating a memory device according to example embodiments are shown.

[0084] refer to Fig. 9, main cells MC11 to MC82 may have a threshold voltage distribution E corresponding to an erase state or a threshold voltage distribution P1 corresponding to a first program state according to the operation of memory device 100. In the present example embodiment, although the main cells are described as being programmed in an SLC manner, this is merely an example and example embodiments of the inventive concept are not limited thereto.

[0085] According to the above Fig. 6A and Figure 7 The pseudo-unit DC11 and the pseudo-unit DC12 according to the method of operation described above Fig. 8A The second dummy cell DC11_2 and the second dummy cell DC12_2 of the operation method of the main cell may have a threshold voltage distribution Px at a level higher than that of the threshold voltage distribution P1 corresponding to the first program state of the main cell. For example, according to the erase operation, the dummy cell DC11, the dummy cell DC12, the dummy cell DC11_2, and the dummy cell DC12_2 may have a threshold voltage distribution E corresponding to the erase state according to the erase operation, and then have a threshold voltage distribution Px according to the program operation.

[0086] The dummy cell DC11, the dummy cell DC12, the dummy cell DC11_2, and the dummy cell DC12_2 have a voltage having a level higher than that of the turn-on voltage V_TN_MC of the main cell MC11 to the main cell MC82, whereby the dummy cell DC11, the dummy cell DC12, the dummy cell DC11_2, and the dummy cell DC12_2 may be turned off when the main cell MC11 to the main cell MC82 are turned on for memory operation. In other words, during the memory operation, the dummy hole DH1 may be electrically isolated from the substrate SUB. Therefore, during the memory operation such as data reading, the parasitic capacitance generated between the dummy hole DH1 and the gate conductive layer may be reduced, and therefore, due to the reduced load, the electrical characteristics of the memory device 100 may be improved.

[0087] Fig.10 is a block diagram illustrating an example in which a memory device according to example embodiments is applied to an SSD system.

[0088] refer to Fig.10 , the SSD system 1000 may include a host 1100 and an SSD 1200. The SSD 1200 may send and receive signals to and from the host 1100 via a signal connector, and may receive power input thereto via a power connector. The SSD 1200 may include an SSD controller 1210, an auxiliary power supply 1220, and memory devices 1230, 1240, and 1250. Here, the SSD 1200 may be configured according to the reference Figures 1 to 9The described example embodiment implements SSD 1200. Each of memory device 1230, memory device 1240, and memory device 1250 may include a dummy cell, and each of the plurality of dummy cells may be programmed to have a threshold voltage higher than a threshold voltage of each main cell. Therefore, a load caused by a dummy hole not connected to a bit line may be reduced during a memory operation, and electrical characteristics of the memory device may be improved.

[0089] Although the exemplary embodiments of the present invention have been specifically shown and described with reference to some exemplary embodiments of the present invention, it will be understood by those skilled in the art that various changes may be made to the above exemplary embodiments in form and detail without departing from the spirit and scope of the appended claims. In addition, it should be understood that the specific terms used herein are only used for the purpose of describing the exemplary embodiments and are not intended to limit the exemplary embodiments of the present invention. Therefore, the scope of the exemplary embodiments of the present invention should be limited by the appended claims and their equivalents.

Claims

1. A method of operating a memory device, the memory device comprising: substrate; at least one dummy word line located above the substrate; a plurality of word lines located above the at least one dummy word line; and a plurality of vertical holes extending through the at least one dummy word line and the plurality of word lines in a direction perpendicular to the substrate, the plurality of vertical holes including channel holes and dummy holes, the channel holes being vertical holes connected to the bit lines among the plurality of vertical holes, the method comprising: performing an erase operation on a plurality of dummy cells, each of the plurality of dummy cells including one of the at least one dummy word line and one of the dummy holes; verifying the erase operation; and A program operation is performed on at least one of the plurality of dummy cells so that a threshold voltage of the plurality of dummy cells is higher than a threshold voltage of a main cell, the main cells each including one of the at least one dummy word line and one of the channel holes.

2. The method according to claim 1, wherein: The at least one dummy word line includes a first dummy word line and a second dummy word line, the second dummy word line is located above the first dummy word line, and performing the programming operation includes: A threshold voltage of each of a first dummy cell and the main cell is controlled, the first dummy cell being a dummy cell including one of the first dummy word line and the dummy hole among the plurality of dummy cells.

3. The method according to claim 2, wherein: The controlling the threshold voltage of each of the first dummy cell and the main cell comprises: applying a program voltage to the first dummy word line; and A driving voltage is applied to the bit line.

4. The method according to claim 3, wherein: Performing the programming operation on the dummy cell includes: After controlling the threshold voltage of each of the first pseudo cell and the main cell, a programming operation is performed on each of the second pseudo cells so that the second pseudo cells have a threshold voltage higher than the threshold voltage of the main cell, the second pseudo cells including one of the second pseudo word line and the pseudo hole.

5. The method according to claim 4, wherein: Performing the programming operation on each of the second dummy cells includes: A turn-on voltage having a voltage level lower than that of the threshold voltage of the main cell and higher than that of the threshold voltage of the first dummy cell is applied to the first dummy word line for a period of time.

6. The method according to claim 5, wherein: Performing the programming operation on each of the second dummy cells includes: The program voltage is applied to the second dummy word line for at least a portion of the time period.

7. The method according to claim 6, wherein: Applying the programming voltage to the second dummy word line comprises: applying a first voltage to the second dummy word line for a first portion of the time period, the first voltage being lower than the programming voltage; and The program voltage is applied to the second dummy word line for a second portion of the time period.

8. The method according to claim 1, further comprising: performing the programming operation on the master unit; as well as A dummy program voltage is searched for to program at least one of the plurality of dummy cells based on a program operation on the main cell.

9. The method according to claim 8, wherein: Performing the programming operation on at least one of the plurality of dummy cells includes: The program operation is performed on the at least one of the plurality of dummy cells based on the dummy program voltage.

10. The method according to claim 8, wherein: Performing the programming operation on the master unit includes: applying a first voltage having a first level to the at least one dummy word line for a first portion of a time period; and A second voltage having a second level higher than the first level is applied to the at least one dummy word line for a second portion of the time period.

11. The method according to claim 10, wherein: The memory device further includes a ground selection line between the substrate and the at least one dummy word line, and applying the second voltage having the second level to the at least one dummy word line includes: A turn-on voltage is applied to the ground select line.

12. The method according to claim 10, wherein: The memory device further includes a string selection line between the plurality of word lines and the bit lines, and performing the program operation on the main cell includes: An off voltage is applied to the string selection line for the period of time.

13. The method according to claim 1, wherein: The memory device further includes a ground selection line between the substrate and the at least one dummy word line, and performing the programming operation on the dummy cell includes: a first applying step of applying a conduction voltage to the ground selection line; a second applying step of applying a pass voltage to the at least one dummy word line and the plurality of word lines for a first period of time after the first applying step; a third applying step of applying an off voltage to the ground selection line and applying the pass voltage to the at least one dummy word line and the plurality of word lines for a second period of time; and A fourth applying step of applying the off voltage to the ground selection line and applying a program voltage to the at least one dummy word line for a third period of time.

14. The method according to claim 13, wherein: The memory device further includes a string selection line between the plurality of word lines and the bit lines, and performing the program operation on the dummy cell includes: An inhibit voltage is applied to the bit line and a string select voltage is applied to the string select line for the second period of time, the string select voltage being equal to or greater than a sum of the turn-on voltage and the pass voltage.

15. The method according to claim 13, wherein: The memory device further includes a common source line in a portion of the substrate, and performing the programming operation on the dummy cell includes: A ground voltage is applied to the common source line for the first time period to the third time period.

16. A method of operating a memory device, the memory device comprising a substrate, a first dummy word line above the substrate, a second dummy word line above the first dummy word line, a plurality of word lines above the second dummy word line, and a plurality of vertical holes extending through the first dummy word line, the second dummy word line, and the plurality of word lines in a direction perpendicular to the substrate, each of the plurality of vertical holes comprising one of a first vertical hole and a second vertical hole, the method comprising: performing an erase operation on a first dummy cell and a second dummy cell, the first dummy cell including one of the first vertical holes and the first dummy word line, and the second dummy cell including one of the first vertical holes and the second dummy word line, wherein one of the first vertical holes is a dummy hole; verifying the erase operation; In response to verifying that the erase operation is complete, controlling a threshold voltage of each of the first dummy cell and a main cell, each of the main cells including one of the second vertical holes and the first dummy word line, wherein one of the second vertical holes is a channel hole; and The second dummy cell is programmed.

17. The method according to claim 16, wherein: The memory device further includes a plurality of bit lines connected to corresponding second vertical holes, and controlling the threshold voltage includes: forming a first threshold voltage by applying a driving voltage to the plurality of bit lines; and A second threshold voltage is formed in the first dummy cell by applying a program voltage to the first dummy word line, the second threshold voltage being lower than the first threshold voltage.

18. The method according to claim 17, wherein: Programming the second dummy cell includes: A voltage is applied to the first dummy word line, the voltage being lower than the first threshold voltage and higher than the second threshold voltage.

19. The method according to claim 16, wherein: The memory device further includes a string selection line above the plurality of word lines and a plurality of bit lines above the string selection line, the plurality of bit lines being connected to corresponding second vertical holes, and programming the second dummy cells includes: applying a turn-on voltage to the string selection line for a period of time; and An inhibit voltage is applied to the plurality of bit lines for at least a portion of the time period.

20. The method according to claim 19, wherein: Programming the second dummy cell includes: A pass voltage is applied to the plurality of word lines and a program voltage is applied to the second dummy word line for at least the portion of the time period.

21. A non-volatile memory device comprising: substrate; a plurality of gate conductive layers including at least one dummy word line located above the substrate and a plurality of word lines located above the at least one dummy word line; a plurality of bit lines located above the plurality of gate conductive layers, the plurality of bit lines being spaced apart from each other in a first direction and extending in a second direction, the second direction being perpendicular to the first direction; a plurality of vertical holes extending through the plurality of gate conductive layers in a direction perpendicular to the substrate, the plurality of vertical holes including channel holes and dummy holes, the channel holes being vertical holes among the plurality of vertical holes connected to corresponding bit lines among the plurality of bit lines; dummy cells, each of the dummy cells comprising one of the at least one dummy word line and one of the dummy holes; main cells, each of the main cells including one of the plurality of word lines and one of the channel holes; and A row decoder is configured to apply a voltage to each of the plurality of gate conductive layers such that when a turn-on voltage associated with the main cell is applied to the at least one dummy word line, the dummy cell is configured to be turned off.

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