A cell structure and preparation method thereof, power semiconductor device and electronic equipment

Abstract

The present invention provides a cellular structure and a preparation method thereof, a power semiconductor device and an electronic device. The cellular structure substrate is provided with a plurality of grooves arranged in a single row on the substrate, wherein at least part of the grooves are provided with transverse reinforcing sidewalls; and the sidewalls of the grooves are provided with notches for connecting the grooves blocked by the transverse reinforcing sidewalls with other grooves in an electrically conductive manner. The overall strength of the entire cellular structure is enhanced by partially adding transverse reinforcing sidewalls in the formed grooves, and the grooves are electrically connected by the provided notches, so that the performance of the power semiconductor device can be improved by opening relatively dense grooves.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a cellular structure and a preparation method thereof, a power semiconductor device and an electronic device. Background Art

[0002] Power semiconductor devices are widely used in various power control circuits, drive circuits and other circuits. In particular, they play an irreplaceable role in various variable frequency motors, photovoltaic inverters and smart grids, new energy vehicles, electric locomotive traction drives and other fields.

[0003] After decades of development of power semiconductor technology, IGBT and MOSFET have gradually become mainstream devices in today's power electronics field. Especially in high-power application scenarios such as high voltage and high current, IGBT has almost an absolute dominant position. It is widely used in various power control circuits, drive circuits and other circuits. In particular, it plays an irreplaceable role in various variable frequency motors, photovoltaic inverters and smart grids, new energy vehicles, electric locomotive traction drives and other fields.

[0004] The most advanced IGBT technology at present is the trench field stop IGBT technology (Trench FS-IGBT). IGBT devices produced using this technology usually require strict control of the thickness of the entire chip. Generally, the thickness of a 650V FS-IGBT is around 60 to 80um.

[0005] Power semiconductor devices are generally made on silicon wafers through semiconductor process technology, and then go through steps such as dicing, wire bonding and packaging to finally form packaged finished devices. Compared with other power semiconductor devices, the thickness of IGBT devices is very thin, so that a piece of IGBT wafer will naturally bend and droop like a piece of paper in your hand. It is conceivable how difficult it is to package such a thin device. However, with the improvement of semiconductor process equipment performance and process technology level, the current density of IGBT devices is also further improved. Therefore, the groove density in the cell area also increases, and the resulting increase in packaging difficulty is also very obvious.

[0006] After the IGBT device completes all the production processes, looking down from top to bottom, the cell area 1 can be divided into the emitter wiring area and the gate wiring area. Figure 1 As shown in Figure 2, as the density of the trench 2 increases, the silicon at the bottom of the emitter bonding area that bears the bonding pressure will become less and less, and the stress from the bonding that the silicon structure can withstand will become smaller and smaller. Therefore, the bonding may cause greater damage. When the damage exceeds a certain limit, the device will fail, which may be a failure of electrical parameters or a failure of reliability. Summary of the invention

[0007] The invention provides a cellular structure and a preparation method thereof, a power semiconductor device and an electronic device, which are used to improve the performance of the power semiconductor device.

[0008] The present invention provides a cellular structure, wherein the cellular structure substrate is provided with a plurality of grooves arranged in a single row on the substrate, wherein at least part of the grooves are provided with transverse reinforcing sidewalls; and the sidewalls of the grooves are provided with notches for connecting the grooves blocked by the transverse reinforcing sidewalls with other grooves in an electrically conductive manner. The overall strength of the entire cellular structure is enhanced by partially adding transverse reinforcing sidewalls in the formed grooves, and the grooves are electrically connected by the provided notches, so that relatively dense grooves can be opened to improve the performance of power semiconductor devices.

[0009] In a specific configuration, the groove provided with the transverse reinforcing sidewall is provided with a plurality of transverse reinforcing sidewalls, and at least one of the groove walls of the groove between any two transverse reinforcing sidewalls is provided with the notch. By connecting the two grooves, conductive connection of the grooves is achieved.

[0010] In a specific configuration, in the grooves provided with the transverse reinforcing sidewalls, in any two adjacent grooves, at least one transverse reinforcing sidewall forms a cross-shaped structure with the common sidewall of the two grooves, thereby further increasing the strength of the entire cellular structure.

[0011] When the transverse reinforcing side walls are specifically arranged, the plurality of transverse reinforcing side walls are arranged in a plurality of rows, and each row includes a plurality of transverse reinforcing side walls arranged at intervals, wherein the plurality of rows of transverse reinforcing side walls are staggered in sequence along the vertical direction, thereby enhancing the strength of the entire cellular structure.

[0012] In a specific configuration, the transverse reinforcing side wall and the side wall of the groove are an integrated structure, thereby enhancing the strength of the entire cellular structure.

[0013] In a specific configuration, the height of the transverse reinforcing side wall is the same as the height of the side wall of the groove, which facilitates preparation.

[0014] The present invention also provides a method for preparing the above-mentioned cellular structure, which comprises the following steps:

[0015] A groove is etched in the substrate, and when the groove is formed, a transverse reinforcing sidewall is formed in at least part of the groove; and a notch is formed on the sidewall of the groove for connecting the groove blocked by the transverse reinforcing sidewall with other grooves. The overall strength of the entire cellular structure is enhanced by partially adding the transverse reinforcing sidewall in the formed groove, and the groove is connected electrically through the provided notch, so that the performance of the power semiconductor device can be improved by opening relatively dense grooves.

[0016] During the specific preparation, the formed grooves are also subjected to surface treatment.

[0017] The present invention also provides a power semiconductor device, which also includes any of the above-mentioned cellular structures. The overall strength of the entire cellular structure is enhanced by partially adding lateral reinforcement sidewalls in the formed grooves, and the grooves are electrically connected through the provided gaps, so that the performance of the power semiconductor device can be improved by opening relatively dense grooves.

[0018] The present invention also provides an electronic device, which includes any of the above-mentioned cellular structures. The overall strength of the entire cellular structure is enhanced by partially adding lateral reinforcing sidewalls in the formed grooves, and the grooves are electrically connected through the provided gaps, so that the performance of the power semiconductor device can be improved by opening relatively dense grooves. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a structural schematic diagram of an IGBT device in the prior art;

[0020] Figure 2 A schematic diagram of the structure of an IGBT device provided by an embodiment of the present invention;

[0021] Figure 3 A cellular structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] In order to facilitate understanding of the cell structure 10 provided in the embodiment of the present invention, the application scenario thereof is first described. The cell structure 10 is applied to power semiconductor devices, such as IGBT devices. Figure 2 As shown in Figure 2 The top view of the IGBT device is shown, in which the E pole is the emitter, located on the front of the chip. In order to ensure the overcurrent capability, the aluminum wire bonding generally uses a wire diameter of 15 mil or more; there is a groove 14 structure under the E pole. The G pole is the gate, which is the input end of the driving voltage. Since it is only used to transmit pulse signals, the wire diameter is relatively small, and generally an aluminum wire of about 5 mil is used. The cell structure 10 provided in the embodiment of the present invention is located in the area corresponding to the E pole.

[0024] Power semiconductor devices are generally manufactured on silicon wafers using semiconductor process technology, and then undergo dicing, wire bonding, packaging, and other steps to ultimately form packaged finished devices. Compared with other power semiconductor devices, the thickness of an IGBT device is very thin, so that a piece of IGBT wafer held in the hand will naturally bend and sag like a piece of paper held in the hand. It is conceivable how difficult it is to package such a thin device. In order to improve the strength of the power semiconductor device, an embodiment of the present invention provides a cellular structure 10.

[0025] For reference Figure 2 and Figure 3 , wherein the cellular structure 10 provided in the embodiment of the present application includes: the present invention provides a cellular structure 10, the cellular structure 10 has a substrate, the substrate is a silicon wafer, when the cellular structure 10 is located on a power semiconductor device, the substrate is the substrate of the power semiconductor device.

[0026] When the cell structure 10 is provided, in the embodiment of the present invention, a plurality of grooves 14 arranged in a single row are formed on the substrate, such as Figure 1 and Figure 2 As shown in Figure 1 The placement direction of the power semiconductor device shown is the reference direction, the groove 14 is arranged in the vertical direction, and multiple grooves 14 are arranged in the horizontal direction. In order to improve the strength between the grooves 14 and to improve the strength of the power semiconductor device, when the grooves 14 are arranged, a lateral reinforcing sidewall 12 is arranged on at least part of the grooves 14 of the cell structure 10. Figure 2 As shown in , a transverse reinforcing sidewall 12 connecting the two sidewalls 11 is added between the sidewalls 11 on both sides of the groove 14, thereby enhancing the connection strength between the two sidewalls 11, and improving the strength reduction in the direction of the arrangement of the grooves 14 caused by the single-row arrangement of the grooves 14. In addition, when the transverse reinforcing sidewall 12 is set, since the transverse reinforcing sidewall 12 connects the two sidewalls 11 of the groove 14 together, the groove 14 is blocked. In order to ensure the flow effect of the current, when setting, the sidewall 11 of the groove 14 is provided with a corresponding notch 13, so that the blocked groove 14 can be connected with the adjacent groove 14 to achieve the effect of conductivity.

[0027] For ease of understanding, the transverse reinforcing sidewalls 12 and the notches 13 provided on the cellular structure 10 provided by the present application are described in detail below.

[0028] like Figure 1As shown in , when the transverse reinforcing sidewalls 12 and the notches 13 are specifically provided, the cellular structure 10 can be provided in some or all of the grooves 14. Specifically, it can be determined according to the strength of the entire power semiconductor device. When the transverse reinforcing sidewalls 12 and the notches 13 are provided in some of the grooves 14, a plurality of transverse reinforcing sidewalls 12 are provided in the grooves 14 provided with the transverse reinforcing sidewalls 12, such as Figure 2 As shown in , a plurality of transverse reinforcing side walls 12 are arranged along the length direction of the groove 14 and are arranged at intervals, so that the groove 14 is closed into a segmented structure. To achieve conductive connection, when the notch 13 is set, at least one side wall 11 of the groove wall of the groove 14 between any two transverse reinforcing side walls 12 is provided with a notch 13. That is, for each groove 14, when a plurality of transverse reinforcing side walls 12 are set therein, on the side wall 11 of the groove 14 located between two adjacent transverse reinforcing side walls 12, at least one side wall 11 of the groove 14 is provided with a notch 13 connected to the adjacent groove 14, as shown in FIG. Figure 2 As shown in Figure 2 Different modes are shown, that is, only one of the side walls 11 of the groove 14 between any two transverse reinforcing side walls 12 is provided with a notch 13 , and that both of the side walls 11 of the groove 14 between any two transverse reinforcing side walls 12 are provided with a notch 13 .

[0029] In addition, when multiple transverse reinforcing sidewalls 12 are specifically set, in order to ensure the transverse strength of the connection (the direction in which the grooves 14 are arranged), when the transverse reinforcing sidewalls 12 are set, the adjacent grooves 14 are all provided with transverse reinforcing sidewalls 12 to improve the transverse connection strength. At this time, among the multiple transverse reinforcing sidewalls 12 formed, the multiple transverse reinforcing sidewalls 12 are arranged in multiple rows; and each row includes multiple transverse reinforcing sidewalls 12 arranged at intervals; wherein the multiple rows of transverse reinforcing sidewalls 12 are staggered in sequence along the vertical direction. Thereby enhancing the strength of the entire cellular structure 10. When specifically set, multiple transverse reinforcing structures are respectively set in multiple grooves 14, and the transverse reinforcing structures have multiple in the direction in which the grooves 14 are arranged, and form multiple rows in the length direction of the grooves 14. In order to ensure the strength of the connection and the conductive effect between the grooves 14. When the transverse reinforcing structure is set, the transverse reinforcing sidewalls 12 in different rows in the grooves 14 are staggered one by one. So that the transverse reinforcing structures located in different rows are connected to enhance the strength of different grooves 14.

[0030] In a specific embodiment, Figure 2 As shown in the figure, in the grooves 14 provided with the transverse reinforcing sidewalls 12, in any two adjacent grooves 14, at least one transverse reinforcing sidewall 12 forms a cross-shaped structure with the common sidewall 11 of the two grooves 14. This further increases the strength of the entire cellular structure 10. Figure 2, wherein at least one transverse reinforcing side wall 12 is located in the same row in any two adjacent grooves 14, and at this time, the transverse reinforcing side walls 12 in the two grooves 14 can be regarded as one, that is, the two transverse reinforcing side walls 12 form a reinforcing structure. When arranged, the reinforcing structure also satisfies the above: in the arrangement direction of the grooves 14, a row of reinforcing structures is formed, and in the length direction of the grooves 14, multiple rows of reinforcing structures are formed, and when staggered, the reinforcing structures in different rows are staggered by one groove 14, that is, in the reinforcing structures in adjacent rows, they jointly strengthen the strength of one groove 14.

[0031] When the above structure is adopted, it can be seen that the formed reinforcement structure and the common groove wall between the two grooves 14 form a cross-shaped structure. The cross-shaped reinforcement structure can effectively improve the strength of the cellular structure 10, thereby enhancing the strength of the entire power semiconductor device, so that more grooves 14 can be set on the power semiconductor device, thereby improving the performance of the power semiconductor device.

[0032] In addition, in order to improve the connection strength of the lateral reinforcing sidewall 12, the lateral reinforcing sidewall 12 is an integrated structure with the sidewall 11 of the groove 14 when it is set. That is, when the groove 14 is etched on the silicon wafer, the sidewall 11 of the groove 14 and the lateral reinforcing sidewall 12 are formed at the same time. By adopting the method of integrally forming the sidewall 11 of the groove 14 and the lateral reinforcing sidewall 12, the connection strength between the lateral reinforcing sidewall 12 and the sidewall 11 of the groove 14 is improved, thereby improving the strength of the cellular structure 10.

[0033] When specifically setting the lateral reinforcing sidewall 12 and the sidewall 11 of the groove 14, they can have the same height or different heights. In a specific setting scheme, the height of the lateral reinforcing sidewall 12 is the same as the height of the sidewall 11 of the groove 14, thereby facilitating etching and improving processing efficiency.

[0034] In addition, the embodiment of the present invention also provides a method for preparing the above-mentioned cellular structure 10, which comprises the following steps: etching a groove 14 in a substrate, and when forming the groove 14, forming a transverse reinforcing sidewall 12 in at least part of the groove 14; and forming a notch 13 on the sidewall 11 of the groove 14 for electrically connecting the groove 14 blocked by the transverse reinforcing sidewall 12 with other grooves 14. By partially adding the transverse reinforcing sidewall 12 in the formed groove 14, the overall strength of the entire cellular structure 10 is enhanced, and the groove 14 is electrically connected by the provided notch 13, so that the performance of the power semiconductor device can be improved by opening relatively dense grooves 14.

[0035] During the specific preparation, etching needs to be performed through a mask. Therefore, when forming the above-mentioned groove 14, it is necessary to start etching with the sidewall 11 of the groove 14 and the structure of the lateral reinforcement sidewall 12 on the mask to achieve etching.

[0036] The above preparation method further includes performing surface treatment on the formed groove 14 .

[0037] In addition, the present invention also provides a power semiconductor device, which also includes any of the above-mentioned cellular structures 10. The overall strength of the entire cellular structure 10 is enhanced by partially adding lateral reinforcing sidewalls 12 in the formed grooves 14, and the grooves 14 are electrically connected through the provided notches 13, so that the performance of the power semiconductor device can be improved by opening relatively dense grooves 14.

[0038] Taking IGBT devices as an example, during preparation, there is no obvious difference between its manufacturing process and the traditional structure. The difference mainly comes from the design of the structure, that is, the mask used is different, mainly the mask of the trench 14 layer, and the mask of the N+, Cantact and other layers are adjusted accordingly according to the trench 14 structure. The brief manufacturing process is introduced as follows: 1) Raw material preparation: semiconductor silicon epitaxial wafer, the thickness and resistivity of the wafer and other parameters vary according to the withstand voltage requirements of different products. 2) Terminal lithography, injection (P-) and debonding. 3) Terminal diffusion well. 4) Oxide layer growth. It should be noted that this step can be completed at the same time as step 3, depending on the actual process. 5) Active area lithography, oxide layer etching and debonding. 6) Hard mask deposition. 7) Trench 14 lithography. 8) Hard mask etching and debonding. 9) Trench 14 etching. 10) Hard mask removal. 11) Trench 14 surface treatment. After completing this step, the structure of the emitter region is as follows Figure 3 As shown. 12) Gate oxide layer growth. 13) Polysilicon deposition. 14) Polysilicon doping. 15) Polysilicon lithography. 16) Polysilicon etching. 17) P-well (P-) implantation and well push. 18) N+ lithography and etching. 19) N+ implantation and well push. 20) Dielectric layer deposition. 21) Dielectric layer lithography and etching. 22) Metal sputtering. 23) Metal lithography and etching. 24) Metal alloy. After this step, all necessary front processes have been completed. It should be noted that some products will deposit a passivation layer (also called a protective layer) after the metal alloy according to special requirements. 25) Subsequent back process. Depending on the product type, the back process is slightly different. Such as the thickness of the thinning, whether the irradiation process is required, etc. The above steps are similar to the preparation process in the prior art, so they will not be repeated here.

[0039] In addition, the present invention also provides an electronic device, which includes any of the above-mentioned cellular structures 10. The overall strength of the entire cellular structure 10 is enhanced by partially adding lateral reinforcing sidewalls 12 in the formed grooves 14, and the grooves 14 are electrically connected through the provided notches 13, so that the performance of the power semiconductor device can be improved by opening relatively dense grooves 14.

[0040] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A cellular structure, characterized in that: include: A substrate, a plurality of grooves arranged in a single row on the substrate, wherein: Each of the grooves is arranged along the vertical direction, and a plurality of the grooves are arranged along the horizontal direction; At least part of the grooves are provided with transverse reinforcing sidewalls; and the sidewalls of the grooves are provided with notches for electrically connecting the grooves blocked by the transverse reinforcing sidewalls with other grooves; A plurality of the transverse reinforcing side walls are arranged in the groove in which the transverse reinforcing side walls are provided, and the plurality of the transverse reinforcing side walls are arranged along the length direction of the groove and are arranged at intervals; and the notch is provided on at least one side wall of the groove wall between any two adjacent transverse reinforcing side walls.

2. The cellular structure according to claim 1, characterized in that In the grooves provided with transverse reinforcing side walls, in any two adjacent grooves, at least one transverse reinforcing side wall forms a cross-shaped structure with the common side wall of the two grooves.

3. The cellular structure according to claim 1, characterized in that: The plurality of transverse reinforcing side walls are arranged in a plurality of rows; and each row includes a plurality of transverse reinforcing side walls arranged at intervals; wherein, The multiple rows of transverse reinforcing side walls are staggered in sequence along the vertical direction.

4. The cellular structure according to claim 2, characterized in that: The transverse reinforcing side wall and the side wall of the groove are an integral structure.

5. The cellular structure according to claim 1, characterized in that: The height of the lateral reinforcing sidewall is the same as the height of the sidewall of the groove.

6. A method for preparing a cellular structure according to any one of claims 1 to 5, characterized in that: The following steps are involved: A groove is etched in the substrate, and when the groove is formed, a transverse reinforcing sidewall is formed in at least a portion of the groove; and a notch is formed on the sidewall of the groove for conductively connecting the groove blocked by the transverse reinforcing sidewall with other grooves.

7. The preparation method according to claim 6, characterized in that: The method also includes performing surface treatment on the formed grooves.

8. A power semiconductor device, characterized in that: The invention comprises the cellular structure as claimed in any one of claims 1 to 5.

9. An electronic device, characterized in that: The invention comprises the cellular structure as claimed in any one of claims 1 to 5.

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