Semiconductor Package

Abstract

The present invention provides a semiconductor package, which may include a connection structure, wherein the connection structure includes one or more redistribution layers. A semiconductor chip is arranged on the connection structure and has an active surface and an inactive surface opposite to the active surface, and a connection pad electrically connected to the redistribution layer is arranged on the active surface. An encapsulant is arranged on the connection structure and covers at least a portion of the inactive surface of the semiconductor chip. A conductor pattern layer is embedded in the encapsulant so that an exposed surface of the conductor pattern layer is exposed from the encapsulant. A metal layer is arranged on the encapsulant and covers the exposed surface of the conductor pattern layer.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2018-0137526 filed on November 9, 2018, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0002] The present disclosure relates to a semiconductor package, for example, a fan-out type semiconductor package capable of extending an electrical connection structure to the outside of a region in which a semiconductor chip is disposed. Background Art

[0003] In recent years, one of the main trends in the development of technology related to semiconductor chips is to reduce the size of components. Therefore, in the field of packaging, efforts have been made to achieve a large number of pins and a small size in accordance with the surging demand for small semiconductor chips and the like.

[0004] To meet this need, one proposed semiconductor package technology is a fan-out type semiconductor package, which can redistribute electrical connection structures outside a region where a semiconductor chip is disposed, thereby enabling a large number of pins while maintaining a small size. Summary of the invention

[0005] An aspect of the present disclosure is to provide a semiconductor package which may have excellent heat dissipation characteristics and reliability, may have a warpage control effect and an electromagnetic shielding effect, and may improve a yield of a semiconductor chip.

[0006] One aspect of the present disclosure is to introduce a heat dissipation structure into an encapsulant for encapsulating a semiconductor chip, wherein at least a portion of the heat dissipation structure is embedded in the encapsulant.

[0007] According to one aspect of the present disclosure, a semiconductor package includes: a connection structure including one or more redistribution layers; a semiconductor chip disposed on the connection structure and having an active surface and an inactive surface opposite to the active surface, wherein a connection pad electrically connected to the redistribution layer is disposed on the active surface; and an encapsulant disposed on the connection structure and covering at least a portion of the inactive surface of the semiconductor chip. A conductor pattern layer is embedded in the encapsulant so that an exposed surface of the conductor pattern layer is exposed from the encapsulant, and a metal layer is disposed on the encapsulant and covers the exposed surface of the conductor pattern layer.

[0008] According to another aspect of the present disclosure, a semiconductor package includes: a connection structure including one or more redistribution layers; a semiconductor chip disposed on the connection structure and having an active surface and an inactive surface opposite to the active surface, wherein the active surface is provided with a connection pad electrically connected to the redistribution layer; a first encapsulant disposed on the connection structure and covering at least a portion of the inactive surface of the semiconductor chip; and a second encapsulant disposed on and covering the first encapsulant. A heat dissipation structure is disposed on the second encapsulant and is at least partially embedded in the second encapsulant.

[0009] According to another aspect of the present disclosure, a semiconductor package includes: a semiconductor chip having an active surface and an inactive surface opposite to the active surface, the active surface including connection pads disposed thereon; an encapsulant covering at least a portion of the inactive surface of the semiconductor chip; and a heat dissipation structure disposed on the encapsulant. The surface of the heat dissipation structure facing the encapsulant includes a plurality of conductor patterns protruding into the encapsulant. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description taken in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a schematic block diagram illustrating an example of an electronic device system.

[0012] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0013] Figure 3A and Figure 3B 2 is a schematic cross-sectional view showing states of a fan-in type semiconductor package before and after being packaged.

[0014] Figure 4 is a schematic cross-sectional view illustrating a packaging process of a fan-in type semiconductor package.

[0015] Figure 5 is a schematic cross-sectional view showing that a fan-in type semiconductor package is mounted on a printed circuit board and finally mounted on a main board of an electronic device.

[0016] Figure 6 is a schematic cross-sectional view showing that a fan-in type semiconductor package is embedded in a printed circuit board and finally mounted on a main board of an electronic device.

[0017] Figure 7 is a schematic cross-sectional view showing a fan-out type semiconductor package.

[0018] Figure 8is a schematic cross-sectional view showing that a fan-out type semiconductor package is mounted on a main board of an electronic device.

[0019] Fig. 9 is a schematic cross-sectional view illustrating an example of a semiconductor package.

[0020] Fig.10 It is taken along the line I-I' Fig. 9 Schematic plan view of a semiconductor package.

[0021] Fig.11 , Fig.12 and Fig.13 It is shown Fig. 9 Schematic diagram of an example manufacturing process of a semiconductor package.

[0022] Fig.14 Another example of a fan-out type semiconductor package is schematically shown.

[0023] Fig.15 Another example of a fan-out type semiconductor package is schematically shown. DETAILED DESCRIPTION

[0024] Hereinafter, embodiments of the present disclosure will be described below with reference to the accompanying drawings. For clarity, the shapes and sizes of elements in the drawings may be exaggerated or reduced.

[0025] Electronic Devices

[0026] Figure 1 is a block diagram schematically illustrating an exemplary embodiment of an electronic device system.

[0027] Referring to the drawings, the electronic device 1000 may include a mainboard 1010. The mainboard 1010 may be physically and / or electrically connected to chip-related components 1020, network-related components 1030, and other components 1040. They may also be combined with other components to be described later through various signal lines 1090.

[0028] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), flash memory, etc.; application processor chips, such as central processing units (e.g., CPU), graphics processors (e.g., GPU), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; logic chips, such as analog-to-digital converters, application-specific ICs (ASICs), etc.; etc., but are not limited thereto, and may include other types of chip-related components. These chip-related components 1020 may be combined with each other.

[0029] The network-related components 1030 may include components operating according to the following protocols: Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, Long Term Evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G protocol, 4G protocol, and 5G protocol, as well as any other wireless protocol and wired protocol specified later, but are not limited thereto, but may also include any other various wireless standards or protocols or wired standards or protocols. The network-related components 1030 may also be combined with the chip-related components 1020.

[0030] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramics (LTCC), electromagnetic interference (EMI) filters, multilayer ceramic condensers (MLCC), but are not limited thereto and may include other passive components for various other purposes. In addition to being combined with chip-related components 1020 and / or network-related components 1030, other components 1040 may also be combined with each other.

[0031] Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and / or electrically connected to the mainboard 1010. The other components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, an audio codec (not shown), a video codec (not shown), a power amplifier (not shown), a compass (not shown), an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a mass storage device (e.g., a hard disk drive) (not shown), a compact disk (CD) drive (not shown), a digital versatile disk (DVD) drive (not shown), etc., but are not limited thereto and may include other components for various purposes according to the type of the electronic device 1000.

[0032] The electronic device 1000 may be a smart phone, a personal digital assistant, a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet computer, a laptop, a netbook, a television, a video game console, a smart watch, an automotive component, etc., but is not limited thereto and may be any other electronic device that processes data.

[0033] Figure 2 is a perspective view schematically illustrating an exemplary embodiment of an electronic device.

[0034] Referring to the accompanying drawings, the semiconductor package may be applied to various electronic devices as described above for various purposes. For example, a printed circuit board 1110 such as a main board may be included in the body 1101 of the smart phone 1100. In addition, various components 1120 may be physically and / or electrically connected to the printed circuit board 1110. In addition, other components (such as a camera 1130) that may or may not be physically and / or electrically connected to the printed circuit board 1110 may be accommodated in the body 1101. A portion of the components 1120 may be chip-related components, such as but not limited to the semiconductor package 1121. The electronic device is not necessarily limited to the smart phone 1100, but may be other electronic devices as described above.

[0035] Semiconductor Package

[0036] Generally, a semiconductor chip may have many microelectronic circuits integrated therein, but the semiconductor chip itself is not necessarily used as a finished semiconductor product, and the semiconductor chip may be damaged by external physical impact or chemical impact. Therefore, the semiconductor chip itself may not be used as it is, but may be packaged and used as an electronic device, etc. in such a package state.

[0037] Considering the electrical connection, the semiconductor package can be used in a case where there is a difference in circuit width between the semiconductor chip and the main board of the electronic device, for example. Specifically, for the semiconductor chip, the size of the connection pad (pad, or "pad") and the spacing between the connection pads are very small and narrow, while the size of the component mounting pad and the spacing between the component mounting pads are much larger and wider than the specifications of the semiconductor chip, respectively. Therefore, since it is difficult to directly mount the semiconductor chip on such a main board, there is a need for a packaging technology that can alleviate the difference in circuit width between the semiconductor chip and the main board.

[0038] Semiconductor packages manufactured by such packaging technology may be classified into fan-in type semiconductor packages and fan-out type semiconductor packages according to their structures and uses.

[0039] Hereinafter, a fan-in type semiconductor package and a fan-out type semiconductor package will be described in more detail with reference to the accompanying drawings.

[0040] Fan-in semiconductor package

[0041] Figure 3A and Figure 3B is a cross-sectional view schematically showing states of a fan-in type semiconductor package before and after being packaged.

[0042] Figure 4 is a cross-sectional view schematically illustrating a packaging process of a fan-in type semiconductor package.

[0043] Referring to the accompanying drawings, the semiconductor chip 2220 may be an integrated circuit (IC) in a bare state. The body 2221 may include silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. The connection pad 2222 may include a conductive material such as aluminum (Al) formed on one surface of the body 2221. A passivation film 2223 such as an oxide film, a nitride film, etc. may be formed on one surface of the body 2221 and cover at least a portion of the connection pad 2222. At this time, since the connection pad 2222 is very small, it may be difficult to mount the integrated circuit (IC) on even a medium-sized printed circuit board (PCB) and a main board of an electronic device.

[0044] In order to redistribute the connection pads 2222, the connection structure 2240 may be formed on the semiconductor chip 2220 according to the size of the semiconductor chip 2220. The connection structure 2240 may be prepared by forming an insulating layer 2241 on the semiconductor chip 2220 using an insulating material such as a photosensitive dielectric (PID) resin; forming a via hole 2243h that opens the connection pad 2222; and forming a wiring pattern 2242 and a via 2243. Thereafter, a passivation layer 2250 for protecting the connection structure 2240 may be formed, an opening 2251 may be formed, and an under bump metallization layer 2260 may be formed, etc. For example, a fan-in type semiconductor package 2200 including, for example, a semiconductor chip 2220, a connection structure 2240, a passivation layer 2250, and an under bump metallization layer 2260 may be formed by a series of processes.

[0045] As described above, a fan-in semiconductor package may be a package type in which all the connection pads (e.g., input / output (I / O) terminals) of a semiconductor chip are arranged inside the component. The fan-in semiconductor package may have good electrical characteristics and may be produced at a relatively low cost. Therefore, many components in a smart phone may be manufactured in the form of a fan-in semiconductor package. Specifically, development is being made in the direction of simultaneously achieving a small size and achieving fast signal transmission.

[0046] In a fan-in semiconductor package, since all I / O terminals should be arranged inside the semiconductor chip, there may be many spatial limitations. Therefore, such a structure may be difficult to apply to a semiconductor chip with a large number of I / O terminals or a semiconductor chip with a small size. In addition, due to such problems, it may not be possible to directly install and use the fan-in semiconductor package on the mainboard of an electronic device. Even when the size and spacing of the I / O terminals of the semiconductor chip are increased in the redistribution process, they still do not have a size and spacing sufficient to be directly installed on the mainboard of the electronic device.

[0047] Figure 5is a cross-sectional view schematically showing that a fan-in type semiconductor package is mounted on a printed circuit board and finally mounted on a main board of an electronic device.

[0048] Figure 6 is a cross-sectional view schematically showing that a fan-in type semiconductor package is embedded in a printed circuit board and finally mounted on a main board of an electronic device.

[0049] Referring to the drawings, the fan-in type semiconductor package 2200 may be configured such that the connection pads 2222 (i.e., I / O terminals) of the semiconductor chip 2220 are redistributed again through the printed circuit board 2301, and the fan-in type semiconductor package 2200 mounted on the printed circuit board 2301 is mounted on the main board 2500 of the electronic device. At this time, the solder balls 2270 and the like may be fixed by the bottom filling resin 2280, and the outside of the semiconductor chip 2220 may be covered with the molding material 2290 and the like. Alternatively, the fan-in type semiconductor package 2200 may be embedded in a separate printed circuit board 2302, and the connection pads 2222 (i.e., I / O terminals) of the semiconductor chip 2220 may be redistributed again in an embedded form, and the fan-in type semiconductor package 2200 may be finally mounted on the main board 2500 of the electronic device.

[0050] As mentioned above, it may be difficult to directly mount a fan-in type semiconductor package on a main board of an electronic device. Therefore, the fan-in type semiconductor package may be mounted on a separate printed circuit board and then mounted on the main board of the electronic device through a packaging process, or may be mounted on the main board of the electronic device in a form embedded in a printed circuit board.

[0051] Fan-out semiconductor packages

[0052] Figure 7 is a cross-sectional view schematically showing a fan-out type semiconductor package.

[0053] Referring to the drawings, in a fan-out type semiconductor package 2100, for example, the outside of a semiconductor chip 2120 may be protected by an encapsulant 2130, and a connection pad 2122 of the semiconductor chip 2120 may be redistributed to the outside of the semiconductor chip 2120 by a connection structure 2140. A passivation layer 2150 may also be formed on the connection structure 2140. An under bump metallization layer 2160 may also be formed on an opening of the passivation layer 2150. A solder ball 2170 may also be formed on the under bump metallization layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, a connection pad 2122, and the like. The connection structure 2140 may include: an insulating layer 2141; a wiring layer 2142 formed on the insulating layer 2141; and a via 2143 to electrically connect the connection pad 2122 and the wiring layer 2142.

[0054] A fan-out semiconductor package can be formed by redistributing the I / O terminals to the outside of the semiconductor chip via a connection structure formed on the semiconductor chip. As described above, in a fan-in semiconductor package, all the I / O terminals of the semiconductor chip should be arranged inside the semiconductor chip. When the size of the element is reduced, the size and pitch of the ball should be reduced. Therefore, a standardized ball layout may not be used. On the other hand, in a fan-out semiconductor package, the I / O terminals can be redistributed from the semiconductor chip to the outside through a connection structure formed on the semiconductor chip. Although the size of the semiconductor chip is reduced, the standardized ball layout can still be used as it is. Therefore, as described later, the fan-out semiconductor package can be mounted on the mainboard of an electronic device without using a separate printed circuit board.

[0055] Figure 8 is a cross-sectional view schematically showing that a fan-out type semiconductor package is mounted on a main board of an electronic device.

[0056] Referring to the drawings, the fan-out type semiconductor package 2100 may be mounted on a main board 2500 of an electronic device through solder balls 2170, etc. For example, as described above, the fan-out type semiconductor package 2100 may include a connection structure 2140 located on the semiconductor chip 2120, and the connection structure 2140 may redistribute the connection pads 2122 to a fan-out area outside the size of the semiconductor chip 2120. The standardized ball layout may be used as it is, and as a result, the fan-out type semiconductor package 2100 may be mounted on the main board 2500 of the electronic device without using a separate printed circuit board, etc.

[0057] As mentioned above, since the fan-out semiconductor package can be mounted on the mainboard of the electronic device without using a separate printed circuit board, the fan-out semiconductor package can be manufactured to be thinner than the fan-in semiconductor package using a printed circuit board. Therefore, the fan-out semiconductor package can be miniaturized and thinned. Due to the excellent thermal and electrical properties of the fan-out semiconductor package, it can also be suitable for mobile products. In addition, the fan-out semiconductor package can be implemented to be more compact than the ordinary laminate package (POP) type using a printed circuit board (PCB), and problems caused by the bending phenomenon can be prevented.

[0058] A fan-out semiconductor package may refer to a packaging technology used to mount a semiconductor chip on a mainboard of an electronic device, etc. and to protect the semiconductor chip from external impacts, and may have a different concept from a printed circuit board (PCB) (such as a printed circuit board in which a fan-in semiconductor package is embedded), which differ from each other in specifications, uses, etc.

[0059] Hereinafter, a semiconductor package having a novel structure will be described with reference to the accompanying drawings, which significantly reduces the mounting area of ​​semiconductor chips and passive components, significantly reduces the electrical path between the semiconductor chips and passive components, significantly reduces process defects such as undulations and cracks, and further, easily connects electrodes of passive components to connecting vias through a laser via process, etc.

[0060] Fig. 9 is a schematic cross-sectional view illustrating an example of a semiconductor package.

[0061] Fig.10 It is taken along line I-I' Fig. 9 Schematic plan view of a semiconductor package.

[0062] A semiconductor package 100A according to example embodiments (which may also be referred to as a package 100A or a fan-out type semiconductor package 100A) may include: a connection structure 140 including one or more redistribution layers 142; a semiconductor chip 120 disposed on the connection structure 140 and having an active surface and an inactive surface opposite to the active surface, on which a connection pad 122 electrically connected to the redistribution layer 142 is disposed; an encapsulant 130 disposed on the connection structure 140 and covering at least a portion of the inactive surface of the semiconductor chip 120; and a heat dissipation structure 180 disposed on the encapsulant 130 and at least partially embedded in the encapsulant 130. The heat dissipation structure 180 may include: a conductor pattern layer 181 embedded in the encapsulant 130 such that one surface of the conductor pattern layer 181 is exposed from the encapsulant 130; and a metal layer 182 disposed on one exposed surface of the encapsulant 130 and the conductor pattern layer 181. The heat dissipation structure 180 may further include a conductive adhesive 183 disposed on the metal layer 182 , and a heat dissipation member 184 disposed on the conductive adhesive 183 .

[0063] In recent years, as the functions of semiconductor chips have improved, it has become important to effectively release the heat generated therefrom. For this purpose, generally, the generated heat has been dissipated in such a way that a heat dissipation member such as a metal plate is simply attached to the upper part of the semiconductor package with an adhesive, or a metal layer is simply plated. In this case, since the distance between the heat dissipation member and the semiconductor chip is quite large, there may be a problem in which it is difficult to obtain a sufficient heat dissipation effect. In addition, since the heat dissipation member will be formed on the manufactured semiconductor package, when a defect occurs in the process of forming the heat dissipation member, the semiconductor chip should also be discarded, thereby reducing the yield of the semiconductor chip manufacturing process. Specifically, when a heat dissipation member such as a metal plate is simply attached, the adhesion using the encapsulant or the molding material will be low, which leads to the problem of peeling risk.

[0064] The semiconductor package 100A according to example embodiments may include a heat dissipation structure 180 disposed on and at least partially embedded in the encapsulant 130. The heat dissipation structure 180 may include a conductor pattern layer 181 embedded in the encapsulant 130 such that one surface of the conductor pattern layer 181 is exposed from or through the encapsulant 130, and a metal layer 182 disposed on the encapsulant 130 and one exposed surface of the conductor pattern layer 181. The embedded conductor pattern layer 181 may be closer to an ineffective surface of the semiconductor chip 120 (e.g., closer to the ineffective surface than to an effective surface of the semiconductor chip 120), and may more reliably dissipate heat generated from the semiconductor chip 120 in an upward direction. The conductor pattern layer 181 may be embedded in the encapsulant 130 to have good adhesion, and the metal layer 182 may also be formed to cover and contact the surface of the conductor pattern layer 181 exposed through the encapsulant 130 and the surface of the encapsulant 130 exposed through the conductor pattern layer 181 to have excellent adhesion.

[0065] The heat dissipation structure 180 may also include a conductive adhesive 183 disposed on the metal layer 182 and a heat dissipation member 184 disposed on the conductive adhesive 183 to better dissipate heat. In this case, since the conductive adhesive 183 is disposed on the metal layer 182 instead of the encapsulant 130 (the encapsulant 130 may be formed using an organic material), better adhesion may also be exerted. Since the semiconductor package 100A according to the example embodiment has a heat dissipation structure 180 of a special structure, both the heat dissipation effect and the reliability may be improved compared to a conventional semiconductor package. In addition, by arranging such a metal material, the warping problem of the package 100A may also be improved, and an electromagnetic wave shielding effect may also be provided. The conductor pattern layer 181 and the metal layer 182 of the heat dissipation structure 180 may be manufactured separately using a carrier or the like, so that only a good product may be introduced into the upper part of the package 100A. Therefore, the yield problem of the manufacturing process of the semiconductor chip 120 may be improved, and the entire process time of the product may not be affected.

[0066] The encapsulant 130 may include: a first encapsulant 130a disposed on the connection structure 140 and covering at least a portion of the semiconductor chip 120 (such as at least a portion of the ineffective surface); and a second encapsulant 130b disposed on the first encapsulant 130a and covering the first encapsulant 130a. The first encapsulant 130a and the second encapsulant 130b may be provided as different layers separated from each other. In this case, the conductor pattern layer 181 may be embedded in the second encapsulant 130b so that one exposed surface of the conductor pattern layer 181 is exposed from the second encapsulant 130b, and the metal layer 182 may be provided on the second encapsulant 130b to cover one exposed surface of the conductor pattern layer 181. The conductor pattern layer 181 and the metal layer 182 may be formed on a carrier, and then the conductor pattern layer 181 and the metal layer 182 may be introduced by laminating the conductor pattern layer 181 and the metal layer 182 on the first encapsulant 130a of the package 100A while being covered by the second encapsulant 130b. In this case, since the conductor pattern layer 181 is embedded in the second encapsulant 130b and the metal layer 182 covers the second encapsulant 130b in an uncured state of the second encapsulant 130b, the adhesion between the heterogeneous materials may be improved to reduce the risk of peeling at the interface. In addition, the connection of the insulating resin between the first encapsulant 130a and the second encapsulant 130b may have a better adhesion effect, and the reliability of the package 100A may be further improved.

[0067] The conductor pattern layer 181 may include a plurality of metal patterns 181P, and at least a portion of the plurality of metal patterns 181P may be spaced apart from each other and face the ineffective surface of the semiconductor chip 120 at a predetermined distance from the ineffective surface of the semiconductor chip 120. In this case, adhesion can be improved while maintaining an excellent heat dissipation effect by an embossing effect. The metal layer 182 may have the form of a single metal plate to provide a flat surface. The metal layer 182 may extend across the space between the metal patterns 181P of the conductor pattern layer 181, and may extend across the ineffective surface of the semiconductor chip 120 as a whole. The metal layer 182 may contact the encapsulant 130 between the plurality of conductor patterns 181P. In this case, the bonding reliability of the heat dissipation member 184 may be further improved by the conductive adhesive 183. The conductive adhesive 183 may include a thermally conductive interface material (TIM), and the heat dissipation member 184 may include a metal block. In this case, the heat dissipation effect may be maximized.

[0068] The conductor pattern layer 181 may include a first conductor layer 181a in contact with the metal layer 182 and embedded in the encapsulant 130, and a second conductor layer 181b disposed on the first conductor layer 181a and embedded in the encapsulant 130. The first conductor layer 181a may be a seed layer formed on one surface of the metal layer 182 located on the carrier by an electroless plating process such as metal sputtering, and the second conductor layer 181b may be a plated layer formed by an electroplating process using the first conductor layer 181a as a seed layer. Therefore, the thickness of the second conductor layer 181b may be thicker than that of the first conductor layer 181a. As described above, the conductor pattern layer 181 may be embedded in the encapsulant 130 in such a manner that the seed layer and the plated layer are reversed (for example, when the package is disposed on Fig. 9 The seed layer may be disposed above the plating layer when in the orientation shown in FIG.

[0069] The semiconductor package 100A according to the example embodiment may further include a frame 110, which is disposed on the connection structure 140 and has a through hole 110H. In this case, the semiconductor chip 120 may be disposed in the through hole 110H so that its effective surface faces the connection structure 140, and the encapsulant 130 (particularly the first encapsulant 130a) may cover or directly contact at least a portion of the frame 110 and may fill at least a portion of the through hole 110H. When the frame 110 is provided, better rigidity may be introduced into the package, and thickness uniformity of the encapsulant 130 (particularly the first encapsulant 130a) may be helped to ensure. The frame 110 may include: an insulating layer 111 in which the through hole 110H is formed; a first metal layer 115a and a second metal layer 115b, which are respectively disposed on the back-facing lower and upper surfaces of the insulating layer 111; and a third metal layer 115c, which is disposed on the wall surface of the through hole 110H. In this case, a better heat dissipation effect may be achieved. In addition, the electromagnetic wave shielding effect and the warpage improvement effect can be further enhanced.

[0070] As shown, the semiconductor package 100A according to the example embodiment may further include: a passivation layer 150, which is disposed on the lower side of the connection structure 140 and has a plurality of openings for respectively opening or exposing at least a portion of the lowest redistribution layer 142 in the redistribution layers 142; a plurality of under bump metals 160, which are disposed on or in the plurality of openings and are electrically connected to the lowest redistribution layer 142; and a plurality of electrical connection metals 170, which are disposed on the lower side of the passivation layer 150 and are electrically connected to the plurality of under bump metals 160.

[0071] Hereinafter, each configuration included in the semiconductor package 100A according to one example will be described in more detail.

[0072] The frame 110 can further improve the rigidity of the package 100A according to the specific material of the insulating layer 111, and can play a role in ensuring the uniformity of the thickness of the first encapsulant 130a. The frame 110 may have a through hole 110H passing through the insulating layer 111. As needed, the semiconductor chip 120 may be arranged in the through hole 110H, and the passive components (not shown) may be arranged together (for example, in the through hole 110H with the semiconductor chip 120 or in different through holes in the frame 110). The through hole 110H may have a wall surface surrounding the semiconductor chip 120, but the present disclosure is not limited thereto. The metal layers 115a, 115b and 115c may be respectively arranged on the lower and upper surfaces of the insulating layer 111 and the wall surface of the through hole 110H, and may be connected to each other or directly contacted. The metal layers 115a, 115b and 115c may have a better heat dissipation effect, and may further enhance the electromagnetic wave shielding effect and the warpage improvement effect.

[0073] The material of the insulating layer 111 is not particularly limited. For example, an insulating material can be used. As the insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or a resin in which these resins are mixed with an inorganic filler (for example, ABF (Ajinomoto Build-up Film) etc.) can be used. Alternatively, a material in which the above-mentioned resin is impregnated with an inorganic filler in a core material such as glass fiber, glass cloth, glass fabric, etc. (for example, a prepreg etc.) can be used.

[0074] The metal layers 115a, 115b, and 115c may be formed using a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), alloys thereof, etc. The metal layers 115a, 115b, and 115c may be electrically connected to a ground pattern and / or a power pattern of the redistribution layer 142 to perform the functions of the ground pattern and / or the power pattern as needed.

[0075] The semiconductor chip 120 may be an integrated circuit (IC) in which hundreds to millions of devices are integrated into one chip. In this case, the integrated circuit may be an application processor chip, such as a central processing unit (e.g., CPU), a graphics processor (e.g., GPU), a digital signal processor, a cryptographic processor, a microprocessor, etc., but is not limited thereto, and the integrated circuit may be a power management integrated circuit (PMIC), or may be: a memory chip, such as a volatile memory (e.g., a dynamic random access memory (DRAM)), a non-volatile memory (e.g., a read-only memory (ROM)), a flash memory, etc.; a logic chip, such as an analog-to-digital converter, an application-specific IC (ASIC), etc.

[0076] The semiconductor chip 120 may be an integrated circuit in a bare state in which no separate bump or wiring layer is formed. The present disclosure is not limited thereto, and may be a packaged integrated circuit as required. The integrated circuit may be formed based on an active wafer. In this case, silicon (Si), germanium (Ge), gallium arsenide (GaAs), etc. may be used as the base material of the main body 121 of the semiconductor chip 120. Various circuits may be formed in the main body 121. The connection pad 122 may be used to electrically connect the semiconductor chip 120 to other components, and a conductive material such as aluminum (Al) may be used as its formation material without any particular restrictions. A passivation film 123 exposing the connection pad 122 may be formed on the main body 121. The passivation film 123 may be an oxide film or a nitride film, etc., or may be a double layer of an oxide film and a nitride film. An insulating film (not shown) or the like may be further provided at other appropriate locations. In addition, in the semiconductor chip 120, the surface on which the connection pad 122 is provided may become an effective surface, and the surface opposite thereto may become an ineffective surface. At this time, when the passivation film 123 is formed on the effective surface of the semiconductor chip 120 , the effective surface of the semiconductor chip 120 may determine a positional relationship based on the lowermost surface of the passivation film 123 .

[0077] The first encapsulant 130a may encapsulate the frame 110 and the semiconductor chip 120, and may also fill at least a portion of the through hole 110H. The first encapsulant 130a may include an insulating material. Examples of insulating materials may include resins such as thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide) or resins including the above materials and reinforcing materials such as inorganic fillers (specifically, ABF, FR-4, BT resins, etc.). In addition, known molding materials such as EMC may be used. In addition, as required, photosensitive materials such as photosensitive encapsulants (PIE) may be used. As required, a material in which an insulating resin such as a thermosetting resin or a thermoplastic resin is impregnated with a core material such as an inorganic filler and / or glass fiber, glass cloth, glass fabric, etc. may be used.

[0078] The second encapsulant 130b may also provide an insulating layer on the back side of the package 100A, and the conductor pattern layer 181 may be embedded therein. The second encapsulant 130b may also include an insulating material. Examples of insulating materials may include resins such as thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or resins including the above materials and reinforcing materials such as inorganic fillers (specifically ABF, FR-4, BT resins, etc.). In addition, as required, photosensitive materials such as photosensitive dielectric (PID) materials may be used. As required, materials in which an insulating resin such as a thermosetting resin or a thermoplastic resin is impregnated with a core material such as an inorganic filler and / or glass fiber, glass cloth, glass fabric, etc. may be used. The second encapsulant 130b may be formed using the same material as the first encapsulant 130a, or may be formed using different materials. The first encapsulant 130a and the second encapsulant 130b may be provided as different layers separated from each other, and may be separated from each other.

[0079] The connection structure 140 may redistribute the connection pads 122 of the semiconductor chip 120. Tens to hundreds of connection pads 122 of the semiconductor chip 120 having various functions may be redistributed through the connection structure 140. The connection pads 122 may be physically connected to the outside and / or may be electrically connected to the outside through the electrical connection metal 170 according to their functions. The connection structure 140 may include: an insulating layer 141; a redistribution layer 142 disposed on the insulating layer 141; and a connection via 143 penetrating the insulating layer 141 and electrically connecting the connection pad 122 and the redistribution layer 142. The number of insulating layers, redistribution layers, connection vias, and connection pads may be more or less than the number of insulating layers, redistribution layers, connection vias, and connection pads shown in the drawings.

[0080] As the material of the insulating layer 141, an insulating material can be used. In this case, a photosensitive dielectric (PID) material can be used as the insulating material. In this case, a fine pitch can be introduced by a photo-via process. As in the usual case, tens to hundreds of connection pads 122 in the semiconductor chip 120 can be redistributed very effectively. A plurality of insulating layers 141 may have boundaries with each other, or the boundaries between them may not be clear.

[0081] The redistribution layer 142 may be redistributed to electrically connect the connection pads 122 of the semiconductor chip 120 to the electrical connection metal 170. As a material for forming the redistribution layer 142, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof may be used. Depending on the desired design, the redistribution layer 142 may also perform various functions. For example, a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. may be included. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. In addition, the redistribution layer 142 may include various types of via pads, electrical connection metal pads, etc. The redistribution layer 142 may be formed by a plating process and may include a seed layer and a conductor layer.

[0082] The connection via 143 can electrically connect the redistribution layer 142 formed on different layers, and can electrically connect the connection pad 122 of the semiconductor chip 120 to the redistribution layer 142. When the semiconductor chip 120 is a bare chip, the connection via 143 can be in physical contact with the connection pad 122. As a material for forming the connection via 143, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof can be used. The connection via 143 may include a signal via, a power via, a ground via, etc. The power via and the ground via may be the same via. The connection via 143 may also be a filled via filled with a metal material, or may be a conformal via formed along the wall surface of the via hole. In addition, the connection via 143 may have a tapered shape. The connection via 143 may also be formed using a plating process, and may include a seed layer and a conductor layer.

[0083] The passivation layer 150 may be an additional structure for protecting the connection structure 140 from external physical damage or chemical damage, etc. The passivation layer 150 may include a thermosetting resin. For example, the passivation layer 150 may be ABF, but is not limited thereto. The passivation layer 150 may have an opening for opening or exposing at least a portion of the lowest redistribution layer 142 in the redistribution layer 142. The number of openings may be in the range of tens to tens of thousands or more or less. Each of the openings may be formed by a plurality of holes. A surface mount component such as a capacitor may be disposed on the lower surface of the passivation layer 150 to be electrically connected to the redistribution layer 142, and as a result, may be electrically connected to the semiconductor chip 120. Although not shown in the drawings, a separate surface mount component such as a capacitor (not shown) may also be disposed on the lower surface of the passivation layer 150, and may be electrically connected to the connection pad 122 through the redistribution layer 142.

[0084] The under bump metal 160 may also be an additional component, which improves the connection reliability of the electrical connection metal 170 and thus improves the board-level reliability of the fan-out semiconductor package 100A according to an example. The under bump metal 160 may be provided in a number of tens to tens of thousands, and may be provided in a number more or less than the number. Each under bump metal 160 may be electrically connected to the open lowermost redistribution layer 142 formed at the opening of the passivation layer 150. The under bump metal 160 may be formed by a known metallization method using a known conductive material (e.g., metal), but is not limited thereto.

[0085] The electrical connection metal 170 may also be an additional component (a structure for physically connecting and / or electrically connecting the semiconductor package 100A to the outside). For example, the semiconductor package 100A may be mounted on a mainboard of an electronic device through the electrical connection metal 170. The electrical connection metal 170 may be disposed on the passivation layer 150 and may be electrically connected to the under-bump metal 160, respectively. The electrical connection metal 170 may include a low melting point metal, for example, tin (Sn) or an alloy including tin (Sn). More specifically, the electrical connection metal 170 may be formed using solder or the like, but this may be merely an example embodiment, and the material is not particularly limited thereto.

[0086] The electrical connection metal 170 may be a pad, a solder ball, a pin, etc. The electrical connection metal 170 may be formed using multiple layers or a single layer. In the case of forming using multiple layers, the electrical connection metal 170 may include a copper column and a solder. In the case of forming using a single layer, a tin-silver solder or copper may be included, but this may be only an example and not limited thereto. There is no particular limitation on the number, spacing, arrangement type, etc. of the electrical connection metal 170, and the technician may make full modifications according to the design specifications. For example, depending on the number of connection pads 122, the number of electrical connection metals 170 may be in the range of tens to thousands, and may be greater than or less than the above range.

[0087] At least one electrical connection metal 170 may be provided in the fan-out region. The fan-out region may be a region other than the region in which the semiconductor chip 120 is provided (e.g., a region outside the region overlapping the semiconductor chip 120). The fan-out type package may be more reliable than the fan-in type package, may have many I / O terminals, and may facilitate 3D interconnection. In addition, a package thinner than a ball grid array (BGA) package, a land grid array (LGA) package, etc. may be manufactured, and may have excellent price competitiveness.

[0088] The conductor pattern layer 181 may be embedded in the second encapsulant 130b to provide a plurality of metal patterns 181P that can perform a heat dissipation function on the back side of the package 100A. The conductor pattern layer 181 may also include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. The conductor pattern layer 181 may be formed by a known plating process and may include a first conductor layer 181a (seed layer) and a second conductor layer 181b (plating layer). The conductor pattern layer 181 may be formed to be relatively thick to shorten the distance from the ineffective surface of the semiconductor chip 120. For example, the thickness of the conductor pattern layer 181 may be greater than the thickness of each of the redistribution layers 142.

[0089] The metal layer 182 may be disposed on the second encapsulant 130b to provide a metal plate capable of performing a heat dissipation function on the back side of the package 100A. The metal layer 182 may also include a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or an alloy thereof. The metal layer 182 may completely cover the upper surface of the second encapsulant 130b and the upper surface of the exposed conductor pattern layer 181.

[0090] The conductive adhesive 183 may be any material that can transfer heat, regardless of the type of the material, and may include, for example, a thermal interface material (TIM). The heat dissipation member 184 may also be any material that has a heat dissipation effect, and may include, for example, a metal block (more specifically, a copper block). For excellent heat dissipation effect, the heat dissipation member 184 may be thicker than the thickness of the conductive adhesive 183, the thickness of the metal layer 182, and the thickness of the conductor pattern layer 181.

[0091] Figures 11 to 13 It is shown Fig. 9 A schematic diagram of an example of a manufacturing process of a semiconductor package.

[0092] Reference Fig.11, first, a carrier 210 having a metal layer 182 formed on at least one surface thereof may be prepared. The carrier 210 may include a release layer (not shown) disposed between the carrier 210 and the metal layer 182 so as to be more easily peeled off at the interface with the metal layer 182. Next, a conductor pattern layer 181 may be formed on the metal layer 182 using a plating process. The conductor pattern layer 181 may be formed by: forming a first conductor layer 181a as a seed layer by an electroless plating process such as metal sputtering; and forming a second conductor layer 181b as a substantial plating layer on the first conductor layer 181a by an electrolytic plating process. As a plating method used, an additive process (AP), a semi-AP (SAP), a modified SAP (MSAP), a tenting process, etc. may be used. Next, an ABF or the like in an uncured state may be stacked on the metal layer 182 so that the conductor pattern layer 181 may be embedded in the ABF or the like, and cured to form a second encapsulant 130b. The curing process may be performed later with the first encapsulant 130a.

[0093] Reference Fig.12 , a frame 110 including an insulating layer 111 having a through hole 110H and metal layers 115a, 115b and 115c may be attached to a tape 220. A semiconductor chip 120 formed using a body 121, a connection pad 122, a passivation film 123, etc. may be disposed in the through hole 110H and may be attached to the tape 220 in a face-down manner. ABF or the like in an uncured state may be used to cover the semiconductor chip 120 on the frame 110 and the tape 220, and a first encapsulant 130a filling the through hole 110H may be formed. The first encapsulant 130a may be cured. Thereafter, a metal layer 182 and a conductor pattern layer 181 covered with a second encapsulant 130b, which is manufactured separately, may be laminated so that the first encapsulant 130a and the second encapsulant 130b are connected to each other. After lamination, the first encapsulant 130a may be cured together with the second encapsulant 130b.

[0094] Next, the tape 220 may be removed, and the insulating layer 141 may be formed by applying PID or the like to the area where the tape 220 has been removed and hardening the PID or the like. After forming the via hole by the photolithography process, the operation of forming the redistribution layer 142 and the connection via 143 may be repeated once, twice, or more times to form the connection structure 140. In addition, as needed, the passivation layer 150 may be formed using ABF or the like, and one or more openings may be formed in the passivation layer 150, and a plurality of under bump metals 160 may be formed by filling the openings in a plating process (refer to Fig.13 ).

[0095] Reference Fig.13, and then, the carrier 210 may be peeled off from the metal layer 182. Next, a conductive adhesive 183 may be formed on the metal layer 182 using a thermal interface material (TIM) or the like, and a heat dissipation member 184 such as a metal block may be attached through the conductive adhesive 183. As needed, an electrical connection metal 170 connected to the under bump metal 160 may be formed on the passivation layer 150, and then may be reflowed to manufacture the semiconductor package 100A according to the above example.

[0096] Fig.14 Another example of a fan-out type semiconductor package is schematically shown.

[0097] Referring to the drawings, a semiconductor package 100B according to another example may have a different configuration from the frame 110 in the semiconductor package 100A according to the above example. For example, the frame 110 may include: a first insulating layer 111a in contact with the connection structure 140; a first wiring layer 112a in contact with the connection structure 140 and embedded in the first insulating layer 111a; a second wiring layer 112b disposed on a side of the first insulating layer 111a opposite to a side on which the first wiring layer 112a is disposed; a second insulating layer 111b disposed on the first insulating layer 111a and covering the second wiring layer 112b; and a third wiring layer 112c disposed on a side of the second insulating layer 111b opposite to a side in which the second wiring layer 112b is embedded. The first wiring layer 112a and the second wiring layer 112b may be electrically connected to the first wiring via 113a passing through the first insulating layer 111a, and the second wiring layer 112b and the third wiring layer 112c may be electrically connected to the second wiring via 113b passing through the second insulating layer 111b. The first wiring layer 112a, the second wiring layer 112b, and the third wiring layer 112c may be electrically connected to the connection pad 122 through the redistribution layer 142 and the connection via 143 according to their functions. The frame 110 may be used as a vertical electrical connection path having the wiring layers 112a, 112b, and 112c, and the design of the redistribution layer 142 of the connection structure 140 may be simplified to promote its slimming. In addition, the yield problem of the semiconductor chip 120 caused by defects occurring in the process of forming the connection structure 140 may be improved.

[0098] The material of the insulating layers 111a and 111b is not particularly limited. For example, an insulating material can be used. As the insulating material, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or a mixture of these resins and an inorganic filler, or a resin in which the above resin and an inorganic filler such as silica are impregnated in a core material such as glass fiber, glass cloth, or glass fabric (e.g., a prepreg) can be used.

[0099] The wiring layers 112a, 112b and 112c together with the wiring vias 113a and 113b can provide a vertical electrical connection path for the package, and can play a role in redistributing the connection pads 122. As materials for forming the wiring layers 112a, 112b and 112c, metal materials such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or their alloys can be used. The wiring layers 112a, 112b and 112c can perform various functions according to the desired design of the layers. For example, a ground (GND) pattern, a power (PWR) pattern, a signal (S) pattern, etc. may be included. Here, the signal (S) pattern may include various signal patterns other than the ground (GND) pattern, the power (PWR) pattern, etc., such as a data signal pattern, etc. The ground (GND) pattern and the power (PWR) pattern may be the same pattern. The wiring layers 112a, 112b, and 112c may include various types of via pads, etc. The wiring layers 112a, 112b, and 112c may be formed by a known plating process, and may each include a seed layer and a conductor layer.

[0100] The thickness of each of the wiring layers 112a, 112b, and 112c may be thicker than the thickness of each of the redistribution layers 142. For example, the frame 110 may have a thickness equal to or greater than the thickness of the semiconductor chip 120. In order to maintain rigidity, a prepreg or the like may be selected as a material of the insulating layers 111a and 111b, and the wiring layers 112a, 112b, and 112c may be relatively thick. The connection structure 140 may provide a microcircuit and a high-density design. Therefore, a PID or the like may be selected as a material of the insulating layer 141, and the thickness of the redistribution layer 142 obtained thereby may be relatively thin.

[0101] The first wiring layer 112a may be recessed in the first insulating layer 111a. In this manner, in a case where the first wiring layer 112a is recessed in the first insulating layer 111a to have a step difference between the lower surface of the first insulating layer 111a in contact with the connection structure 140 and the lower surface of the first wiring layer 112a in contact with the connection structure 140, when the semiconductor chip 120 and the frame 110 are encapsulated with the first encapsulant 130a, it is possible to prevent the formation material (e.g., the material used to form the first encapsulant 130a) from seeping out and contaminating the first wiring layer 112a and / or contaminating the contact between the first wiring layer 112a and the redistribution layer 142.

[0102] The wiring vias 113a and 113b can electrically connect the wiring layers 112a, 112b and 112c formed on different layers, thereby forming an electrical path in the frame 110. As a material for forming the wiring vias 113a and 113b, a metal material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof can be used. The wiring vias 113a and 113b may include signal vias, power vias, ground vias, etc. The power vias and the ground vias may be the same vias. The wiring vias 113a and 113b may also be filled vias filled with a metal material, or may be conformal vias in which a metal material is formed along the wall surface of the via hole. In addition, the wiring vias 113a and 113b may each have a tapered shape. The wiring vias 113a and 113b may also be formed by a plating process, and may include a seed layer and a conductor layer.

[0103] When forming a hole for the first wiring via 113a, a portion of the pad of the first wiring layer 112a may be used as a barrier. In terms of process, the first wiring via 113a may have a tapered shape in which the width of the upper surface of the first wiring via 113a is wider than the width of its lower surface. In this case, the first wiring via 113a may be integrated with the pad pattern of the second wiring layer 112b. When forming a hole for the second wiring via 113b, a portion of the pad of the second wiring layer 112b may be used as a barrier. In terms of process, the second wiring via 113b may have a tapered shape in which the width of the upper surface of the second wiring via 113b is wider than the width of its lower surface. In this case, the second wiring via 113b may be integrated with the pad pattern of the third wiring layer 112c.

[0104] Although not shown in the drawings, a metal layer (not shown) may be provided on the wall surface of the through hole 110H of the frame 110 for the purpose of shielding electromagnetic waves or for heat dissipation, and the metal layer (not shown) may surround the semiconductor chip 120 .

[0105] Other details may be substantially the same as those described above with respect to the semiconductor package 100A according to the above example, and a detailed description thereof will be omitted.

[0106] Fig.15 Another example of a fan-out type semiconductor package is schematically shown.

[0107] Referring to the drawings, a semiconductor package 100C according to another example may have a different configuration from the frame 110 in the semiconductor package 100A according to the above-described example. For example, the frame 110 may include: a first insulating layer 111a; a first wiring layer 112a and a second wiring layer 112b, which are respectively disposed on the lower surface and the upper surface of the first insulating layer 111a facing away from each other; a second insulating layer 111b and a third insulating layer 111c, which are respectively disposed on the lower side and the upper side of the first insulating layer 111a facing away from each other and cover the first wiring layer 112a and the second wiring layer 112b, respectively; a third wiring layer 112c, which is disposed on the lower side of the second insulating layer 111b facing away from the side in which the first wiring layer 112a is embedded; and a fourth wiring layer 112c, which is disposed on the lower side of the second insulating layer 111b facing away from each other. The wiring layer 112d is provided on the upper side of the third insulating layer 111c opposite to the side in which the second wiring layer 112b is embedded; the first wiring via 113a penetrates the first insulating layer 111a and electrically connects the first wiring layer 112a and the second wiring layer 112b; the second wiring via 113b penetrates the second insulating layer 111b and electrically connects the first wiring layer 112a and the third wiring layer 112c; and the third wiring via 113c penetrates the third insulating layer 111c and electrically connects the second wiring layer 112b and the fourth wiring layer 112d. The first wiring layer 112a, the second wiring layer 112b, the third wiring layer 112c, and the fourth wiring layer 112d can be electrically connected to the connection pad 122 through the redistribution layer 142. Since the frame 110 has a relatively large number of wiring layers 112a, 112b, 112c, and 112d, the connection structure 140 can be further simplified.

[0108] The first insulating layer 111a may be thicker than the second insulating layer 111b and the third insulating layer 111c. The first insulating layer 111a may be relatively thick to maintain rigidity, and the second insulating layer 111b and the third insulating layer 111c may be introduced to have a relatively larger number of wiring layers. In a similar manner, the height and average diameter of the first wiring via 113a penetrating the first insulating layer 111a may be greater than the height and average diameter of the second wiring via 113b penetrating the second insulating layer 111b and the height and average diameter of the third wiring via 113c penetrating the third insulating layer 111c. In addition, the first wiring via 113a may have an hourglass shape or a cylindrical shape, while the second wiring via 113b and the third wiring via 113c may have a tapered shape with directions opposite to each other. The thickness of each of the wiring layers 112a, 112b, 112c, and 112d may be thicker than the thickness of the redistribution layer 142 (e.g., thicker than the thickness of the wiring layer provided in the redistribution layer 142).

[0109] Other details may be substantially the same as the details described with respect to the semiconductor package 100A according to the above-described one example and the semiconductor package 100B according to the above-described another example, and a detailed description thereof will be omitted.

[0110] In the present disclosure, for the sake of convenience, words such as below, lower part, and lower surface are used to indicate the downward direction relative to the cross section of the drawings (in the vertical direction of the drawings, also referred to as the thickness direction), and words such as above, upper part, and upper surface are used to indicate the opposite direction. It should be understood that the definition indicating the direction is for the convenience of interpretation, the scope of the claims is not particularly limited by the description of such direction, and the concept of upward direction / downward direction can be changed at any time.

[0111] The term "connecting..." or "connection" in the present disclosure may be not only a direct connection but also a concept including an indirect connection through an adhesive layer or the like. In addition, the term "electrically connected" or "electrically connected" means a concept including both physical connection and physical disconnection. In addition, expressions such as "first", "second", etc. are used to distinguish one component from another and do not limit the order and / or importance of the components. In some cases, without departing from the spirit of the present invention, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component.

[0112] In the present disclosure, the use of the expression "exemplary embodiment" does not necessarily refer to the same embodiment, but may be provided to emphasize and explain different unique features. However, the above-mentioned exemplary embodiments do not exclude that they can be implemented in combination with the features of other exemplary embodiments. For example, although the description in a specific exemplary embodiment may not be described in another exemplary embodiment, it may be understood as an explanation related to another exemplary embodiment unless otherwise described by other exemplary embodiments or contradicted with other exemplary embodiments.

[0113] The terms used in the present disclosure are only used to explain the exemplary embodiments and are not intended to limit the present disclosure.At this time, unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0114] As one of various effects of the present disclosure, a semiconductor package having excellent heat dissipation characteristics and reliability as well as warpage control, electromagnetic shielding effect, and improved yield of semiconductor chips by introducing a heat dissipation structure may be provided.

[0115] While example embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A semiconductor package, comprising: a connection structure including one or more redistribution layers; a semiconductor chip disposed on the connection structure and having an active surface and an inactive surface opposite to the active surface, wherein connection pads electrically connected to the redistribution layer are disposed on the active surface; an encapsulant including a first encapsulant disposed on the connection structure and covering at least a portion of the semiconductor chip and a second encapsulant disposed on the first encapsulant, the first encapsulant having a first portion covering at least a portion of the ineffective surface of the semiconductor chip; a plurality of conductor pattern layers spaced apart from each other in a direction parallel to the ineffective surface of the semiconductor chip, each of the plurality of conductor pattern layers spaced apart from the semiconductor chip, and embedded in the second encapsulant such that a first surface of each of the plurality of conductor pattern layers is covered by the second encapsulant and a second surface of each of the plurality of conductor pattern layers opposite to the first surface is exposed from the second encapsulant; as well as a metal layer disposed on the second encapsulant to align with both sides of the second encapsulant and completely cover the second surfaces of the plurality of conductor pattern layers, Each of the plurality of conductor pattern layers comprises: a first conductor layer located on the lower surface of the metal layer; and a second conductor layer located below the first conductor layer, wherein the thickness of the second conductor layer is greater than the thickness of the first conductor layer. wherein the conductor pattern layer located at the edge of the plurality of conductor pattern layers is spaced apart from the two sides of the second encapsulant, and The maximum thickness of the second encapsulant is greater than the thickness of the first portion of the first encapsulant.

2. The semiconductor package according to claim 1, wherein: The first encapsulant and the second encapsulant are provided as different layers separated from each other.

3. The semiconductor package according to claim 2, wherein: The metal layer contacts the second surface of each of the plurality of conductor pattern layers and the second encapsulant.

4. The semiconductor package according to claim 1, wherein: Each of the plurality of conductor pattern layers includes a plurality of metal patterns spaced apart from each other, and The metal layer has a form of a metal plate extending across spaces between the metal patterns of the plurality of conductor pattern layers.

5. The semiconductor package according to claim 4, wherein: At least a portion of the plurality of metal patterns is disposed to face the ineffective surface of the semiconductor chip at a predetermined distance from the ineffective surface of the semiconductor chip.

6. The semiconductor package according to claim 1, further comprising: A conductive adhesive is disposed on the metal layer; as well as The heat dissipation member is disposed on the conductive adhesive.

7. The semiconductor package according to claim 6, wherein: The electrically conductive adhesive comprises a thermally conductive interface material, and The heat dissipation member includes a metal block.

8. The semiconductor package according to claim 1, wherein: A thickness of each of the plurality of conductor pattern layers is thicker than a thickness of each of the redistribution layers.

9. The semiconductor package according to claim 1, further comprising a frame, the frame being disposed on the connection structure and having a through hole, in, The semiconductor chip is arranged in the through hole so that the active surface of the semiconductor chip faces the connection structure, and The first encapsulant also covers at least a portion of the frame and also fills at least a portion of the through hole.

10. The semiconductor package according to claim 9, wherein: The frame includes: an insulating layer in which the through hole is formed; a first metal layer and a second metal layer respectively disposed on opposite surfaces of the insulating layer; and a third metal layer disposed on a wall surface of the through hole.

11. The semiconductor package according to claim 9, wherein: The frame includes: a first insulating layer in contact with the connection structure; a first wiring layer in contact with the connection structure and embedded in the first insulating layer; a second wiring layer disposed on a side of the first insulating layer opposite to a side on which the first wiring layer is disposed; a second insulating layer disposed on the first insulating layer and covering the second wiring layer; and a third wiring layer disposed on a side of the second insulating layer opposite to a side in which the second wiring layer is embedded, Wherein, the first wiring layer, the second wiring layer and the third wiring layer are electrically connected to the connection pad.

12. The semiconductor package according to claim 9, wherein: The frame includes: a first insulating layer; a first wiring layer and a second wiring layer, which are respectively arranged on the opposite surfaces of the first insulating layer; a second insulating layer and a third insulating layer, which are respectively arranged on the opposite surfaces of the first insulating layer and cover the first wiring layer and the second wiring layer respectively; a third wiring layer, which is arranged on the side of the second insulating layer opposite to the side in which the first wiring layer is embedded; and a fourth wiring layer, which is arranged on the side of the third insulating layer opposite to the side in which the second wiring layer is embedded, Wherein, the first wiring layer, the second wiring layer, the third wiring layer and the fourth wiring layer are electrically connected to the connection pad.

13. The semiconductor package according to claim 1, wherein: The semiconductor package is a fan-out type semiconductor package.

14. A semiconductor package, comprising: a connection structure including one or more redistribution layers; a semiconductor chip disposed on the connection structure and having an active surface and an inactive surface opposite to the active surface, wherein connection pads electrically connected to the redistribution layer are disposed on the active surface; a first encapsulant disposed on the connection structure and covering at least a portion of the semiconductor chip, the first encapsulant having a first portion covering at least a portion of the ineffective surface of the semiconductor chip; a second encapsulant, disposed on and covering the first encapsulant; as well as a heat dissipation structure disposed on the second encapsulant and at least partially embedded in the second encapsulant, wherein the heat dissipation structure comprises: a plurality of conductor pattern layers spaced apart from each other in a direction parallel to the ineffective surface of the semiconductor chip, each of the plurality of conductor pattern layers spaced apart from the semiconductor chip and embedded in the second encapsulant such that a first surface of each of the plurality of conductor pattern layers is covered by the second encapsulant and a second surface of each of the plurality of conductor pattern layers opposite to the first surface is exposed from the second encapsulant; a metal layer disposed on the second encapsulant to be aligned with both sides of the second encapsulant, in contact with the second encapsulant, and completely covering the second surface of each of the plurality of conductor pattern layers, Each of the plurality of conductor pattern layers comprises: a first conductor layer located on the lower surface of the metal layer; and a second conductor layer located below the first conductor layer, wherein the thickness of the second conductor layer is greater than the thickness of the first conductor layer, and The maximum thickness of the second encapsulant is greater than the thickness of the first portion of the first encapsulant.

15. The semiconductor package according to claim 14, wherein: The heat dissipation structure further includes: a thermally conductive interface material disposed on the metal layer; and a metal block disposed on the thermally conductive interface material.

16. A semiconductor package, comprising: A semiconductor chip having an active surface and an inactive surface opposite to the active surface, wherein the active surface includes connection pads disposed thereon; an encapsulant including a first encapsulant having a first portion covering at least a portion of the semiconductor chip and a second encapsulant disposed on the first encapsulant; as well as A heat dissipation structure is disposed on the second encapsulant, wherein a surface of the heat dissipation structure facing the second encapsulant includes a plurality of conductor patterns spaced apart from the semiconductor chip and protruding into the second encapsulant, wherein the heat dissipation structure comprises a metal layer having one surface facing the semiconductor chip and integrally extending across the ineffective surface of the semiconductor chip, and the metal layer is aligned with both sides of the second encapsulant on the second encapsulant, and the plurality of conductor patterns protrude from the one surface of the metal layer into the second encapsulant, Each of the plurality of conductor patterns includes: a seed layer located on the lower surface of the metal layer; and a plating layer located below the seed layer, wherein the thickness of the plating layer is greater than the thickness of the seed layer. wherein a conductor pattern located at an edge of the plurality of conductor patterns is spaced apart from the two sides of the second encapsulant, and The maximum thickness of the second encapsulant is greater than the thickness of the first portion of the first encapsulant.

17. The semiconductor package according to claim 16, wherein: The metal layer contacts the second encapsulant between the plurality of conductor patterns.

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