Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device is provided. The method includes selecting a target pattern from a target design layout. The target pattern includes: a target net; a target via electrically connected to the target net; and a crossover net electrically connected to the target via and located at a different level than the target net. The method includes analyzing peripheral patterns adjacent to the target net. The method also includes generating a redundant net and a redundant via electrically connecting the redundant net to the crossover net.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2018-0141497, filed on November 16, 2018, and all rights arising therefrom, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a method of manufacturing a semiconductor device. Background Art

[0004] As the fabrication of semiconductor devices has become more complex, the demand for miniaturized semiconductor devices has also increased. In order to fabricate miniaturized semiconductor devices, a layout design that can ensure the reliability of the finished device may be advantageous. Summary of the Invention

[0005] Embodiments of the present disclosure provide a method of manufacturing a semiconductor device, which can improve the yield, reliability, and processability of the semiconductor device.

[0006] Embodiments of the present disclosure also provide a layout design system that can improve the yield, reliability, and processability of semiconductor devices.

[0007] However, the inventive concepts of the present disclosure are not limited to the example embodiments set forth herein.

[0008] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device may include providing a database including design information and process information for the semiconductor device. The method may include generating a prediction model by performing machine learning using a feature set based on the database. The prediction model may predict bad patterns of the semiconductor device. The method may include selecting a target pattern from a target design layout using the prediction model. The target pattern may include: a target net; a target via electrically connected to the target net; and a cross net electrically connected to the target via and located at a different level than the target net. The method may include analyzing peripheral patterns adjacent to the target net. The method may include generating a redundant net intersecting the cross net based on the analysis of the peripheral patterns, the redundant net being located at the same level as the target net, and generating a redundant via electrically connecting the redundant net and the cross net. Furthermore, the method may include inspecting the redundant net and the redundant via to determine whether the redundant net and the redundant via meet predetermined design rules.

[0009] A method for manufacturing a semiconductor device according to some embodiments may include providing a target design layout for the semiconductor device. The method may include selecting a target pattern from the target design layout. The target pattern may include: a target net extending along a first direction; a first target via electrically connected to the target net; and a first cross net electrically connected to the first target via and extending along a second direction intersecting the first direction, the first cross net being located at a different level than the target net in a third direction intersecting the first and second directions. The method may include analyzing a peripheral pattern adjacent to the target net. The peripheral pattern may include a first peripheral net and a second peripheral net, the first peripheral net and the second peripheral net extending along the first direction, the first peripheral net and the second peripheral net being located at the same level as the target net in the third direction, and the first peripheral net and the second peripheral net being spaced apart from each other in the second direction. The method may include generating a redundant net extending along the first direction, the redundant net being located at the same level as the target net in the third direction, and the redundant net being located between the first peripheral net and the second peripheral net. The method may also include generating a first redundant via electrically connecting the redundant net and the first cross net.

[0010] A method for manufacturing a semiconductor device according to some embodiments may include providing a target design layout for the semiconductor device. The method may include selecting a target pattern from the target design layout. The target pattern may include: a target net extending along a first direction; a first target via electrically connected to the target net; a second target via spaced apart from the first target via and electrically connected to the target net; a first intersection net electrically connected to the first target via and extending along a second direction intersecting the first direction, the first intersection net being located at a different level than the target net in a third direction intersecting the first and second directions; and a second intersection net electrically connected to the second target via and extending along the second direction, the second intersection net being located at a different level than the target net in the third direction, or at another different level than the target net. The method may include analyzing peripheral patterns adjacent to the target net. The peripheral patterns may include a first peripheral net extending along the first direction, being located at the same level as the target net in the third direction, and being spaced apart from the target net in the second direction. The method may include generating a first redundant net, the first redundant net extending along the first direction, the first redundant net being located at the same level as the target net in the third direction. The first peripheral net may be located between the target net and the first redundant net. Furthermore, the method may include generating a first redundant via and a second redundant via, the first redundant via electrically connecting the first redundant net and the first cross net, and the second redundant via electrically connecting the first redundant net and the second cross net.

[0011] According to some embodiments, a layout design system may include a processor. The layout design system may include a selection unit configured to select a target pattern from a target design layout of a semiconductor device using the processor. Furthermore, the layout design system may include a generation unit configured to generate redundant nets and redundant vias in the target pattern using the processor. The target pattern may include: a target net; a target via electrically connected to the target net; and a first intersection net electrically connected to the target via and located at a different level than the target net. The generation unit may include an analysis module configured to analyze a peripheral pattern adjacent to the target net. The generation unit may include a generation module configured to generate a redundant net based on the analyzed peripheral pattern. The redundant net may intersect with the first intersection net and be located at the same level as the target net. The redundant via may electrically connect the redundant net and the first intersection net. Furthermore, the generation unit may include an inspection module configured to inspect the redundant net and the redundant via to determine whether the redundant net and the redundant via meet predetermined design rules. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other objects and features of the present inventive concept will become apparent by describing in detail example embodiments of the present inventive concept with reference to the accompanying drawings, in which:

[0013] Figure 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0014] Figure 2A It shows Figure 1 Flowchart of block 10.

[0015] Figure 2B It shows Figure 1 Schematic diagram of box 10.

[0016] Figure 3A It shows Figure 1 Flowchart of block 20.

[0017] Figure 3B It shows Figure 1 Layout diagram of box 20.

[0018] Figure 4 is a flow chart illustrating the generation of redundant nets and redundant vias according to some embodiments of the present disclosure.

[0019] Figure 5 It shows that according to Figure 4 Schematic diagram of the generation of redundant nets and redundant vias.

[0020] Figure 6 is a schematic diagram illustrating the generation of redundant nets and redundant vias according to some embodiments of the present disclosure.

[0021] Figure 7 is a flow chart illustrating the generation of redundant nets and redundant vias according to some embodiments of the present disclosure.

[0022] Figure 8 It shows that according to Figure 7 Schematic diagram of the generation of redundant nets and redundant vias.

[0023] Figure 9 is a flow chart illustrating the generation of redundant nets and redundant vias according to some embodiments of the present disclosure.

[0024] Figure 10 It shows that according to Figure 9 Schematic diagram of the generation of redundant nets and redundant vias.

[0025] Figure 11 is a schematic diagram illustrating the generation of redundant nets and redundant vias according to some embodiments of the present disclosure.

[0026] Figure 12 is a schematic diagram illustrating the generation of redundant nets and redundant vias according to some embodiments of the present disclosure.

[0027] Figure 13 is a flow chart illustrating the generation of redundant nets and redundant vias according to some embodiments of the present disclosure.

[0028] Figure 14 and Figure 15 It shows that according to Figure 13 Schematic diagram of performing a timed impairment test.

[0029] Figure 16 is a schematic diagram illustrating the generation of redundant nets and redundant vias according to some embodiments of the present disclosure.

[0030] Figure 17 is a schematic diagram illustrating the generation of redundant nets and redundant vias according to some embodiments of the present disclosure.

[0031] Figure 18 is a schematic diagram illustrating the generation of redundant nets and redundant vias according to some embodiments of the present disclosure.

[0032] Figure 19 is a block diagram of a layout design system according to some embodiments of the present disclosure.

[0033] Figure 20 yes Figure 19 Block diagram of the selection unit.

[0034] Figure 21 yes Figure 19 Block diagram of the generation unit. DETAILED DESCRIPTION

[0035] The following will refer to Figures 1 to 17 Methods of manufacturing semiconductor devices according to some embodiments of the present disclosure are described.

[0036] Figure 1 is a flowchart illustrating a method of manufacturing a semiconductor device according to some embodiments of the present disclosure. Figure 2A It shows Figure 1 Flowchart of block 10. Figure 2B It shows Figure 1 Schematic diagram of box 10. Figure 3A It shows Figure 1 Flowchart of block 20. Figure 3B It shows Figure 1 Layout diagram of box 20. Figure 4 is a flow chart illustrating the generation of redundant nets and redundant vias according to some embodiments of the present disclosure. Figure 5 It shows that according to Figure 4Schematic diagram of the generation of redundant nets and redundant vias.

[0037] refer to Figure 1 According to some embodiments of the present disclosure, a method for manufacturing a semiconductor device includes selecting a target pattern from a target design layout (block 10), forming (e.g., generating) redundant nets and redundant vias in the target pattern (block 20), and performing a design rule test (block 30). As used herein, the terms "redundant" and "redundant" may be used interchangeably.

[0038] refer to Figure 1 、 Figure 2A and Figure 2B , selecting a target pattern from a target design layout (i.e., block 10) may include providing / accessing a database DB (block 1110), generating a feature set FS from the database DB (block 1120), using machine learning based on the feature set FS to generate a prediction model PM that predicts bad patterns (block 1130), and selecting a target pattern from the target design layout using the prediction model PM (block 1140).

[0039] Specifically, a database DB may be provided / accessed first (block 1110 ). The database DB may include, for example, design information and process information of semiconductor devices.

[0040] The design information may include a design layout diagram and information processed by simulation based on the design layout diagram, but the present disclosure is not limited thereto. That is, the design information is not limited to a specific form of data.

[0041] The process information may include information specifying process conditions of a semiconductor device corresponding to a specific node (e.g., 7 nanometers (nm), 8 nm, 10 nm, 14 nm, etc.), information defining bad patterns based on experimental values ​​obtained under the process conditions, and simulation information regarding the process conditions, but the present disclosure is not limited thereto. That is, the process information is not limited to a specific form of data.

[0042] The database DB may be provided by a plurality of semiconductor devices. For example, design information and process information of a first semiconductor device SD1 may be provided to a first database, and design information and process information of a second semiconductor device SD2 different from the first semiconductor device SD1 may be provided to a second database.

[0043] Thereafter, a feature set FS may be generated from the database DB (block 1120). The generation of the feature set FS may include, for example, separating the normal pattern NP and the bad pattern FP of the semiconductor device from the database DB. Figure 2BAs shown, the feature set FS may include a first feature set FS1 and a second feature set FS2, wherein the first feature set FS1 includes features of a normal pattern NP (or non-hotspot) of the first semiconductor device SD1, and the second feature set FS2 includes features of a bad pattern FP (or hotspot) of the first semiconductor device SD1.

[0044] Thereafter, a prediction model PM for predicting defective patterns of the semiconductor device may be generated using machine learning based on the feature set FS (block 1130). For example, a machine learning process may be performed based on the first feature set FS1 and the second feature set FS2. As a result, a prediction model PM for predicting bad patterns of the semiconductor device may be generated.

[0045] The machine learning process may include, for example, at least one of support vector machine (SVM) learning, clustering, classification, regression, and a combination thereof, but the present disclosure is not limited thereto.

[0046] Thereafter, a target pattern may be selected from the target design layout using the prediction model PM (block 1140). As a result, a target pattern predicted to be a bad pattern may be selected from the target design layout.

[0047] refer to Figure 1 、 Figure 3A and Figure 3B Generating redundant nets and redundant vias in a target pattern (i.e., block 20) ​​may include specifying a first target net 110, a first target via 112, a second target via 114, a first crossing net 210, and a second crossing net 220 in the target pattern (block 1210), analyzing a first peripheral net 120 and a second peripheral net 130 adjacent to the first target net 110 (block 1220), and forming (e.g., generating) redundant nets and redundant vias corresponding to the first target net 110 and the target vias 112 and 114 (block 1230).

[0048] As used herein, the term "net" refers to wiring in a target design layout. For example, a net may include interconnects, routing, and metal lines in a target design layout.

[0049] The target pattern is described below as having Figure 3B For example, Figure 3B As shown, the target pattern may include a first target net 110, a first cross net 210, a second cross net 220, a first target via 112, and a second target via 114, but the present disclosure is not limited thereto. The target pattern may have Figure 3B Various configurations other than those shown in .

[0050] Specifically, a first target net 110 , a first target via 112 , a second target via 114 , a first intersection net 210 , and a second intersection net 220 in a target pattern may be designated (eg, selected / identified) (block 1210 ).

[0051] The first target net 110 may be a net predicted to be bad in the target design layout.The first target net 110 may extend along a first direction Y, for example.

[0052] The first crossing net 210 and the second crossing net 220 may be nets intersecting the first target net 110. For example, the first crossing net 210 may extend in the second direction X intersecting the first direction Y, and the second crossing net 220 may be spaced apart from the first crossing net 210 in the first direction Y, and the second crossing net 220 may extend in the second direction X.

[0053] The first and second crossing webs 210 and 220 may be disposed at a different level from the first target web 110 in a third (eg, vertical) direction intersecting (eg, perpendicular to) the first and second directions Y and X. Figure 3B The first cross net 210 and the second cross net 220 are shown to be arranged at a lower level than the first target net 110, but the present disclosure is not limited thereto. Alternatively, one of the first cross net 210 and the second cross net 220 may be arranged at a higher level than the first target net 110, or both of the first cross net 210 and the second cross net 220 may be arranged at a higher level than the first target net 110.

[0054] The first target via 112 may electrically connect the first target net 110 and the first intersection net 210, which are disposed at different levels. The second target via 114 may be spaced apart from the first target via 112 and may electrically connect the first target net 110 and the second intersection net 220, which are disposed at different levels. For example, if the first intersection net 210 and the second intersection net 220 are disposed at the same level, the first target via 112 and the second target via 114 may be disposed at the same level.

[0055] Figure 3B The first target net 110 is shown as extending beyond the first target via 112 and the second target via 114 in the first direction Y, but the present disclosure is not limited thereto. For example, at least one of the first target via 112 and the second target via 114 can be provided at an end of the first target net 110, as long as the first target via 112 and the second target via 114 can be electrically connected to the first target net 110. For example, the first target via 112 can be provided at one end of the first target net 110, and the second target via 114 can be provided at the other end of the first target net 110.

[0056] Similarly, Figure 3B The first intersection mesh 210 and the second intersection mesh 220 are shown to extend beyond the first target via 112 and the second target via 114 in the second direction X, respectively, but the present disclosure is not limited thereto. In some embodiments, the first target via 112 can be disposed at one end of the first intersection mesh 210, and the second target via 114 can be disposed at one end of the second intersection mesh 220.

[0057] Thereafter, the first peripheral net 120 and the second peripheral net 130 adjacent to the first target net 110 may be analyzed (block 1220 ).

[0058] For example, the first and second peripheral nets 120 and 130 may be disposed adjacent to the first target net 110. The first and second peripheral nets 120 and 130 may extend, for example, in the first direction Y. The first and second peripheral nets 120 and 130 may be spaced apart from the first target net 110 in the second direction X.

[0059] In some embodiments, the first peripheral net 120 may be disposed adjacent to one side of the first target net 110, and the second peripheral net 130 may be disposed adjacent to the other side of the first target net 110. That is, the first target net 110 may be interposed between the first peripheral net 120 and the second peripheral net 130.

[0060] Figure 3B The first and second peripheral nets 120 and 130 are shown to intersect with both the first and second crossing nets 210 and 220 , but the present disclosure is not limited thereto. In some embodiments, the first and second peripheral nets 120 and 130 may not intersect with at least one of the first and second crossing nets 210 and 220 .

[0061] The redundant network 110R may be generated (ie, block 1232a ( Figure 4 )) Then, the first redundant via 112R and the second redundant via 114R are performed ( Figure 5 ), but the present disclosure is not limited thereto. For example, the generation of the first redundant via 112R and the second redundant via 114R (block 1234a) may be performed before the generation of the redundant net 110R (block 1232a), or the generation of the first redundant via 112R and the second redundant via 114R (block 1234a) and the generation of the redundant net 110R (block 1232a) may be performed simultaneously.

[0062] Thereafter, a redundant net corresponding to the first target net 110 and redundant vias corresponding to the first target via 112 and the second target via 114 may be generated (block 1230). Figures 4 to 18Description box 1230.

[0063] Reference again Figure 1 , a design rule test may be performed (block 30). For example, a determination may be made as to whether the generated redundant nets and the generated redundant vias meet predetermined design rules.

[0064] In some embodiments, if the generated redundant nets and the generated redundant vias satisfy predetermined design rules, a resulting design layout including the generated redundant nets and the generated redundant vias may be provided. After determining that the generated redundant nets and the generated redundant vias satisfy the predetermined design rules, a semiconductor device may be constructed (i.e., physically manufactured) using metal layers and metal vias, the metal layers and metal vias corresponding to the generated redundant nets and the generated redundant vias, respectively. On the other hand, if the generated redundant nets and the generated redundant vias do not satisfy the predetermined design rules, the generated redundant nets and the generated redundant vias may be removed from the target design layout.

[0065] In some embodiments, in addition to the above reference Figure 2A and Figure 2B Selecting a target pattern from a target design layout (ie, block 10 ) may be performed in various ways other than those described.

[0066] For example, information about a net that significantly affects the performance of a semiconductor device and design information of the semiconductor device can be provided, and the corresponding net can be selected as a target pattern. For example, the following can be selected as the target pattern: a clock net used for synchronization of the semiconductor device, a power net for inputting power to or outputting power from the semiconductor device, or a timing-critical net for determining the timing of a signal input to or output from the semiconductor device.

[0067] Furthermore, for example, it is not necessary to refer to Figure 2A and 2B In the method described above, a target pattern is defined. In this case, any pattern that can add redundant nets or redundant vias within the target design layout can be selected as the target pattern.

[0068] refer to Figure 4 and Figure 5 , according to Figure 1 Generating redundant nets and redundant vias (ie, block 1230 ( Figure 3A)) may include generating a redundant net 110R having a greater width than the first target net 110 in the second direction X (block 1232a), generating a first redundant via 112R and a second redundant via 114R having a greater width than the first target via 112 and the second target via 114 in the second direction X (block 1234a), and replacing the first target net 110, the first target via 112, and the second target via 114 with the redundant net 110R, the first redundant via 112R, and the second redundant via 114R, respectively (block 1236a).

[0069] Specifically, a redundant net 110R having a greater width than the first target net 110 may be generated (block 1232a). The redundant net 110R may be a net that may prevent / suppress any defects that may be generated in the target design layout by the first target net 110. The redundant net 110R may extend, for example, along a first direction Y at the same level as the first target net 110.

[0070] In some embodiments, a redundant network 110R may be generated between the first peripheral network 120 and the second peripheral network 130 .

[0071] In some embodiments, the redundant net 110R may have a greater width than the first target net 110. For example, Figure 5 As shown, the width W21 of the redundant net 110R in the second direction X may be greater than the width W11 of the first target net 110 in the second direction X.

[0072] In some embodiments, analyzing the peripheral nets adjacent to the first target net 110 (i.e., block 1220) may include analyzing the distances between the peripheral nets adjacent to both sides of the first target net 110. For example, block 1220 may include measuring a distance D11 between the first target net 110 and the first peripheral net 120 in the second direction X, and a distance D12 between the first target net 110 and the second peripheral net 130 in the second direction X. If the distances D11 and D12 exceed predetermined distances, a redundant net 110R having a greater width than the first target net 110 may be generated (block 1232a).

[0073] Thereafter, a first redundant via 112R and a second redundant via 114R having a greater width than the first target via 112 and the second target via 114 may be generated (block 1234 a ).

[0074] The first redundant via 112R may electrically connect the redundant net 110R and the first crossing net 210 disposed at different levels. The second redundant via 114R may be spaced apart from the first redundant via 112R and may electrically connect the redundant net 110R and the second crossing net 220 disposed at different levels.

[0075] Figure 5 The redundant net 110R is shown to extend beyond the first redundant via 112R and the second redundant via 114R along the first direction Y, but the present disclosure is not limited thereto. For example, at least one of the first redundant via 112R and the second redundant via 114R may be provided at an end of the redundant net 110R, as long as the first redundant via 112R and the second redundant via 114R can be electrically connected to the redundant net 110R.

[0076] In some embodiments, the first redundant via 112R and the second redundant via 114R may have a greater width than the first target via 112 and the second target via 114. Figure 5 As shown, the width W22 of the first redundant via 112R in the second direction X may be greater than the width W12 of the first target via 112 in the second direction X.

[0077] Figure 5 The first redundant via 112R and the second redundant via 114R are both shown to have a greater width than the first target via 112 and the second target via 114, but the present disclosure is not limited thereto. For example, the first redundant via 112R may have a greater width than the first target via 112, and the second redundant via 114R may have substantially the same width as the second target via 114.

[0078] The distance E12 between the first redundant via 112R and the second redundant via 114R is illustrated as being the same as the distance E11 between the first target via 112 and the second target via 114 , but the present disclosure is not limited thereto.

[0079] Thereafter, the first target net 110 , the first target via 112 , and the second target via 114 may be replaced with the redundant net 110R, the first redundant via 112R, and the second redundant via 114R, respectively (block 1236 a ).

[0080] In some embodiments, performing a design rule test (i.e., block 30) may include performing a design rule test on the redundant net 110R, the first redundant via 112R, and the second redundant via 114R. For example, performing a design rule test on the redundant net 110R may include measuring a distance D21 between the redundant net 110R and the first peripheral net 120 and a distance D22 between the redundant net 110R and the second peripheral net 130.

[0081] In some embodiments, if the distances D21 and D22 satisfy predetermined design rules, a resulting design layout including a redundant net 110R may be provided.

[0082] according to Figures 1 to 5A method of manufacturing a semiconductor device can generate redundant nets and redundant vias for a pattern predicted to be bad in a target design layout (ie, a target pattern), and thus can provide a semiconductor device with improved reliability.

[0083] Figure 6 Schematic diagram showing the generation of redundant nets and redundant vias according to some embodiments of the present disclosure. Figures 1 to 5 A description of the element or feature being described.

[0084] refer to Figure 6 In the method of manufacturing a semiconductor device according to some embodiments of the present disclosure, the first crossing web 210 and the second crossing web 220 may be disposed at different levels.

[0085] For example, the first cross net 210 may be disposed at a level lower than the redundant net 110R, and the second cross net 220 may be disposed at a level higher than the redundant net 110R.

[0086] The first redundant via 112R may electrically connect the redundant net 110R and the first cross net 210, and the second redundant via 114R may electrically connect the redundant net 110R and the second cross net 220. Therefore, the first redundant via 112R and the second redundant via 114R may be arranged at different respective levels in a third direction intersecting the first direction Y and the second direction X. The first redundant via 112R and the second redundant via 114R may replace the first target via 112 and the second target via 114, respectively.

[0087] Figure 7 is a flow chart illustrating the generation of redundant nets and redundant vias according to some embodiments of the present disclosure. Figure 8 It shows that according to Figure 7 For the sake of convenience, the above referenced diagrams can be omitted or at least simplified. Figures 1 to 6 A description of the element or feature being described.

[0088] refer to Figure 7 and Figure 8 In the method of manufacturing a semiconductor device according to some embodiments of the present disclosure, generating a redundant net and a redundant via may include: generating a redundant net 110R spaced apart from the first target net 110 with a peripheral net (e.g., the second peripheral net 130) of the first target net 110 inserted between the redundant net 110R and the first target net 110 (block 1232b), and generating a first redundant via 112R and a second redundant via 114R electrically connecting the redundant net 110R to the first cross net 210 and the second cross net 220, respectively (block 1234b).

[0089] Specifically, a redundant net 110R spaced apart from the first target net 110 may be generated, and a peripheral net (eg, the second peripheral net 130 ) is inserted between the first target net 110 and the redundant net 110R (block 1232 b ).

[0090] In some embodiments, the third peripheral net 140 may be disposed adjacent to the second peripheral net 130. For example, the third peripheral net 140 may be spaced apart from the first target net 110, with the second peripheral net 130 interposed between the first target net 110 and the third peripheral net 140.

[0091] The first peripheral net 120, the second peripheral net 130, and the third peripheral net 140 are shown as not crossing the second crossing net 220, but the present disclosure is not limited thereto. For example, at least one of the first peripheral net 120, the second peripheral net 130, and the third peripheral net 140 may cross (e.g., vertically overlap) the second crossing net 220.

[0092] In some embodiments, the redundant net 110R may be generated between the second peripheral net 130 and the third peripheral net 140. Therefore, the redundant net 110R may be spaced apart from the first target net 110, with the second peripheral net 130 interposed therebetween.

[0093] In some embodiments, the peripheral nets adjacent to the first target net 110 (ie, block 1220 ( Figure 3A )) may include analyzing distances between peripheral nets adjacent to the first target net 110. For example, block 1220 may include analyzing a distance D33 between the second peripheral net 130 and the third peripheral net 140 in the second direction X. If the distance D33 exceeds a predetermined distance, a redundant net 110R may be generated between the second peripheral net 130 and the third peripheral net 140 (block 1232b).

[0094] In some embodiments, the distance D33 between the second peripheral net 130 and the third peripheral net 140 may be greater than the distance D31 between the first target net 110 and the first peripheral net 120 in the second direction X and the distance D32 between the first target net 110 and the second peripheral net 130 in the second direction X.

[0095] The width W31 of the redundant net 110R in the second direction X is shown to be the same as the width W11 of the first target net 110 in the second direction X, but the present disclosure is not limited thereto. For example, the redundant net 110R may have a different width from the first target net 110 .

[0096] Thereafter, a first redundant via 112R and a second redundant via 114R electrically connecting the redundant net 110R to the first cross net 210 and the second cross net 220 may be generated (block 1234b).

[0097] The first redundant via 112R may electrically connect the redundant net 110R and the first crossing net 210 disposed at different levels. The second redundant via 114R may be spaced apart from the first redundant via 112R and may electrically connect the redundant net 110R and the second crossing net 220 disposed at different levels.

[0098] The width W32 of the first redundant via 112R in the second direction X is shown to be the same as the width W12 of the first target via 112 in the second direction X, but the present disclosure is not limited thereto. For example, the first redundant via 112R may have a different width than the first target via 112. Similarly, the second redundant via 114R may have a different width than the second target via 114.

[0099] In some embodiments, a distance E22 between the first redundant via 112R and the second redundant via 114R may be substantially the same as a distance E21 between the first target via 112 and the second target via 114 .

[0100] In some embodiments, performing a design rule test (i.e., block 30) may include performing a design rule test on the redundant net 110R, the first redundant via 112R, and the second redundant via 114R. For example, performing a design rule test on the redundant net 110R may include measuring a distance D41 between the redundant net 110R and the second peripheral net 130 in the second direction X, and a distance D42 between the redundant net 110R and the third peripheral net 140 in the second direction X.

[0101] In some embodiments, if the distances D41 and D42 satisfy predetermined design rules, a resulting design layout including a redundant net 110R may be provided.

[0102] according to Figure 7 and Figure 8 A method of manufacturing a semiconductor device can generate redundant nets and redundant vias that can complement patterns predicted to be bad in a target design layout (ie, target patterns), and thus the method can provide a semiconductor device with improved reliability.

[0103] Figure 9 is a flow chart illustrating the generation of redundant nets and redundant vias according to some embodiments of the present disclosure. Figure 10 It shows that according to Figure 9For the sake of convenience, the above referenced diagrams can be omitted or at least simplified. Figures 1 to 8 A description of the element or feature being described.

[0104] refer to Figure 9 and Figure 10 In the method of manufacturing a semiconductor device according to some embodiments of the present disclosure, generating a redundant net and a redundant via may include: generating a redundant net 110R spaced apart from the first target net 110, with a peripheral net (e.g., the second peripheral net 130) of the first target net 110 inserted between the redundant net 110R and the first target net 110 (block 1232b); generating an extension net 220E extending from a crossing net (e.g., the second crossing net 220) (block 1236b); and generating a second redundant via 114R electrically connecting the redundant net 110R and the extension net 220E (block 1234b').

[0105] In some embodiments, the second target via 114 may be disposed at an end of the second crossing net 220. For example, the second crossing net 220 may not extend to the area between the second peripheral net 130 and the third peripheral net 140. Therefore, the second crossing net 220 may not overlap with the redundant net 110R.

[0106] The extension net 220E may extend from the end of the second crossing net 220 along the second direction X. Thus, the extension net 220E may even extend to the area between the second peripheral net 130 and the third peripheral net 140. Furthermore, the extension net 220E may overlap with the redundant net 110R. The extension net 220E may be disposed at the same level as the second crossing net 220.

[0107] Thereafter, a second redundant via 114R electrically connecting the redundant net 110R and the extension net 220E may be generated (block 1234b'). Thus, the second redundant via 114R may be spaced apart from the first redundant via 112R and may electrically connect the redundant net 110R and the second cross net 220 disposed at different levels. In some embodiments, the second redundant via 114R may be directly connected to the extension net 220E.

[0108] Figure 11 Schematic diagram showing the generation of redundant nets and redundant vias according to some embodiments of the present disclosure. Figures 1 to 10 A description of the element or feature being described.

[0109] refer to Figure 11 In the method of manufacturing a semiconductor device according to some embodiments of the present disclosure, the first crossing web 210 and the second crossing web 220 may be disposed at different respective levels.

[0110] For example, Figure 11 As shown, the first cross net 210 may be disposed at a lower level than the first target net 110 and the redundant net 110R, and the second cross net 220 and the extension net 220E may be disposed at a higher level than the first target net 110 and the redundant net 110R. Therefore, the first target via 112 and the second target via 114 may be disposed at different respective levels, and the first redundant via 112R and the second redundant via 114R may be disposed at different respective levels.

[0111] Figure 12 Schematic diagram showing the generation of redundant nets and redundant vias according to some embodiments of the present disclosure. Figures 1 to 10 A description of the element or feature being described.

[0112] refer to Figure 12 In the method of manufacturing a semiconductor device according to some embodiments of the present disclosure, a plurality of peripheral nets (eg, the second peripheral net 130 and the third peripheral net 140 ) may be inserted between the first target net 110 and the redundant net 110R.

[0113] In some embodiments, the fourth peripheral net 150 may be disposed adjacent to the third peripheral net 140. For example, the fourth peripheral net 150 may be spaced apart from the first target net 110, with the second peripheral net 130 and the third peripheral net 140 interposed therebetween.

[0114] In some embodiments, the redundant net 110R may be generated between the third peripheral net 140 and the fourth peripheral net 150. Therefore, the redundant net 110R may be spaced apart from the first target net 110, with the second peripheral net 130 and the third peripheral net 140 interposed therebetween.

[0115] Figure 13 is a flow chart illustrating the generation of redundant nets and redundant vias according to some embodiments of the present disclosure. Figure 14 and Figure 15 It shows that according to Figure 13 For convenience, the above referenced diagrams may be omitted or at least simplified. Figures 1 to 10 A description of the element or feature being described.

[0116] refer to Figures 13 to 15 In the method of manufacturing a semiconductor device according to some embodiments of the present disclosure, generating redundant nets and redundant vias may further include performing a timing damage test on the generated redundant nets and generated redundant vias (block 1238b).

[0117] A timing hurt test may be performed by, for example, measuring the length of the generated trace path. As used herein, the term "trace path" refers to a path through which an electrical signal is transmitted.

[0118] For example, if the length of the routing path of the generated redundant net is substantially the same as the length of the routing path of the target net, a resulting design layout including the generated redundant net and the generated redundant via may be provided. On the other hand, if the routing path of the generated redundant net is longer than the routing path of the target net, the generated redundant net and the generated redundant via may be removed from the target design layout.

[0119] For example, a first routing path RP1 and a second routing path RP2 extending from a first point P1 located on the left side of the second crossing net 220 to a second point P2 located on the right side of the first crossing net 210 may be defined.

[0120] The first routing path RP1 may extend from the first point P1 to the second point P2 through the first target net 110. Figure 14 As shown, the length of the first routing path RP1 can be the sum of the following three: the distance L11 from the first point P1 to the second target via 114 along the second cross network 220 in the second direction X, the distance L12 from the second target via 114 to the first target via 112 along the first target network 110 in the first direction Y, and the distance L13 from the first target via 112 to the second point P2 in the second direction X.

[0121] The second routing path RP2 can extend from the first point P1 to the second point P2 through the redundant network 110R. Figure 15 As shown, the length of the second routing path RP2 can be the sum of the following three: the distance L21 from the first point P1 to the second redundant via 114R along the second cross network 220 in the second direction X, the distance L22 from the second redundant via 114R to the first redundant via 112R along the redundant network 110R in the first direction Y, and the distance L23 from the first redundant via 112R to the second point P2 in the second direction X.

[0122] In some embodiments, the length of the first routing path RP1 (i.e., the sum of distances L11, L12, and L13) may be substantially the same as the length of the second routing path RP2 (i.e., the sum of distances L21, L22, and L23). Thus, a resulting design layout including a redundant net 110R may be provided.

[0123] Figure 16 Schematic diagram showing the generation of redundant nets and redundant vias according to some embodiments of the present disclosure. Figures 1 to 15 A description of the element or feature being described.

[0124] refer to Figure 16 In the method of manufacturing a semiconductor device according to some embodiments of the present disclosure, a plurality of redundant nets (ie, a first redundant net 110Ra and a second redundant net 110Rb) may be generated.

[0125] For example, a first redundant net 110Ra having a greater width than the first target net 110 may be generated between the first peripheral net 120 and the second peripheral net 130. For example, a width W41 of the first redundant net 110Ra in the second direction X may be greater than a width W11 of the first target net 110 in the second direction X.

[0126] In some embodiments, the first redundant via 112Ra and the second redundant via 114Ra electrically connected to the first redundant net 110Ra may have a greater width than the first target via 112 and the second target via 114. For example, the width W42 of the first redundant via 112Ra in the second direction X may be greater than the width W12 of the first target via 112 in the second direction X.

[0127] Furthermore, for example, a second redundant net 110Rb may be generated spaced apart from the first redundant net 110Ra, with the second peripheral net 130 interposed therebetween. For example, the second redundant net 110Rb may be generated between the second peripheral net 130 and the third peripheral net 140.

[0128] In some embodiments, a third redundant via 112Rb electrically connecting the second redundant net 110Rb and the first cross net 210 , and a fourth redundant via 114Rb electrically connecting the second redundant net 110Rb and the second cross net 220 may be generated.

[0129] Figure 17 Schematic diagram showing the generation of redundant nets and redundant vias according to some embodiments of the present disclosure. Figures 1 to 15 A description of the element or feature being described.

[0130] refer to Figure 17 In the method of manufacturing a semiconductor device according to some embodiments of the present disclosure, a redundant net 110R having a greater width than the first target net 110 and spaced apart from the first target net 110 may be generated, and a peripheral net is inserted between the redundant net 110R and the first target net 110.

[0131] For example, a redundant net 110R having a greater width than the first target net 110 may be disposed between the second peripheral net 130 and the third peripheral net 140. For example, a width W61 of the redundant net 110R in the second direction X may be greater than a width W51 of the first target net 110 in the second direction X.

[0132] In some embodiments, the first and second redundant vias 112R and 114R may have greater widths than the first and second target vias 112 and 114. For example, the width W62 of the first redundant via 112R in the second direction X may be greater than the width W52 of the first target via 112 in the second direction X.

[0133] Figure 18 Schematic diagram showing the generation of redundant nets and redundant vias according to some embodiments of the present disclosure. Figures 1 to 17 A description of the element or feature being described.

[0134] refer to Figure 18 In the method of manufacturing a semiconductor device according to some embodiments of the present disclosure, when there are two or more target nets, a redundant net and a redundant via may be generated for each target net.

[0135] For example, the target design layout may include a first target net 110 , a first target via 112 , a second target via 114 , a first intersection net 210 , and a second intersection net 220 , and may also include a second target net 115 , a third target via 117 , a fourth target via 119 , a third intersection net 215 , and a fourth intersection net 225 .

[0136] Similar to the first target net 110, the second target net 115 may be a net predicted to be bad in the target design layout. The second target net 115 may be spaced apart from the first target net 110. For example, the second target net 115 may perform a different function than the first target net 110. The second target net 115 is shown as extending along the first direction Y, but the present disclosure is not limited thereto.

[0137] The third crossing web 215 and the fourth crossing web 225 may intersect the second destination web 115. For example, the third crossing web 215 may extend in the second direction X, and the fourth crossing web 225 may be spaced apart from the second crossing web 220 and may extend in the second direction X. The third crossing web 215 and the fourth crossing web 225 may be disposed at a different level than the first destination web 110. In some embodiments, the third crossing web 215 may be spaced apart from the first crossing web 210, and the fourth crossing web 225 may be spaced apart from the second crossing web 220.

[0138] The third target via 117 may electrically connect the second target net 115 and the third intersection net 215 disposed at different levels. The fourth target via 119 may be spaced apart from the third target via 117 and may electrically connect the second target net 115 and the fourth intersection net 225 disposed at different levels.

[0139] In some embodiments, a first redundant net 110Ra may be generated corresponding to the first target net 110, and a second redundant net 110Rb may be generated corresponding to the second target net 115. Similarly, a first redundant via 112Ra and a second redundant via 114Ra may be generated corresponding to the first target via 112 and the second target via 114, and a third redundant via 112Rb and a fourth redundant via 114Rb may be generated corresponding to the third target via 117 and the fourth target via 119.

[0140] For example, a first redundant net 110Ra having a greater width than the first target net 110 may be generated between the first peripheral net 120 and the second peripheral net 130. For example, a width W41 of the first redundant net 110Ra in the second direction X may be greater than a width W11 of the first target net 110 in the second direction X.

[0141] In some embodiments, the first redundant via 112Ra and the second redundant via 114Ra electrically connected to the first redundant net 110Ra may have a greater width than the first target via 112 and the second target via 114. For example, the width W42 of the first redundant via 112Ra in the second direction X may be greater than the width W12 of the first target via 112 in the second direction X.

[0142] Furthermore, for example, a second redundant net 110Rb may be generated spaced apart from the second target net 115, with the fourth peripheral net 150 interposed between the second redundant net 110Rb and the second target net 115. The second redundant net 110Rb may be spaced apart from the first redundant net 110Ra. For example, the second redundant net 110Rb may be generated between the third peripheral net 140 and the fourth peripheral net 150.

[0143] In some embodiments, the extension net 220E may extend from an end portion of the fourth crossing net 225 along the second direction X. Thus, the fourth redundant via 114Rb may electrically connect the second redundant net 110Rb and the fourth crossing net 225 .

[0144] The following will refer to Figures 1 to 21 A layout design system according to some embodiments of the present disclosure is described.

[0145] Figure 19 is a block diagram of a layout design system according to some embodiments of the present disclosure. Figure 20 yes Figure 19 Block diagram of the selection unit. Figure 21 yes Figure 19 Block diagram of the generation unit.

[0146] The term "unit" or "module" used herein means, but is not limited to, a software and / or hardware component that performs certain tasks, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0147] The units or modules can advantageously be configured to reside in a tangible addressable storage medium and to execute on one or more processors. Thus, as examples, units or modules can include components (e.g., software components, object-oriented software components, class components, and task components), processes, functions, properties, procedures, subroutines, program code segments, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, or variables.

[0148] The functionality provided in the components and units or modules may be combined into fewer components and units or modules, or may be further separated into additional components and units or modules.

[0149] refer to Figures 19 to 21 , the layout design system includes a processor 1000 and a storage unit 2000 .

[0150] The storage unit 2000 may include a selection unit 2100 and a generation unit 2200 .

[0151] The selection unit 2100 may select a target pattern from a target design layout of a semiconductor device using the processor 1000. In some embodiments, the selection unit 2100 may include an input module 2110, a prediction module 2120, and a selection module 2130.

[0152] The input module 2110 may be provided with a database (eg, Figure 2B The database includes design information and process information of semiconductor devices.

[0153] The prediction module 2120 may generate a prediction model (eg, Figure 2B of “PM”).

[0154] The selection module 2130 may use the prediction model provided by the prediction module 2120 to select a target pattern predicted to be a bad pattern from the target design layout.

[0155] The generating unit 2200 may generate redundant nets and redundant vias in the target pattern selected by the selecting module 2130 using the processor 1000. In some embodiments, the generating unit 2200 may include an analyzing module 2210, a generating module 2220, and an inspecting module 2230.

[0156] The analyzing module 2210 may analyze peripheral patterns (including, for example, Figure 3B a first peripheral network 120 and a second peripheral network 130).

[0157] The generation module 2220 may generate a redundant net (eg, Figure 5 Redundant nets 110R) and redundant vias (e.g., Figure 5 The generation module 2220 can use, for example, the first redundant via 112R and the second redundant via 114R as described above. Figures 4 to 18 Use any of the methods described to generate redundant nets and redundant vias.

[0158] The checking module 2230 may check (e.g., test / analyze) the generated redundant nets and generated redundant vias provided by the generating module 2220 to determine whether the generated redundant nets and generated redundant vias satisfy predetermined design rules. If the generated redundant nets and generated redundant vias satisfy the predetermined design rules, the checking module 2230 may provide a result design layout including the generated redundant nets and generated redundant vias.

[0159] While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the scope of the present invention as defined in the appended claims. It is therefore intended that the present embodiments be considered in all respects as illustrative and not restrictive, reference being made to the appended claims rather than the foregoing description as indicating the scope of the invention.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: providing a database including design information and process information of the semiconductor device; generating a prediction model by performing machine learning using a feature set based on the database, wherein the prediction model predicts a bad pattern of the semiconductor device; selecting a target pattern from a target design layout using the prediction model, wherein the target pattern comprises: Target Network; a target via electrically connected to the target net; and a cross net electrically connected to the target via and located at a different level than the target net; analyzing a peripheral pattern adjacent to the target web; generating a redundant net intersecting the cross net based on analyzing the peripheral pattern, the redundant net being located at the same level as the target net, and generating a redundant via electrically connecting the redundant net and the cross net; and The redundant net and the redundant via are checked to determine whether the redundant net and the redundant via meet predetermined design rules.

2. The method according to claim 1, wherein The feature set includes: a first feature set comprising features of a normal pattern; and The second feature set includes features of bad patterns.

3. The method according to claim 1, in, The peripheral pattern includes a first peripheral mesh and a second peripheral mesh, Before generating the redundant net and the redundant via, the target net is located between the first peripheral net and the second peripheral net, and Wherein, analyzing the peripheral pattern comprises measuring: a first distance between the target net and the first peripheral net; and A second distance between the target net and the second peripheral net.

4. The method according to claim 1, in, The peripheral pattern includes a first peripheral mesh and a second peripheral mesh, wherein the first peripheral network is located between the target network and the second peripheral network, and Wherein, analyzing the peripheral pattern comprises measuring a distance between the first peripheral mesh and the second peripheral mesh.

5. The method according to claim 1, in, The redundant network is wider than the target network in one direction, wherein the redundant via is wider than the target via in the direction, and The generating of the redundant net and the redundant via comprises replacing the target net and the target via respectively with the redundant net and the redundant via.

6. The method according to claim 1, in, The peripheral pattern includes a peripheral net that is spaced apart from the target net, the peripheral net being located at the same level as the target net, and The peripheral network is located between the redundant network and the target network.

7. The method according to claim 6, further comprising: After the redundant net and the redundant via are generated, a timing impairment test is performed on a routing path passing through the redundant net.

8. A method for manufacturing a semiconductor device, the method comprising: providing a target design layout of the semiconductor device; selecting a target pattern from the target design layout using a prediction model that predicts a bad pattern of the semiconductor device, Wherein, the target pattern includes: a target web extending in a first direction; a first target via electrically connected to the target net; and a first crossing net electrically connected to the first target via and extending in a second direction intersecting the first direction, the first crossing net being located at a different level than the target net in a third direction intersecting the first direction and the second direction; analyzing a peripheral pattern adjacent to the target web, wherein the peripheral pattern includes a first peripheral web and a second peripheral web, the first peripheral web and the second peripheral web extending along the first direction, the first peripheral web and the second peripheral web being located at the same level as the target web in the third direction, and the first peripheral web and the second peripheral web being spaced apart from each other in the second direction; generating a redundant net, the redundant net extending along the first direction, the redundant net being located at the same level as the target net in the third direction, the redundant net being located between the first peripheral net and the second peripheral net; and A first redundant via is generated to electrically connect the redundant net and the first cross net.

9. The method according to claim 8, in, Before generating the redundant network, the target network is located between the first peripheral network and the second peripheral network, and Wherein, analyzing the peripheral pattern comprises measuring: a first distance between the target net and the first peripheral net; and A second distance between the target net and the second peripheral net.

10. The method according to claim 9, in, The redundant net is wider than the target net in the second direction, Wherein, generating the redundant network includes replacing the target network with the redundant network. wherein the first redundant via is wider than the first target via in the second direction, and The generating of the first redundant via includes replacing the first target via with the first redundant via.

11. The method according to claim 8, in, The first peripheral network is located between the target network and the second peripheral network, and Wherein, analyzing the peripheral pattern comprises measuring a distance between the first peripheral mesh and the second peripheral mesh.

12. The method according to claim 8, wherein The target pattern also includes: a second target via electrically connected to the target net; and A second cross net extending along the second direction, the second cross net being located at a different level from the target net in the third direction, or at another different level from the target net, and the second cross net being electrically connected to the second target via.

13. The method according to claim 12, further comprising: A second redundant via is generated to electrically connect the redundant net and the second cross net.

14. The method according to claim 13, wherein A first distance between the first redundant via and the second redundant via is equal to a second distance between the first target via and the second target via.

15. The method according to claim 12, wherein: The first crossing network and the second crossing network are located at different corresponding horizontal heights in the third direction.

16. A method for manufacturing a semiconductor device, the method comprising: providing a target design layout of the semiconductor device; selecting a target pattern from the target design layout, Wherein, the target pattern includes: a target web extending in a first direction; a first target via electrically connected to the target net; a second target via spaced apart from the first target via and electrically connected to the target net; a first crossing net electrically connected to the first target via and extending in a second direction intersecting the first direction, the first crossing net being located at a different level than the target net in a third direction intersecting the first direction and the second direction; and a second crossing net electrically connected to the second target via and extending along the second direction, the second crossing net being located at a different level than the target net in the third direction, or at another different level than the target net; analyzing a peripheral pattern adjacent to the target web, wherein the peripheral pattern includes a first peripheral web, the first peripheral web extending along the first direction, the first peripheral web being located at the same level as the target web in the third direction, and the first peripheral web being spaced apart from the target web in the second direction; generating a first redundant net, the first redundant net extending along the first direction, the first redundant net being located at the same level as the target net in the third direction, wherein the first peripheral net is located between the target net and the first redundant net; and A first redundant via and a second redundant via are generated, wherein the first redundant via electrically connects the first redundant net and the first cross net, and the second redundant via electrically connects the first redundant net and the second cross net.

17. The method according to claim 16, wherein A first length of a first routing path passing through the target net and extending from the first cross-net to the second cross-net is equal to a second length of a second routing path passing through the first redundant net and extending from the first cross-net to the second cross-net.

18. The method according to claim 16, further comprising: generating an extended network extending from the second crossing network along the second direction, The extended network is directly connected to the second redundant via.

19. The method according to claim 16, further comprising: generating a second redundant net, wherein the second redundant net is wider than the target net in the second direction; and The target network is replaced by the second redundant network.

20. The method according to claim 16, in, The first redundant net is wider than the target net in the second direction, and The first redundant via is wider than the first target via in the second direction.

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