Semiconductor device and method of forming the same

Abstract

A semiconductor device and method of forming the same includes first and second semiconductor fins extending from a substrate, and a source / drain region epitaxially grown in a recess of the first and second semiconductor fins. An upper surface of the source / drain region is higher than a surface level with upper surfaces of the first and second semiconductor fins. The source / drain region includes a plurality of buffer layers. Individual buffer layers are buried between individual layers of the source / drain region. An average thickness of each of the buffer layers can be from 1 A to 10 A.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices, and more particularly to methods for forming epitaxial source and / or drain regions. Background Art

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor device fabrication typically involves sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers onto a semiconductor substrate. Photolithography is then used to pattern these various material layers to form electronic components and units on the substrate.

[0003] The semiconductor industry continues to reduce minimum feature sizes, which can significantly improve the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, and the like) by allowing more components to be integrated into a given area. However, as minimum feature sizes shrink, additional problems arise that need to be addressed.

[0004] Integrated circuit processes are increasingly adopting FinFETs, which offer small size and high performance. Fully strained channels also improve FinFET performance, but fully strained channel structures also create unique challenges that need to be addressed. Summary of the Invention

[0005] An embodiment of the present invention provides a semiconductor device, comprising: a first semiconductor fin and a second semiconductor fin extending from a substrate; a gate located on the first semiconductor fin and the second semiconductor fin; and a source / drain region located on the first semiconductor fin and the second semiconductor fin and adjacent to the gate, wherein the upper surface of the source / drain region is higher than the upper surface of the first semiconductor fin and the second semiconductor fin under the gate, wherein the source / drain region includes a plurality of buffer layers and a plurality of main layers, wherein the source / drain region includes buffer layers and main layers interlaced with each other, wherein the average thickness of each buffer layer is to

[0006] An embodiment of the present invention provides a semiconductor device, comprising: a first semiconductor fin and a second semiconductor fin protruding from a substrate; and a first source / drain region located on the first semiconductor fin, and a second source / drain region located on the second semiconductor fin, wherein the first source / drain region is separated from the second source / drain region, wherein the upper surfaces of the first source / drain region and the second source / drain region are higher than the upper surfaces of the first semiconductor fin and the second semiconductor fin, wherein the first source / drain region and the second source / drain region each include: a first buffer layer; a first bulk layer located on the first buffer layer; a second buffer layer located on the first bulk layer; and a second bulk layer located on the second buffer layer, wherein the average thickness of each of the first buffer layer and the second buffer layer is to

[0007] An embodiment of the present invention provides a method for forming a semiconductor device, comprising: forming a first semiconductor fin and a second semiconductor fin protruding from a substrate; forming a first gate structure on the first semiconductor fin; recessing the first semiconductor fin to form a first recess adjacent to the first gate structure; forming a first source / drain region in the first recess, wherein the step of forming the first source / drain region comprises: epitaxially growing a first main body layer in the first recess; epitaxially growing a second main body layer on the first main body layer; and forming one or more bonding layers, wherein the step of forming each bonding layer comprises: epitaxially growing an upper main body layer; depositing a buffer layer on the upper main body layer; and recessing the sidewalls of the upper main body layer and the buffer layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a three-dimensional diagram of a FinFET in some embodiments.

[0009] Figures 2 to 7 Figures 2 to 7 、 Figures 8A to 23A 、 Figures 8B to 23B 、 Figures 11C to 17C 、 Figure 21C 、 Figures 12D to 17D FIG. 1 is a cross-sectional view of an intermediate stage of forming a fin field effect transistor in some embodiments.

[0010] Description of reference numerals:

[0011] AA, BB, CC reference sections

[0012] H1 Height

[0013] L1, L2 lateral distance

[0014] W1 width

[0015] 50 substrate

[0016] 50N, 50P, 89 areas

[0017] 51 Divider

[0018] 52 fins

[0019] 54 Insulation Materials

[0020] 56 Quarantine Zone

[0021] 58 Channel Area

[0022] 60 dummy dielectric layer

[0023] 62 dummy gate layer

[0024] 64 Mask Layers

[0025] 70 grid assembly

[0026] 72 dummy gate

[0027] 74 Mask

[0028] 80 Gate seal spacer

[0029] 81, 90 Depression

[0030] 82 Source / drain region

[0031] 82A First Floor

[0032] 82B Second Floor

[0033] 82C Third Floor

[0034] 82D Fourth Floor

[0035] 82E Fifth Floor

[0036] 84 buffer layer

[0037] 84A first buffer layer

[0038] 84B Second buffer layer

[0039] 84C third buffer layer

[0040] 84D Fourth buffer layer

[0041] 86 Gate spacer

[0042] 87 Contact Etch Stop Layer

[0043] 88 first interlayer dielectric layer

[0044] 92 gate dielectric layer

[0045] 94 gate

[0046] 94A liner

[0047] 94B work function adjustment layer

[0048] 94C filling material

[0049] 106 gate

[0050] 108 second interlayer dielectric layer

[0051] 110 Gate contact

[0052] 112 Source / Drain Contacts DETAILED DESCRIPTION

[0053] The following provides different embodiments or examples for implementing different structures of the embodiments of the present invention. The embodiments of specific components and arrangements are intended to simplify the present disclosure and are not intended to limit the present invention. For example, the description of forming a first component on a second component includes the two being in direct contact, or the two being separated by additional components rather than in direct contact. In addition, the same reference numerals may be repeatedly used in various embodiments of the present invention for simplicity, but elements with the same reference numerals in various embodiments and / or arrangements do not necessarily have the same corresponding relationship.

[0054] Additionally, spatially relative terms such as "below," "beneath," "lower," "above," "upper," or similar terms may be used to simplify the description of an element relative to another element in a diagram. Spatially relative terms extend to elements used in other orientations and are not limited to the orientation shown. Elements may also be rotated 90° or other angles, so directional terms are used only to describe the orientation shown in the diagram.

[0055] Advantageous features of one or more embodiments described herein include a multi-cycle epitaxial growth process for the source / drain regions. Multi-cycle growth employs repeated deposition and etching to limit the horizontal growth of the source / drain regions and increase their height. Limiting the horizontal growth prevents adjacent source / drain regions from merging when fabricating static random access memory devices.

[0056] Multiple cycles of deposition and etching to grow the source / drain regions increase their height. In epitaxially grown source / drain regions, the top surface of the source / drain regions can be higher than the top surface of the semiconductor fin. Multiple cycles of deposition and etching also improve the consistency of critical dimensions of the source / drain regions and increase the total volume of the source / drain regions. The higher top surface and increased volume of the source / drain regions provide larger source / drain regions for electrical coupling to metal contacts, which reduces contact resistance and improves device performance.

[0057] Figure 1 A three-dimensional diagram of a fin field-effect transistor is shown in some embodiments. The fin field-effect transistor includes a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Isolation regions 56 are located in the substrate 50, and the fin 52 protrudes from between adjacent isolation regions 56 and is higher than the isolation regions 56. Although the isolation regions 56 and the substrate 50 are described as different units in the drawings and the specification, the term "substrate" described herein may refer to a semiconductor substrate alone, or a semiconductor substrate containing an isolation region. In addition, although the fin 52 and the substrate 50 in the drawings are a single continuous material, the fin 52 and / or the substrate 50 may include a single material or multiple materials. In this document, the fin 52 refers to the portion extending between adjacent isolation regions 56.

[0058] A gate dielectric layer 92 is formed along the top surface and sidewalls of the fin 52, and a gate 94 is formed on the gate dielectric layer 92. Source / drain regions 82 are formed on both sides of the fin 52 opposite the gate dielectric layer 92 and the gate 94. Figure 1 Reference cross sections used in subsequent figures are also shown. Reference cross section AA is along the longitudinal axis of gate 94 and perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. Reference cross section BB is perpendicular to reference cross section AA and along the length of fin 52, in the direction of current flow between the source / drain regions 82 of the FinFET. Reference cross section CC is parallel to reference cross section AA and extends through the source / drain regions of the FinFET. Subsequent figures will reference these reference cross sections for clarity.

[0059] Some embodiments described herein utilize a gate-last process to form a fin field-effect transistor. In other embodiments, a gate-first process may be employed. Furthermore, some embodiments may be implemented in planar devices such as planar field-effect transistors.

[0060] Figures 2 to 23B FIG. 1 is a cross-sectional view of an intermediate stage of forming a fin field effect transistor in some embodiments. Figures 2 to 7 Display along Figure 1 The cross-sectional view shown with reference to section AA differs from that shown in that multiple fins and / or FinFETs are included. Figure 8A 、 Figure 9A 、 Figure 10A 、 Figure 11A 、 Figure 12A 、 Figure 13A 、 Figure 14A 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18A 、 Figure 19A 、 Figure 20A 、 Figure 21A 、 Figure 22A ,and Figure 23A Display along Figure 1 The cross-sectional view shown is a reference cross-sectional view of section AA, and Figure 8B 、 Figure 9B 、 Figure 10B 、 Figure 11B 、 Figure 12B 、 Figure 13B 、 Figure 14B 、 Figure 15B 、 Figure 16B 、 Figure 17B 、 Figure 18B 、 Figure 19B 、 Figure 20B 、 Figure 21B 、 Figure 21C 、 Figure 22B ,and Figure 23B Display along Figure 1 The cross-sectional view shown with reference to section BB differs from the plurality of fins and / or FinFETs. Figure 11C 、 Figure 12C 、 Figure 12D 、 Figure 13C 、 Figure 13D 、 Figure 14C 、 Figure 14D 、 Figure 15C 、 Figure 15D 、 Figure 16C 、 Figure 16D 、 Figure 17C ,and Figure 17D Display along Figure 1 The cross-section shown is referenced to section CC, with the difference being multiple fins and / or FinFETs.

[0061] exist Figure 2 In the embodiment, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator substrate, or the like, which may be doped (e.g., doped with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer such as a silicon wafer. Generally speaking, a semiconductor-on-insulator substrate is a semiconductor material layer formed on an insulating layer. For example, the insulating layer may be a buried oxide layer, a silicon oxide layer, or the like. The insulating layer is located on the substrate, and the substrate is typically a silicon substrate or a glass substrate. Other substrates such as multi-layer substrates or composition-gradient substrates may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, a semiconductor compound (e.g., silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide), a semiconductor alloy (e.g., silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide), or a combination thereof.

[0062] Substrate 50 has a region 50N and a region 50P. Region 50N may be used to form an n-type device, such as an n-type metal oxide semiconductor transistor, such as an n-type fin field effect transistor. Region 50P may be used to form a p-type device, such as a p-type metal oxide semiconductor transistor, such as a p-type fin field effect transistor. Region 50N may be physically separated from region 50P (e.g., as shown by separation line 51), and any number of device structures (e.g., other active devices, doped regions, isolation structures, or the like) may be located between regions 50N and 50P.

[0063] exist Figure 3 In the embodiment of the present invention, fins 52 are formed in substrate 50. Fins 52 are semiconductor strips. In some embodiments, trenches may be etched in substrate 50 to form fins 52 in substrate 50. The etching process may be any acceptable etching process, such as reactive ion etching, neutral beam etching, similar methods, or combinations thereof. The etching process may be anisotropic.

[0064] The fins may be patterned by any suitable method. For example, the fins may be patterned using one or more photolithographic processes, including double patterning or multiple patterning processes. Generally, double patterning or multiple patterning processes combine photolithography with a self-aligned process to produce a pattern pitch that is smaller than the pattern pitch obtained using a single direct photolithographic process. For example, one embodiment forms a sacrificial layer on a substrate and patterns the sacrificial layer using a photolithographic process. Spacers are formed along the sides of the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the fins are patterned using the retained spacers.

[0065] exist Figure 4 In the embodiment, the insulating material 54 is formed on the substrate 50 and between the adjacent fins 52. The insulating material 54 can be an oxide such as silicon oxide, nitride, the like, or a combination thereof, and its formation method can be high-density plasma chemical vapor deposition, flowable chemical vapor deposition (such as depositing a chemical vapor deposition-based material in a remote plasma system and then curing the material to convert it into another material such as an oxide), a similar method, or a combination thereof. Other insulating materials formed by any acceptable process can also be used. In the embodiment, the insulating material 54 is silicon oxide formed by a flowable chemical vapor deposition process. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material 54 is formed so that excess insulating material 54 covers the fins 52. Although the insulating material 54 in the drawings is a single layer, some embodiments may use multiple layers of insulating material 54. For example, some embodiments may first form a liner layer (not shown) along the surface of the substrate 50 and the fins 52. The above-mentioned filling material can then be formed on the liner layer.

[0066] exist Figure 5 In the process, a removal process is performed on the insulating material 54 to remove excess insulating material 54 on the fin 52. In some embodiments, a planarization process such as chemical mechanical polishing, an etch-back process, a combination thereof, or the like may be used. The planarization process exposes the fin 52 so that the fin 52 is flush with the upper surface of the insulating material 54 after the planarization process.

[0067] exist Figure 6In the embodiment of the present invention, the insulating material 54 is recessed to form the isolation region 56 of the shallow trench. The insulating material 54 is recessed so that the upper portion of the fin 52 in the region 50N and the region 50P protrudes from between the isolation regions 56 of the adjacent shallow trenches. In addition, the upper surface of the isolation region 56 of the shallow trench may be a flat surface (as shown), a raised surface, a recessed surface (such as dishing), or a combination thereof. By suitable etching, the isolation region 56 of the shallow trench can have a flat, raised, or recessed upper surface. The isolation region 56 of the shallow trench can be recessed by an acceptable etching process, such as an etching process that is selective for the insulating material 54. For example, the etching process etches the insulating material 54 faster than the rate at which the material of the fin 52 is etched. For example, a chemical oxide removal method can be used in combination with a suitable etching process (such as using dilute hydrofluoric acid).

[0068] Figures 2 to 6 The process shown is only one example of how to form the fin 52. In some embodiments, the fin may be formed by an epitaxial growth process. For example, a dielectric layer may be formed on the upper surface of the substrate 50, and a trench may be etched through the dielectric layer to expose the substrate 50 below. A homoepitaxial structure may be epitaxially grown in the trench, and the dielectric layer may be recessed so that the homoepitaxial structure protrudes from the dielectric layer to form the fin. In addition, some embodiments may use a heteroepitaxial structure as the fin 52. For example, Figure 5 The fin 52 in the substrate 50 is recessed, and a material different from the fin 52 can be epitaxially grown on the recessed fin 52. In these embodiments, the fin 52 includes the recessed material, and the epitaxially grown material located on the recessed material. In other embodiments, a dielectric layer can be formed on the upper surface of the substrate 50, and a trench can be etched through the dielectric layer. A heteroepitaxial structure of a material different from the substrate 50 can then be epitaxially grown in the trench, and the dielectric layer is recessed so that the heteroepitaxial structure protrudes from the dielectric layer to form the fin 52. In some embodiments, a homoepitaxial structure or a heteroepitaxial structure is epitaxially grown, and the epitaxially grown material can be in-situ doped during growth to omit previous and subsequent implantation, but in-situ doping and implantation doping can also be used in combination.

[0069] Furthermore, epitaxially growing different materials in region 50N (eg, n-type metal oxide semiconductor region) and region 50P (eg, p-type metal oxide semiconductor region) has advantages. In various embodiments, the composition of the upper portion of fin 52 may be silicon germanium (SiGe). x Ge 1-x, where x can be 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V semiconductor compound, a II-VI semiconductor compound, or the like. For example, feasible materials for forming a III-V semiconductor compound include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, or the like.

[0070] also, Figure 6 Suitable wells (not shown) may be formed in fin 52 and / or substrate 50. In some embodiments, a p-type well may be formed in region 50N, and an n-type well may be formed in region 50P. In some embodiments, a p-type well (or an n-type well) may be formed in both regions 50N and 50P.

[0071] In embodiments of wells of different configurations, a photoresist or other mask (not shown) may be used to achieve the different implantation steps used in regions 50N and 50P. For example, a photoresist may be formed on the fin 52 and the isolation region 56 of the shallow trench in region 50N. The photoresist is patterned to expose region 50P (e.g., a p-type metal oxide semiconductor region) of the substrate 50. The photoresist may be formed using a spin coating technique and patterned using an acceptable photolithography technique. Once the photoresist is patterned, n-type impurity implantation may be performed in region 50P, and the photoresist may act as a mask to substantially prevent n-type impurities from being implanted into region 50N (e.g., an n-type metal oxide semiconductor region). The n-type impurity may be phosphorus, arsenic, or the like, implanted into the region at a concentration less than or equal to 10 18 cm -3 , for example about 10 17 cm -3 to about 10 18 cm -3 The photoresist is removed after implantation, and the removal method can be an acceptable ashing process.

[0072] After implanting the region 50P, a photoresist is formed on the fin 52 and the isolation region 56 of the shallow trench in the region 50P. The patterned photoresist has exposed the region 50N (such as the n-type metal oxide semiconductor region) of the substrate 50. The photoresist can be formed by a spin coating technique and patterned using an acceptable photolithography technique. Once the photoresist is patterned, the implantation of p-type impurities can be performed in the region 50N, and the photoresist can be used as a mask to substantially prevent the implantation of p-type impurities into the region 50P (such as the p-type metal oxide semiconductor region). The p-type impurity can be boron, boron difluoride, or the like, and the concentration of the p-type impurity implanted in the region is less than or equal to 10 18 cm -3 , for example about 10 17 cm -3 to about 10 18 cm-3 After implantation, the photoresist can be removed, and the removal method can be an acceptable ashing process.

[0073] After implanting regions 50N and 50P, an annealing step may be performed to activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material may be in-situ doped during epitaxial fin growth, omitting the implantation step. However, in-situ doping and implantation doping can be used in conjunction.

[0074] exist Figure 7 In the embodiment of the present invention, a dummy dielectric layer 60 is formed on the fin 52. For example, the dummy dielectric layer 60 can be silicon oxide, silicon nitride, a combination thereof, or the like, and can be formed according to an acceptable technique such as deposition or thermal growth. A dummy gate layer 62 is formed on the dummy dielectric layer 60, and a mask layer 64 is formed on the dummy gate layer 62. The dummy gate layer 62 can be deposited on the dummy dielectric layer 60, and then the dummy gate layer 62 can be planarized (e.g., by chemical mechanical polishing). The mask layer 64 can be deposited on the dummy gate layer 62. The dummy gate layer 62 can be a conductive material, which can be polysilicon, polysilicon germanium, metal nitride, metal silicide, metal oxide, or metal. In one embodiment, amorphous silicon is deposited and then recrystallized to produce polysilicon. The dummy gate layer 62 can be deposited by physical vapor deposition, chemical vapor deposition, sputtering deposition, or other known techniques used to deposit conductive materials. The composition of the dummy gate layer 62 can be other materials with high etching selectivity when etching the isolation region. For example, the mask layer 64 can include silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 pass over the region 50N and the region 50P. In some embodiments, separate dummy gate layers and separate mask layers can be formed in the region 50N and the region 50P, respectively. It is worth noting that although the dummy dielectric layer 60 in the figure only covers the fin 52, this is only for illustrative purposes. In some embodiments, the dummy dielectric layer 60 can be deposited so that the dummy dielectric layer 60 covers the isolation region 56 of the shallow trench and extends between the dummy gate layer 62 and the isolation region 56 of the shallow trench.

[0075] Figures 8A to 23B There are various additional steps in forming the device of the embodiments. Figures 8A to 23B The structure shown may be in region 50N and region 50P. For example, Figures 8A to 23B The illustrated structure can be implemented in both regions 50N and 50P. If there are any differences between the structures of region 50N and region 50P, they will be described with reference to the accompanying drawings.

[0076] exist Figure 8A and Figure 8BIn the embodiment of the present invention, the mask layer 64 can be patterned using acceptable photolithography and etching techniques to form a mask 74. The pattern of the mask 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of the mask 74 can also be transferred to the dummy dielectric layer 60 using acceptable etching techniques to form a dummy gate 72. The dummy gate 72 covers the channel region 58 of each fin 52. The pattern of the mask 74 can be used to physically separate adjacent dummy gates 72. The length direction of the dummy gate 72 can also be substantially perpendicular to the length direction of each epitaxial fin 52.

[0077] also, Figure 8A and Figure 8B The gate sealing spacer 80 may be formed on the exposed surface of the dummy gate 72, the mask 74, and / or the fin 52. The gate sealing spacer 80 may be formed by performing anisotropic etching after thermal oxidation or deposition.

[0078] After forming the gate seal spacer 80, implantation of lightly doped source / drain regions (not shown) may be performed. Figure 6 The impurities described above are similar), a mask such as a photoresist can be formed on the region 50N and expose the region 50P, and impurities of a suitable form (such as n-type or p-type) can be implanted into the fin 52 exposed in the region 50P. The mask can then be removed. A mask such as a photoresist can then be formed on the region 50P and expose the region 50N, and impurities of a suitable type can be implanted into the fin 52 exposed in the region 50N. The mask can then be removed. The n-type impurity can be any of the aforementioned n-type impurities, and the p-type impurity can be any of the aforementioned p-type impurities. The impurity concentration of the lightly doped source / drain region can be about 10 15 cm -3 to about 10 16 cm -3 Annealing can be used to activate the implanted impurities.

[0079] exist Figure 9A and Figure 9B , a gate spacer 86 is formed on the gate sealing spacer 80 along the sidewalls of the dummy gate 72 and the mask 74. The gate spacer 86 may be formed by conformally depositing an insulating material followed by anisotropic etching of the insulating material. The insulating material of the gate spacer 86 may be silicon nitride, silicon carbonitride, a combination thereof, or the like. The gate spacer 86 may comprise multiple layers. The layers of the gate spacer 86 may also comprise different materials. The anisotropic etching may not completely remove the horizontal portion of the gate spacer 86 from the isolation region 56 between adjacent fins 52. In these embodiments, the unremoved horizontal portion of the gate spacer 86 may cover the upper surface of the isolation region 56 between adjacent fins 52. The dummy gate 72, the mask 74, and the gate spacer 86 comprise the gate assembly 70.

[0080] exist Figure 10A and Figure 10B In FIG. 5 , a recess 81 is etched into the fin 52. The etching process can be isotropic or anisotropic, which can be selective to one or more crystallographic planes of the fin material. Figure 10B The recess 81 is shown as having a rounded bottom profile, but the recess 81 can actually have a variety of profiles depending on the etching process used. The etching process can be dry etching (such as reactive ion etching, neutral beam etching, or the like) or wet etching (such as wet etching using tetramethylammonium hydroxide, ammonium hydroxide, or other etchants). Figure 10B A depression 81 is shown, which is along Figure 1 Reference section BB is shown.

[0081] exist 11A to 17D In the embodiment of the present invention, epitaxial source / drain regions 82 are formed in the fin 52 to apply stress to each channel region 58, thereby improving performance. The epitaxial source / drain regions 82 are formed in the fin 52 so that each dummy gate 72 is located between a respective pair of adjacent epitaxial source / drain regions 82. The epitaxial source / drain regions 82 may extend into the fin 52. Gate spacers 86 may be used to separate the epitaxial source / drain regions 82 from the dummy gate 72 at an appropriate lateral distance so that the epitaxial source / drain regions 82 do not short to the subsequently formed gate of the final fin field-effect transistor.

[0082] The epitaxial source / drain regions 82 in region 50N (e.g., an n-type metal oxide semiconductor region) may be formed by masking region 50P (e.g., a p-type metal oxide semiconductor region) and etching the source / drain regions of the fin 52 in region 50N to form a recess in the fin 52. The epitaxial source / drain regions 82 in region 50N are then epitaxially grown in the recess. The epitaxial source / drain regions 82 may comprise any acceptable material, such as a material suitable for an n-type fin field effect transistor. For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in region 50N may comprise a material that applies tensile stress to the channel region 58, such as silicon, silicon carbide, silicon carbon phosphide, silicon phosphide, or the like. The epitaxial source / drain regions 82 in region 50N may also have surfaces that are raised from respective surfaces of the fin 52. In one embodiment, the epitaxial source / drain regions 82 may be epitaxially grown in the region 50N, and the epitaxial growth process does not produce crystal facets. In other embodiments, the epitaxial source / drain regions 82 may have crystal facets.

[0083] The epitaxial source / drain regions 82 in region 50P (e.g., a p-type metal oxide semiconductor region) may be formed by masking region 50N (e.g., an n-type metal oxide semiconductor region) and etching the source / drain regions of the fin 52 in region 50P to form a recess in the fin 52. The epitaxial source / drain regions 82 in region 50P are then epitaxially grown in the recess. The epitaxial source / drain regions 82 may comprise any acceptable material, such as a material suitable for a p-type fin field effect transistor. For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in region 50P may comprise a material that applies compressive stress to the channel region 58, such as silicon germanium, silicon germanium boride, germanium, germanium tin, or the like. The epitaxial source / drain regions 82 in region 50P may also have surfaces that are raised from respective surfaces of the fin 52. In one embodiment, the epitaxial source / drain regions 82 may be epitaxially grown in the region 50P, and the epitaxial growth process does not produce crystal facets. In other embodiments, the epitaxial source / drain regions 82 may have crystal facets.

[0084] The epitaxial source / drain regions 82 and / or fins 52 may be implanted with dopants to form source / drain regions, followed by annealing. The implantation steps may be similar to the steps for forming lightly doped source / drain regions described above. The impurity concentration of the source / drain regions may be approximately 10 19 cm -3 to about 10 21 cm -3 The n-type and / or p-type impurities used in the source / drain regions may be any of the impurities described above. In some embodiments, in-situ doping may be performed during the growth of the epitaxial source / drain regions 82 .

[0085] 11A to 17D The step of forming epitaxial source / drain regions 82 in region 50P is shown. The source / drain regions 82 may comprise boron-doped silicon germanium (eg, Si x Ge 1-x , and x can be 0 to 1). In some embodiments, each epitaxial source / drain region 82 includes a first layer 82A, a second layer 82B, a third layer 82C, a fourth layer 82D, and a fifth layer 82E. Figure 17B As shown in FIG. First layer 82A may also be referred to as a first bulk layer, second layer 82B may also be referred to as a second bulk layer, third layer 82C may also be referred to as a third bulk layer, fourth layer 82D may also be referred to as a fourth bulk layer, and fifth layer 82E may also be referred to as a fifth bulk layer. In other embodiments, epitaxial source / drain regions 82 may have fewer or more layers. In other embodiments of n-type metal oxide semiconductor devices, epitaxial source / drain regions 82 may be formed in region 50N and may comprise silicon doped with arsenic or phosphorus.

[0086] The epitaxial growth method of the epitaxial source / drain region 82 can adopt organic metal chemical vapor deposition, molecular tree epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, a combination of the above, or the like. When the composition of the epitaxial source / drain region 82 is boron-doped silicon germanium, the epitaxial growth process adopts a suitable silicon precursor, a suitable germanium precursor, and a suitable boron precursor. The boron source provided by the boron precursor can be used to in-situ dope the epitaxial source / drain region 82 during the epitaxial growth process. The suitable silicon precursor can be silane, disilane, trisilane, a combination of the above, or the like. In some embodiments, the suitable germanium precursor can be tetrahydrogermanium, digermane, a combination of the above, or the like. In other embodiments, the suitable boron precursor can be diborane.

[0087] Figure 11B and Figure 11C The steps of forming the first layer 82A in an exemplary process are shown. The dotted line around the fin 52 shows the maximum height of the fin 52 in the reference cross section AA, for comparison. Figure 11C The height of the epitaxial source / drain regions in the reference cross section CC is compared. In the exemplary process,

[0088] The germanium concentration of the first layer 82A may be about 10 atomic % to 40 atomic %. In some embodiments, the boron concentration of the first layer 82A may be about 5×10 19 atoms / cm 3 to 2×10 21 atoms / cm 3 The flow rate of the silicon precursor may be approximately 5 sccm to approximately 500 sccm, and the flow rate of the germanium precursor may be approximately 10 sccm to approximately 800 sccm. The flow rate of the boron precursor may be approximately 10 sccm to approximately 800 sccm. The temperature of the epitaxial growth process may be approximately 350° C. to approximately 800° C., and the pressure may be approximately 5 Torr to approximately 450 Torr.

[0089] Figure 11B and Figure 11C The step of forming a first buffer layer 84A on the first layer 82A is further shown. The first buffer layer 84A may include silicon germanium (Si 1-x Ge x , x may be 0 to 0.1), which may be doped with boron. In some embodiments, a buffer layer is located in the source / drain region 82 to improve the epitaxial growth of the source / drain structure. The germanium concentration of the first buffer layer 84A is about 0 atomic % to about 15 atomic %. The boron concentration of the first buffer layer 84A may be about 0 atoms / cm 3 to 5×10 20 atoms / cm 3The flow rate of the silicon precursor may be about 5 sccm to about 500 sccm. In some embodiments, the flow rate of the germanium precursor may be about 10 sccm to about 800 sccm, and the flow rate of the boron precursor may be about 10 sccm to about 800 sccm. The temperature of the epitaxial growth process may be about 350°C to about 800°C, and the pressure may be about 5 Torr to about 450 Torr. The thickness of the first buffer layer 84A may be about to about

[0090] Figure 12B 、 Figure 12C ,and Figure 12D The step of forming the second layer 82B is shown. Figure 12C The embodiment shown includes fabricating a logic circuit where source / drain regions on adjacent fins are merged. Figure 12D The embodiments shown include fabricating a static random access memory device in which the source / drain regions on adjacent fins are separated and not merged. The merging of the source / drain regions on adjacent fins can be limited by an etching process that is selective for dense areas of the source / drain regions. The etching process can be a dry etch, and the etchant used includes hydrofluoric acid, hydrogen chloride, hydrogen bromide, a fluorine-containing gas (such as carbon tetrafluoride, difluoromethane, fluoromethane, fluoroform, octafluorocyclobutane, hexafluorobutadiene, nitrogen trifluoride, or sulfur hexafluoride), some carbon polymer gases (such as methane, carbon monoxide, carbon dioxide, or carbonyl sulfide), the like, or a combination thereof. The dry etching can be performed at a suitable pressure (such as about 2 mTorr to about 100 mTorr) and a suitable temperature (such as about 30°C to about 80°C).

[0091] The germanium concentration of the second layer 82B may be about 30 atomic % to about 70 atomic %, and the boron concentration of the second layer 82B may be about 1×10 20 atoms / cm 3 to 2×10 21 atoms / cm 3. The flow rate of the silicon precursor may be from about 5 sccm to about 500 sccm, and the flow rate of the germanium precursor may be from about 10 sccm to about 800 sccm. The flow rate of the boron precursor may be from about 10 sccm to about 800 sccm. The temperature of the epitaxial growth process may be from about 350°C to about 800°C, and the pressure may be from about 5 Torr to about 450 Torr. The epitaxial growth process may be performed so that the second layer 82B does not have a crystal plane. An etching process that is selective to the dense area of ​​the source / drain region may be performed to limit the growth of the crystal plane. The etching process may be dry etching, and the etchant used includes hydrofluoric acid, hydrogen chloride, hydrogen bromide, a fluorine-containing gas (such as carbon tetrafluoride, difluoromethane, fluoromethane, fluoroform, octafluorocyclobutane, hexafluorobutadiene, nitrogen trifluoride, or sulfur hexafluoride), some carbon polymer gases (such as methane, carbon monoxide, carbon dioxide, or carbonyl sulfide), the like, or a combination thereof. The dry etching may be performed at a suitable pressure (eg, about 2 mTorr to about 100 mTorr) and a suitable temperature (eg, about 30° C. to about 80° C.).

[0092] like Figure 12C As shown, in an embodiment where the source / drain regions on adjacent fins are merged, the lateral distance L1 between the fin 52 and the outer vertex of the second layer 82B can be less than about 10 nm. The ratio of the width W1 of the fin 52 to the lateral distance L1 can be about 3:10 to 3:3. In addition, an air gap can be located between the second layer 82B and the gate spacer 86, as shown in FIG. Figure 12C As shown, the height H1 of the air gap may be from about 5 nm to about 30 nm.

[0093] Figure 12B 、 Figure 12C ,and Figure 12D The second buffer layer 84B is formed on the second layer 82B. The second buffer layer 84B may include silicon germanium (Si 1-x Ge x , x may be 0 to 0.15), which may be doped with boron. In some embodiments, a buffer layer is located in the source / drain region 82 to improve the epitaxial growth of the source / drain structure. The germanium concentration of the second buffer layer 84B is about 0 atomic % to about 15 atomic %. The boron concentration of the second buffer layer 84B may be about 0 atoms / cm 3 to 5×10 20 atoms / cm 3 The flow rate of the silicon precursor may be about 5 sccm to about 500 sccm. In some embodiments, the flow rate of the germanium precursor may be about 10 sccm to about 800 sccm, and the flow rate of the boron precursor may be about 10 sccm to about 800 sccm. The temperature of the epitaxial growth process may be about 350°C to about 800°C, and the pressure may be about 5 Torr to about 450 Torr. The thickness of the second buffer layer 84B may be about to about

[0094] Figures 13C to 16D In the embodiment shown, two cycles of deposition and etch-back steps are performed for the additional epitaxial growth layer of the source / drain regions 82. In other embodiments, more than two cycles of deposition and etch steps may be performed. Figure 13C and Figure 13D The step of forming the third layer 82C is shown. Figure 13C The embodiment shown includes fabricating a logic circuit where source / drain regions on adjacent fins are merged. Figure 13D The embodiment shown includes fabricating a static random access memory device in which the source / drain regions on adjacent fins are separated and not merged. The germanium concentration of the third layer 82C may be about 30 atomic % to about 70 atomic %, and the boron concentration of the third layer 82C may be about 2×10 20 atoms / cm 3 to 2×10 21 atoms / cm 3 The flow rate of the silicon precursor may be approximately 5 sccm to approximately 500 sccm, and the flow rate of the germanium precursor may be approximately 10 sccm to approximately 800 sccm. The flow rate of the boron precursor may be approximately 10 sccm to approximately 800 sccm. The temperature of the epitaxial growth process may be approximately 350° C. to approximately 800° C., and the pressure may be approximately 5 Torr to approximately 450 Torr.

[0095] Figure 13C and Figure 13D The third buffer layer 84C is formed on the third layer 82C. The third buffer layer 84C may include silicon germanium (Si 1-x Ge x , x may be 0 to 0.15), which may be doped with boron. In some embodiments, a buffer layer is located in the source / drain region 82 to improve the epitaxial growth of the source / drain structure. The germanium concentration of the third buffer layer 84C is about 0 atomic % to about 15 atomic %. The boron concentration of the third buffer layer 84C may be about 0 atoms / cm 3 to 5×10 20 atoms / cm 3 The flow rate of the silicon precursor may be about 5 sccm to about 500 sccm. In some embodiments, the flow rate of the germanium precursor may be about 10 sccm to about 800 sccm, and the flow rate of the boron precursor may be about 10 sccm to about 800 sccm. The temperature of the epitaxial growth process may be about 350°C to about 800°C, and the pressure may be about 5 Torr to about 450 Torr. The thickness of the third buffer layer 84C may be about to about

[0096] Figure 14C and Figure 14DThe step of first etching back the third layer 82C and the third buffer layer 84C is shown. Figure 14C The embodiment shown includes fabricating logic circuits where source / drain regions on adjacent fins can be merged. Figure 14D The embodiments shown include fabricating a static random access memory device in which the source / drain regions on adjacent fins are separated and not merged. The first etch back process may be a dry etch using a gas comprising hydrogen chloride, hydrofluoric acid, hydrogen bromide, hydrogen, germanium, or a combination thereof. In some embodiments, the dry etch uses a mixed gas comprising hydrogen chloride, germanium, and hydrogen. The temperature of the first etch back may be from about 400°C to about 700°C and last from 20 seconds to 600 seconds. The first etch back may use nitrogen or hydrogen as a carrier gas. After the first etch back, a purge step may be performed using hydrogen, which lasts from about 10 seconds to about 60 seconds. As Figure 14C and Figure 14D As shown, the first etch-back removes portions of the third layer 82C and the third buffer layer 84C on respective sidewalls to reduce the horizontal widths of the third layer 82C and the third buffer layer 84C. Figure 14D In some embodiments shown, such as SRAM devices, reducing the horizontal width helps prevent adjacent source / drain regions 82 from merging.

[0097] Figure 15C and Figure 15D The step of forming the fourth layer 82D is shown. Figure 15C The embodiment shown includes fabricating a logic circuit where source / drain regions on adjacent fins are merged. Figure 15D The embodiment shown includes fabricating a static random access memory device in which the source / drain regions on adjacent fins are separated and not merged. The germanium concentration of the fourth layer 82D may be about 30 atomic % to about 70 atomic %, and the boron concentration of the fourth layer 82D may be about 2×10 20 atoms / cm 3 to 2×10 21 atoms / cm 3 The flow rate of the silicon precursor may be approximately 5 sccm to approximately 500 sccm, and the flow rate of the germanium precursor may be approximately 10 sccm to approximately 800 sccm. The flow rate of the boron precursor may be approximately 10 sccm to approximately 800 sccm. The temperature of the epitaxial growth process may be approximately 350° C. to approximately 800° C., and the pressure may be approximately 5 Torr to approximately 450 Torr.

[0098] Figure 15C and Figure 15D The fourth buffer layer 84D is formed on the fourth layer 82D. The fourth buffer layer 84D may include silicon germanium (Si 1-x Ge x, x may be 0 to 0.15), which may be doped with boron. The germanium concentration of the fourth buffer layer 84D is about 0 atomic % to about 15 atomic %, and the boron concentration of the fourth buffer layer 84D may be about 0 atoms / cm 3 to 5×10 20 atoms / cm 3 The flow rate of the silicon precursor may be about 5 sccm to about 500 sccm. The flow rate of the germanium precursor may be about 10 sccm to about 800 sccm, and the flow rate of the boron precursor may be about 10 sccm to about 800 sccm. The temperature of the epitaxial growth process may be about 350° C. to about 800° C., and the pressure may be about 5 Torr to about 450 Torr. The thickness of the fourth buffer layer 84D may be about to about

[0099] Figure 16C and Figure 16D The second step of etching back the fourth layer 82D and the fourth buffer layer 84D is shown. Figure 16C The illustrated embodiment includes fabricating logic circuits where source / drain regions on adjacent fins are merged. Figure 16D The embodiment shown includes making a static random access memory device in which the source / drain regions on adjacent fins are separated and not merged. The second back etch process may be a dry etch, which may use hydrogen chloride, hydrofluoric acid, hydrogen bromide, hydrogen, germanium, the like, or a combination thereof. In some embodiments, the dry etch uses a mixed gas containing hydrogen chloride, germanium, and hydrogen. The temperature of the second back etch is between 400°C and about 700°C, and lasts for 20 seconds to 600 seconds. The second back etch may use nitrogen or hydrogen as a carrier gas. After the second back etch, hydrogen may be used for purge, and the purge time is about 10 seconds to 60 seconds. As Figure 16C and Figure 16D As shown, the second etch-back may remove portions of the fourth layer 82D and the fourth buffer layer 84D on respective sidewalls to reduce the horizontal widths of the fourth layer 82D and the fourth buffer layer 84D.

[0100] like 17B to 17D As shown, a fifth layer 82E is formed and the source / drain regions 82 are completed. Figure 17B Along Figure 1 Reference cross section BB of shows the completed source / drain regions 82 . Figure 17C Along Figure 1 Reference cross section CC is shown and illustrates an embodiment of fabricating a logic circuit where source / drain regions on adjacent fins are merged. Figure 17D Along Figure 1 Reference cross section CC is shown and illustrates an embodiment of fabricating a static random access memory device in which the source / drain regions on adjacent fins are separated and not merged. 17B to 17DIn some embodiments shown, the fifth layer 82E is formed on the fourth layer 82D and the fourth buffer layer 84D. The fifth layer 82E may also be referred to as a cap layer or a protective layer. The fifth layer may include boron-doped silicon germanium (Si 1-x Ge x , where x can be 0 to 0.3). The deposition method or epitaxial growth method of the fifth layer 82E can be organic metal chemical vapor deposition, molecular beam epitaxy, liquid phase epitaxy, vapor phase epitaxy, selective epitaxial growth, a combination of the above, or a similar method. The thickness of the fifth layer 82E can be less than 6nm. The total thickness of the deposited layer of the source / drain region 82 and the buffer layer 84 can be about 40nm to about 80nm. In one embodiment, the total thickness of the deposited layer of the source / drain region 82 and the buffer layer 84 is about 12nm. Figure 17D As shown, in embodiments where the source / drain regions on adjacent fins are separated rather than merged, the lateral distance L2 between the sidewalls of the fin 52 and the outer vertices of the source / drain regions 82 can be less than half the spacing between adjacent fins 52 to prevent merging of the epitaxial source / drain regions 82. For example, lateral distance L2 can be approximately 15 nm. The ratio of the width W1 of the fin 52 to the lateral distance L2 can be between approximately 1:1 and 1:2.5.

[0101] exist Figure 18A and Figure 16B In the embodiment, a first interlayer dielectric layer 88 is deposited on Figure 10A and Figure 10B The first interlayer dielectric layer 88 may be composed of a dielectric material and may be deposited by any suitable method such as chemical vapor deposition, plasma-assisted chemical vapor deposition, or flowable chemical vapor deposition. The dielectric material may include phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like. The semiconductor material may include amorphous silicon, silicon germanium (SiGe), or the like. x Ge 1-x , where x may be between approximately 0 and 1), pure germanium, or the like. Other insulating or semiconductor materials formed using any acceptable process may also be used. In some embodiments, a contact etch stop layer 87 is located between the first interlayer dielectric layer 88 and the epitaxial source / drain regions 82, the hard mask 74, and the gate spacer 86. The contact etch stop layer 87 may comprise a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like that has a different etch rate than the overlying first interlayer dielectric layer 88.

[0102] exist Figure 19A and Figure 19BDuring the process, a planarization process, such as chemical mechanical polishing, can be performed to make the upper surface of the first interlayer dielectric layer 88 flush with the upper surface of the dummy gate 72. The planarization process can also remove the mask 74 on the dummy gate 72, as well as the portions of the gate sealing spacer 80 and the gate spacer 86 along the sidewalls of the mask 74. After the planarization process, the upper surface of the dummy gate 72, the upper surface of the gate sealing spacer 80, and the upper surface of the gate spacer 86 are flush with the upper surface of the first interlayer dielectric layer 88. In summary, the upper surface of the dummy gate 72 can be exposed from the first interlayer dielectric layer 88.

[0103] exist Figure 20A and Figure 20B In the embodiment of the present invention, the dummy gate 72 is removed by an etching step to form a recess 90. Portions of the dummy dielectric layer 60 in the recess 90 may also be removed. In some embodiments, only the dummy gate 72 is removed, leaving the dummy dielectric layer 60 exposed in the recess 90. In some embodiments, the dummy dielectric layer 60 is removed from the recess 90 in a first region of the die (e.g., the core logic region), while the dummy dielectric layer 60 in a second region of the die (e.g., the input / output region) remains in the recess 90. In some embodiments, the dummy gate 72 is removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas that selectively etches the dummy gate 72 without etching the first interlayer dielectric layer 88 or the gate spacer 86. Each recess 90 exposes the channel region 58 of a respective fin 52. Each channel region 58 is located between a pair of adjacent epitaxial source / drain regions 82. The dummy dielectric layer 60 serves as an etch stop when etching away the dummy gate 72. After removing the dummy gate 72 , the dummy dielectric layer 60 may be removed as appropriate.

[0104] exist Figure 21A and Figure 21B In the process, a gate dielectric layer 92 and a gate 94 are formed for replacing the gate. Figure 21C show Figure 21BDetail of region 89 in the figure. A gate dielectric layer 92 is conformally deposited in the recess 90, such as on the upper surface and sidewalls of the fin 52, on the sidewalls of the gate seal spacer 80, and on the sidewalls of the gate spacer 86. The gate dielectric layer 92 may also be formed on the upper surface of the first interlayer dielectric layer 88. In some embodiments, the gate dielectric layer 92 comprises silicon oxide, silicon nitride, or a multilayer thereof. In some embodiments, the gate dielectric layer 92 is a high-k dielectric material. In these embodiments, the gate dielectric layer 92 may have a dielectric constant greater than approximately 7.0 and may comprise a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, magnesium, barium, titanium, lead, or a combination thereof. The gate dielectric layer 92 may be formed by molecular beam deposition, atomic layer deposition, plasma-assisted chemical vapor deposition, or the like. In the embodiment where a portion of the dummy dielectric layer 60 remains in the recess 90 , the gate dielectric layer 92 includes the material of the dummy dielectric layer 60 (eg, silicon oxide).

[0105] A gate 94 is deposited on the gate dielectric layer 92 and fills the remainder of the recess 90. The gate 94 can be a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, although Figure 21B A single-layer gate 94 is shown, but the gate 94 may include any number of liner layers 94A, any number of work function adjustment layers 94B, and filler material 94C, such as Figure 21C As shown. After gate 94 is filled, a planarization process, such as chemical mechanical polishing, may be performed to remove excess portions of gate dielectric layer 92 and gate 94 material located on the upper surface of first interlayer dielectric layer 88. Thus, the remaining portion of gate 94 material and gate dielectric layer 92 form the replacement gate of the final fin field-effect transistor. Gate 94 and gate dielectric layer 92 may be collectively referred to as a gate stack. The gate and gate stack may extend along the sidewalls of channel region 58 of fin 52.

[0106] The gate dielectric layer 92 in the region 50N and the region 50P may be formed simultaneously so that the gate dielectric layer 92 in each region is composed of the same material. The gate 94 may also be formed simultaneously so that the gate 94 in each region is composed of the same material. In some embodiments, the gate dielectric layer 92 in each region may be formed by a separate process so that the gate dielectric layer 92 in each region may be a different material. The gate 94 in each region may be formed by a separate process so that the gate 94 in each region may be a different material. When using separate processes, a variety of masking steps may be used to mask and expose appropriate areas. Figure 22A and Figure 22BIn the embodiment, the second interlayer dielectric layer 108 is deposited on the first interlayer dielectric layer 88. In one embodiment, the second interlayer dielectric layer 108 is a flowable film formed by a flowable chemical vapor deposition method. In some embodiments, the second interlayer dielectric layer 108 is composed of a dielectric material such as phosphosilicate glass, borosilicate glass, borophosphosilicate glass, undoped silicate glass, or the like, and its deposition method can be any suitable method such as chemical vapor deposition or plasma-assisted chemical vapor deposition. Figure 23A and Figure 23B In some embodiments shown, gate contact 110 and source / drain contacts 112 extend through second interlayer dielectric layer 108 and first interlayer dielectric layer 88. Openings for source / drain contacts 112 can be formed through first interlayer dielectric layer 88 and second interlayer dielectric layer 108, and openings for gate contact 110 can be formed through second interlayer dielectric layer 108. Acceptable photolithography and etching techniques can be used to form the openings. A liner layer (e.g., a diffusion barrier layer, an adhesion layer, or the like) and a conductive material can be formed in the openings. The liner layer can include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as chemical mechanical polishing, can be performed to remove excess material from the surface of second interlayer dielectric layer 108. The remaining liner and conductive material form source / drain contacts 112 and gate contact 110 in the openings. An annealing process may be performed to form silicide at the interface between the epitaxial source / drain regions 82 and the source / drain contacts 112. The source / drain contacts 112 are physically and electrically coupled to the epitaxial source / drain regions 82 and to the gate contacts 110, which are physically and electrically coupled to the gate 106. The source / drain contacts 112 and the gate contacts 110 may be formed using different processes or the same process. Although the source / drain contacts 112 and the gate contacts 110 are shown as being formed in the same cross-section in the figures, they may be formed in different cross-sections to avoid shorting of the contacts.

[0107] As described above, FinFET-based devices, including SRAM devices and logic devices, can benefit from increasing the volume of epitaxially grown source / drain regions. Increasing the height of the source / drain regions above the top surface of the semiconductor fin, burying the source / drain regions and increasing their volume, can reduce contact resistance and improve device performance. This is because intermediate fabrication processes consume a significant amount of the epitaxially grown source / drain regions. Therefore, the increased source / drain volume during the epitaxial growth stage results in a larger final source / drain volume. Increasing the volume of the epitaxially grown source / drain regions reduces the energy barrier between the subsequently formed source / drain contacts and the epitaxially grown source / drain regions (due to the high dopant concentration of the epitaxially grown source / drain regions), thereby reducing the contact resistance of the FinFET device. This structure is achieved through repeated deposition and etching cycles to increase the height of the source / drain regions and limit their horizontal growth.

[0108] In one embodiment, a semiconductor device includes: a first semiconductor fin and a second semiconductor fin extending from a substrate; a gate located on the first semiconductor fin and the second semiconductor fin; and a source / drain region located on the first semiconductor fin and the second semiconductor fin and adjacent to the gate, wherein an upper surface of the source / drain region is higher than an upper surface of the first semiconductor fin and the second semiconductor fin under the gate, wherein the source / drain region includes a plurality of buffer layers and a plurality of main layers, wherein the source / drain region includes interlaced buffer layers and main layers, wherein an average thickness of each of the buffer layers is to In one embodiment, the upper surface of the source / drain region is at least 6 nm higher than the upper surfaces of the first and second semiconductor fins. In one embodiment, the buffer layer comprises boron-doped silicon germanium. In one embodiment, the germanium concentration of the buffer layer is 0 atomic % to 15 atomic %. In one embodiment, the source / drain region comprises germanium at a concentration of approximately 10 atomic % to approximately 70 atomic %. In one embodiment, the gate and source / drain region are transistor components in a logic circuit. In one embodiment, an air gap is disposed between the source / drain region and the substrate. In one embodiment, the air gap has a height of 5 nm to 30 nm.

[0109] In another embodiment, the semiconductor device includes: a first semiconductor fin and a second semiconductor fin protruding from a substrate; and a first source / drain region located on the first semiconductor fin and a second source / drain region located on the second semiconductor fin, wherein the first source / drain region is separated from the second source / drain region, wherein the upper surfaces of the first source / drain region and the second source / drain region are higher than the upper surfaces of the first semiconductor fin and the second semiconductor fin, wherein the first source / drain region and the second source / drain region each include: a first buffer layer; a first bulk layer located on the first buffer layer; a second buffer layer located on the first bulk layer; and a second bulk layer located on the second buffer layer, wherein the average thickness of each of the first buffer layer and the second buffer layer is to In one embodiment, the first source / drain region and the second source / drain region comprise 10 atomic % to 70 atomic % germanium. In one embodiment, the first source / drain region and the second source / drain region are components of a static random access memory device. In one embodiment, the ratio of the width of the first semiconductor fin to the lateral distance between the sidewall of the first semiconductor fin and the outer vertex of the first source / drain region is 1:1 to 1:2.5.

[0110] In another embodiment, a method for forming a semiconductor device includes: forming a first semiconductor fin and a second semiconductor fin protruding from a substrate; forming a first gate structure on the first semiconductor fin; recessing the first semiconductor fin to form a first recess adjacent to the first gate structure; and forming a first source / drain region in the first recess. The step of forming the first source / drain region includes: epitaxially growing a first body layer in the first recess; epitaxially growing a second body layer on the first body layer; and forming one or more bonding layers, wherein the step of forming each bonding layer includes: epitaxially growing an upper body layer; depositing a buffer layer on the upper body layer; and recessing the sidewalls of the upper body layer and the buffer layer. In one embodiment, the upper surface of the uppermost upper body layer is 6 nm higher than the upper surface of the first semiconductor fin. In one embodiment, the step of recessing the sidewalls of the upper body layer includes dry etching using hydrogen chloride, hydrofluoric acid, or hydrogen bromide. In one embodiment, the method also includes depositing a protective layer on the uppermost upper body layer. In one embodiment, the method further comprises: forming a second gate structure on the second semiconductor fin; and recessing the second semiconductor fin to form a second recess adjacent to the second gate structure, wherein the step of forming the first source / drain region simultaneously forms the second source / drain region, and wherein the first source / drain region is maintained separate from the second source / drain region. In one embodiment, the step of forming one or more bonding layers comprises forming more than two bonding layers. In one embodiment, the total thickness of the one or more bonding layers is approximately 12 nm. In one embodiment, the step of recessing the sidewalls of the upper body layer comprises dry etching using a mixture of hydrogen chloride, germanium, and hydrogen.

[0111] The above description has described the features of several embodiments to facilitate understanding of the detailed description by those skilled in the art. Those skilled in the art will appreciate that the embodiments of the present invention can clearly serve as a basis for designing or adjusting other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art will also appreciate that these equivalent structures do not depart from the spirit and scope of the embodiments of the present invention, and that various changes, substitutions, or modifications may be made without departing from the spirit and scope of the embodiments of the present invention.

Claims

1. A semiconductor device comprising: a first semiconductor fin and a second semiconductor fin extending from a substrate; a gate located on the first semiconductor fin and the second semiconductor fin; as well as A source / drain region is located on the first semiconductor fin and the second semiconductor fin and is adjacent to the gate, wherein the upper surface of the source / drain region is higher than the upper surface of the first semiconductor fin and the second semiconductor fin under the gate, wherein the source / drain region includes a plurality of buffer layers and a plurality of main layers, wherein the source / drain region includes the buffer layers and the main layers interlaced with each other, wherein the average thickness of each of the buffer layers is to The lower sidewall of a second main body layer of the main body layers contacts a first main body layer of the main body layers. 2 . The semiconductor device of claim 1 , wherein a top surface of the source / drain region is at least 6 nm higher than top surfaces of the first semiconductor fin and the second semiconductor fin. 3 . The semiconductor device as claimed in claim 1 , wherein the buffer layers comprise boron-doped silicon germanium. 4 . The semiconductor device according to claim 3 , wherein the germanium concentration of the buffer layers is 0 atomic % to 15 atomic %. 5 . The semiconductor device of claim 1 , wherein the source / drain regions comprise germanium at a concentration of 10 atomic % to 70 atomic %. 6 . The semiconductor device of claim 1 , wherein the gate and the source / drain regions are transistor components in a logic circuit. 7 . The semiconductor device of claim 1 , wherein an air gap is interposed between the source / drain region and the substrate. The semiconductor device according to claim 7 , wherein a height of the air gap is 5 nm to 30 nm.

9. A semiconductor device comprising: a first semiconductor fin and a second semiconductor fin extending from a substrate; as well as A first source / drain region is located on the first semiconductor fin, and a second source / drain region is located on the second semiconductor fin, wherein the first source / drain region is separate from the second source / drain region, wherein upper surfaces of the first source / drain region and the second source / drain region are higher than upper surfaces of the first semiconductor fin and the second semiconductor fin, wherein the first source / drain region and the second source / drain region each include: a first buffer layer; a first main body layer, located on the first buffer layer; a second buffer layer located on the first main layer; and A second main layer is located on the second buffer layer, wherein the average thickness of each of the first buffer layer and the second buffer layer is to The lower sidewall of the second main layer contacts the first main layer. 10 . The semiconductor device of claim 9 , wherein the first source / drain region and the second source / drain region comprise 10 atomic % to 70 atomic % of germanium. 11 . The semiconductor device of claim 9 , wherein the first source / drain region and the second source / drain region are components of a static random access memory device. 12 . The semiconductor device of claim 9 , wherein a ratio of a width of the first semiconductor fin to a lateral distance between a sidewall of the first semiconductor fin and an outer vertex of a sidewall of the first source / drain region is 1:1 to 1:2.

5.

13. A method for forming a semiconductor device, comprising: forming a first semiconductor fin and a second semiconductor fin protruding from a substrate; forming a first gate structure on the first semiconductor fin; recessing the first semiconductor fin to form a first recess adjacent to the first gate structure; as well as A first source / drain region is formed in the first recess, wherein the step of forming the first source / drain region comprises: Epitaxially growing a first main body layer in the first recess; depositing a first buffer layer on the first bulk layer; epitaxially growing a second main layer on the first buffer layer; depositing a second buffer layer on the second bulk layer; Epitaxially growing a third main layer on the second buffer layer, wherein the third main layer is recessed to be lower than the upper surface of the first semiconductor fin; depositing a third buffer layer on the third bulk layer; recessing the sidewalls of the third body layer and the third buffer layer; and A fourth main layer is epitaxially grown on the third buffer layer, wherein a lower sidewall of the fourth main layer contacts the third main layer. 14 . The method for forming a semiconductor device as claimed in claim 13 , further comprising epitaxially growing one or more upper body layers above the fourth body layer, wherein a top surface of the uppermost upper body layer is 6 nm higher than a top surface of the first semiconductor fin. 15 . The method for forming a semiconductor device according to claim 13 , wherein the step of recessing the sidewall of the third body layer comprises dry etching using hydrogen chloride, hydrofluoric acid, or hydrogen bromide. 16 . The method for forming a semiconductor device as claimed in claim 14 , further comprising depositing a protection layer on the upper body layer.

17. The method for forming a semiconductor device according to claim 13, further comprising: forming a second gate structure on the second semiconductor fin; as well as The second semiconductor fin is recessed to form a second recess adjacent to the second gate structure, wherein the step of forming the first source / drain region simultaneously forms a second source / drain region, and wherein the first source / drain region is maintained separate from the second source / drain region. 18 . The method for forming a semiconductor device according to claim 13 , wherein the step of recessing the sidewall of the third body layer comprises dry etching using a mixed gas of hydrogen chloride, germanium, and hydrogen.

19. A method for forming a semiconductor device, comprising: forming a first fin and a second fin extending from a semiconductor substrate; forming a dummy gate structure on the first fin and the second fin; Etching a first recess in the first fin and etching a second recess in the second fin, the first recess being adjacent to the dummy gate structure, and the second recess being adjacent to the dummy gate structure; A source / drain region is formed extending from the first recess and the second recess, wherein the step of forming the source / drain region comprises: forming a first main body layer in the first recess and the second recess; forming a first buffer layer on the first main layer, wherein the first buffer layer has a first germanium concentration; forming a second body layer on the first buffer layer, wherein the second body layer has a second germanium concentration greater than the first germanium concentration; and A plurality of additional buffer layers and a plurality of additional main layers are formed in an alternating manner, wherein the average thickness of each of the additional buffer layers is to wherein the germanium concentration of each of the additional buffer layers is less than the second germanium concentration, wherein the germanium concentration of each of the additional body layers is greater than the germanium concentration of each of the additional buffer layers, and wherein a lower sidewall of a second additional body layer of the additional body layers contacts a first additional body layer of the additional body layers; and The dummy gate structure is replaced with a gate, wherein the upper surface of the first fin under the gate is lower than the upper surface of the source / drain region. 20 . The method for forming a semiconductor device according to claim 19 , wherein an upper surface of the first fin under the gate is at least 6 nm lower than an upper surface of the source / drain region. 21 . The method for forming a semiconductor device according to claim 19 , wherein the first buffer layer and the additional buffer layers comprise boron-doped silicon germanium. 22 . The method for forming a semiconductor device according to claim 21 , wherein a germanium concentration in the first buffer layer and the additional buffer layers is less than 15 atomic %. 23 . The method for forming a semiconductor device as claimed in claim 19 , further comprising forming an air gap between the source / drain region and the semiconductor substrate. 24 . The method for forming a semiconductor device as claimed in claim 23 , wherein a height of the air gap is 5 nm to 30 nm. 25 . The method for forming a semiconductor device as claimed in claim 23 , wherein a top of the air gap is lower than a top of a bottommost body layer of the source / drain region.

26. A method for forming a semiconductor device, comprising: A source / drain region is formed in a first semiconductor fin and a second semiconductor fin, wherein the steps of forming the source / drain region include: epitaxially growing a first portion of a first body layer in the first semiconductor fin and a second portion of the first body layer in the second semiconductor fin; epitaxially growing a first portion of a first buffer layer on the first portion of the first body layer and a second portion of the first buffer layer on the second portion of the first body layer; Epitaxially growing a second bulk layer on the first buffer layer, wherein the second bulk layer is a single continuous material, wherein the second bulk layer does not contain a crystal face; epitaxially growing a second buffer layer on the second main layer; epitaxially growing a third main layer on the second buffer layer; epitaxially growing a third buffer layer on the third main layer; removing the third buffer layer and lateral portions of the third body layer by a first etch-back process; and A fourth main layer is epitaxially grown on the third buffer layer, wherein a lower sidewall of the fourth main layer contacts the third main layer.

27. The method for forming a semiconductor device according to claim 26, further comprising: epitaxially growing a fourth buffer layer on the fourth main layer; as well as A second etch-back process is performed to remove the lateral portions of the fourth buffer layer and the fourth body layer.

28. The method for forming a semiconductor device according to claim 26, wherein the average thickness of the first buffer layer is to 29 . The method for forming a semiconductor device according to claim 26 , wherein the first etch-back process is dry etching using a gas containing hydrogen chloride. 30 . The method for forming a semiconductor device according to claim 26 , wherein a temperature of the first etch-back process is 400° C. to 700° C. 31 . The method for forming a semiconductor device as claimed in claim 26 , wherein the first etch-back process lasts from 20 seconds to 600 seconds. 32 . The method for forming a semiconductor device according to claim 26 , wherein the third body layer is lower than an upper surface of the second semiconductor fin.

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