Semiconductor device and method of manufacturing a semiconductor device

Abstract

Semiconductor devices and methods of manufacturing semiconductor devices are disclosed. In an embodiment, a semiconductor device includes a support substrate having a first surface capable of supporting epitaxial growth of at least one III-V semiconductor, and a second surface opposite the first surface; at least one mesa positioned on the first surface, each mesa including a multilayer structure of epitaxial III-V semiconductor bases on the first surface of the support substrate, the multilayer structure of epitaxial III-V semiconductor bases forming a boundary with the first surface; and a parasitic channel inhibition region positioned laterally adjacent to the boundary.

Description

Technical Field

[0001] This invention relates to semiconductor devices and methods for manufacturing semiconductor devices. Background Technology

[0002] To date, silicon (Si) semiconductor materials have been typically used to fabricate transistors for power electronics applications. Common transistor devices for power applications include Si CoolMOS®, Si power MOSFETs, and Si insulated-gate bipolar transistors (IGBTs). More recently, silicon carbide (SiC) power devices have been considered. Group III nitride semiconductor devices, such as gallium nitride (GaN) devices, are now emerging as attractive candidates for carrying high currents, supporting high voltages, and providing very low on-resistance and fast switching times. However, further improvements are desired. Summary of the Invention

[0003] In one embodiment, a semiconductor device includes: a support substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface opposite to the first surface; at least one mesa positioned on the first surface, each mesa including a multilayer structure of an epitaxial III-V semiconductor base on the first surface of the support substrate, the multilayer structure of the III-V semiconductor base forming a boundary with the first surface; and a parasitic channel suppression region positioned laterally adjacent to the boundary.

[0004] In one embodiment, a method for manufacturing a semiconductor device is provided, the method comprising: providing a substrate having a first surface capable of supporting epitaxial growth of at least one III-V semiconductor layer; epitaxially growing a multilayer III-V semiconductor structure on the first surface; removing regions of the multilayer III-V semiconductor structure and generating at least one mesa; and forming a parasitic channel suppression region at the first surface of the substrate laterally adjacent to the mesa and / or on the side of the mesa.

[0005] Those skilled in the art will recognize the additional features and advantages when reading the following detailed description and viewing the accompanying drawings. Attached Figure Description

[0006] The elements in the accompanying drawings are not necessarily to scale. The same reference numerals denote corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Exemplary embodiments are depicted in the accompanying drawings and described in detail below.

[0007] Figure 1 A semiconductor device according to an embodiment is illustrated.

[0008] Figure 2 includes Figures 2A to 2F The diagram illustrates a method for manufacturing semiconductor devices.

[0009] Figure 3 includes Figures 3A to 3E The illustration shows a semiconductor device according to various embodiments.

[0010] Figure 4A The illustration shows a cross-sectional view of a semiconductor device comprising multiple mesa.

[0011] Figure 4B The illustration shows a plan view of a semiconductor device that includes multiple platforms. Detailed Implementation

[0012] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and which illustrate, as illustrations, specific embodiments in which the invention may be practiced. In this regard, directional terms, such as “top,” “bottom,” “front,” “back,” “lead,” “tail,” etc., are used with reference to the orientation of the (multiple) figures being described. Because the components of the embodiments can be positioned in many different orientations, the directional terms are for illustrative purposes and are by no means limiting. It is to be understood that other embodiments may be utilized, and structural or logical changes may be made without departing from the scope of the invention. The following detailed description thereto should not be construed in a limiting sense, and the scope of the invention is defined by the appended claims.

[0013] Several exemplary embodiments will be explained below. In this context, the same structural features are identified by the same or similar reference numerals in the various figures. In the context of this description, "lateral" or "lateral direction" should be understood to mean a direction or extension that generally extends parallel to the lateral extension of the semiconductor material or semiconductor carrier. The lateral direction thus generally extends parallel to these surfaces or sides. In contrast, the term "vertical" or "vertical direction" is understood to mean a direction that generally extends orthogonally to these surfaces or sides and thus orthogonal to the lateral direction. The vertical direction thus extends in the thickness direction of the semiconductor material or semiconductor carrier.

[0014] As used in this specification, when an element such as a layer, region, or substrate is referred to as being "on" or extending "to" another element, it may be directly on or directly extending to that other element, or an intermediary element may also be present. In contrast, when an element is referred to as "directly on" or "directly extending to" another element, no intermediary element is present.

[0015] As used in this specification, when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to said other element, or there may be an intermediary element. In contrast, when an element is referred to as "directly connected" or "directly coupled" to another element, no intermediary element exists.

[0016] As used herein, the phrase "Group III nitride" refers to a compound semiconductor comprising nitrogen (N) and at least one Group III element, including aluminum (Al), gallium (Ga), indium (In), and boron (B), and including, but not limited to, any alloys thereof, such as, for example, aluminum gallium nitride (Al). x Ga (1-x) N), Indium gallium nitride (In) y Ga (1-y) N), aluminum indium gallium nitride (Al) x In y Ga (1-x-y) N), gallium arsenide phosphide (GaAs) a P b N (1-a-b) ), and aluminum indium gallium arsenide phosphorus nitride (Al x In y Ga (1-x-y) As a PbN (1-a-b) AlGaN and AlGaN refer to aluminum gallium nitride produced by the formula Al x Ga (1-x) N, where 0 < x < 1, describes the alloy.

[0017] In III-V semiconductor devices formed on heterogeneous substrates such as silicon, and in GaAs- or GaN-based devices, parasitic conductive channels can form at the interface between the substrate and the III-V semiconductor device. Coupling between the device's electrodes, such as the drain electrode in the case of a transistor device, and these parasitic electron or hole channels can lead to losses and limit performance.

[0018] In some embodiments, a III-V semiconductor multilayer structure is epitaxially grown on a support substrate comprising different materials, and the III-V semiconductor multilayer structure is patterned to form a plurality of discrete mesa separated from each other by regions on the support substrate. These regions on the support substrate may be filled with an insulating material, which may form a surface substantially coplanar with the upper surface of the mesa. One or more devices, such as transistor devices, are formed in some or all of the mesa on the support substrate. The insulating material may also be used to reduce substrate or wafer warpage caused by compressive or tensile stresses arising from differences in lattice parameters between the III-V semiconductor and the support substrate.

[0019] Parasitic electron or hole channels can be formed at the interface between the III-V semiconductor and the insulating material, as well as at the interface between the III-V semiconductor and the supporting substrate.

[0020] The purpose of this disclosure is to reduce the effects of parasitic charge channels by providing parasitic channel suppression regions that impede or suppress charge mobility at the interface between the insulating material and the supporting substrate and / or at the interface between the insulating material and the III-V semiconductor, for example at the side of a mesa formed by a multilayer stack of III-V semiconductor layers.

[0021] In some embodiments, a parasitic channel suppression region is provided, which is highly resistive, thereby preventing or hindering the movement of free charges. In these embodiments, the parasitic channel suppression provides a charge mobility reduction region. The charge mobility reduction region may include an amorphous layer or region, a polycrystalline layer or region, or a layer or region with high defects. The charge mobility reduction region may also include a combination of amorphous and / or polycrystalline portions.

[0022] In some embodiments, a parasitic channel suppression region is provided, which reduces charge density by providing a charge density reduction region laterally adjacent to the sidewalls of the mesa and / or at the interface between the insulating material and the substrate, and thus to the boundary between the III-V semiconductor and the substrate. The charge density reduction region may include traps for trapping free charges, thereby preventing the formation of parasitic conductive electron or hole channels.

[0023] In some embodiments, parasitic channels are suppressed by using a combination of charge traps for reducing the density of free charges and highly resistive regions for preventing the movement of free charges.

[0024] Epitaxial group III nitride-based multilayer structures, such as those used in HEMTs, have large polarization charges and are epitaxially grown at high temperatures. Therefore, including parasitic channel suppression regions can be particularly advantageous for group III nitride-based multilayer structures.

[0025] In group III nitride-based transistors formed on substrates of various materials, such as silicon, parasitic conductive electron or hole channels can form at the interface between the substrate and the group III nitride structure. These parasitic electron or hole channels can be induced by polarization of the group III nitride layer, creating both charge and electrostatic attraction through the transistor's drain electrode. Coupling between the drain electrode and these parasitic electron or hole channels can lead to RF losses.

[0026] In embodiments where a group III nitride transistor device is formed in a mesa embedded in an insulator, parasitic electron or hole channels may also be formed at the interface between the group III nitride layer and the insulator, and at the interface between the group III nitride and the supporting substrate.

[0027] In one aspect, the present disclosure aims to reduce the mobility of mobile charge carriers present in the inter-mesa region by decoupling these parasitic charge channels from the substrate, thereby achieving an improvement in efficiency. According to the present disclosure, any mobile charge parasitic channels present at the Group III nitride / substrate interface directly beneath the device formed in the mesa are not directly physically interrupted, and the charge is not compensated by adjusting the composition of the layers located on and below the interface.

[0028] Without being bound by theory, this disclosure is based on the following implementation: positive body charge and interface charge may exist in an insulating region surrounding a mesa comprising a group III nitride layer and an active transistor device structure. These fixed positive charges induce negative mobile charges in adjacent semiconductor regions, which may have the form of electron channels in the silicon substrate and in the group III structure near the boundary with the insulating layer, i.e., at the sidewalls of the mesa. These parasitic electron channels are capacitively coupled to a drain electrode and to a conductive electrode, which is typically coupled to a ground potential on the back side of the substrate. RF losses increase due to the RF current flowing between the drain electrode and the substrate through these parasitic electron channels.

[0029] To reduce RF losses and improve device efficiency, this disclosure seeks to suppress current flow in parasitic channels by inhibiting the movement of electrons in these channels. This is achieved in some embodiments by providing a charge mobility reduction region laterally adjacent to the sidewalls of the mesa and / or at the interface between the insulating material and the substrate, and thus to the boundary between the group III nitride structure and the substrate. The parasitic electron channels are considered to still exist and are capacitively coupled to the drain electrode and the electrodes on the rear surface of the substrate. However, the charge mobility reduction region prevents current flow through the parasitic electron channels, thus preventing an increase in RF losses.

[0030] The charge mobility reduction region can be a highly resistive region, which can be formed by: forming an amorphous or polycrystalline or high defect density region at the location where parasitic electron channels are formed, for example at the sidewalls of the group III nitride layer on the mesa and / or at the interface between the insulating material and the substrate, for example at the surface of the substrate. The charge mobility reduction region can be formed by implantation and locally disrupting the crystallinity of the substrate and the epitaxial group III nitride layer. An increase of at least 4 to 5% in drain efficiency can be achieved. Drain efficiency is the ratio of (RF output power delivered to the load) to (DC power supplied to the transistor drain terminal).

[0031] In a second aspect, this disclosure seeks to suppress current flow in parasitic channels by reducing the charge density in the regions where these parasitic channels are formed. This is achieved by providing charge density reduction regions laterally adjacent to the sidewalls of the mesa and / or at the interface between the insulating material and the substrate, and thus to the boundary between the group III nitride structure and the substrate. The charge density reduction regions may include traps for capturing charges, thereby preventing the formation of parasitic conductive electron or hole channels.

[0032] The charge density reduction region can be amorphous, polycrystalline, or high-defect-density regions formed therein, such as at the location where parasitic electron channels are formed, for example at the sidewalls of a group III nitride layer on a mesa and / or at the interface between the insulating material and the substrate, such as at the surface of the substrate. The charge density reduction region can be formed by implantation and by locally disrupting the crystallinity of the substrate and the epitaxial group III nitride layer, and by forming charge traps in these regions.

[0033] In some embodiments, the channel suppression region may include a combination of a high trap density for reducing charge density and a locally increased resistivity for reducing charge mobility.

[0034] These principles can also be applied to semiconductor materials other than group III nitrides, such as III-V semiconductor materials.

[0035] Figure 1 The illustration shows a semiconductor device 10 according to an embodiment. The semiconductor device 10 includes a support substrate 11 having a first surface 12 capable of supporting the epitaxial growth of at least one III-V semiconductor and a second surface 13 opposite to the first surface 12. The semiconductor device 10 includes at least one mesa 14 positioned on the first surface 12. The mesa 14 includes an epitaxial III-V multilayer structure 15 disposed on the first surface 12 of the support substrate 11. The III-V multilayer structure 15 forms a boundary 16 with the first surface 12. The semiconductor device 10 also includes a parasitic channel suppression region 17 positioned laterally adjacent to the boundary 16.

[0036] In some embodiments, such as Figure 1 In the one illustrated, the III-V semiconductor is a group III nitride, and the III-V multilayer structure 15 is a group III nitride-based multilayer structure, such as a GaN-based multilayer structure.

[0037] In some embodiments, boundary 16 is the interface between the lowermost epitaxial III-nitride layer of the multilayer structure 15 and the first surface 12 of the supporting substrate 11. In other embodiments, boundary 16 has a thickness and forms a boundary region or boundary layer between the first surface 12 and the lowermost epitaxial III-nitride layer. For example, boundary 16 may include a silicon nitride layer disposed between the first surface 12 of the substrate 11 and the lowermost epitaxial III-nitride layer. In some embodiments, the silicon nitride layer is formed by nitriding the first surface 12 of the silicon supporting substrate 11. A first interface is formed between boundary 16 and the first surface 12, and a second interface is formed between boundary 16 and the lowermost epitaxial III-nitride layer.

[0038] The supporting substrate 11 may include a single-crystal heterostructure, such as silicon. <111> or <110> The wafer may be a sapphire wafer, a SiC wafer, or an epitaxial single-crystal silicon layer. The supporting substrate 11 may be a high-resistivity silicon substrate having a bulk resistivity greater than 100 Ohm·cm, or greater than 500 Ohm·cm, or greater than approximately 1000 Ohm·cm.

[0039] Mesa 14 protrudes from a first surface 12 of the supporting substrate 11 and has a lateral region defined by sidewalls 18 comprising a group III nitride-based material. Each mesa 14 may provide a semiconductor device, such as a transistor device, for example a high electron mobility transistor (HEMT), a MISFET, a MIS-HEMT, or a JFET. The transistor device may have an operating frequency of 800 MHz or more. In some embodiments, the mesa may provide a passive device.

[0040] The mesa 14 includes a metallization structure 19 on its upper surface 20. In embodiments where the semiconductor device 10 is a transistor device, the metallization structure 19 includes a source electrode 21, a gate electrode 22, and a drain electrode 23, wherein the gate electrode 22 is laterally positioned between the source electrode 21 and the drain electrode 23. In some embodiments, the source electrode 21, the gate electrode 22, and the drain electrode 23 have elongated strip-like structures and extend generally parallel to each other. Figure 1 In the cross-sectional view, the source electrode 21, the gate electrode 22, and the drain electrode 23 extend into the plane of the figure.

[0041] The area of ​​the first surface 12 located between adjacent mesa 14 is the non-device region 24. In some embodiments, the non-device region 24 may include an insulating material 25 such that the side surface 18 of the mesa 14 is embedded in the insulating material 25. Parasitic channel suppression regions 17 can therefore be arranged in these non-device regions 24 and located between adjacent mesa 14.

[0042] To reduce RF losses and increase the efficiency of device 10, semiconductor device 10 includes a parasitic channel suppression region 17, which is positioned laterally adjacent to a boundary 16 between the group III nitride-based multilayer structure 15 and the first surface 12 of the support substrate 11. In some embodiments, the parasitic channel suppression region 17 is positioned in the support substrate 11, at the first surface 12, and laterally adjacent to the mesa 14.

[0043] The parasitic channel suppression region 17 may be adjacent to the boundary 16. In some embodiments, the entire boundary 16 is free of the parasitic channel suppression region 17, such that the boundary 16 has the same width as the platform 14. In other embodiments, the central portion of the boundary 16 is free of the parasitic channel suppression region 17, and the peripheral portion below the side 18 of the platform 14 includes the parasitic channel suppression region 17.

[0044] In some embodiments, the parasitic channel suppression region 17 is positioned on at least one side 18 of the mesa 14. In some embodiments, the parasitic channel suppression region 17 is positioned laterally adjacent to the mesa 14 in the non-device region 24, both on the sidewall 18 of the mesa and at the first surface 12 of the supporting substrate 11, as shown in the figure. Figure 1 As shown in the diagram.

[0045] The parasitic channel suppression region 17 may include an amorphous region or layer, a polycrystalline region or layer, a high defect density region or layer, a region of the mesa 14 or the supporting substrate 11 having a damaged crystal structure, or a side surface 18 of the mesa 14 and a region of the first surface 12 of the supporting substrate 11 including interstitial atoms or ions or charge traps. In some embodiments, the parasitic channel suppression region 17 further includes implanted species, wherein the implanted species include at least one of the following groups: Ar, Kr, Xe, Ne, He, N, O, H, Fe, C, Si, and Al.

[0046] The non-device region 24 may be filled with an insulating material 25 such that the side surface 18 of the mesa 14 in the semiconductor device 10 is embedded in the insulating material 25. The insulating material 25 may form a planar surface 26 with respect to the upper surface 20 of the mesa 14. The insulating material 25 may be silicon dioxide.

[0047] In other embodiments, at least one cavity is arranged laterally adjacent to a mesa 14 in the non-device region 24, the cavity being defined by one or more insulating layers and filled with gas or a vacuum. For example, the cavity may be defined by an insulating layer disposed on the side 18 of the adjacent mesa 14, on the first surface 12 of the support substrate 11 disposed in the non-device region 24, and capped by an additional insulating layer.

[0048] exist Figure 1 In this embodiment, the epitaxial III-V semiconductor multilayer structure 15 is an epitaxial group III nitride-based multilayer structure 15. However, in other embodiments, the epitaxial III-V semiconductor multilayer structure 15 may include GaAs, and the supporting substrate may be a silicon wafer.

[0049] Epitaxial group III nitride-based multilayer structures, such as those used in HEMTs, have large polarization charges and are epitaxially grown at high temperatures. Therefore, the parasitic channel suppression region 17 includes the group III nitride-based multilayer structure 15, and particularly for silicon... <111> or <110> Devices based on group III nitrides grown on wafers or sapphire wafers or SiC wafers or epitaxial single-crystal silicon layers or highly resistive silicon wafers can be particularly advantageous.

[0050] The epitaxial group III nitride-based multilayer structure 15 may include a stack of epitaxial group III nitride layers. For a high electron mobility transistor (HEMT), the epitaxial group III nitride-based multilayer structure 15 may include: an epitaxial group III nitride-based buffer structure on a first surface 12 of a supporting substrate 11, an epitaxial group III nitride channel layer disposed on the group III nitride buffer structure, and a group III nitride barrier layer disposed on the group III nitride buffer structure. The group III nitride barrier layer and the group III nitride channel layer may have different compositions and different band gaps, thereby forming a heterojunction between them capable of supporting a two-dimensional charge gas. The channel layer may include GaN and the barrier layer AlGaN.

[0051] Group III nitride-based buffer structures for silicon substrates may include an AlN initiation layer on the silicon substrate, which may have a thickness of several 100 nm, followed by Al... x Ga (1-x) An N-layer sequence, with a thickness of several 100 nm for each layer, reduces the Al content from approximately 50-75% to 10-25% before the GaN layer growth at the AlGaN backstop. Alternatively, a superlattice buffer can be used. Again, an AlN initiation layer is used on a silicon substrate. Depending on the chosen superlattice, AlN and Al... x Ga (1-x)N pairs of sequences, where AlN layer and Al x Ga (1-x) The thickness of N ranges from 5 to 15 nm. Depending on the desired breakdown voltage, the superlattice can comprise pairs between 20 and 100. Alternatively, Al, as described above, can be used. x Ga (1-x) N-layer sequences can be used in combination with the superlattices mentioned above.

[0052] The conductive electrode 27 can be disposed on the second surface 13 of the supporting substrate 11. The conductive electrode 27 can be coupled to a ground potential.

[0053] Parasitic channel suppression regions 17 are arranged to suppress the mobility of charge in parasitic conductive channels from the drain electrode 23 to the electrode 27 on the rear surface 13 of the support substrate 11. These parasitic conductive channels can be formed at the interface between the insulating material 25 and the mesa 14, at the interface between the insulating material 25 and the support substrate 11, and at the boundary 16 between the group III nitride structure 15 and the first surface 12 of the support substrate 11. The parasitic channel suppression regions 17 are arranged next to the boundary 16, at the interface between the side surface 18 of the mesa 14 and the insulating material 25, and at the interface between the first surface 12 of the support substrate 11 and the insulating material 25.

[0054] In some embodiments, the parasitic channel suppression region 17 impedes or suppresses the mobility of charge present at the interface between the insulating material 25 and the support substrate and / or at the interface between the insulating material 25 and the side surface 18 of the mesa 14. This can be achieved by providing the parasitic channel suppression region 17, which is highly resistive, such that it prevents or impedes charge movement. In these embodiments, the parasitic channel suppression provides a charge mobility reduction region 17. The charge mobility reduction region 17 may include an amorphous layer or region, a polycrystalline layer or region, or a layer or region with high defects.

[0055] In some embodiments, the parasitic channel suppression region 17 impedes or suppresses the effect of parasitic hole or electron channels by reducing charge density, for example by providing traps within the parasitic channel suppression region. When the charge density is reduced, less charge is available to generate parasitic currents, thus suppressing the formation of parasitic channels.

[0056] In some embodiments, a combination of charge traps for reducing charge density and means for impeding the flow of any free charge, such as locally increased resistance provided by the polycrystalline, amorphous, or defective crystal structure in the parasitic region 17, can be used to suppress parasitic channels.

[0057] Figure 2 includes Figures 2A to 2F The diagram illustrates a method for manufacturing semiconductor devices.

[0058] Figure 2A The illustration shows a support substrate 30 having a first surface 31 capable of supporting the epitaxial growth of at least one group III nitride layer. The support substrate 30 may include, and may be a single-crystal substrate, such as silicon. <111> or silicon <110> Wafers, or single-crystal sapphire wafers or silicon carbide wafers. The silicon substrate can be a high-resistivity silicon substrate.

[0059] Figure 2 illustrates the fabrication of a single semiconductor device in a single component positioning 32. However, typically, the support substrate 30 has an area sufficient to support the fabrication of multiple semiconductor devices, which are typically formed in multiple device positions arranged in rows and columns on a first surface 31.

[0060] A multilayer group III nitride structure 33 is epitaxially grown on a first surface 31. The multilayer group III nitride-based structure 33 may include a group III nitride buffer structure 34 grown on the first surface 31, a group III nitride channel layer 35 grown on the group III nitride buffer structure 34, and a group III nitride barrier layer 36 grown on the group III nitride channel layer 35. The group III nitride barrier layer 36 may include aluminum gallium nitride, and the group III nitride channel layer 35 may include gallium nitride, such that a heterojunction 37 capable of supporting a two-dimensional charge gas is formed between the group III nitride channel layer 35 and the group III nitride barrier layer 36.

[0061] The multilayer group III nitride structure 33 can then be structured by removing regions 39 of the multilayer group III nitride structure 33 to create a plurality of mesas 38. For example, a mask 40 can be applied to the multilayer group III nitride structure 33 and structured to provide openings 41 that expose regions of the group III nitride structure 33, which can then be removed, for example by etching, to expose the first surface 31 of the supporting substrate 30. Adjacent mesas 38 are then spaced apart by non-device regions 42 that define the mesas 38.

[0062] As in Figure 2B As illustrated, a parasitic channel suppression region in the form of a charge mobility reduction region 43 is formed at a location on the first surface 31 of the support substrate 30, laterally adjacent to the mesa 38 in the non-device region 39 of the support substrate 30. In some embodiments, by placing a substance such as Ar at the location laterally adjacent to the mesa 38... + Species such as ions are implanted into the first surface 31 of the substrate 30, such as in Figure 2BThe charge mobility reduction region 43 is formed as schematically indicated by arrow 44. The injected species may include one of the following group: Ar, Kr, Xe, Ne, He, N, O, H, Fe, C, Si, and Al. The upper surface of the mesa 38 is covered by mask 40 and is not injected with the species.

[0063] In some embodiments, a parasitic channel inhibition region in the form of a charge mobility reduction region 45 is also formed on the side surface 46 of the mesa 38. The charge mobility reduction region 45 can be formed on the side surface 46 of the mesa 38 by injection, for example by injection of one or more species at an angle relative to the side surface 45 and the first surface 31. The injection of the species into the side surface 46... Figure 2C The species are schematically indicated by arrow 47. As an example, these species may be injected at a 45° angle relative to the side 46 and the first surface 31.

[0064] In some embodiments, the species can be implanted at two or more different energies to increase the implantation depth and the thickness of the charge mobility reduction regions 43, 45. In a particular example, the species is Ar+ ions, which are implanted at energies in the range of 20 keV to 250 keV using 1e 13 cm -2 up to 5e 15 cm -2 or 1e 14 cm -2 up to 5e 15 cm -2 The injection dose is used to inject the drug. In one example, 3e is used at 50 keV. 14 cm -2 And 3e at 250keV 14 cm -2 The ion implantation dose is used to implant the species.

[0065] The charge mobility reduction regions 43 and 35 may have a polycrystalline structure, an amorphous structure, or a high defect density structure. Alternatively, the charge mobility reduction regions 43 and 45 may be replaced by charge density reduction regions including charge traps. The charge mobility reduction regions may include regions with high trap density, where electrons or holes occupy the traps. In this case, the number of electrons or holes available for current conduction is reduced. Due to the reduction in the density of free electrons or holes at the interface, the resistance of the charge mobility reduction regions 43 and 45 increases. In some embodiments, a combination of high trap density and a polycrystalline or amorphous or high defect density structure is used.

[0066] As in Figure 2DAs illustrated, each side 46 of the mesa 38 can be separately and sequentially implanted to create a charge mobility reduction region on each of the four sides of the mesa 38. In practice, since the supporting substrate 30 includes a plurality of discrete mesa 38 spaced apart by non-device regions 42, and the mesa 38 are arranged in multiple rows and columns, a particular side of each of the mesa 38 on the substrate 30, for example... Figure 2D Side 46 is injected using a single injection step. The relative orientation between the platform 38 and the injection beam is adjusted to inject the other sides 48, 49, and 50.

[0067] After forming one or more charge mobility reduction regions 43, 45, the non-device region 42 can be filled with an insulating layer 51, such as... Figure 2E The diagram shows the upper surface 52 of the material, which is generally a plane of insulating material 51, and the upper surface 53 of the multilayer structure 33 based on group III nitrides.

[0068] As in Figure 2F As illustrated, a semiconductor device 54 can be fabricated by applying a metallization structure to the upper surface 53 of mesa 38, which, for a transistor device, may include a source electrode 55, a gate electrode 56, and a drain electrode 57 on each of the mesa 38. The semiconductor device 54 can then be diced from the wafer.

[0069] A boundary 58 is formed between the lowest layer of the group III nitride structure 33, particularly the group III nitride buffer structure 34, and the first surface 31 of the support substrate 30. An electrode 59 may be formed on the rear surface of the support substrate 30. One or more charge mobility reduction regions 43, 45 are arranged on the sides 46, 48, 49, 50 of the mesa 38 and on the first surface 31 of the substrate 30 in the non-device region 42, and are laterally adjacent to the mesa 38 and the boundary 58. These regions serve to impede the movement of charge formed at the interfaces between the sides 46, 48, 49, 50 of the group III nitride structure 33 and the insulating material 51, at the interfaces between the insulating material 51 and the first surface 31 of the support substrate 30, and at the boundary 58 between the group III nitride structure 33 and the first surface 31 of the support substrate 30, and thus impede RF loss due to the formation of a parasitic conductive channel between the drain electrode 57 and the electrode 59 on the rear surface of the substrate 30.

[0070] Figure 3 includes Figures 3A to 3E The illustration shows another embodiment of a device including a charge mobility reduction region.

[0071] Figure 3AThe illustration shows a semiconductor device 60 according to an embodiment. The semiconductor device 60 includes a mesa 14 comprising an epitaxial group III nitride-based multilayer structure 15 disposed on a first surface 12 of a support substrate 11, as shown in... Figure 1 As illustrated in the embodiment. The semiconductor device 60 also includes a charge mobility reduction region 17, which is positioned laterally adjacent to the boundary 16 between the first surface 12 of the substrate 11 and the epitaxial group III nitride-based module structure 15. The charge mobility reduction region 17 is disposed on the side surface 18 of the mesa 14 and in the non-device region 24 of the semiconductor device 60.

[0072] The charge mobility reduction region 17 provides a parasitic channel suppression region. In some embodiments, a charge density reduction region is used in addition to or instead of the charge mobility reduction region 17 to suppress parasitic channel formation or the effect of parasitic channels.

[0073] Semiconductor device 60 is different Figure 1 The semiconductor device 10 illustrated herein is characterized by the vertical positioning of the boundary 16 and the charge mobility reduction region 17 disposed in the non-device region 24. In the semiconductor device 60, the boundary 16 between the epitaxial group III nitride multilayer structure 15 and the first surface 12 of the supporting substrate 11 is positioned within the protrusion of the mesa 14 and is disposed in a plane perpendicular to the plane of the charge mobility reduction region 17.

[0074] In some embodiments, such as Figure 1 In the embodiment illustrated, the first surface 12 is generally planar in the area covered by the mesa 14 and in the non-device area 24. In some embodiments, such as Figure 3A In the one illustrated, the semiconductor device 60 includes a support substrate 11, which includes a first working surface 12' in a non-device region 24 not occupied by the mesa 14. A boundary 16 between the first surface 12 of the support substrate 11 and the epitaxial group III nitride-based multilayer structure 15 is disposed within a protrusion of the mesa 14 and is vertically spaced by a distance above the first working surface 12'. In other words, the first working surface 12' of the non-device region 24 is positioned in a plane below the plane of the boundary 16, such that a protrusion is provided including the mesa 14, which includes the epitaxial group III nitride-based multilayer structure 15 and a raised portion 61 of the support substrate 11.

[0075] The non-device region 24 is formed by removing a portion of the group III nitride-based multilayer structure 15 and a portion of the substrate 11 in the non-device region to create a first working surface 12', which is positioned in a plane perpendicular to and lower than the plane of the first surface 12. The non-device region 24 may be filled with an insulating material 25, such as in... Figure 1 As illustrated in the embodiment. The insulating material 25 may have an upper surface 62 that is coplanar with the upper surface 20 of the platform 14 and forms a planarized surface 63.

[0076] Figure 3B The illustration shows a semiconductor device 70 including a mesa 14, which includes an epitaxial group III nitride-based multilayer structure 15 disposed on a first surface 12 of a support substrate 11, wherein the first surface 12 is coplanar in the region below the mesa 14 and in the non-device region 24, as shown in Figure 1 As illustrated in the embodiment. Figure 3B In the embodiment illustrated, the semiconductor device 70 includes a cavity 71 in the non-device region 24, which replaces the insulating material 25. The cavity 71 may be defined by an insulating layer 72 that limits the gap 73 to the sidewalls and substrate liner of the non-device region 24 defined by the charge mobility reduction region 17 (if present) or the sidewalls 18 of the mesa 14 and the first surface 12 of the support substrate 11, if the charge mobility reduction region 17 is present. The gap 73 is capped by a capping layer 74 to seal and completely enclose the cavity 71. The cavity 71 may be filled with a gas or vacuum, which may be the same as or similar to the gas or vacuum present in the apparatus used for depositing the cap 74.

[0077] In some embodiments, the insulating layer 72 may extend to the upper surface 20 of the tabletop 14, and the cover layer 74 is positioned on the upper surface 20 and extends between two adjacent upper surfaces 20 of two adjacent tabletops 14.

[0078] Figure 3C The illustration shows a semiconductor device 80, which is similar to Figure 1 The one illustrated in the figure, but the difference is that the charge mobility reduction layer 17 is only disposed on the side 18 of the mesa 14 and the first surface 12 of the substrate 11 in the non-device region 24 remains without the charge mobility reduction layer.

[0079] Figure 3D The illustration shows a semiconductor device 81, which is similar to Figure 1 The one shown in the figure, but the difference is that the charge mobility reduction layer 17 is only arranged on the first surface 12 of the substrate 11 in the non-device region 24, so that the side surface 18 of the mesa 14 remains without the charge mobility reduction layer.

[0080] Figure 3E The illustration shows a semiconductor device 82, which is similar to Figure 1 The diagram shows the same structure, but with the difference that the charge mobility reduction layer 17 is partially disposed under the mesa 15 and at the peripheral edge 83 of the boundary 16 between the group III nitride structure 33 and the first surface 12 of the supporting substrate 11. The charge mobility reduction layer 17 is disposed under the side surface 18 of the mesa 38. The charge mobility reduction layer 17 is also disposed on the first surface 12 of the substrate 11 in the non-device region 24. The side surface 18 of the mesa 14 remains substantially free of the charge mobility reduction layer 17.

[0081] In some embodiments, each mesa provides a single device, such as a transistor device for use in an application. In some embodiments, each mesa provides a substructure, such as a small-area transistor device, which is coupled to other structures to form a device.

[0082] In some embodiments, one or more mezzanines are provided, which are not formed on the mezzanine or any active or passive devices therein. These one or more mezzanines can be used to facilitate manufacturing, for example by providing a dummy mezzanine structure around an active mezzanine structure to facilitate uniform CMP (chemical mechanical polishing) processes.

[0083] Figure 4A A cross-sectional view of the semiconductor device 100 is illustrated, and Figure 4B The diagram illustrates a partial plan view of the semiconductor device 100, which comprises a group III nitride-based transistor device including a plurality of mesa 101, three of which are illustrated in the figures. The mesa 101 are disposed on a first surface 102 of a supporting substrate 103. Each of the mesa 101 is spaced apart from its adjacent neighbor by a non-device region 104, wherein the non-device region 104 comprises an insulating material 105. Each mesa 101 includes a multilayer group III nitride structure 106.

[0084] The supporting substrate 103 may be a single-crystal silicon substrate. In some embodiments, the multilayer group III nitride-based structure 106 includes: a buffer structure disposed on a first surface 102 of the supporting substrate 103, a channel layer disposed on the buffer structure, and a barrier layer disposed on the channel layer, wherein the barrier layer and the channel layer comprise group III nitrides with different compositions, such that a heterojunction capable of supporting a two-dimensional charge gas is formed therebetween. The channel layer may be formed of gallium nitride, and the barrier layer may be formed of aluminum gallium nitride.

[0085] The upper surface 107 of the mesa 101 includes: an elongated drain electrode 108 arranged towards the center; two elongated gate electrodes 109 and 110 arranged on opposite sides of the drain electrode 108; and two elongated source electrodes 111 and 112, respectively arranged at opposite peripheral edges of the mesa 101 and adjacent to the gate electrodes 109 and 110, such that the gate electrode 109 is arranged between the source electrode 111 and the drain electrode 108, and the gate electrode 110 is arranged between the drain electrode 108 and the source electrode 112. The drain electrode 108, the gate electrode 109 and 110, and the source electrodes 111 and 112 extend substantially parallel to each other.

[0086] Drain electrodes 108 arranged on each of the mesa 101 are electrically coupled by means of a redistribution structure comprising: drain fingers 113 arranged on top of the drain electrodes 108, extending along the length of the drain electrodes 108 and extending onto a non-device region 104 arranged adjacent to a first side surface 114 of the mesa 101; and drain channels 115 that electrically couple the drain fingers 113 to each other. The drain channels 115 extend orthogonally to the drain fingers 113 and are arranged adjacent to the first side surface 114 of the mesa 101.

[0087] Gates 109 and 110, disposed on mesa 101, are electrically coupled to each other by means of a gate metallization structure comprising gate fingers 116 and 116', which are disposed on gate electrodes 109 and 110, respectively, and extend onto non-device region 104, adjacent to a second side 117 of mesa 101 opposite to the first side 114. Gate fingers 116 are electrically connected together by gate channels 118, which extend orthogonally to gate fingers 116 and substantially parallel to drain fingers 115. Gate channels 118 and drain channels 115 are disposed on opposite lateral sides of mesa 101.

[0088] Source electrode 111 is electrically coupled to source electrode 112' on a nearby mesa 101' via source connection 119, which extends over the sides 123, 124' of mesa 101, 101' and extends into a non-device region 104 located between two grounded adjacent mesa 101, 101'. Source connection 119 is laterally arranged between drain channel 115 and source channel 118. Semiconductor device 100 includes a conductive via 120 located in non-device region 114 and extending through insulating material 105 and support substrate 103 to the rear surface 121 of support substrate 103. Conductive via 120 is electrically coupled to a conductive layer 122 disposed on rear surface 121 and to a conductive layer 119 extending between source electrodes 111, 112 on the upper surfaces of mesa 101, 101'. Therefore, the source electrodes 111, 112' are positioned on two adjacent mesa 101, 101' and facing each other, and are electrically coupled to layer 122 on the rear surface 121 of the support substrate 103 by means of conductive layer 119 and conductive via 120.

[0089] Each of the non-device regions 104 includes a parasitic channel suppression region in the form of a charge mobility reduction layer 125. The charge mobility reduction layer 125 is formed in the side surfaces 114, 117, 123, 124 of the mesa 101 and in the upper surface 102 of the supporting substrate 103 in the non-device regions 104. The charge mobility reduction layer 125 is arranged to be laterally adjacent to the boundary 126 between the group III nitride structure 106 and the upper surface 102 of the underlying substrate 103.

[0090] The charge mobility reduction region 125 can be a highly resistive region, which can be formed by: forming an amorphous or polycrystalline region or a high defect density region at the location where parasitic electron channels are formed, for example at the sidewalls 114, 117, 123, 124 of the group III nitride layer 106 of the mesa 101, and / or at the interface between the insulating material 105 and the substrate 103, for example at the first surface 102 of the substrate 103 in the non-device region 104. The charge mobility reduction region 125 can be formed by implantation and local disruption of the crystallinity of the substrate 103 and the epitaxial group III nitride layer 106. An increase of at least 4 to 5% in drain efficiency can be achieved.

[0091] The charge mobility reduction layer 125 is used to suppress current flow in parasitic channels by suppressing the movement of electrons in these parasitic channels, thereby reducing RF losses and increasing device efficiency.

[0092] It is assumed that the parasitic electron channel still exists and is capacitively coupled to the drain electrode 108 and the electrode 122 on the rear surface of the substrate 103. However, the charge mobility reduction region 125 prevents the current flow through the parasitic electron channel(s), thus preventing an increase in RF loss.

[0093] In some embodiments, a charge density reduction region is used in addition to or instead of the charge mobility reduction region 125 to suppress parasitic channel formation or the effect of parasitic channels. A high trap density can be provided in region 125 to reduce charge density, and as a result, the current in the parasitic channel is reduced due to the reduction in the number of charges.

[0094] In some embodiments, the semiconductor device 100 may be a monolithic microwave integrated circuit (MMIC) and includes at least one transistor device and at least one passive device, such as a capacitor, inductor or transmission line, which are integrated into the semiconductor device, for example, under the mesa 101, in the non-device region 104, on the upper surface or in a metallization layer on the upper surface.

[0095] Spatial relative terms, such as "below," "below," "lower," "above," "upper," etc., are used for descriptive purposes, thereby explaining the positioning of one element relative to a second element. These terms are intended to encompass different orientations of the device, in addition to those different from those depicted in the figures. Furthermore, terms such as "first," "second," etc., are used to describe various elements, areas, sections, etc., and are not intended to be limiting. The same terms are used throughout this description to refer to the same elements.

[0096] As used herein, the terms “having,” “comprising,” “including,” “including,” etc., are open-ended terms that indicate the presence of a stated element or feature, but do not exclude additional elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise. It is to be understood that features of the various embodiments described herein may be combined with each other unless specifically indicated otherwise.

[0097] Although specific embodiments have been illustrated and described herein, those skilled in the art will appreciate that various alternative and / or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that the invention be limited only by the claims and their equivalents.

Claims

1. A semiconductor device, comprising: A support substrate having a first surface capable of supporting the epitaxial growth of at least one III V semiconductor and a second surface opposite to the first surface; At least one mesa positioned on the first surface, each mesa comprising a multilayer structure of an epitaxial III-V semiconductor base on the first surface of the supporting substrate, the multilayer structure of the III-V semiconductor base forming a boundary with the first surface; The parasitic channel suppression zone is positioned laterally adjacent to the boundary. as well as A non-device region of insulating material is arranged on the support substrate and laterally adjacent to the at least one mesa. The non-device region is filled with the insulating material, and the insulating material has an upper surface that is coplanar with the upper surface of the at least one mesa. The parasitic channel suppression region includes a span that extends along the first surface and forms an interface with the non-device region; and The conductive via is located within the non-device region and extends through the insulating material and the support substrate to the rear surface of the support substrate. The conductive via is electrically coupled to a conductive layer disposed on the rear surface and electrically coupled to a conductive layer extending between source electrodes on the upper surfaces of two adjacent mesa.

2. The semiconductor device according to claim 1, wherein the parasitic channel suppression region comprises an amorphous layer, a polycrystalline layer, or a high defect density region.

3. The semiconductor device according to claim 1 or claim 2, wherein the parasitic channel suppression region is arranged laterally adjacent to the mesa at a first surface of the supporting substrate.

4. The semiconductor device according to any one of claims 1 to 2, wherein the parasitic channel suppression region is disposed on at least one side of the mesa.

5. The semiconductor device according to any one of claims 1 to 2, wherein the III-V semiconductor is a group III nitride.

6. The semiconductor device according to any one of claims 1 to 2, wherein the side of the mesa is embedded in an insulating material.

7. The semiconductor device according to any one of claims 1 to 2, further comprising at least one cavity arranged laterally adjacent to the mesa.

8. The semiconductor device according to any one of claims 1 to 2, wherein the parasitic channel suppression region further comprises implanted species, wherein the species comprises at least one of the group consisting of Ar, Kr, Xe, Ne, He, N, O, H, Fe, C, Si and Al.

9. A method for manufacturing a semiconductor device, the method comprising: A substrate is provided, the substrate having a first surface capable of supporting the epitaxial growth of at least one III-V semiconductor layer; A multilayer III-V semiconductor structure is epitaxially grown on the first surface; Remove the regions of the multilayer III-V semiconductor structure and create at least one mesa. A parasitic channel suppression region is formed on the first surface of the substrate, laterally adjacent to the mesa and / or on the side of the mesa; as well as An insulating layer is applied to the area between the tabletops, the insulating layer having an upper surface coplanar with the upper surface of the at least one tabletop; The parasitic channel suppression region includes a span that extends along the first surface and forms an interface with the insulating layer; and The conductive via is located within the insulating layer and extends through the insulating layer and the substrate to the rear surface of the substrate, wherein the conductive via is electrically coupled to a conductive layer disposed on the rear surface and electrically coupled to a conductive layer extending between source electrodes on the upper surfaces of two adjacent mesa.

10. The method of claim 9, wherein forming the parasitic channel suppression region comprises injecting species into a first surface of the substrate and / or injecting species into at least one side of the mesa at a location laterally adjacent to the mesa.

11. The method of claim 10, wherein the species comprises at least one of the group consisting of Ar, Kr, Xe, Ne, He, N, O, H, Fe, C, Si, and Al.

12. The method of claim 10, wherein the species is injected with two or more different energies.

13. The method according to any one of claims 9 to 12, further comprising: A portion of the first surface of the wafer adjacent to the mesa is removed to create a first working surface, such that the boundary between the wafer and the multilayer III-V semiconductor structure is arranged in the mesa and at a certain distance above the first working surface.

14. The method according to any one of claims 9 to 12, wherein the III-V semiconductor is a group III nitride, the method further comprising forming a metallization structure on a mesa multilayer group III nitride structure, the metallization structure providing a source, gate, and drain for a transistor structure.

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