Dual in-line memory module device of storage-level memory and data access method

Abstract

The present invention relates to a dual in-line memory module (DIMM) device of a storage class memory (SCM) and a method for accessing data. The device and the method for reading and writing data of the present invention can increase the memory space of the device, improve the speed performance of the device, reduce the difficulty of printed circuit board design, and enable a host to access a non-volatile memory with low overhead.

Description

Technical Field

[0001] The present invention relates to the field of memory, and more specifically, to a dual in-line memory module (DIMM) device of a storage class memory (SCM) and a method for accessing data. Background Art

[0002] The nature of storage-class memory SCM is dual in-line memory module DIMM, which is a new type of dual in-line memory module. There is memory space on the module that can be accessed in the form of storage.

[0003] A schematic diagram of the signal flow and interface in a dual in-line memory module DIMM of a storage class memory SCM known in the prior art is shown in FIG. Figure 1 As shown. Figure 1 In the present invention, by using a stub signal, a host or a central processing unit CPU (Central Processing Unit) can access a dynamic random access memory DRAM (Dynamic Random Access Memory) and a controller such as a non-volatile controller NVC (Non-Volatile Controller) during normal operation, and access the non-volatile memory such as NAND Flash through the access controller, thereby increasing the memory space of the system.

[0004] The bifurcation signal is specifically manifested in the following aspects: after the command / address CA (Command / Address) signal is output from the DIMM slot, there is a bifurcation signal, which is connected to the register clock driver RCD (Register Clock Driver) and the controller respectively; the data DQ signal also has a bifurcation signal between the data buffer DB (Data Buffer) and the dynamic random access memory DRAM. This bifurcation signal is very difficult to implement high-speed signals on printed circuit boards because the feedback of high-speed signals will interfere with the signals of another channel, affecting the rate performance.

[0005] Another known technical solution for removing bifurcation signals in the prior art is as follows: Figure 2 As shown. Figure 2 In the process, the command / address CA signal and the data DQ signal enter the controller first, eliminating the need for Figure 1 However, in Figure 2 There are two problems in the scenario shown:

[0006] First, the data DQ signal is enhanced in driving capability through the data buffer DB, but after entering the controller, it is difficult to maintain the enhanced driving signal in the chip and transmit it to a non-volatile memory such as NAND Flash.

[0007] Secondly, the high-speed data DQ signals are on both sides of the DIMM slot, making it difficult to achieve equal length connections between the high-speed data DQ signals and the controller when wiring on the printed circuit board. However, the unequal length of high-speed parallel signals leads to different arrival times at the destination, which also leads to a decrease in rate performance.

[0008] Therefore, there is an urgent need for a dual in-line memory module (DIMM) device and a data access method for a storage class memory (SCM) that can solve the above problems. Summary of the invention

[0009] The present invention relates to a dual in-line memory module (DIMM) device and a data access method of a storage-class memory (SCM) capable of increasing the memory space of a device, improving the speed performance of the device, reducing the difficulty of printed circuit board design, and enabling a host to access a non-volatile memory with low overhead.

[0010] According to a first aspect of the present invention, there is provided a dual in-line memory module device of a storage-level memory, comprising:

[0011] a first storage area storing data having a first range of host access frequencies; and

[0012] a second storage area storing data having a second range of host access frequencies;

[0013] The host access frequency in the first range is greater than the host access frequency in the second range.

[0014] Thus, the storage area of ​​the dual in-line memory module device is divided into a "hot area" (i.e., the first storage area) where the host or the central processing unit frequently reads and writes, and a "cold area" (i.e., the second storage area) where the host or the central processing unit does not frequently read and write. The processing speed of the "hot area" is relatively fast, and the processing speed of the "cold area" is relatively slow. In this way, the rate performance of the module device can be improved.

[0015] According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the data having a host access frequency in the second range is stored in the second storage area indirectly via the first storage area.

[0016] Therefore, the present invention clarifies the method of accessing the "cold zone" (i.e., the second storage area), that is, it is necessary to access the "cold zone" via the "hot zone" (i.e., the first storage area), and increase the memory space of the device by accessing the "cold zone".

[0017] According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the first storage area includes a storage space of a predetermined size for data having a host access frequency in a second range.

[0018] Preferably, the sizes of these storage spaces are each greater than 64KB. When developing the sizes of these storage spaces, factors to be considered include the data rate at which the host accesses the dynamic random access memory DRAM, the data rate at which the controller accesses the dynamic random access memory DRAM, and the data rate at which the controller accesses the non-volatile memory such as NAND Flash.

[0019] According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the second storage area includes a plurality of sub-storage areas, each of the plurality of sub-storage areas stores data with a host access frequency in a different range.

[0020] According to a preferred embodiment of the dual in-line memory module device of the storage-level memory of the present invention, the second storage area includes two sub-storage areas, and the two sub-storage areas are:

[0021] a first sub-storage area storing data having a first sub-range of host access frequencies;

[0022] a second sub-storage area storing data having a second sub-range of host access frequencies;

[0023] The host access frequency of the first sub-range is greater than the host access frequency of the second sub-range.

[0024] According to a preferred embodiment of the dual in-line memory module device of the storage-level memory of the present invention, the first storage area is a plurality of dynamic random access memories.

[0025] Since the processing speed of the dynamic random access memory is relatively fast, the rate performance of the module device can be improved by storing data that is frequently read and written by the host or the central processing unit in the dynamic random access memory.

[0026] According to a preferred embodiment of the dual in-line memory module device of the storage-level memory of the present invention, the first sub-storage area is a dynamic random access memory cache module; and the second sub-storage area is a non-volatile memory.

[0027] Thus, the data with a relatively high host access frequency in the "cold data" is written into the dynamic random access memory cache module, and the data with a relatively low host access frequency in the "cold data" is written into the non-volatile memory. In this way, the rate performance of the device is further improved, and frequent access to the non-volatile memory is avoided, thereby avoiding damage to the non-volatile memory.

[0028] A preferred embodiment of the dual in-line memory module device of the storage class memory according to the present invention further comprises:

[0029] A controller is connected to the dynamic random access memory cache module and the non-volatile memory respectively.

[0030] The dual in-line memory module device of the storage-level memory according to the present invention further comprises:

[0031] A clock driver is connected to the controller.

[0032] According to a preferred embodiment of the dual in-line memory module device of the storage-class memory of the present invention, in response to the host writing data with a host access frequency in a second range to one or more of the plurality of dynamic random access memories, and in response to the controller receiving the address of the data with a host access frequency in the second range notified by the host via the system management bus, the controller sends a get data command to one or more of the plurality of data buffers to instruct the one or more of the plurality of data buffers to get the data with a host access frequency in the second range from one or more of the plurality of dynamic random access memories and send the data with a host access frequency in the second range to the controller; and,

[0033] In response to receiving the data having the host access frequency in the second range, the controller writes the data having the host access frequency in the second range into the DRAM cache module or the non-volatile memory.

[0034] Thus, the host can access the controller during normal operation, and by writing data with a host access frequency in the second range into the controller, the memory space of the device is increased. In addition, writing data that is not frequently accessed by the host (i.e., cold data) into the dynamic random access memory cache module or the non-volatile memory can improve the rate performance of the device.

[0035] According to a preferred embodiment of the dual in-line memory module device of the storage-level memory of the present invention, the clock driver is connected to the controller via a local command bus; the clock driver is connected to each of the multiple data buffers via a data buffer command bus; and the multiple data buffers are each connected to the controller via a local data bus.

[0036] According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the controller sends the get data command to one or more of the plurality of data buffers via the local command bus and the data buffer command bus.

[0037] According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, one or more of the plurality of data buffers sends the data having the host access frequency in the second range to the controller via the local data bus.

[0038] Thus, the difficulty of designing the printed circuit board of the device is reduced. At the same time, the cache is used to balance the speed difference between the non-volatile memory and the internal memory, so that the host can stably access the non-volatile memory with low overhead.

[0039] According to a preferred embodiment of the dual in-line memory module device of the storage-level memory of the present invention, the controller writes data having the host access frequency of the first sub-range into the dynamic random access memory cache module; and the controller writes data having the host access frequency of the second sub-range into the non-volatile memory.

[0040] According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the host directly writes data to one or more of the multiple dynamic random access memories via one or more of the multiple data buffers.

[0041] This can avoid the host and the controller from being connected to high-speed signals at the same time, thereby not causing difficulties in the design of the printed circuit board.

[0042] According to a preferred embodiment of the dual in-line memory module device of the storage-class memory of the present invention, in response to receiving the address of the data with the host access frequency in the second range notified by the host via the system management bus, the controller reads the data with the host access frequency in the second range from the dynamic random access memory cache module or the non-volatile memory and sends a write data command to one or more of the multiple data buffers to command one or more of the multiple data buffers to obtain the data with the host access frequency in the second range from the controller and then write the data with the host access frequency in the second range to one or more of the multiple dynamic random access memories; and,

[0043] The host reads data from one or more of the plurality of dynamic random access memories.

[0044] According to a preferred embodiment of the dual in-line memory module device of the storage-level memory of the present invention, the clock driver is connected to the controller via a local command bus; the clock driver is connected to each of the multiple data buffers via a data buffer command bus; and the multiple data buffers are each connected to the controller via a local data bus.

[0045] According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the controller sends a write data command to one or more of the plurality of data buffers via the local command bus and the data buffer command bus.

[0046] According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, one or more of the plurality of data buffers obtains the data having the host access frequency in the first range from the controller via the local data bus.

[0047] Thus, the difficulty of designing the printed circuit board of the device is reduced. At the same time, the cache is used to balance the speed difference between the non-volatile memory and the internal memory, so that the host can stably access the non-volatile memory with low overhead.

[0048] According to a preferred embodiment of the dual in-line memory module device of the storage-level memory of the present invention, the controller reads the data of the host access frequency having a first sub-range from the dynamic random access memory cache module; and the controller reads the data of the host access frequency having a second sub-range from the non-volatile memory.

[0049] According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the host reads data directly from one or more of the multiple dynamic random access memories via one or more of the multiple data buffers.

[0050] This can avoid the host and the controller from being connected to high-speed signals at the same time, thereby not causing difficulties in the design of the printed circuit board.

[0051] According to a preferred embodiment of the dual in-line memory module device of the storage class memory of the present invention, the wirings of the printed circuit board between the plurality of dynamic random access memories and the plurality of data buffers are of equal length.

[0052] As a result, the signal will not arrive at the destination at different times, further improving the rate performance.

[0053] According to a second aspect of the present invention, there is provided a method for accessing data of a dual in-line memory module device for a storage-level memory, the dual in-line memory module device comprising a first storage area and a second storage area;

[0054] The data access method comprises:

[0055] storing data having a first range of host access frequencies in a first storage area; and

[0056] storing data having a second range of host access frequencies in a second storage area;

[0057] The host access frequency in the first range is greater than the host access frequency in the second range.

[0058] According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

[0059] The data having a second range of host access frequencies is stored in the second storage area indirectly via the first storage area.

[0060] According to a preferred embodiment of the method for accessing data of the present invention, the first storage area includes a storage space of a predetermined size for data having a host access frequency in a second range.

[0061] According to a preferred embodiment of the method for accessing data of the present invention, the second storage area includes a plurality of sub-storage areas;

[0062] The method for accessing data further comprises:

[0063] Data having host access frequencies in different ranges are respectively stored in the plurality of sub-storage areas.

[0064] According to a preferred embodiment of the method for accessing data of the present invention, the second storage area includes two sub-storage areas, and the two sub-storage areas are a first sub-storage area and a second storage area;

[0065] The method for accessing data further comprises:

[0066] storing data having a first sub-range of host access frequencies in the first sub-storage area; and

[0067] storing data having a second sub-range of host access frequencies in the second sub-storage area;

[0068] The host access frequency of the first sub-range is greater than the host access frequency of the second sub-range.

[0069] According to a preferred embodiment of the method for accessing data of the present invention, the first storage area is a plurality of dynamic random access memories.

[0070] According to a preferred implementation of the data access method of the present invention, the first sub-storage area is a dynamic random access memory cache module; and the second sub-storage area is a non-volatile memory.

[0071] According to a preferred embodiment of the method for accessing data of the present invention, the dual in-line memory module device further comprises a controller;

[0072] The method for accessing data further comprises:

[0073] The controller is connected to the dynamic random access memory cache module and the non-volatile memory respectively.

[0074] According to a preferred embodiment of the method for accessing data of the present invention, the dual in-line memory module device further comprises a clock driver;

[0075] The method for accessing data further comprises:

[0076] The clock driver is connected to the controller.

[0077] According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

[0078] In response to the host writing data with host access frequencies in a second range to one or more of the plurality of dynamic random access memories, and in response to the controller receiving an address of the data with host access frequencies in the second range notified by the host via a system management bus, the controller sends a get data command to one or more of the plurality of data buffers to instruct the one or more of the plurality of data buffers to get the data with host access frequencies in the second range from one or more of the dynamic random access memories and send the data with host access frequencies in the second range to the controller; and

[0079] In response to receiving the data having the host access frequency in the second range, the controller writes the data having the host access frequency in the second range into the DRAM cache module or the non-volatile memory.

[0080] According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

[0081] The clock driver is connected to the controller via a local command bus;

[0082] The clock driver is connected to each of the plurality of data buffers via a data buffer command bus; and

[0083] Each of the plurality of data buffers is connected to the controller via a local data bus.

[0084] According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

[0085] The controller sends the get data command to one or more of the plurality of data buffers via the local command bus and the data buffer command bus.

[0086] According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

[0087] One or more of the plurality of data buffers transmits the data having a host access frequency in a second range to the controller via the local data bus.

[0088] According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

[0089] The controller writes data having the host access frequency in the first sub-range into the dynamic random access memory cache module; and

[0090] The controller writes data having the host access frequency of the second sub-range into the nonvolatile memory.

[0091] According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

[0092] The host directly writes data to one or more of the plurality of dynamic random access memories via one or more of the plurality of data buffers.

[0093] According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

[0094] In response to receiving an address of data with a host access frequency in a second range notified by the host via a system management bus, the controller reads the data with the host access frequency in the second range from the dynamic random access memory cache module or the non-volatile memory and sends a write data command to one or more of the plurality of data buffers to instruct the one or more of the plurality of data buffers to obtain the data with the host access frequency in the second range from the controller and then write the data with the host access frequency in the second range to one or more of the plurality of dynamic random access memories; and

[0095] The host reads data from one or more of the plurality of dynamic random access memories.

[0096] According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

[0097] The clock driver is connected to the controller via a local command bus;

[0098] The clock driver is connected to each of the plurality of data buffers via a data buffer command bus; and

[0099] Each of the plurality of data buffers is connected to the controller via a local data bus.

[0100] According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

[0101] The controller sends a write data command to one or more of the plurality of data buffers via the local command bus and the data buffer command bus.

[0102] According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

[0103] One or more of the plurality of data buffers retrieves the data having a first range of host access frequencies from the controller via the local data bus.

[0104] According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

[0105] The controller reads the data having the host access frequency of the first sub-range from the dynamic random access memory cache module; and

[0106] The controller reads the data having the host access frequency of the second sub-range from the non-volatile memory.

[0107] According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

[0108] The host reads data directly from one or more of the plurality of dynamic random access memories via one or more of the plurality of data buffers.

[0109] According to a preferred embodiment of the method for accessing data of the present invention, the method for accessing data further comprises:

[0110] The wirings of the printed circuit board between the plurality of dynamic random access memories and the plurality of data buffers are arranged to have equal lengths.

[0111] Those skilled in the art should understand that the second aspect of the present invention can achieve the technical effects described in relation to the first aspect of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0112] The present invention will be more easily understood through the following description in conjunction with the accompanying drawings, in which:

[0113] Figure 1 The present invention is a schematic diagram of signal flow and interface in a dual in-line memory module (DIMM) of a storage class memory (SCM) in the prior art.

[0114] Figure 2 The present invention is a schematic diagram of the signal flow and interface in a dual in-line memory module (DIMM) of another storage-class memory (SCM) in the prior art.

[0115] Figure 3 The structure of a dual in-line memory module DIMM of a storage class memory SCM according to one embodiment of the present invention. DETAILED DESCRIPTION

[0116] The embodiments of the present invention will be further described in detail below with reference to the accompanying drawings.

[0117] Figure 3 The structure of a dual in-line memory module DIMM of a storage class memory SCM according to one embodiment of the present invention.

[0118] exist Figure 3 In the structure, the host can access the dynamic random access memory DRAM 301 and the controller 304 during normal operation, and access the non-volatile memory such as NAND Flash 302 through the access controller 304, thereby increasing the memory space of the system.

[0119] Compared to Figure 2 ,exist Figure 3 In the structure, the clock driver RCD 305 and the data buffer DB 306 are used to improve the driving capability of the data DQ signal and the command / address CA signal. In addition, the host directly writes data to the dynamic random access memory DRAM 301 via the data buffer DB 306, avoiding the host and the controller 304 from connecting high-speed signals at the same time, and will not cause difficulties in the design of the printed circuit board. In addition, the wiring of the printed circuit board between the data buffer DB 306 and the dynamic random access memory DRAM 301 is also of equal length, which will not cause the signal to arrive at the destination at different times, further improving the rate performance.

[0120] In addition, when the host needs to access a non-volatile memory such as NAND Flash 302, it notifies the controller 304 via the system management bus SMBus that it wants to access the address segment of the non-volatile memory such as NAND Flash 302; the controller 304 uses a portion of the space of the dynamic random access memory DRAM 301 on the device as a buffer to enable the host to access the non-volatile memory such as NAND Flash 302.

[0121] Thus, the difficulty of designing the system printed circuit board is reduced, and at the same time, the cache is used to balance the rate difference between the non-volatile memory and the internal memory, so that the host can stably access the non-volatile memory with low overhead.

[0122] The following is further detailed Figure 3 structure.

[0123] like Figure 3 As shown in FIG. 1 , the dual in-line memory module DIMM of the storage class memory SCM includes a plurality of dynamic random access memories DRAM 301 , a non-volatile memory such as NAND Flash 302 and a dynamic random access memory DRAM cache module 303 .

[0124] In the present invention, the dynamic random access memory DRAM 301 ultimately stores "hot data", while the non-volatile memory such as NAND Flash 302 and the dynamic random access memory DRAM cache module 303 store "cold data", and the dynamic random access memory DRAM cache module 303 stores data with a relatively high host access frequency in the "cold data", and the non-volatile memory such as NAND Flash 302 stores data with a relatively low host access frequency in the "cold data".

[0125] In the present invention, "hot data" refers to data frequently accessed by a host or a central processing unit, and "cold data" refers to data infrequently accessed by a host or a central processing unit.

[0126] In the definition of "hot data" and "cold data", whether it is frequently accessed is defined based on the specific situation, and there is no specific value to define it.

[0127] The configuration described in the present invention can improve the rate performance of the device and avoid frequent access to the non-volatile memory, thereby avoiding damage to the non-volatile memory.

[0128] like Figure 3 As further shown in FIG. 3 , the dual in-line memory module DIMM of the storage class memory SCM includes a controller 304, a clock driver RCD 305, and a plurality of data buffers DB 306. The clock driver RCD 305 is connected to the controller 304 via a local command bus LCOM, the clock driver RCD 305 is connected to each of the plurality of data buffers DB 306 via a data buffer command bus BCOM, and the data buffers DB 306 are each connected to the controller 304 via a local data bus LDQ.

[0129] The following further understands the process of writing data to the controller 304 or the dynamic random access memory DRAM cache module 303 and reading data from the host. Figure 3 The structure in .

[0130] When the host writes data to a non-volatile memory such as NAND Flash 302 or a dynamic random access memory DRAM cache module 303, the host first writes the data to one or more of the multiple dynamic random access memories DRAM 301. In the method of the present invention, since this "data" will eventually be written to a non-volatile memory such as NAND Flash 302 or a dynamic random access memory DRAM cache module 303, this "data" refers to "cold data".

[0131] It should be understood that the host can write hot data and cold data into the dynamic random access memory DRAM 301, and the hot data is finally stored in the dynamic random access memory DRAM 301, while the cold data is finally stored in a non-volatile memory such as NAND Flash 302 or a dynamic random access memory DRAM cache module 303. In the present invention, in each of the multiple dynamic random access memories DRAM 301, there is a reserved cache area with a fixed space size for caching cold data.

[0132] Preferably, the space size of these buffer areas is greater than 64KB respectively. When developing the space size of these buffer areas, factors to be considered are such as the data rate at which the host accesses the dynamic random access memory DRAM, the data rate at which the controller 304 accesses the dynamic random access memory DRAM, and the data rate at which the controller 304 accesses the non-volatile memory such as NAND Flash 302.

[0133] After the host writes the cold data to one or more of the multiple dynamic random access memories DRAM 301, the controller 304 obtains the "cold data" from one or more of the multiple dynamic random access memories DRAM 301 and writes the "cold data" to a non-volatile memory such as NAND Flash 302 and a dynamic random access memory DRAM cache module 303 according to a cache algorithm.

[0134] In the present invention, the host can directly write data into one or more of the multiple dynamic random access memories DRAM 301 via one or more of the multiple data buffers DB 306 , and the host has the operation control right of the multiple dynamic random access memories DRAM 301 .

[0135] Then, the host notifies the controller 304 of the address of the data with the host access frequency in the second range (i.e., the "cold data" that is not frequently accessed by the host) via the system management bus SMBus, and the controller 304 switches the operation control of the dynamic random access memory DRAM 301 from the host. Afterwards, the controller 304 sends the acquisition data command to one or more of the multiple data buffers DB 306 via the local command bus LCOM between the clock driver RCD 305 and the controller 304 and the data buffer command bus BCOM between the clock driver RCD 305 and each of the multiple data buffers DB 306, so as to command one or more of the multiple data buffers DB 306 to acquire the "cold data" from one or more of the multiple dynamic random access memories DRAM 301 and send the "cold data" to the controller 304 via the local data bus LDQ. Finally, the controller 304 writes the "cold data" into the dynamic random access memory DRAM cache module 303 or the non-volatile memory such as NAND Flash 302 according to the cache algorithm.

[0136] The overall idea of ​​the cache algorithm is: write the data with a first sub-range of host access frequency (i.e., relatively high host access frequency) in the "cold data" into the dynamic random access memory cache module 303; and write the data with a second sub-range of host access frequency (i.e., relatively low host access frequency) in the "cold data" into the non-volatile memory 302.

[0137] When the host reads data from a non-volatile memory such as NAND Flash 302 or a dynamic random access memory DRAM cache module 303, the host first notifies the controller 304 of the address of the "cold data". The controller 304 reads the "cold data" from the non-volatile memory such as NAND Flash 302 and the dynamic random access memory DRAM cache module 303 according to the address, and writes the "cold data" to one or more of the multiple dynamic random access memories DRAM 301. Then the host reads the "cold data" from one or more of the multiple dynamic random access memories DRAM 301.

[0138] Specifically, the host first notifies the controller 304 of the address of data (i.e., "cold data") with a host access frequency in a first range via the system management bus SMBus, and the controller 304 reads the "cold data" from the non-volatile memory such as NAND Flash 302 and the dynamic random access memory DRAM cache module 303 according to the address, and sends the write data command to one or more of the multiple data buffers DB 306 via the local command bus LCOM between the clock driver RCD 305 and the controller 304 and the data buffer command bus BCOM between the clock driver RCD 305 and one or more of the multiple data buffers DB 306, so as to command one or more of the multiple data buffers DB 306 to obtain the "cold data" from the controller 304 via the local data bus LDQ and then write the "cold data" to one or more of the multiple dynamic random access memories DRAM 301. Finally, the host reads data from one or more of the multiple dynamic random access memories DRAM 301.

[0139] in addition, Figure 3 The dual in-line memory module DIMM of the storage-class memory SCM shown in the figure is a typical NVDIMM-N type. Figure 3 A typical SAVE_n signal between the host and the dual inline memory module DIMM of the storage class memory SCM is shown in FIG. The SAVE_n signal is used to be pulled low by the host when the system loses power abnormally to notify the dual inline memory module NVDIMM to perform data backup.

[0140] It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative embodiments without departing from the scope of the appended claims.It should be understood that the scope of the invention is defined by the claims.

Claims

1. A dual in-line memory module device of a storage-level memory, characterized in that: include: Controller; A clock driver connected to the controller; a first storage area storing data having a first range of host access frequencies, wherein the first storage area is a plurality of dynamic random access memories; as well as a second storage area, the second storage area storing data having a second range of host access frequencies, wherein the first range of host access frequencies is greater than the second range of host access frequencies; wherein the data having the second range of host access frequencies is stored in the second storage area indirectly via the first storage area, wherein the first storage area includes a storage space of a predetermined size for the data having the second range of host access frequencies; The second storage area includes two sub-storage areas, and the two sub-storage areas are: A first sub-storage area, wherein the first sub-storage area stores data having a first sub-range host access frequency, wherein the first sub-storage area is a dynamic random access memory cache module; a second sub-storage area storing data having a second sub-range host access frequency, wherein the second sub-storage area is a non-volatile memory, wherein the first sub-range host access frequency is greater than the second sub-range host access frequency; wherein the controller is connected to the dynamic random access memory cache module and the non-volatile memory respectively; wherein in response to the host writing data with a host access frequency in a second range to one or more of the plurality of dynamic random access memories, and in response to the controller receiving an address of the data with a host access frequency in the second range notified by the host via a system management bus, the controller sends a get data command to one or more of the plurality of data buffers to instruct the one or more of the plurality of data buffers to get the data with a host access frequency in the second range from one or more of the plurality of dynamic random access memories and send the data with a host access frequency in the second range to the controller; as well as, In response to receiving the data with the host access frequency in the second range, the controller writes the data with the host access frequency in the second range into the dynamic random access memory cache module or the non-volatile memory.

2. The dual in-line memory module device of the storage-level memory according to claim 1, characterized in that: The clock driver is connected to the controller via a local command bus; The clock driver is connected to each of the plurality of data buffers via a data buffer command bus; as well as Each of the plurality of data buffers is connected to the controller via a local data bus.

3. The dual in-line memory module device of the storage-level memory according to claim 2, characterized in that: The controller sends the get data command to one or more of the plurality of data buffers via the local command bus and the data buffer command bus.

4. The dual in-line memory module device of the storage-level memory according to claim 3, characterized in that: One or more of the plurality of data buffers transmits the data having a second range of host access frequencies to the controller via the local data bus.

5. The dual in-line memory module device of the storage-level memory according to any one of claims 1 to 4, characterized in that: The controller writes data having the first sub-range host access frequency into the dynamic random access memory cache module; as well as The controller writes data having the second sub-range host access frequency into the nonvolatile memory.

6. The dual in-line memory module device of the storage-level memory according to any one of claims 1 to 4, characterized in that: The host directly writes data to one or more of the plurality of dynamic random access memories via one or more of the plurality of data buffers.

7. The dual in-line memory module device of the storage-level memory according to any one of claims 1 to 4, characterized in that: The wirings of the printed circuit board between the plurality of dynamic random access memories and the plurality of data buffers are of equal length.

8. A dual in-line memory module device of a storage-level memory, characterized in that: include: Controller; A clock driver connected to the controller; a first storage area storing data having a first range of host access frequencies, wherein the first storage area is a plurality of dynamic random access memories; as well as a second storage area, the second storage area storing data having a second range of host access frequencies, wherein the first range of host access frequencies is greater than the second range of host access frequencies; wherein the data having the second range of host access frequencies is stored in the second storage area indirectly via the first storage area, wherein the first storage area includes a storage space of a predetermined size for the data having the second range of host access frequencies; The second storage area includes two sub-storage areas, and the two sub-storage areas are: A first sub-storage area, wherein the first sub-storage area stores data having a first sub-range host access frequency, wherein the first sub-storage area is a dynamic random access memory cache module; a second sub-storage area storing data having a second sub-range host access frequency, wherein the second sub-storage area is a non-volatile memory, wherein the first sub-range host access frequency is greater than the second sub-range host access frequency; wherein the controller is connected to the dynamic random access memory cache module and the non-volatile memory respectively; In response to receiving the address of the data with the host access frequency in the second range notified by the host via the system management bus, the controller reads the data with the host access frequency in the second range from the dynamic random access memory cache module or the non-volatile memory and sends a write data command to one or more of the plurality of data buffers to instruct the one or more of the plurality of data buffers to obtain the data with the host access frequency in the second range from the controller and then write the data with the host access frequency in the second range to one or more of the plurality of dynamic random access memories; as well as, The host reads data from one or more of the plurality of dynamic random access memories.

9. The dual in-line memory module device of the storage-level memory according to claim 8, characterized in that: The clock driver is connected to the controller via a local command bus; The clock driver is connected to each of the plurality of data buffers via a data buffer command bus; as well as Each of the plurality of data buffers is connected to the controller via a local data bus.

10. The dual in-line memory module device of the storage-level memory according to claim 9, characterized in that: The controller sends a write data command to one or more of the plurality of data buffers via the local command bus and the data buffer command bus.

11. The dual in-line memory module device of the storage-level memory according to claim 10, characterized in that: One or more of the plurality of data buffers retrieves the data having a first range of host access frequencies from the controller via the local data bus.

12. The dual in-line memory module device of the storage-level memory according to any one of claims 8 to 11, characterized in that: The controller reads the data having a first sub-range of host access frequencies from the dynamic random access memory cache module; and The controller reads the data having the second sub-range host access frequency from the non-volatile memory.

13. The dual in-line memory module device of the storage-level memory according to any one of claims 8 to 11, characterized in that: The host reads data directly from one or more of the plurality of dynamic random access memories via one or more of the plurality of data buffers.

14. The dual in-line memory module device of the storage-level memory according to any one of claims 8 to 11, characterized in that: The wirings of the printed circuit board between the plurality of dynamic random access memories and the plurality of data buffers are of equal length.

15. A method for accessing data of a dual in-line memory module device for a storage-level memory, characterized in that: The dual in-line memory module device comprises a first storage area, a second storage area, a controller and a clock driver; The data access method comprises: storing data having a first range of host access frequencies in a first storage area, wherein the first storage area is a plurality of dynamic random access memories; and storing data having a second range of host access frequencies indirectly in the second storage area via the first storage area; wherein the first range of host access frequencies is greater than the second range of host access frequencies, wherein the first storage area includes a storage space of a predetermined size for the data having the second range of host access frequencies, The second storage area includes two sub-storage areas, the two sub-storage areas are a first sub-storage area and a second sub-storage area, wherein the first sub-storage area is a dynamic random access memory cache module, and the second sub-storage area is a non-volatile memory; the data access method further includes: storing data having a first sub-range of host access frequencies in the first sub-storage area; and storing data having a second sub-range host access frequency in the second sub-storage area, wherein the first sub-range host access frequency is greater than the second sub-range host access frequency, The method for accessing data further comprises: Connecting the controller to the dynamic random access memory cache module and the non-volatile memory respectively, and connecting the clock driver to the controller; The method for accessing data further comprises: In response to the host writing data with a host access frequency in a second range to one or more of the plurality of dynamic random access memories, and in response to the controller receiving an address of the data with a host access frequency in the second range notified by the host via a system management bus, the controller sends a get data command to one or more of the plurality of data buffers to instruct the one or more of the plurality of data buffers to get the data with a host access frequency in the second range from one or more of the dynamic random access memories and send the data with a host access frequency in the second range to the controller; and In response to receiving the data with the host access frequency in the second range, the controller writes the data with the host access frequency in the second range into the dynamic random access memory cache module or the non-volatile memory.

16. The method for accessing data according to claim 15, characterized in that: The method for accessing data further comprises: The clock driver is connected to the controller via a local command bus; The clock driver is connected to each of the plurality of data buffers via a data buffer command bus; and Each of the plurality of data buffers is connected to the controller via a local data bus.

17. The method for accessing data according to claim 16, characterized in that: The method for accessing data further comprises: The controller sends the get data command to one or more of the plurality of data buffers via the local command bus and the data buffer command bus.

18. The method for accessing data according to claim 17, characterized in that: The method for accessing data further comprises: One or more of the plurality of data buffers transmits the data having a second range of host access frequencies to the controller via the local data bus.

19. The method for accessing data according to any one of claims 15 to 18, characterized in that: The method for accessing data further comprises: The controller writes data having the first sub-range of host access frequencies into the dynamic random access memory cache module; and The controller writes data having the second sub-range host access frequency into the nonvolatile memory.

20. The method for accessing data according to any one of claims 15 to 18, characterized in that: The method for accessing data further comprises: The host directly writes data to one or more of the plurality of dynamic random access memories via one or more of the plurality of data buffers.

21. The method for accessing data according to any one of claims 15 to 18, characterized in that: The wirings of the printed circuit board between the plurality of dynamic random access memories and the plurality of data buffers are of equal length.

22. A method for accessing data of a dual in-line memory module device for a storage-level memory, characterized in that: The dual in-line memory module device comprises a first storage area, a second storage area, a controller and a clock driver; The data access method comprises: storing data having a first range of host access frequencies in a first storage area, wherein the first storage area is a plurality of dynamic random access memories; and storing data having a second range of host access frequencies indirectly in the second storage area via the first storage area; wherein the first range of host access frequencies is greater than the second range of host access frequencies, wherein the first storage area includes a storage space of a predetermined size for the data having the second range of host access frequencies, The second storage area includes two sub-storage areas, the two sub-storage areas are a first sub-storage area and a second sub-storage area, wherein the first sub-storage area is a dynamic random access memory cache module, and the second sub-storage area is a non-volatile memory; the data access method further includes: storing data having a first sub-range of host access frequencies in the first sub-storage area; and storing data having a second sub-range host access frequency in the second sub-storage area, wherein the first sub-range host access frequency is greater than the second sub-range host access frequency, The method for accessing data further comprises: Connecting the controller to the dynamic random access memory cache module and the non-volatile memory respectively, and connecting the clock driver to the controller; The method for accessing data further comprises: In response to receiving an address of data with a host access frequency in a second range notified by the host via a system management bus, the controller reads the data with a host access frequency in the second range from the dynamic random access memory cache module or the non-volatile memory and sends a write data command to one or more of the plurality of data buffers to instruct the one or more of the plurality of data buffers to obtain the data with a host access frequency in the second range from the controller and then write the data with a host access frequency in the second range to one or more of the plurality of dynamic random access memories; and The host reads data from one or more of the plurality of dynamic random access memories.

23. The method for accessing data according to claim 22, characterized in that: The method for accessing data further comprises: The clock driver is connected to the controller via a local command bus; The clock driver is connected to each of the plurality of data buffers via a data buffer command bus; and Each of the plurality of data buffers is connected to the controller via a local data bus.

24. The method for accessing data according to claim 23, characterized in that: The method for accessing data further comprises: The controller sends a write data command to one or more of the plurality of data buffers via the local command bus and the data buffer command bus.

25. The method for accessing data according to claim 24, characterized in that: The method for accessing data further comprises: One or more of the plurality of data buffers retrieves the data having a first range of host access frequencies from the controller via the local data bus.

26. The method for accessing data according to any one of claims 22 to 25, characterized in that: The method for accessing data further comprises: The controller reads the data having a first sub-range of host access frequencies from the dynamic random access memory cache module; and The controller reads the data having the second sub-range host access frequency from the non-volatile memory.

27. The method for accessing data according to any one of claims 22 to 25, characterized in that: The method for accessing data further comprises: The host reads data directly from one or more of the plurality of dynamic random access memories via one or more of the plurality of data buffers.

28. The method for accessing data according to any one of claims 22 to 25, characterized in that: The wirings of the printed circuit board between the plurality of dynamic random access memories and the plurality of data buffers are of equal length.

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