Dual-mode frequency multiplier

Abstract

The present invention is entitled "Dual-Mode Frequency Multiplier" and provides an exemplary dual-mode frequency multiplier embodiment, which includes: a first nonlinear element and a second nonlinear element, a summing node and a switchable phase shifter. The first nonlinear element and the second nonlinear element are driven by a differential signal to generate a first branch signal and a second branch signal, each having even harmonics and odd harmonics, the even harmonics being in phase and the odd harmonics being out of phase. The first branch signal and the second branch signal are combined at the summing node to form a combined signal. The switchable phase shifter couples the first nonlinear element to the summing node, thereby providing a phase shift switchable between 0° and 180° to the first branch signal to suppress odd harmonics or even harmonics from the combined signal.

Description

Technical Field

[0001] This application relates generally to electronics and, more particularly, to designs for dual-mode frequency multipliers. Background Art

[0002] With the development of fifth-generation communication systems, multiple millimeter-wave frequency bands have been allocated worldwide, including but not limited to spectrum near 28 GHz and 39 GHz. The availability of multiple such frequency bands enables integrated frequency-reconfigurable transceivers to facilitate multiple-input and multiple-output (MIMO) frequency diversity and reduce the cost of silicon (Si) integrated circuit (IC) components, thereby eliminating the need for dedicated ICs for each frequency band. Such multi-band transceivers can achieve adequate performance with existing multi-band components such as low-noise amplifiers (LNAs), power amplifiers (PAs), and filters.

[0003] Gigahertz band transceivers routinely employ frequency multipliers. Existing variable frequency multiplier designs can use self-mixing or injection locking, but inherently suffer from low output power, insufficient harmonic suppression, and / or separate outputs for different tones. Some designs may use complex frequency generation circuits that include parallel frequency multipliers and amplifier chains that are switched to a single output by a multiplexer. Using more than one voltage-controlled oscillator (VCO) or a multimode VCO is also contemplated, but this approach is expected to undesirably impact system complexity, chip area, and / or phase noise performance. Summary of the Invention

[0004] The above-identified problems may be solved, at least in part, by the disclosed transceiver, frequency multiplier, and method.

[0005] According to one aspect of the present application, a dual-mode frequency multiplier is provided, characterized in that it includes: a first nonlinear element and a second nonlinear element, which are driven by a differential signal to generate a first branch signal and a second branch signal, each having even harmonics and odd harmonics, the even harmonics are in phase and the odd harmonics are out of phase; a summing node, wherein the first branch signal and the second branch signal are combined to form a combined signal; and a switchable phase shifter, which couples the first nonlinear element to the summing node, thereby providing a phase shift switchable between 0° and 180° for the first branch signal to suppress odd harmonics or even harmonics from the combined signal.

[0006] In one embodiment, the dual-mode frequency multiplier is characterized in that the switchable phase shifter includes: a first portion and a second portion of an integrated transmission line, the first portion and the second portion each having a signal conductor and a return current conductor; a first switch pair, the first switch pair coupling the signal conductors together and coupling the return current conductors together to provide a 0° phase shift; and a second switch pair, the second switch pair coupling the signal conductor of the first portion to the return current conductor of the second portion, and coupling the return current conductor of the first portion to the signal conductor of the second portion to provide a 180° phase shift.

[0007] In one embodiment, the dual-mode frequency doubler is characterized in that the first portion and the second portion each include a coplanar waveguide, and the switch pair each includes a SiGe heterojunction bipolar transistor.

[0008] In one embodiment, the dual-mode frequency doubler is characterized in that the first nonlinear element and the second nonlinear element each comprise a heterojunction bipolar transistor biased at an exponential portion of a characteristic current-voltage curve.

[0009] In one embodiment, the dual-mode frequency multiplier is further characterized by including: an input transformer that converts a single-ended input signal into the differential signal, the differential signal being provided to the base of the heterojunction bipolar transistor together with a bias signal; and a second switchable phase shifter that couples the second nonlinear element to the summing node, wherein one or more transformers couple the first branch signal and the second branch signal to the switchable phase shifter and the second switchable phase shifter, respectively.

[0010] According to another aspect, a dual-band transceiver is provided, characterized in that it includes: a phase-locked loop (PLL) that provides a PLL signal in the 10.5 GHz to 11.5 GHz frequency band; a dual-mode frequency multiplier including a switchable phase shifter that converts the PLL signal into a local oscillator signal having a frequency twice or three times that of the PLL signal based on whether the switchable phase shifter is set for a 0° phase shift or a 180° phase shift; and a mixer that uses the local oscillator signal to up-convert a 6 GHz intermediate frequency transmit signal to a radio frequency transmit signal in the 28 GHz or 39 GHz frequency band.

[0011] In one embodiment, the dual-band transceiver is characterized by including a second mixer that uses a local oscillator signal to down-convert a radio frequency receive signal in the 28 GHz or 39 GHz band to a 6 GHz intermediate frequency receive signal.

[0012] In one embodiment, the dual-band transceiver is characterized in that the dual-mode frequency multiplier includes a differential pair of transistors that convert the PLL signal into a first branch signal and a second branch signal having even harmonics and odd harmonics, the even harmonics are in phase and the odd harmonics are out of phase between the first branch signal and the second branch signal, the differential pair of transistors is biased to operate in an exponential portion of its characteristic current-voltage curve, wherein a switchable phase shifter couples the first branch signal to a summing node to form a combined signal with the second branch signal.

[0013] In one embodiment, a dual-band transceiver is characterized in that the switchable phase shifter includes: a first portion and a second portion of an integrated transmission line, the first portion and the second portion each having a signal conductor and a return current conductor; a first switch pair that couples the signal conductors together and the return current conductors together to provide a 0° phase shift; and a second switch pair that couples the signal conductors of the first portion to the return current conductors of the second portion, and couples the return current conductors of the first portion to the signal conductors of the second portion to provide a 180° phase shift.

[0014] According to another aspect, a frequency doubling method is provided, characterized in that it includes: driving a first nonlinear element and a second nonlinear element with a differential signal to generate a first branch signal and a second branch signal, each having even harmonics and odd harmonics, between the branch signals, the even harmonics are in phase and the odd harmonics are out of phase; coupling the first branch signal to a summing node to form a combined signal with the second branch signal, the coupling being performed by a switchable phase shifter; and switching the switchable phase shifter between 0° and 180° to suppress odd harmonics or even harmonics from the combined signal.

[0015] In one embodiment, the frequency doubling method is characterized in that the switchable phase shifter includes a first portion and a second portion of an integrated transmission line, the first portion and the second portion each having a signal conductor and a return current conductor, and wherein the switching includes: coupling the signal conductors of the first portion and the second portion together and coupling the return current conductors of the first portion and the second portion together to provide a 0° phase shift; and coupling the signal conductor of the first portion to the return current conductor of the second portion and coupling the return current conductor of the first portion to the signal conductor of the second portion to provide a 180° phase shift. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a schematic diagram of an exemplary radio frequency (RF) transceiver with a multi-mode frequency multiplier.

[0017] Figure 2 is a schematic diagram of an exemplary multi-mode frequency multiplier circuit.

[0018] Figures 3A to 3Bis a schematic diagram of an exemplary multi-band driver-amplifier circuit.

[0019] Figure 4 is a schematic diagram of an exemplary multi-mode frequency multiplier circuit including a dual-band output driver-amplifier.

[0020] Figure 5 is a schematic diagram of an exemplary switchable phase shifter.

[0021] Figure 6 is a schematic diagram of an exemplary unit cell for a transmission line.

[0022] 7A to 7B is a histogram showing the impact of process variations. DETAILED DESCRIPTION

[0023] It should be understood that the drawings and following description do not limit the disclosure, but rather provide a basis for those skilled in the art to understand all modifications, equivalents, and alternatives falling within the scope of the claims.

[0024] Now refer to Figure 1 , shows an exemplary 28 / 39 GHz fifth generation (5G) transceiver having a phase-locked loop (PLL) and a frequency multiplier / tripler operating at 10.5-11.5 GHz. The PLL signal may be provided by a voltage controlled oscillator (VCO) 101. For 28 GHz operation, a multimode frequency multiplier 102 doubles the PLL signal frequency to provide a 22 GHz local oscillator (LO) signal to a mixer 103, while for 39 GHz operation, the frequency multiplier 102 may operate in tripler mode with an output of 33 GHz. For both bands, a wideband mixer 103 multiplies the LO signal by an intermediate frequency transmit (TX_IF) signal from a variable gain amplifier (VGA) 104. The IF signal may be centered at 6 GHz, causing the mixer to produce upconverted signals centered at 28 GHz and 39 GHz, respectively. The bandpass filter 105 passes the desired frequency of the up-converted signal from the mixer 103, thereby suppressing the energy of the signal image at other frequencies, and the driver 106 amplifies the up-converted signal to drive the radio frequency output (TX_RF).

[0025] Multimode frequency multiplier 102 can similarly be used to generate an LO signal for a second mixer 113, which downconverts the received RF signal (RX_RF) from the 28 GHz and 39 GHz bands to the 6 GHz band. A low-noise VGA 114 supplies the RF signal to mixer 113, and a bandpass filter 115 passes the desired frequency of the downconverted signal as an intermediate frequency (IF) received signal (RX_IF). An optional driver 116 buffers the received signal.

[0026] Referring now to exemplary embodiments of the present disclosure, integrated circuit (IC) transceivers may be fabricated using, for example, 120 nm SiGe8XP technology (available from Global Foundries, Santa Clara, CA), which provides a 120 nm SiGe 8XP transceiver having ... T / f max = 260 / 340 GHz high speed heterojunction bipolar transistors (HBTs). This exemplary process provides a 7-layer metallization with a 4 μm thick Al top metal and CMOS transistors, which can also be used for RF applications. Other suitable fabrication techniques are known and available.

[0027] The frequency multiplier 102 can be designed to achieve high harmonic rejection and sufficient output power to drive a mixer in both modes. Single-ended devices operating in a nonlinear regime may generate both strong 2nd and 3rd harmonics, and various methods can be employed to suppress the undesirable harmonics. For example, a tunable and highly selective filter can be used to suppress the undesirable harmonics, which may result in high insertion loss and, therefore, output power loss. As another example, a conventional differential pair with a common node output or a balun-loaded output can be used to generate higher output power, but only at even or odd harmonics, respectively.

[0028] Here, it is desirable to provide higher output power combined with configurable harmonic suppression for dual-mode operation. This multimode frequency multiplier can be implemented using various technologies (such as, but not limited to, SiGe BiCMOS technology) and can be paired with a driver amplifier. An example of such a driver amplifier is a transmission line-based tuned driver amplifier capable of 40% tuning range and greater than 2 dBm output power over the full bandwidth in both modes. Other driver amplifiers are known and would also be suitable. This frequency multiplier would enable a single VCO operating in the X-band with moderate tuning range and low phase noise to provide local oscillator (LO) signals for the 28 GHz and 39 GHz bands with minimal area penalty.

[0029] Now refer to Figure 2Some exemplary embodiments of the frequency multiplier may use a 1-bit phase shifter (i.e., 0° / 180°) following the differential pair to obtain dual-mode operation. Transistors Q1, Q2 have a common emitter or source node coupled to ground, and their collectors or drains Q1, Q2 are coupled to a summing node 202 through respective phase shifters PS1, PS2. The bases or gates of transistors Q1, Q2 are coupled to a differential input voltage Vin+, Vin-. An impedance matching network MN transmits the combined signal from the summing node 202 to the output terminal OUT and may also provide a supply voltage to the summing node to bias transistors Q1, Q2 at a desired operating point. The matching network may also operate to filter out any undesirable harmonics of the fundamental frequency and the differential input voltage.

[0030] Since it is desirable to provide frequency multiplication, transistors Q1 and Q2 can be biased to operate in a nonlinear regime (such as the exponential region of the HBT current-voltage curve) so that the collector current through Q1 includes the input signal V in+ = the stronger 2nd and 3rd harmonics of Acos(ωt), and the collector current through Q2 includes V in- = -A cos(ωt)'s stronger 2nd and 3rd harmonics. The even harmonics in the collector current are unaffected by the input sign difference, while the odd harmonics are placed 180° out of phase. If both phase shifters are in the same state, the even harmonics sum at summing node 202, while the odd harmonics cancel. Conversely, if one of the phase shifters is switched 180° out of phase with the other, the even harmonics cancel at the summing node, while the odd harmonics sum together. In this way, the frequency multiplier can easily switch between doubling and tripling the input signal frequency.

[0031] Figure 2 The frequency doubler may be followed by a multi-band driver amplifier such as Figure 3A and Figure 3B The peak frequency can be tuned from 22 GHz to 33 GHz using a variable matching network based on a variable artificial transmission line (T-line) and switched capacitors.

[0032] The exemplary driver-amplifier employs two HBTs Q3 and Q4 in a cascode amplifier configuration. The summing node signal can be transmitted to the base of transistor Q3 by an input impedance matching network IMN, which also provides a bias voltage BIAS to the base via a resistor. The emitter is coupled to ground and the collector is coupled to the emitter of cascode transistor Q4. The base of cascode transistor Q4 receives a bias voltage VCB via a resistor and capacitor C5. The collector of the cascode transistor is coupled to the output terminal OUT via an output impedance matching network OMN. In some embodiments, a single matching network (MN) can be utilized at the output. MN can be tuned to be closer to the 3rd harmonic optimal load impedance than the 2nd harmonic optimal load impedance to help equalize the output power roll-off.

[0033] The matching network can be used Figure 3B The exemplary embodiments can be adjusted to operate in multiple different frequency bands. The exemplary IMN and OMN matching networks each include a simple LC network formed by transmission line elements TL1, TL2, which provide variable shunt impedance and capacitance, optionally in combination with a variable series capacitance, which can be embodied as a parallel bank of one or more switched capacitors in parallel with a fixed capacitor. The switched capacitors can be selectively enabled to adjust the series capacitance, where different capacitance values ​​produce different passbands. Multimode operation can be achieved by adjusting the input and output matching networks to the desired frequency range. TL1 and TL2 can represent cascaded unit T-line cells, as discussed further below.

[0034] Figure 4 A possible implementation of a frequency multiplier core is shown, which has a differential pair of transistors Q1 and Q2 transformer-coupled to phase shifters PS1 and PS2 to potentially avoid affecting their DC operating points. A single-ended PLL signal can be provided to input terminal IN, which is AC-coupled to the primary of transformer T1 via capacitor C0. Transformer T1 has a center-tapped secondary to convert the single-ended signal on the primary to a differential signal on the secondary. The center tap of the secondary is coupled to a bias voltage BIAS for setting the DC operating point of transistors Q1 and Q2. As previously mentioned, transistors Q1 and Q2 are preferably biased into a nonlinear portion of their current-voltage curves to generate strong harmonics in response to the input signal. The collectors of transistors Q1 and Q2 are coupled to the ends of the center-tapped primary of transformer T2, the center tap of which is coupled to a supply voltage (shown here as 1.6V). The collector currents from Q1, Q2 generate magnetic fields that may combine in the primary of T2, but the secondary of T2 has a center tap coupled to ground, resulting in a differential signal between the end terminals of the secondary.

[0035] Phase shifters PS1 and PS2 operate as previously described to enhance even or odd harmonics at summing node 202, depending on whether the phase shifters are in the same state or 180° out of phase. Inductor L1 and capacitors C1, C2, and C3 form a filter with a high-pass filter response with a notch at the fundamental harmonic, which can be used in tripler mode. These tripler modes do not provide tonal suppression other than the frequency response of the output balun. The notched high-pass filter transmits the multiplied signal from summing node 202 to an input impedance matching network (IMN) formed by transmission line elements TL1 and TL3 and capacitor C4. The base of transistor Q3 receives the filtered signal from the IMN. Q3 and Q4 form a cascode amplifier that amplifies the filtered signal and supplies it to an output impedance matching network (OMN) formed by transmission line element TL2, capacitor C6, and switched capacitor C7. Band selector input B is provided to the gate of transistor M5 to selectively add the capacitance of C7 to capacitor C6.

[0036] It should be noted that Figure 4 Matching network design and Figures 3A to 3B The designs of the MOSFETs are different because they are tailored for dual-band operation. As shown, the series capacitance at the driver output is divided into fixed capacitors and switched capacitors. The switches in the driver (e.g., transistor M5) can be implemented using triple-well nMOS devices with deep trench isolation to achieve minimal parasitic capacitance to the substrate. However, other suitable switching devices can be used instead. The driver can be designed for small signal gain with a large bandwidth (such as >8 GHz) in both modes. The frequency response of the driver can be designed to further attenuate major out-of-band harmonics.

[0037] Phase shifters PS1, PS2 can provide frequency-independent phase shift, thereby enabling a broadband design.Some embodiments can be further configured to reduce and balance insertion loss (IL) to minimize degradation of output power and degradation of harmonic suppression.

[0038] Figure 5 One possible implementation of each phase shifter PS1, PS2 is shown. Phase shifter 500 can include two coplanar waveguide (CPW) transmission line sections 502A, 502B connected in series. The transmission line section shown has a center conductor between two coplanar shield conductors. Insulated cross conductors can optionally be located below and / or above the center conductor and shield conductors to slow signal propagation along the conductors. Phase shifter 500 also includes a switch arrangement Q5-Q8. Switches Q5 and Q7 are shown as NPN transistors that receive a select voltage VB at their bases, while switches Q6 and Q8 are shown as NPN transistors that receive an inverted select voltage / VB at their bases.

[0039] When select voltage VB is active ("high"), switches Q5 and Q7 are turned on, while switches Q6 and Q8 are turned off. When turned on, switch Q5 couples the center conductor of portion 502A to the center conductor of portion 502B, and switch Q7 couples the shield conductor of portion 502A to the shield conductor of portion 502B. This direct connection configuration corresponds to zero phase shift when a signal propagates from portion 502A to 502B.

[0040] When select voltage VB is deasserted ("low"), switches Q5 and Q7 are off, while switches Q6 and Q8 are on. When on, switch Q6 couples the center conductor of section 502A to the shield conductor of section 502B, and switch Q8 couples the shield conductor of section 502A to the center conductor of section 502B. This cross-connection configuration between the signal path and the return current path corresponds to a 180° phase shift or anti-phase as the signal propagates from section 502A to 502B.

[0041] The size of the switches Q5-Q8 (which may be heterojunction bipolar transistors (HBTs) or field effect transistors (FETs)) and the interconnect layout (vias and metal layers) may be iteratively optimized to achieve lower amplitude and phase errors.

[0042] Figure 6 A unit cell 600 of a slow-wave coplanar waveguide is shown. The unit cell includes a coplanar waveguide transmission line section 502 having a center conductor between two coplanar shield conductors. Insulated cross conductors may be located below and / or above the center conductor and shield conductors to slow signal propagation through the unit cell 600. The unit cell shown includes a load capacitance CL, which may take the form of a metal-insulator-metal (MIM) shunt capacitor that can be selectively coupled to ground via a switch M0. When asserted, a gate voltage Vg turns the switch on, thereby adding the load capacitance to the capacitance of the center conductor and thereby slowing the propagation speed (β). When deasserted, switch M0 turns off, decoupling the load capacitance from ground and thereby removing the additional capacitive load from the center conductor, thereby suppressing any slowing of the propagation speed through the unit cell. In other words, by switching CL, the capacitance per unit length of the segment can be altered, resulting in a tunable propagation speed, which, in the case of a shunt T-line, can be equivalent to a tunable inductor. Compared to conventional CPW or microstrip T-lines, the propagation velocity of such a structure can be higher, resulting in a compact layout.

[0043] Reference again Figure 3B and Figure 4, transmission line elements TL1, TL2, and TL3 can be composed of different numbers of cascaded unit cells to provide the desired response. For example, in one contemplated embodiment, TL1 is a cascade of two unit cells 600, TL2 is a cascade of five unit cells, and TL3 is a cascade of three unit cells. It is expected that these values ​​will vary based on the response of the individual unit cells and the desired response of the matching network.

[0044] Monte Carlo simulations have been performed on the embodiment of Figure 3 to determine the effect of switching one of the phase shifters between two states. 7A to 7B As shown, simulations indicate that both amplitude and phase errors are highly resilient to process variations, favoring correct operation of the variable frequency multiplier. In other words, the design does not depend on any resonances or other effects that may be affected by process variations. When operated well below its 1dB compression point, the simulated HBT switch produces virtually no harmonic distortion.

[0045] The transceiver chip was simulated using a signal generator at the input and a spectrum analyzer at the output to monitor output power up to the fifth harmonic. In this simulation, the doubler's driver consumed 14 mA from a 2.5V supply, and the multiplier core consumed 16 mA from a 1.6V supply. At an input frequency of 11 GHz, the doubler's maximum output power was 5.6 dBm, corresponding to 5.9% efficiency, and the tripler's maximum output power was 3.4 dBm, corresponding to 3.5% efficiency. The doubler achieved over 27 dB of suppression for all harmonics in the input band of interest (10.5-11.5 GHz), and its 3 dB output power bandwidth extended from 19.6 GHz to 25 GHz. From 29.1 GHz to 35.4 GHz, the tripler exhibited over 25 dB of suppression and a 3 dB power bandwidth. The latter's high fundamental suppression likely stems from the driver's frequency response and the explicit high-pass filter preceding the driver.

[0046] The performance of the breakthrough implementation of the driver amplifier was measured using a network analyzer with S-parameter settings. When all switches were switched from "on" to "off" together, the input and output matching and peak gain shifted from 22.4 GHz to 32.5 GHz. Due to the increased losses associated with the switches and MIM capacitors when the FETs were switched "on," the gain in the lower frequency band was only 1 dB higher than in the higher frequency band.

[0047] A network analyzer with S-parameter settings was similarly used to measure the performance of the breakthrough implementation of the phase shifter. The phase shifter showed an insertion loss (IL) of 1.5 dB measured at 40 GHz. In simulations, the IL difference between the 0° / 180° modes was 0.1 dB over the frequency range of 5 GHz to 45 GHz, while the phase imbalance was <2.5°.

[0048] Thus, the above-described embodiments of a frequency doubler-tripler have been disclosed, comprising a K / Ka band single-path frequency doubler-tripler suitable for implementation via a 0.12 μm SiGe BiCMOS process. A compact and broadband 1-bit phase shifter enables switching between even and odd mode operation, and may be followed by an integrated frequency reconfigurable driver that optionally employs a switched capacitor bank to achieve coarse and fine tuning. The designed frequency doubler-tripler may enhance suppression of undesirable harmonics and may serve as a good alternative for broadband frequency synthesis, such as that used for dual-band 5G transceivers. A series of integrated transmission line implementations are known in the literature and may be used to reduce the footprint of the matching network.

[0049] An exemplary dual-mode frequency multiplier embodiment includes: a first nonlinear element and a second nonlinear element, a summing node, and a switchable phase shifter. The first and second nonlinear elements are driven by a differential signal to generate a first branch signal and a second branch signal, each having even harmonics and odd harmonics, the even harmonics being in phase and the odd harmonics being out of phase. The first and second branch signals are combined at the summing node to form a combined signal. The switchable phase shifter couples the first nonlinear element to the summing node, thereby providing a phase shift switchable between 0 and 180 degrees to the first branch signal to suppress odd or even harmonics from the combined signal.

[0050] An exemplary dual-band transceiver embodiment includes a phase-locked loop (PLL), a dual-mode frequency multiplier with a switchable phase shifter, and a mixer. The PLL provides a PLL signal in the 10.5 GHz to 11.5 GHz frequency band. The dual-mode frequency multiplier converts the PLL signal into a local oscillator signal with a frequency twice or three times the PLL signal frequency, depending on whether the switchable phase shifter is set for a 0° or 180° phase shift. The mixer uses the local oscillator signal to up-convert a 6 GHz intermediate frequency transmit signal to a radio frequency transmit signal in the 28 GHz or 39 GHz frequency band.

[0051] An exemplary frequency doubling method includes: driving a first nonlinear element and a second nonlinear element with a differential signal to generate a first branch signal and a second branch signal, each having even harmonics and odd harmonics, wherein the even harmonics are in phase and the odd harmonics are out of phase between the branch signals; coupling the first branch signal to a summing node to form a combined signal with the second branch signal, wherein the coupling is performed by a switchable phase shifter; and switching the switchable phase shifter between 0° and 180° to suppress odd harmonics or even harmonics from the combined signal.

[0052] Each of the foregoing embodiments may be employed alone or in combination, and they may also employ one or more of the following optional features in any appropriate combination: 1. The combined signal is filtered to suppress the frequency band of the differential signal from the combined signal. 2. The switchable phase shifter includes a first portion and a second portion of an integrated transmission line, the first portion and the second portion each having a signal conductor and a return current conductor. 3. The signal conductors of the first portion and the second portion are coupled together and the return current conductors of the first portion and the second portion are coupled together to provide a 0° phase shift. 4. The signal conductor of the first portion is coupled to the return current conductor of the second portion, and the return current conductor of the first portion is coupled to the signal conductor of the second portion to provide a 180° phase shift. 5. The first nonlinear element and the second nonlinear element each include a heterojunction bipolar transistor biased at an exponential portion of a characteristic current-voltage curve. 6. The second mixer uses a local oscillator signal to down-convert an RF receive signal in the 28 GHz or 39 GHz band to a 6 GHz intermediate frequency receive signal. 7. A differential pair of transistors converts the PLL signal into a first branch signal having even harmonics and a second branch signal having odd harmonics, wherein the even harmonics are in phase and the odd harmonics are out of phase between the first branch signal and the second branch signal, and the differential pair of transistors is biased to operate in the exponential portion of its characteristic current-voltage curve. 8. A switchable phase shifter couples the first branch signal to a summing node to form a combined signal with the second branch signal. 9. A first switch pair couples the signal conductors together and the return current conductors together to provide a 0° phase shift. 10. A second switch pair couples the signal conductors of the first section to the return current conductors of the second section, and couples the return current conductors of the first section to the signal conductors of the second section to provide a 180° phase shift. 11. Each of the switch pairs includes a SiGe heterojunction bipolar transistor. 12. The first section and the second section each include a coplanar waveguide. 13. A second switchable phase shifter couples the second nonlinear element to the summing node. 14. One or more transformers couple the first branch signal and the second branch signal to the switchable phase shifter and the second switchable phase shifter, respectively. 15. An input transformer converts a single-ended input signal into the differential signal, which is provided to the base of the heterojunction bipolar transistor along with a bias signal. 16. The frequency multiplier of claim 1, wherein the differential signal comprises a fundamental frequency in the frequency band of 10.5 GHz to 11.5 GHz.

[0053] The foregoing embodiments may omit complicating factors such as parasitic impedances, current limiting resistors, level shifters, clamps, etc., which may be present but do not meaningfully affect the operation of the disclosed circuits. In fact, any suitable form of transistor or integrated circuit switch may be used to implement the transistors described herein as heterojunction bipolar transistors and / or field effect transistors. These and many other modifications, equivalents, and alternatives will become apparent to those skilled in the art once the above disclosure is fully understood. It is intended that the following claims be interpreted as including all such modifications, equivalents, and alternatives where applicable.

Claims

1. A dual-mode frequency multiplier, characterized in that: The dual-mode frequency multiplier comprises: a first nonlinear element and a second nonlinear element, the first nonlinear element and the second nonlinear element being driven by a differential signal to generate a first branch signal and a second branch signal, wherein each of the first branch signal and the second branch signal has even harmonics and odd harmonics, the even harmonics are in phase and the odd harmonics are out of phase between the first branch signal and the second branch signal; a summing node at which the first branch signal and the second branch signal are combined to form a combined signal; and a switchable phase shifter coupling the first nonlinear element to the summing node to provide a phase shift to the first branch signal, the phase shift being switchable to 0° to suppress odd harmonics from the combined signal or to 180° to suppress even harmonics from the combined signal.

2. The dual-mode frequency multiplier according to claim 1, wherein: The switchable phase shifter comprises: a first portion of an integrated transmission line and a second portion of an integrated transmission line, wherein each of the first portion of the integrated transmission line and the second portion of the integrated transmission line has a center conductor and a shield conductor; a first switch pair coupling together a center conductor of the first portion and a center conductor of the second portion and coupling together a shield conductor of the first portion and a shield conductor of the second portion to provide a 0° phase shift; and A second switch pair couples the center conductor of the first section to the shield conductor of the second section and the shield conductor of the first section to the center conductor of the second section to provide a 180° phase shift.

3. The dual-mode frequency multiplier according to claim 2, wherein: The first portion and the second portion each include a coplanar waveguide, and the switch pair each includes a SiGe heterojunction bipolar transistor.

4. The dual-mode frequency multiplier according to any one of claims 1 to 3, characterized in that: The first nonlinear element and the second nonlinear element each comprise a heterojunction bipolar transistor biased at an exponential portion of a characteristic current-voltage curve.

5. The dual-mode frequency multiplier according to claim 4, further characterized in that: The dual-mode frequency multiplier comprises: an input transformer that converts a single-ended input signal into the differential signal, and the differential signal is provided to the base of the heterojunction bipolar transistor together with a bias signal; and a second switchable phase shifter coupling the second nonlinear element to the summing node, One or more transformers couple the first branch signal to the switchable phase shifter and couple the second branch signal to the second switchable phase shifter, respectively.

6. A frequency doubling method, characterized in that: The method comprises: driving a first nonlinear element and a second nonlinear element with a differential signal to generate a first branch signal and a second branch signal each having even harmonics and odd harmonics, wherein the even harmonics are in phase and the odd harmonics are out of phase between the branch signals; coupling the first branch signal to a summing node to form a combined signal with the second branch signal, the coupling being performed via a switchable phase shifter; and The switchable phase shifter is switched to 0° to suppress odd harmonics from the combined signal or to 180° to suppress even harmonics from the combined signal.

7. The frequency doubling method according to claim 6, wherein: The switchable phase shifter comprises a first portion of an integrated transmission line and a second portion of an integrated transmission line, wherein each of the first portion of the integrated transmission line and the second portion of the integrated transmission line has a center conductor and a shield conductor, and wherein the switching comprises: coupling together the center conductor of the first section and the center conductor of the second section and coupling together the shielded conductor of the first section and the shielded conductor of the second section to provide a 0° phase shift; and The center conductor of the first section is coupled to the shield conductor of the second section and the shield conductor of the first section is coupled to the center conductor of the second section to provide a 180° phase shift.

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