Display driver and method of driving the same

Abstract

The present invention relates to a display driver and a method for driving the display driver. The display driver comprises: a segmented pull-up current source circuit comprising a first plurality of transistors; a segmented pull-down current source circuit comprising a second plurality of transistors; a comparator circuit configured to compare an output voltage level at an output of the display driver with a target voltage level and generate a comparator output at one of two output terminals of the comparator circuit, wherein the segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to the two output terminals of the comparator circuit via one or more multiplexers, a first plurality of AND gate circuits, and a second plurality of AND gate circuits; and a logic circuit connected to at least one output terminal of the comparator circuit and configured to control the operation of the segmented pull-up current source circuit and the segmented pull-down current source circuit based on the comparator output.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 62 / 784,337, filed on December 21, 2018, and entitled “HIGH-EFFICIENCY PIECE-WISE LINEAR COLUMN-DRIVERS WITH ASYNCHRONOUS CONTROL FOR DISPLAYS,” the entire contents of which are expressly incorporated herein by reference. Technical Field

[0003] One or more aspects of embodiments according to the present invention relate to a display driver, for example, a system and method for a high-efficiency piecewise linear column driver using asynchronous control for a display. Background Art

[0004] Display devices such as organic light emitting diode (OLED) displays and liquid crystal displays (LCD) include a plurality of pixels at intersections defined by a plurality of scan lines extending in a row direction and a plurality of data lines extending in a column direction. A scan driver sequentially applies scan signals to the scan lines and a data driver supplies data signals to the plurality of data lines to write data to control the pixels to display an image.

[0005] The data driver may include one or more digital-to-analog converters (DACs) for converting digital signals into analog signals, and one or more amplifier stages for amplifying the analog data signals and supplying the amplified analog signals to the data lines.

[0006] The above information in the Background section is only for enhancement of understanding of the background of the technology and therefore it should not be construed as an admission of the existence or relevance of prior art. Summary of the invention

[0007] This summary is provided to introduce a selection of features and concepts of embodiments of the present disclosure that are further described in the detailed description below. This summary is not intended to identify key or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. One or more of the described features can be combined with one or more other described features to provide a viable device.

[0008] Aspects of example embodiments of the present disclosure relate to a system and method for a high efficiency piecewise linear column driver for a display with asynchronous control.

[0009] In some embodiments, a display driver includes: a segmented pull-up current source circuit, the segmented pull-up current source circuit being configured to supply a pull-up current to a load connected to an output of the display driver, wherein the segmented pull-up current source circuit includes: a first plurality of transistors including m groups of transistors, wherein each group of transistors in the m groups of the first plurality of transistors includes a p-type metal oxide semiconductor field effect transistor MOSFET and an n-type MOSFET connected in series with each other; a segmented pull-down current source circuit, the segmented pull-down current source circuit being configured to supply a pull-down current to a load connected to the output of the display driver, wherein the segmented pull-down current source circuit includes: a second plurality of transistors including m groups of transistors, wherein each group of transistors in the m groups of the second plurality of transistors includes two n-type MOSFET, wherein the segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to each other via a first plurality of AND gate circuits and a second plurality of AND gate circuits; a comparator circuit configured to compare an output voltage level at an output of a display driver with a target voltage level and generate a comparator output at one of two output terminals of the comparator circuit, wherein the segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to the two output terminals of the comparator circuit via one or more multiplexers, a first plurality of AND gate circuits and a second plurality of AND gate circuits; and a logic circuit connected to at least one output terminal of the comparator circuit and configured to control the operation of the segmented pull-up current source circuit and the segmented pull-down current source circuit based on the comparator output, wherein m is a positive integer.

[0010] In some embodiments, the display driver is a column driver for an organic light emitting diode (OLED) display, and wherein the load connected to the output of the display driver is an OLED. In some embodiments, in each of the m groups of transistors in the first plurality of transistors, the source terminal of the p-type MOSFET is connected to a power supply voltage, the drain terminal of the p-type MOSFET is connected to the drain terminal of the n-type MOSFET, and the gate terminal of the p-type MOSFET is connected to a bias voltage. In some embodiments, in the m groups of transistors in the first plurality of transistors, the source terminals of the n-type MOSFETs are connected to each other and to the output of the display driver, and the gate terminal of the n-type MOSFET is connected to the output terminal of a corresponding AND gate circuit in the first plurality of AND gate circuits including m individual AND gate circuits.

[0011] In some embodiments, in the m groups of transistors of the second plurality of transistors, drain terminals of the first n-type MOSFET are connected to each other and to the output of the display driver, and wherein the gate terminal of the first n-type MOSFET is connected to the output terminal of a corresponding AND gate circuit of the second plurality of AND gate circuits including m individual AND gate circuits. In some embodiments, in each of the m groups of transistors of the second plurality of transistors, the source terminal of the first n-type MOSFET is connected to the drain terminal of the second n-type MOSFET, the source terminal of the second n-type MOSFET is grounded, and the gate terminal of the second n-type MOSFET is connected to a bias voltage.

[0012] In some embodiments, the comparator circuit is an operational amplifier. In some embodiments, the logic circuit is an n-bit shift register, which includes n individual shift registers configured to turn on or off one or more transistor groups in the first plurality of transistors or the second plurality of transistors based on the comparator output, wherein n is a positive integer. In some embodiments, the first output terminal of each of the n individual shift registers is connected to the input terminal of the next shift register of the n individual shift registers via a multiplexer in n-1 multiplexers. In some embodiments, the logic circuit is used to determine the amplitude of the difference between the new pixel grayscale and the old pixel grayscale. In some embodiments, the logic circuit is connected to at least one output terminal of the comparator circuit via a pulse generator configured to generate a pulse at each transition of the comparator output, wherein the pulse generator is an exclusive OR gate circuit.

[0013] In some embodiments, a display driver includes: a segmented pull-up current source circuit, which is configured to supply a pull-up current to a load connected to the output of the display driver; a segmented pull-down current source circuit, which is configured to supply a pull-down current to a load connected to the output of the display driver; a comparator circuit, which is configured to compare an output voltage level at the output of the display driver with a target voltage level and generate a comparator output at one of two output terminals of the comparator circuit; and a logic circuit, which is connected to at least one output terminal of the comparator circuit and is configured to control the operation of the segmented pull-up current source circuit and the segmented pull-down current source circuit based on the comparator output.

[0014] In some embodiments, a segmented pull-up current source circuit comprises: a first plurality of transistors including m groups of transistors, wherein each group of transistors in the m groups of transistors of the first plurality of transistors comprises a p-type metal oxide semiconductor field effect transistor MOSFET and an n-type MOSFET connected in series with each other; a segmented pull-down current source circuit comprises: a second plurality of transistors including m groups of transistors, wherein each group of transistors in the m groups of transistors of the second plurality of transistors comprises two n-type MOSFETs connected in series with each other, wherein the segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to each other via a first plurality of AND gate circuits and a second plurality of AND gate circuits; and the segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to two output terminals of a comparator circuit via one or more multiplexers, a first plurality of AND gate circuits, and a second plurality of AND gate circuits, wherein m is a positive integer.

[0015] In some embodiments, the display driver is a column driver for an organic light emitting diode (OLED) display, and wherein the load connected to the output of the display driver is an OLED. In some embodiments, in each of the m groups of transistors in the first plurality of transistors, the source terminal of the p-type MOSFET is connected to a power supply voltage, the drain terminal of the p-type MOSFET is connected to the drain terminal of the n-type MOSFET, and the gate terminal of the p-type MOSFET is connected to a bias voltage. In some embodiments, in the m groups of transistors in the first plurality of transistors, the source terminals of the n-type MOSFETs are connected to each other and to the output of the display driver, and the gate terminal of the n-type MOSFET is connected to the output terminal of a corresponding AND gate circuit in the first plurality of AND gate circuits including m individual AND gate circuits.

[0016] In some embodiments, in m groups of transistors in the second plurality of transistors, drain terminals of the first n-type MOSFET are connected to each other and to the output of the display driver, wherein the gate terminal of the first n-type MOSFET is connected to the output terminal of a corresponding AND gate circuit in a second plurality of AND gate circuits including m separate AND gate circuits, and wherein, in each group of m groups of transistors in the second plurality of transistors, the source terminal of the first n-type MOSFET is connected to the drain terminal of the second n-type MOSFET, the source terminal of the second n-type MOSFET is grounded, and the gate terminal of the second n-type MOSFET is connected to a bias voltage.

[0017] In some embodiments, the logic circuit is an n-bit shift register, which includes n separate shift registers configured to turn on or off one or more transistor groups in the first plurality of transistors or the second plurality of transistors based on the comparator output, wherein a first output terminal of each of the n separate shift registers is connected to an input terminal of a next shift register of the n separate shift registers via a multiplexer in n-1 multiplexers, wherein the logic circuit is used to determine the magnitude of the difference between the new pixel gray level and the old pixel gray level, and wherein n is a positive integer.

[0018] In some embodiments, a method of driving a display driver includes: a segmented pull-up current source circuit, the segmented pull-up current source circuit being configured to supply a pull-up current to a load connected to an output of the display driver, wherein the segmented pull-up current source circuit includes: a first plurality of transistors including m groups of transistors, wherein each of the m groups of transistors of the first plurality of transistors includes a p-type metal oxide semiconductor field effect transistor MOSFET and an n-type MOSFET connected in series with each other; a segmented pull-down current source circuit, the segmented pull-down current source circuit being configured to supply a pull-down current to a load connected to the output of the display driver, wherein the segmented pull-down current source circuit includes: a second plurality of transistors including m groups of transistors, wherein each of the m groups of transistors of the second plurality of transistors includes two n-type MOSFETs connected in series with each other, wherein the segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to each other via a first plurality of AND gate circuits and a second plurality of AND gate circuits; a comparator circuit, the comparator The circuit is configured to compare the output voltage level at the output of the display driver with the target voltage level and generate a comparator output at one of the two output terminals of the comparator circuit, wherein a segmented pull-up current source circuit and a segmented pull-down current source circuit are connected to the two output terminals of the comparator circuit via one or more multiplexers, a first plurality of AND gates and a second plurality of AND gates; and a logic circuit, which is connected to at least one output terminal of the comparator circuit and is configured to control the operation of the segmented pull-up current source circuit and the segmented pull-down current source circuit based on the comparator output; the method includes: turning on a first plurality of transistors including m groups of transistors based on receiving a start pulse from a pulse generator at an input terminal of the logic circuit; comparing the output voltage level at the output of the display driver with the target voltage level at the comparator circuit to generate a comparator output; and turning on or off one or more transistor groups in the first plurality of transistors or the second plurality of transistors based on the comparator output, wherein m is a positive integer. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] These and other features of some example embodiments of the invention will be known and understood with reference to the specification, claims and drawings, in which:

[0020] Figure 1 is a block diagram of a display device according to some embodiments of the present disclosure;

[0021] Figure 2 is a block diagram of a data driver according to some embodiments of the present disclosure;

[0022] Figure 3 Figure 2 shows the display column driver architecture of the related art;

[0023] Figure 4 Graphics Figure 3 Related art Direct fast feedback current (DFFC) driver, pixel circuit and control signal of display column driver architecture;

[0024] Figure 5 A block diagram (part) of a related art odd column voltage driver for an OLED display is shown;

[0025] Figure 6 A block diagram of a related art type B buffer is shown;

[0026] Figure 7 illustrates an example embodiment of a display driver according to some embodiments of the present disclosure;

[0027] Figure 8 The diagrams illustrate some embodiments of the present disclosure. Figure 7 An example timing diagram for a display driver of FIG. 10 ; and

[0028] Fig. 9 An example circuit including a logic circuit and an n-bit shift register according to some embodiments of the present disclosure is illustrated. DETAILED DESCRIPTION

[0029] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of some example embodiments of systems and methods for high-efficiency segmented linear column drivers for displays using asynchronous control provided by the present invention, and is not intended to represent the only forms in which the present invention may be constructed or utilized. The description sets forth features of the present invention in conjunction with the illustrated embodiments. However, it is to be understood that the same or equivalent functions and structures may be implemented by different embodiments that are also intended to be included within the scope of the present invention. As indicated elsewhere herein, the same reference numerals are intended to represent the same elements or features.

[0030] Figure 1 is a block diagram of a display device according to some embodiments of the present disclosure. Figure 1, the display device includes a display unit 100 , a scan driver 200 and a data driver 300 connected to the display unit 100 , and a signal controller 400 for controlling the scan driver 200 and the data driver 300 .

[0031] In an exemplary embodiment, the display unit 100 includes a plurality of display signal lines S1-Sn, D1-Dm and a plurality of pixels PX connected to the plurality of display signal lines S1-Sn, D1-Dm and arranged substantially in a matrix form.

[0032] The display signal lines S1-Sn, D1-Dm include a plurality of scan lines S1-Sn for transmitting scan signals (also referred to as gate signals) and data lines D1-Dm for transmitting data signals. The scan lines S1-Sn extend in a row direction and are substantially parallel to each other, and the data lines D1-Dm extend in a column direction and are substantially parallel to each other. The pixel PX is located at the intersection of the scan lines S1-Sn and the data lines D1-Dm.

[0033] The scan driver 200 is connected to the scan lines S1-Sn and applies scan signals formed by combining a gate-on voltage and a gate-off voltage to the scan lines S1-Sn. The gate-on voltage represents a voltage applied to the gate of a transistor to turn on the transistor, and the gate-off voltage represents a voltage applied to the gate of the transistor to turn it off.

[0034] The data driver 300 is connected to the data lines D1 -Dm, generates a data signal representing a grayscale value of the pixel PX, and applies it to the data lines D1 -Dm.

[0035] The signal controller 400 controls the scan driver 200 and the data driver 300. For example, the signal controller 400 supplies data (e.g., digital data) to the data driver 300, and may also supply synchronization signals (VSYNC and HSYNC) to the scan driver 200 and / or the data driver 300 to synchronize the writing of data to the pixel PX with the scan signal, thereby setting the pixel PX to a writable state. The data supplied to the data driver 300 may be digital data representing the brightness or grayscale of light to be emitted by the pixel (e.g., where the data to be supplied to each data line is encoded as an 8-bit value).

[0036] Each pixel PX may include a transistor including a gate electrode connected to a scan line, a source electrode connected to a corresponding one of the data lines (e.g., a data line corresponding to the column where the pixel is located), and a drain electrode. The transistor transmits a data signal provided by the data line in response to a gate-on voltage provided by the scan line, and the data signal controls the grayscale of light emitted by the pixel. When the display device is a liquid crystal display (LCD), the light emitting region may include a capacitor for storing a data signal, and the liquid crystal layer may control the brightness level of light emitted according to the data signal stored in the capacitor. When the display device is an organic light emitting device (e.g., an active organic light emitting device), the light emitting region may include a capacitor for storing a data signal, a driving transistor for transmitting a current according to the data signal stored in the capacitor, and an organic light emitting diode (OLED) for emitting light having a grayscale according to the current provided by the driving transistor.

[0037] The drivers 200, 300 and the controller 400 may be mounted on the display unit 100 as at least one integrated circuit chip, respectively, may be mounted on a flexible printed circuit film (not shown) and attached to the display unit 100 as a tape carrier package (TCP), or may be mounted on an additional printed circuit board (not shown). Alternatively, the drivers 200, 300 and the controller 400 may be integrated with the display unit 100 together with the display signal lines S1-Sn, D1-Dm and the transistors. In addition, the drivers 200, 300 and the controller 400 may be integrated into a single chip, and in this case, at least one of them or at least one circuit element forming them may be provided outside the single chip.

[0038] Figure 2 is a block diagram of a data driver 300 according to some embodiments of the present disclosure. Figure 2 , the signal controller 400 is coupled to the data driver 300 to supply the digital data signal DATA to the digital demultiplexer 310. The digital demultiplexer 310 demultiplexes the digital data to generate m separate digital data signals, one digital data signal for each column of the display unit 100. The m digital data signals are supplied to the digital-to-analog converter 32, which is configured to output the analog data signals to an amplifier or column driver stage 35 including an amplifier or column driver 350. The amplifier or column driver 350 amplifies the analog signal to the operating voltage and current specifications of the pixel and outputs the amplified signal to the data lines D1-Dm.

[0039] Either the current drive scheme or the voltage drive scheme can be used for amplitude modulation (e.g., pulse amplitude modulation (PAM)) in an OLED display. The current drive method can improve the brightness uniformity at the OLED display panel and can provide compensation for the thin film transistor (TFT) characteristics at the pixel. However, with the current drive method, when the parasitic capacitance of the data line increases, the driving speed is greatly reduced. In some example embodiments, the current feedback drive method accurately transmits the data current to the pixel and compares the data with the pixel current. However, the feedback operation in which the pixel current is detected may cause a time delay to charge and discharge the parasitic capacitance of the feedback path using the pixel or data current.

[0040] Figure 3 and Figure 4 A related art DFFC driver is shown that provides a fast settling time with accuracy by directly comparing data to pixel current.

[0041] Figure 3 The display column driver architecture and OLED pixel of the related art current driving method are shown. Figure 3 The digital-to-analog converter (DAC) in the Figure 2 DAC 32. Figure 3 The DFFC driver forms a feedback loop with the pixel circuit through the data line and the feedback line, and transmits the output current of the DAC to the pixel.

[0042] Figure 4 Graphics Figure 3 The DFFC driver, pixel circuit and control signal of the related art display column driver architecture. In some example embodiments, during the programming period, the DFFC driver and pixel circuit are composed of a feedback loop with the OLED turned off. DATA and the pixel current I at node X PIXEL The comparison is made and the error between the two currents is integrated and compensated for by taking into account the total feedback loop. The driving speed can be improved by reducing the effect of parasitic capacitance. Because the amplifier A1 has a low output impedance, the parasitic capacitance C in the data line is reduced. PD The effect of this, and therefore the error signal at the differential input, can quickly change C PD Because the voltage of the feedback line is passed through amplifier A2 and transistor M D1 The sub-loop remains constant, so the parasitic capacitance C is suppressed PF The feedback loop is stabilized by the dominant pole at node X. In some example embodiments, because transistor M P1 The conductance of the circuit changes depending on the current, so the characteristics of the circuit change with I DATATherefore, the compensation capacitor C can also be adaptively changed. C .

[0043] although Figure 4 The DFFC provides fast settling time with good accuracy, but regarding Figure 3 to Figure 4 For circuits with different output current ranges, area overhead may be an issue because different compensation capacitors C C In addition, regarding Figure 3 to Figure 4 For circuits with this design, power overhead can be an issue because, in addition to the current used to charge the outputs (display columns), Figure 4 The operational amplifiers A1 and A2 in the circuit consume quiescent current.

[0044] Typical voltage-mode drivers for displays (eg, OLED displays) use a class B or class AB architecture. In some embodiments of a voltage-mode driver for a display, a single amplifier draws a relatively low quiescent current (eg, on the order of a few μA).

[0045] Figure 5 A block diagram (part) of a related art odd-column voltage driver for an OLED display is shown. Figure 5 The voltage driver includes a 10-bit VDAC (i.e., voltage DAC) and a current sensing resistor R S1 and R S2 Class AB buffer amplifier. S1 can sense the source current, and R S2 The push current can be sensed. In some embodiments, Figure 5 One or more bias current sources in the voltage driver may source or sink a constant current (I BIAS ) to ensure room for noise current swing.

[0046] Figure 6 The block diagram of a related art class B buffer is shown, which includes: an input rail-to-rail differential amplifier including two current comparators C1 and C2, output complementary devices MO1 and MO2, and a series resistor RC that provides phase compensation. Because the two current comparators are freely incorporated into the input differential stage, Figure 6 The Class B buffer amplifier provides an improvement in power efficiency.

[0047] Although voltage-mode drivers for displays (e.g., OLED displays) draw relatively low quiescent current (e.g., on the order of a few μA), in some embodiments, the quiescent current consumption can be significant in relatively large (e.g., on the order of 2000 column drivers combined) displays. Furthermore, in some embodiments, voltage-mode drivers for displays can cause large current spikes during setup (e.g., charging or discharging display columns), and there is no control mechanism for the current spikes during setup (e.g., on the order of 2000 column drivers switching simultaneously).

[0048] Therefore, a display driver with high power efficiency and reduced dynamic current spikes is needed. Example embodiments of the present disclosure provide a display driver with both high power efficiency and programmable dynamic current spikes. For example, in the proposed display driver, because all current drawn by the display driver is used to charge or discharge the column line, energy waste due to static current can be completely eliminated. In the example display driver, the dynamic current spike can be controlled by using a set of current sources. Unlike class B or class AB amplifiers, this limits the peak current drawn from the power supply. For example, because the slower the display driver, the larger the horizontal line time and therefore the larger the time available for the line voltage to converge to the final value, the display driver speed can be weighed for the reduced current spike. The dynamic current spike can also be controlled in the display driver by reducing the initial charging current if the previous gray level (i.e., the column line voltage) is close to the current gray level. Moreover, in order to avoid additional clock distribution networks, the example display driver can use asynchronous signaling between the various stages, because the integrated chip (IC) in the display driver can be quite large and the additional clock distribution power may be significant in the driver IC.

[0049] Figure 7 An example embodiment of a display driver 700 is illustrated. In some example embodiments, the display driver 700 may be a column driver (eg, column driver 350). Figure 7 The display driver 700 includes a comparator 701, a pulse generator 702, a plurality of multiplexers 703a, 703b and 703c, and an n-bit shift register 704 including n individual shift registers 704a, 704b, 704c, 704d, ..., 704n. The comparator 701 may be an operational amplifier (op-amp), and the pulse generator 702 may be an exclusive OR gate circuit. Figure 7 The display driver 700 also includes: a first plurality of AND gate circuits including m individual AND gate circuits 705a1, 705b1, 705c1, ..., 705m1 and a second plurality of AND gate circuits including m individual AND gate circuits 705a2, 705b2, 705c2, ..., 705m2. Figure 7In the example embodiment of , n and m may be positive integers, and n is different from m.

[0050] Figure 7 The display driver 700 also includes: a first plurality of transistors (e.g., pull-up transistors) including m groups of transistors 707a1, 707b1, 707c1, ..., 707m1. The first plurality of transistors 707a1, 707b1, 707c1, ..., 707m1 may be referred to as a segmented pull-up current source. Each of the transistor groups 707a1, 707b1, 707c1, ..., 707m1 may be referred to as a pull-up transistor group or a pull-up current branch. The first plurality of transistors 707a1, 707b1, 707c1, ..., 707m1 may be configured to supply a pull-up current to a load (e.g., an OLED) connected to an output 708 of the display driver 700. Each of the m groups of transistors 707a1, 707b1, 707c1, ..., 707m1 includes a p-type metal oxide semiconductor field effect transistor (MOSFET) and an n-type MOSFET connected in series with each other. For example, in each of the transistor groups 707a1, 707b1, 707c1, ..., 707m1, the source terminal of the p-type MOSFET is connected to the power supply voltage VDD, and the gate terminal of the p-type MOSFET is connected to the bias voltage Vbiasp. The p-type MOSFET in each of the transistor groups 707a1, 707b1, 707c1, ..., 707m1 can be used as a current source.

[0051] In each of transistor groups 707a1, 707b1, 707c1, ..., 707m1, the drain terminal of the p-type MOSFET is connected to the drain terminal of the n-type MOSFET. In addition, the source terminals of the n-type MOSFETs in each of transistor groups 707a1, 707b1, 707c1, ..., 707m1 are connected to each other and to the output 708 of the display driver 700. As such, each of transistor groups 707a1, 707b1, 707c1, ..., 707m1 can be referred to as a pull-up transistor group or a pull-up current branch. The n-type MOSFETs in each of transistor groups 707a1, 707b1, 707c1, ..., 707m1 are simply switches for enabling or disabling the particular current branch (e.g., 707a1, 707b1, 707c1, ..., 707m1). The gate terminal of each of the n-type MOSFETs in each of the transistor groups 707a1, 707b1, 707c1, ..., 707m1 is connected to the output terminal of a corresponding one of the first plurality of AND gate circuits 705a1, 705b1, 705c1, ..., 705m1. For example, the gate terminal of the n-type MOSFET of the transistor group 707a1 is connected to the output terminal of the AND gate circuit 705a1, the gate terminal of the n-type MOSFET of the transistor group 707b1 is connected to the output terminal of the AND gate circuit 705b1, the gate terminal of the n-type MOSFET of the transistor group 707c1 is connected to the output terminal of the AND gate circuit 705c1, etc.

[0052] The display driver 700 further includes: a second plurality of transistors (e.g., pull-down transistors) including m groups of transistors 707a2, 707b2, 707c2, ..., 707m2. The second plurality of transistors 707a2, 707b2, 707c2, ..., 707m2 may be referred to as segmented pull-down current sources. Each group of transistors 707a2, 707b2, 707c2, ..., 707m2 may be referred to as a pull-down transistor group or a pull-down current branch. The second plurality of transistors 707a2, 707b2, 707c2, ..., 707m2 may be configured to supply a pull-down current to a load (e.g., an OLED) connected to an output 708 of the display driver 700. Each group of transistors in the m groups of transistors 707a2, 707b2, 707c2, ..., 707m2 includes two n-type MOSFETs connected in series to each other. For example, drain terminals of the first n-type MOSFETs (eg, 707a2n1, 707b2n1, 707c2n1, . . . , 707m2n1) of each of transistor groups 707a2, 707b2, 707c2, . . . , 707m2 are connected to each other and to the output 708 of the display driver 700.

[0053] The gate terminal of each of the first n-type MOSFETs (e.g., 707a2n1, 707b2n1, 707c2n1, ..., 707m2n1) in each of the transistor groups 707a2, 707b2, 707c2, ..., 707m2 is connected to the output terminal of a corresponding one of the second plurality of AND gate circuits 705a2, 705b2, 705c2, ..., 705m2. For example, the gate terminal of the first n-type MOSFET 707a2n1 of the transistor group 702a2 is connected to the output terminal of the AND gate circuit 705a2, the gate terminal of the first n-type MOSFET 707b2n1 of the transistor group 707b2 is connected to the output terminal of the AND gate circuit 705b2, the gate terminal of the first n-type MOSFET 707c2n1 of the transistor group 707c2 is connected to the output terminal of the AND gate circuit 705c2, and so on.

[0054] In each of the transistor groups 707a2, 707b2, 707c2, ..., 707m2, the source terminal of a first n-type MOSFET (e.g., 707a2n1, 707b2n1, 707c2n1, ..., 707m2n1) is connected to the drain terminal of a second n-type MOSFET (e.g., 707a2n2, 707b2n2, 707c2n2, ..., 707m2n2) in the transistor group. For example, in the transistor group 707a2, the source terminal of the first n-type MOSFET 707a2n1 is connected to the drain terminal of the second n-type MOSFET 707a2n2. In each of the transistor groups 707a2, 707b2, 707c2, ..., 707m2, the source terminal of the second n-type MOSFET (e.g., 707a2n2, 707b2n2, 707c2n2, ..., 707m2n2) is grounded and the gate terminal of the second n-type MOSFET (e.g., 707a2n2, 707b2n2, 707c2n2, ..., 707m2n2) is connected to the bias voltage Vbiasn. Transistors 707a2n2, 707b2n2, 707c2n2, ..., 707m2n2 (with gates connected to Vbiasn) are current sources, and each of transistors 707a2n1, 707b2n1, 707c2n1, ..., 707m2n1 is simply a switch for enabling or disabling that particular current source branch (e.g., 707a2, 707b2, 707c2, ..., 707m2).

[0055] The comparator 701 compares the voltage Vout at the output 708 of the display driver 700 with a reference voltage Vdata. The reference voltage Vdata may be a voltage at which the display driver 700 preferably (or expects) output voltage Vout is located. If the comparison voltage at the comparator 701 is a negative voltage or if the comparator 701 determines that the voltage Vout is less than the reference voltage Vdata, a first output 701a of the comparator 701 connected to a first input of a 2-to-1 multiplexer 703a is turned on. A second input of the 2-to-1 multiplexer 703a is grounded. An output terminal 703a2 of the 2-to-1 multiplexer 703a is connected to a first input terminal (e.g., in1) of each of the first plurality of AND gate circuits 705a1, 705b1, 705c1, ..., 705m1.

[0056] However, if the comparator 701 determines that the voltage Vout is greater than the reference voltage Vdata, the second output 701b of the comparator 701 connected to the first input of the 2-to-1 multiplexer 703b is turned on. The second input of the 2-to-1 multiplexer 703b is grounded. The output terminal 703b2 of the 2-to-1 multiplexer 703b is connected to the first input terminal (e.g., in1) of each of the second plurality of AND gate circuits 705a2, 705b2, 705c2, ..., 705m2. The selector pin or the enable pin of the 2-to-1 multiplexer 703b is connected to the selector pin or the enable pin of the 2-to-1 multiplexer 703a.

[0057] The second output terminal 701b of the comparator 701 is also connected to the pulse generator 702. The pulse generator 702 receives the second output 701b of the comparator 701 at the first input terminal 702a1 of the pulse generator 702 via the delay circuit 709, and the pulse generator 702 directly receives the second output 701b of the comparator 701 at the second input terminal 702a2 of the pulse generator 702. The pulse generator 702 generates a pulse at each output transition at the comparator 701 output (e.g., 701a, 701b). For example, the pulse generator 702 generates a pulse each time the comparator 701 output changes from a positive voltage to a negative voltage or from a negative voltage to a positive voltage. The pulse generator 702 output is connected to the first input of the 2-to-1 multiplexer 703c. The second input of the 2-to-1 multiplexer 703c is grounded. The output terminal 703c2 of the 2-to-1 multiplexer 703c is connected to the clock terminal of each of the individual shift registers 704a, 704b, 704c, 704d, ..., 704n of the n-bit shift register 704. Therefore, the n-bit shift register 704 is clocked by the pulse generator 702 output to turn on or off a desired number of pull-up transistor groups 707a1, 707b1, 707c1, ..., 707m1 or pull-down transistor groups 707a2, 707b2, 707c2, ..., 707m2, so as to make the output voltage Vout at the output 708 of the display driver 700 closer to the desired voltage value of the reference voltage Vdata.

[0058] The first output terminal (e.g., q) of each of the individual shift registers 704a, 704b, 704c, 704d, ..., 704n of the n-bit shift register 704 is connected to the input terminal (e.g., d) of the next shift register of the shift registers 704a, 704b, 704c, 704d, ..., 704n. For example, the first output terminal (e.g., q) of the shift register 704a is connected to the input terminal (e.g., d) of the next shift register 704b, the first output terminal (e.g., q) of the shift register 704b is connected to the input terminal (e.g., d) of the next shift register 704c, the first output terminal (e.g., q) of the shift register 704c is connected to the input terminal (e.g., d) of the next shift register 704d, and so on. The first output terminal (e.g., q) of the shift register 704a is also connected to the clock terminal of the shift register 706. The output terminal (e.g., q) of the shift register 706 is connected to the selector pin or the start pin of the multiplexer 703c.

[0059] A second output terminal (e.g., qb) of each of the individual shift registers 704b, 704c, 704d, ..., 704n of the n-bit shift register 704 is connected to a second input terminal (e.g., in2) of a corresponding AND gate circuit among the first plurality of AND gate circuits 705a1, 705b1, 705c1, ..., 705m1 and the second plurality of AND gate circuits 705a2, 705b2, 705c2, ..., 705m2. For example, the second output terminal (e.g., qb) of shift register 704b is connected to the second input terminal (e.g., in2) of AND gate circuits 705a1 and 705a2, the second output terminal (e.g., qb) of shift register 704c is connected to the second input terminal (e.g., in2) of AND gate circuits 705b1 and 705b2, the second output terminal (e.g., qb) of shift register 704d is connected to the second input terminal (e.g., in2) of AND gate circuits 705c1 and 705c2, and the second output terminal (e.g., qb) of shift register 704n is connected to the second input terminal (e.g., in2) of AND gate circuits 705m1 and 705m2.

[0060] Figure 8 Graphics Figure 7 707m1 are turned on, and thus a first positive slope Vout1 of the output voltage Vout is generated at the output terminal 708. The start signal triggers the start of the column drive. When the display driver 700 is started or at the beginning of the start pulse, a shift pulse (e.g., from the pulse generator 702) is generated. Because all pull-up current branches 707a1, 707b1, 707c1, ..., 707m1 are turned on, the output voltage Vout may overshoot to exceed the reference voltage Vdata. At this point, the current at the output may be Itot=(I msb +I msb-1 +I msb-2 +...+I lsb ). The startup current Itot is the sum of the currents in all the pull-up current branches 707a1, 707b1, 707c1, ..., 707m1.

[0061] Once the output voltage Vout overshoots the reference voltage Vdata at x1, the comparator 701 compares the output voltage Vout at the output 708 of the display driver 700 with the reference voltage Vdata, and due to the overshoot, the comparator 701 determines that the output voltage Vout is greater than the reference voltage Vdata. Based on the comparison voltage at the comparator 701, some of the plurality of pull-down current branches 707a2, 707b2, 707c2, ..., 707m2 from the pull-down current branches are turned on, which can cause the output voltage Vout to be pulled down, and thus generate a first negative slope Vout2 of the output voltage Vout. As such, as the enable signal propagates through the shift registers 704a, 704b, 704c, 704d, ..., 704n, the pull-up (e.g., pull-up current branches 707a1, 707b1, 707c1, ..., 707m1) or pull-down (e.g., pull-down current branches 707a2, 707b2, 707c2, ..., 707m2) current branches are sequentially turned off. At any given moment, only one of the two groups of current branches (e.g., pull-up current branches 707a1, 707b1, 707c1, ..., 707m1 or pull-down current branches 707a2, 707b2, 707c2, ..., 707m2) is conductive. The final error (e.g., after point x3 during Vout4) or the difference between the reference voltage Vdata and the output voltage Vout is the smallest current branch (e.g., the current branch with current I lsb 707m1 or 707m2) and the delay of the comparator 701. At x1, x2, or x3, because the output voltage Vout changes from having a positive slope (during Vout1) to a negative slope or from having a negative slope to a positive slope, a shift pulse (e.g., from the pulse generator 702) is generated. In some example embodiments, a shift pulse is generated at each output transition at the comparator 701 output (e.g., 701a, 701b).

[0062] Fig. 9 An example circuit 900 is shown including a logic circuit 902 and an n-bit shift register 904. In some example embodiments, Figure 7 The n-bit shift register 704 can be replaced by Fig. 9 The n-bit shift register 904, and Figure 7 The shift register 706 can be replaced by Fig. 9Logic circuit 902. The n-bit shift register 904 includes n individual shift registers 904a, 904b, 904c, 904d, ..., 904n. The n-bit shift register 904 is clocked by a shift pulse generated from a pulse generator (e.g., 702). The first output terminal (e.g., q) of each of the n individual shift registers 904a, 904b, 904c, 904d, ..., 904n of the n-bit shift register 904 is connected to the input terminal (e.g., d) of the next shift register of the shift register 904a, 904b, 904c, 904d, ..., 904n via a multiplexer in n-1 (e.g., multiple) multiplexers 906a, 906b, 906c, 906d, ..., 906(n-1). For example, the first output terminal (e.g., q) of the shift register 904a is connected to the first input terminal of the multiplexer 906a and the output terminal of the multiplexer 906a is connected to the input terminal (e.g., d) of the next shift register 904b, the first output terminal (e.g., q) of the shift register 904b is connected to the first input terminal of the multiplexer 906b and the output terminal of the multiplexer 906b is connected to the input terminal (e.g., d) of the next shift register 904c, the first output terminal (e.g., q) of the shift register 904c is connected to the first input terminal of the multiplexer 906c and the output terminal of the multiplexer 906c is connected to the input terminal (e.g., d) of the next shift register 904d, etc. The second input terminal of each of the n-1 multiplexers 906a, 906b, 906c, 906d, ..., 906(n-1) is connected to each other and to the input terminal (e.g., d) of the shift register 904a.

[0063] Logic circuit 902 is used to determine the magnitude of the difference between the new pixel grayscale and the old pixel grayscale, because the smaller difference in the pixel grayscale can allow an increased charging time and therefore a smaller startup current for the display driver (e.g., 700). The new grayscale is the same value that will reach the traditional driver. It comes from the controller (not shown in any figure). The "old" value will simply be a register (not shown) that stores the value for the next write operation. The n-bit hot control bus 908 is used to inject a start signal at the required shift register (e.g., 904a, 904b, 904c, 904d, ..., 904n) position. When approximately 2000 column line drivers are turned on, the example circuit 900 of the shift register 904 with logic circuit 902 reduces the initial current spike. Moreover, the hot control bus 908 can also be configured to use a lower startup current Itot based on the display type, for example, an increased line time can allow a larger charging time and therefore a smaller startup current Itot.

[0064] Compared to column drivers currently available on the market, the disclosed example embodiments of display drivers (e.g., 700) with shift registers (e.g., 704, 904) can provide high efficiency because in the example display driver 700, all current drawn is used to charge the display column lines. Moreover, the example embodiment of the display driver 700 can reduce current spikes caused by the driver IC by using current sources instead of class B or class AB amplifiers. Different example embodiments of the disclosed column drivers or display drivers (e.g., 700) can use programmable start signal injection (e.g., from Fig. 9 Logic circuit 902 using an n-bit unique hot bus 908 is used in the display driver (e.g., 700) to further reduce this current spike based on: 1) the magnitude of the difference between the new pixel gray level setting and the old pixel gray level setting, because a smaller difference in pixel gray level can allow for increased charging time and therefore a smaller startup current for the display driver (e.g., 700); and 2) the refresh rate (e.g., horizontal line time), because an increased line time can allow for a larger charging time and therefore a smaller startup current Itot, as described with respect to Fig. 9 The circuit 900 is discussed above.

[0065] In some example embodiments, for lower resolution displays (e.g., where a larger error between the reference voltage Vdata and the output voltage Vout is tolerated), the current can be further optimized using the example column driver or display driver (e.g., 700) of the present disclosure by disabling (e.g., permanently disabling) a plurality of current branches (e.g., pull-up current branches 707a1, 707b1, 707c1, ..., 707m1 or pull-down current branches 707a2, 707b2, 707c2, ..., 707m2 of the column driver or display driver (e.g., 700). In some example embodiments of the column driver or display driver (e.g., 700) of the present disclosure, the current-DAC (e.g., Figure 2 32) can be repeated for current sensing for each pixel calibration.

[0066] Figure 7The display driver 700 may be a piecewise linear current mode display driver in which the line charging current is adaptively regulated based on the voltage level (e.g., output voltage Vout) at the output 708 of the display driver 700. In the display driver 700, the pull-up current source and the pull-down current source (e.g., pull-up current branches 707a1, 707b1, 707c1, ..., 707m1 or pull-down current branches 707a2, 707b2, 707c2, ..., 707m2) are segmented, and current regulation is performed when the segments (e.g., pull-up current branches 707a1, 707b1, 707c1, ..., 707m1 or pull-down current branches 707a2, 707b2, 707c2, ..., 707m2) are enabled and disabled as the output voltage Vout converges toward the desired level Vdata. In addition, in the display driver 700, when the driver output voltage Vout exceeds the target voltage level Vdata (eg, as described with respect to Figure 8 When the current source of the segment (such as the pull-up current branch 707a1, 707b1, 707c1, ..., 707m1 or the pull-down current branch 707a2, 707b2, 707c2, ..., 707m2) is asynchronously shifted (for example, Fig. 9 The shift register (e.g., 704) of the circuit 900 of FIG. 900 is used to disable and enable the segments (e.g., pull-up current branches 707a1, 707b1, 707c1, ..., 707m1 or pull-down current branches 707a2, 707b2, 707c2, ..., 707m2). Moreover, in the display driver 700, the initial setting of the one-hot code (e.g., at the bus 908, as shown in FIG. 908 ) is performed. Fig. 9 The voltage under discussion) is a function of the current levels of the output voltage Vout and the target output voltage Vdata.

[0067] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited to these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Therefore, the first element, component, region, layer or section discussed herein may be referred to as a second element, component, region, layer or section without departing from the spirit and scope of the present inventive concept.

[0068] For ease of description, spatially relative terms such as "below", "below", "lower", "below", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another (some) element or feature as illustrated in the figure. It will be understood that these spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figure. For example, if the device in the figure is flipped, the element described as being "below" or "below" or "below" other elements or features will then be oriented "above" the other elements or features. Therefore, the example terms "below" and "below" can include both the above and below orientations. The device can be oriented otherwise (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein should be interpreted accordingly. In addition, it will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intermediate layers.

[0069] The terminology used herein is for the purpose of describing specific embodiments only and is not intended to limit the inventive concept. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation rather than as terms of degree, and are intended to take into account the inherent deviations of measured or calculated values ​​that would be recognized by one of ordinary skill in the art.

[0070] As used herein, the singular form "one" is intended to also include the plural form, unless the context clearly indicates otherwise. It will be further understood that when used in this specification, the term "include" and / or "comprising" specifies the presence of the features, integers, steps, operations, elements and / or parts, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or their groups. As used herein, the term "and / or" includes any and all combinations of one or more items in the associated listed items. When after a column of elements, expressions such as "at least one of" modify the entire element list without modifying the individual elements of the list. Further, when describing the embodiments of the present invention, the use of "can" refers to "one or more embodiments of the present invention". In addition, the term "exemplary" is intended to indicate an example or explanation. As used herein, the terms "use", "being used" and "used" can be regarded as synonymous with the terms "utilize", "being utilized" and "utilized", respectively.

[0071] It will be understood that when an element or layer is referred to as being "on," "connected to," "coupled to," or "adjacent to" another element or layer, it can be directly on, directly connected to, directly coupled to, or directly adjacent to the other element or layer, or there may be one or more intervening elements or layers. In contrast, when an element or layer is referred to as being "directly on," "directly connected to," "directly coupled to," or "immediately adjacent to" another element or layer, there are no intervening elements or layers.

[0072] Any numerical range described herein is intended to include all subranges of the same numerical precision contained within the range. For example, a range of "1.0 to 10.0" is intended to include all subranges between (and including) the minimum value of 1.0 and the maximum value of 10.0, that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits contained therein, and any minimum numerical limit described in this specification is intended to include all higher numerical limits contained therein.

[0073] The electronic or electrical devices and / or any other related devices or components according to the embodiments of the present invention described herein can be implemented using any suitable hardware, firmware (e.g., application specific integrated circuits), software, or a combination of software, firmware, and hardware. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. Further, the various components of these devices can be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. Further, the various components of these devices can be processes or threads for executing various functions described herein on one or more processors that execute computer program instructions and interact with other system components in one or more computing devices. Computer program instructions are stored in a memory implemented in a computing device using a standard memory device (such as, for example, a random access memory (RAM)). Computer program instructions can also be stored in other non-transient computer-readable media such as, for example, a CD-ROM, a flash drive, etc. In addition, those skilled in the art should recognize that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a specific computing device can be distributed across one or more other computing devices without departing from the spirit and scope of the exemplary embodiments of the present invention.

[0074] Although exemplary embodiments of a system and method for a high-efficiency piecewise linear column driver for a display using asynchronous control have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it is to be understood that a system and method for a high-efficiency piecewise linear column driver for a display using asynchronous control constructed in accordance with the principles of the present invention may be embodied other than as specifically described herein. The invention is also defined in the appended claims and their equivalents.

Claims

1. A display driver, comprising: a segmented pull-up current source circuit configured to supply a pull-up current to a load connected to an output of the display driver, wherein the segmented pull-up current source circuit comprises: a first plurality of transistors including m groups of transistors, wherein each group of the m groups of transistors of the first plurality of transistors comprises a p-type metal oxide semiconductor field effect transistor MOSFET and an n-type MOSFET connected in series with each other; a segmented pull-down current source circuit configured to supply a pull-down current to the load connected to the output of the display driver, wherein the segmented pull-down current source circuit comprises: a second plurality of transistors including m groups of transistors, wherein each group of the m groups of transistors of the second plurality of transistors comprises two n-type MOSFETs connected in series with each other, wherein the segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to each other via a first plurality of AND gate circuits and a second plurality of AND gate circuits; a comparator circuit configured to compare an output voltage level at the output of the display driver with a target voltage level and to generate a comparator output at one of two output terminals of the comparator circuit, wherein the segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to the two output terminals of the comparator circuit via one or more multiplexers, the first plurality of AND gate circuits, and the second plurality of AND gate circuits; and a logic circuit connected to at least one output terminal of the comparator circuit and configured to control the operation of the segmented pull-up current source circuit and the segmented pull-down current source circuit based on the comparator output, Where m is a positive integer, and wherein the logic circuit is an n-bit shift register comprising n separate shift registers, wherein n is a positive integer, and wherein each of the n separate shift registers is configured to control a corresponding group of transistors among the m groups of transistors of the first plurality of transistors based on the comparator output.

2. The display driver according to claim 1, wherein: The display driver is a column driver for an organic light emitting diode (OLED) display, and wherein the load connected to the output of the display driver is an OLED.

3. The display driver according to claim 1, wherein: In each of the m groups of transistors of the first plurality of transistors, a source terminal of the p-type MOSFET is connected to a power supply voltage, a drain terminal of the p-type MOSFET is connected to a drain terminal of the n-type MOSFET, and a gate terminal of the p-type MOSFET is connected to a bias voltage.

4. The display driver according to claim 3, wherein: In the m groups of transistors of the first plurality of transistors, source terminals of the n-type MOSFETs are connected to each other and to the output of the display driver, and gate terminals of the n-type MOSFETs are connected to output terminals of corresponding AND gate circuits in the first plurality of AND gate circuits including m separate AND gate circuits.

5. The display driver according to claim 1, wherein: In the m groups of transistors of the second plurality of transistors, drain terminals of first n-type MOSFETs are connected to each other and to the output of the display driver, and wherein a gate terminal of the first n-type MOSFET is connected to an output terminal of a corresponding AND gate circuit in the second plurality of AND gate circuits including m individual AND gate circuits.

6. The display driver according to claim 5, wherein: In each of the m groups of transistors of the second plurality of transistors, a source terminal of the first n-type MOSFET is connected to a drain terminal of a second n-type MOSFET, a source terminal of the second n-type MOSFET is grounded, and a gate terminal of the second n-type MOSFET is connected to a bias voltage.

7. The display driver according to claim 1, wherein: The comparator circuit is an operational amplifier.

8. The display driver according to claim 1, wherein: A first output terminal of each of the n individual shift registers is connected to an input terminal of a next shift register of the n individual shift registers via a multiplexer of the n-1 multiplexers.

9. The display driver according to claim 8, wherein: The logic circuit is used to determine the magnitude of the difference between the new pixel gray level and the old pixel gray level.

10. The display driver according to claim 1, wherein: The logic circuit is connected to at least one output terminal of the comparator circuit via a pulse generator configured to generate a pulse at each transition of the comparator output, wherein the pulse generator is an XOR gate circuit.

11. A display driver comprising: a segmented pull-up current source circuit configured to supply a pull-up current to a load connected to an output of the display driver, wherein the segmented pull-up current source circuit comprises: a first plurality of transistors including m groups of transistors; a segmented pull-down current source circuit configured to supply a pull-down current to the load connected to the output of the display driver; a comparator circuit configured to compare an output voltage level at the output of the display driver with a target voltage level and to generate a comparator output at one of two output terminals of the comparator circuit; and a logic circuit connected to at least one output terminal of the comparator circuit and configured to control the operation of the segmented pull-up current source circuit and the segmented pull-down current source circuit based on the comparator output, Where m is a positive integer, and wherein the logic circuit is an n-bit shift register comprising n separate shift registers, wherein n is a positive integer, and wherein each of the n separate shift registers is configured to control a corresponding group of transistors among the m groups of transistors of the first plurality of transistors based on the comparator output.

12. The display driver according to claim 11, wherein: The segmented pull-down current source circuit comprises: a second plurality of transistors including m groups of transistors, wherein the segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to each other via a first plurality of AND gate circuits and a second plurality of AND gate circuits; and The segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to the two output terminals of the comparator circuit via one or more multiplexers, the first plurality of AND gate circuits, and the second plurality of AND gate circuits.

13. The display driver according to claim 12, wherein: The display driver is a column driver for an organic light emitting diode (OLED) display, and wherein the load connected to the output of the display driver is an OLED.

14. The display driver according to claim 12, wherein: Each of the m groups of transistors of the first plurality of transistors includes a p-type metal oxide semiconductor field effect transistor MOSFET and an n-type MOSFET connected in series to each other.

15. The display driver according to claim 14, wherein: In each of the m groups of transistors of the first plurality of transistors, a source terminal of the p-type MOSFET is connected to a power supply voltage, a drain terminal of the p-type MOSFET is connected to a drain terminal of the n-type MOSFET, and a gate terminal of the p-type MOSFET is connected to a bias voltage.

16. The display driver according to claim 15, wherein: In the m groups of transistors of the first plurality of transistors, source terminals of the n-type MOSFETs are connected to each other and to the output of the display driver, and gate terminals of the n-type MOSFETs are connected to output terminals of corresponding AND gate circuits in the first plurality of AND gate circuits including m separate AND gate circuits.

17. The display driver according to claim 12, wherein: Each of the m groups of transistors of the second plurality of transistors includes two n-type MOSFETs connected in series with each other.

18. The display driver according to claim 17, wherein: In the m groups of transistors of the second plurality of transistors, drain terminals of a first n-type MOSFET are connected to each other and to the output of the display driver, wherein a gate terminal of the first n-type MOSFET is connected to an output terminal of a corresponding AND gate circuit in the second plurality of AND gate circuits including m separate AND gate circuits, and wherein, in each of the m groups of transistors of the second plurality of transistors, a source terminal of the first n-type MOSFET is connected to a drain terminal of a second n-type MOSFET, a source terminal of the second n-type MOSFET is grounded, and a gate terminal of the second n-type MOSFET is connected to a bias voltage.

19. The display driver according to claim 12, wherein: The first output terminal of each of the n individual shift registers is connected to the input terminal of the next shift register of the n individual shift registers via a multiplexer in n-1 multiplexers, and wherein the logic circuit is used to determine the magnitude of the difference between the new pixel gray level and the old pixel gray level.

20. A method for driving a display driver, the display driver comprising: a segmented pull-up current source circuit configured to supply a pull-up current to a load connected to an output of the display driver, wherein the segmented pull-up current source circuit comprises: a first plurality of transistors including m groups of transistors, wherein each group of the m groups of transistors of the first plurality of transistors comprises a p-type metal oxide semiconductor field effect transistor MOSFET and an n-type MOSFET connected in series with each other; a segmented pull-down current source circuit configured to supply a pull-down current to the load connected to the output of the display driver, wherein the segmented pull-down current source circuit comprises: a second plurality of transistors including m groups of transistors, wherein each group of the m groups of transistors of the second plurality of transistors comprises two n-type MOSFETs connected in series with each other, wherein the segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to each other via a first plurality of AND gate circuits and a second plurality of AND gate circuits; a comparator circuit configured to compare an output voltage level at the output of the display driver with a target voltage level and to generate a comparator output at one of two output terminals of the comparator circuit, wherein the segmented pull-up current source circuit and the segmented pull-down current source circuit are connected to the two output terminals of the comparator circuit via one or more multiplexers, the first plurality of AND gate circuits, and the second plurality of AND gate circuits; and a logic circuit connected to at least one output terminal of the comparator circuit and configured to control the operation of the segmented pull-up current source circuit and the segmented pull-down current source circuit based on the comparator output, wherein the logic circuit is an n-bit shift register including n individual shift registers, wherein n is a positive integer, and wherein each of the n individual shift registers is configured to control a corresponding group of transistors in the m groups of transistors of the first plurality of transistors based on the comparator output; the method comprising: turning on the first plurality of transistors including m groups of transistors based on receiving a start pulse from a pulse generator at an input terminal of the logic circuit; at the comparator circuit, comparing the output voltage level at the output of the display driver to the target voltage level to produce the comparator output; and turning on or off one or more transistor groups of the first plurality of transistors or the second plurality of transistors based on the comparator output, Here, m is a positive integer.

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