Method for manufacturing semiconductor device

Abstract

A method for manufacturing a semiconductor device includes: stacking a first mold layer and a first support member layer; forming a first support member pattern by etching the first support member layer to expose the first mold layer; forming an insulating layer to cover the exposed first mold layer and the first support member pattern; stacking a second mold layer and a second support member layer on the insulating layer; forming a contact hole by dry etching the second support member layer, the second mold layer, the insulating layer, the first support member pattern and the first mold layer; forming a lower electrode in the contact hole; removing the first mold layer, the second mold layer and the insulating layer; and forming an upper electrode on the lower electrode and the first support member pattern, wherein, during the dry etching, the dry etching rate of the first support member pattern is the same as the dry etching rate of the insulating layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] Korean Patent Application No. 10-2018-0165777, entitled “Method of Manufacturing a Semiconductor Device,” filed on December 20, 2018, in the Korean Intellectual Property Office is hereby incorporated by reference in its entirety. Technical Field

[0003] The present disclosure relates to a method of manufacturing a semiconductor device. Background Art

[0004] With the recent rapid development of miniaturized semiconductor processing technology, the high-density integration of memory products has been accelerated, significantly reducing the unit cell area and lowering the operating voltage. For example, in the case of semiconductor devices (such as dynamic random access memory (DRAM)), the integration density has increased and the area occupied by the device has decreased, however, it is necessary to maintain or increase the necessary capacitance. Summary of the Invention

[0005] According to an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: sequentially stacking a first mold layer and a first support member layer on a substrate; forming a first support member pattern by etching the first support member layer to expose at least a portion of an upper surface of the first mold layer; forming an insulating layer to cover the exposed upper surface of the first mold layer and the first support member pattern; sequentially stacking a second mold layer and a second support member layer on the insulating layer; dry-etching the second support member layer, the second mold layer, the insulating layer, at least a portion of the first support member pattern, and the first mold layer through a mask pattern to form a contact hole; forming a lower electrode in the contact hole; removing the first mold layer, the second mold layer, and the insulating layer; and forming an upper electrode on the lower electrode and the first support member pattern, wherein, during the dry etching, a dry etching rate of the first support member pattern is the same as a dry etching rate of the insulating layer.

[0006] According to an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: sequentially stacking a first mold layer and a first support member layer on a substrate; forming a first support member pattern by etching the first support member layer to expose at least a portion of an upper surface of the first mold member; forming a first insulating layer to cover the exposed upper surface of the first mold layer and the first support member pattern; sequentially stacking a second mold layer, a second support member layer, a third mold layer, and a third support member layer on the first insulating layer; forming a contact hole by dry-etching the third support member layer, the third mold layer, the second support member layer, the second mold layer, the first insulating layer, at least a portion of the first support member pattern, and the first mold layer using a mask pattern as a mask; forming a lower electrode in the contact hole; and removing the first mold layer, the second mold layer, the third mold layer, and the first insulating layer, wherein, during the dry etching, a dry etching rate of the first support member pattern is the same as a dry etching rate of the first insulating layer.

[0007] According to an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, including: sequentially stacking a first mold layer and a first support layer including silicon oxycarbide (SiOC) on a substrate; forming a first support pattern by etching the first support layer to expose at least a portion of an upper surface of the first mold layer; sequentially stacking a second mold layer and a second support layer on the first support pattern; forming a contact hole by dry etching the second support layer, the second mold layer, at least a portion of the first support pattern, and the first mold layer using a mask pattern as a mask; forming a lower electrode in the contact hole; and removing the first mold layer and the second mold layer, wherein, during the dry etching, a dry etching rate of the first support pattern is the same as a dry etching rate of the first mold layer.

[0008] According to an exemplary embodiment of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: sequentially stacking a first mold layer and a first support member layer on a substrate; forming a first support member pattern by etching the first support member layer to expose at least a portion of an upper surface of the first mold layer; forming an insulating layer to cover the exposed upper surface of the first mold layer and the first support member pattern; sequentially stacking a second mold layer and a second support member layer on the insulating layer; forming a contact hole by dry-etching the second support member layer, the second mold layer, the insulating layer, at least a portion of the first support member pattern, and the first mold layer using a mask pattern as a mask; forming a lower electrode in the contact hole; and removing the first mold layer, the second mold layer, and the insulating layer, wherein the insulating layer and the first mold layer include the same material as each other, and the first support member layer includes silicon oxycarbide (SiOC). BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Features will become apparent to those skilled in the art by describing in detail exemplary embodiments with reference to the accompanying drawings, in which:

[0010] Figure 1 shows a plan view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to some exemplary embodiments;

[0011] Figure 2 Shown along Figure 1 A cross-sectional view along line AA;

[0012] Figures 3 to 11 The manufacturing method according to the embodiment is shown Figure 2 cross-sectional views of various stages in a method for manufacturing a semiconductor device;

[0013] Figure 12 shows a plan view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to other exemplary embodiments;

[0014] Figure 13 Shown along Figure 12 A cross-sectional view along line AA;

[0015] Figure 14 and Figure 15 The manufacturing method according to the embodiment is shown Figure 13 cross-sectional views of various stages in a method for manufacturing a semiconductor device;

[0016] Figure 16 and Figure 17 cross-sectional views illustrating stages in a method of manufacturing a semiconductor device according to some other exemplary embodiments;

[0017] Figure 18 and Figure 19 cross-sectional views illustrating stages in a method of manufacturing a semiconductor device according to some other exemplary embodiments;

[0018] Figure 20 shows a cross-sectional view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to some other exemplary embodiments;

[0019] Figure 21 and Figure 22 The manufacturing method according to the embodiment is shown Figure 20 cross-sectional views of various stages in a method for manufacturing a semiconductor device;

[0020] Figure 23 shows a cross-sectional view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to some other exemplary embodiments;

[0021] Figures 24 to 27 The manufacturing method according to the embodiment is shown Figure 23 sectional views of various stages in the method of manufacturing a semiconductor device as shown in ;

[0022] Figure 28 shows a plan view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to some other exemplary embodiments; and

[0023] Figure 29 A plan view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to some other exemplary embodiments is shown. DETAILED DESCRIPTION

[0024] In the following, reference is made to Figure 1 and Figure 2 , a semiconductor device manufactured by a method of manufacturing a semiconductor device according to some exemplary embodiments of the present disclosure will be described.

[0025] Figure 1 A plan view of a semiconductor device manufactured by a method of manufacturing a semiconductor device according to some example embodiments is shown. Figure 2 Shown along Figure 1 However, for convenience of explanation, Figure 1 The capacitor dielectric layer 135 and the upper electrode 140 are omitted.

[0026] Reference Figure 1 and Figure 2 According to some exemplary embodiments, a semiconductor device manufactured by a method of manufacturing a semiconductor device may include a substrate 101, an interlayer insulating layer 102, a contact plug 103, an etch stop layer 105, a first support member 110, a second support member 120, a lower electrode 130, a capacitor dielectric layer 135 and an upper electrode 140.

[0027] The substrate 101 may be a structure in which a substrate base and an epitaxial layer are stacked one on top of the other, but the present disclosure is not limited thereto. That is, in some other exemplary embodiments, the substrate 101 may be a silicon substrate, a gallium arsenide substrate, a silicon germanium substrate, a ceramic substrate, a quartz substrate, or a glass substrate for a display, or any one of a semiconductor-on-insulator (SOI) substrate. Hereinafter, a silicon substrate will be described as an example. The substrate 101 may be of a first conductivity type (e.g., a P-type), but the present disclosure is not limited thereto.

[0028] Although not shown, a gate electrode serving as a word line may be provided in the substrate 101. A cell activation region and an element isolation region may be formed on the substrate 101. For example, two transistors may be formed in a single cell activation region.

[0029] An interlayer insulating layer 102 may be formed on the substrate 101. The interlayer insulating layer 102 may include, for example, at least one of silicon oxide (SiO2), silicon nitride (SiN), and silicon oxynitride (SiON). The interlayer insulating layer 102 may be a single layer or a multilayer.

[0030] The contact plug 103 may be formed in the interlayer insulating layer 102 to penetrate the interlayer insulating layer 102. The contact plug 103 may be electrically connected to the source / drain region formed in the substrate 101. The contact plug 103 may include a conductive material, and for example, may include at least one of polysilicon, metal silicide, conductive metal nitride, and metal. However, the present disclosure is not limited thereto.

[0031] The semiconductor device may include a plurality of contact holes 170 spaced apart from each other. For example, the second contact hole 172 may be spaced apart from the first contact hole 171 in the first direction DR1. Furthermore, the third contact hole 173 may be spaced apart from the first contact hole 171 in the second direction DR2.

[0032] The angle θ formed by the first direction DR1 and the second direction DR2 may be an acute angle. For example, the angle θ formed by the first direction DR1 and the second direction DR2 may be 60 degrees. In this case, the plurality of contact holes 170 may be respectively disposed at the vertices and the center of the honeycomb hexagon.

[0033] Despite Figure 1 1 and 2 show that the plurality of contact holes 170 are spaced apart from each other at the same intervals, but the present disclosure is not limited thereto. That is, in some other exemplary embodiments, at least one of the intervals between the plurality of contact holes 170 may be different. Each of the plurality of contact holes 170 may be formed to extend in a fourth direction DR4 perpendicular to the upper surface of the substrate 101.

[0034] Each of the plurality of contact holes 170 may include a lower electrode 130 disposed therein. In this case, the lower electrode 130 may be disposed to completely fill an inner portion of each of the plurality of contact holes 170. That is, the lower electrode 130 may have a pillar shape. However, the present disclosure is not limited thereto.

[0035] A lower electrode 130 may be disposed within each of the plurality of contact holes 170. The lower electrode 130 may be disposed to extend along a fourth direction DR4 on the substrate 101. The lower electrode 130 may be disposed on a contact plug 103 disposed in the interlayer insulating layer 102. The lower electrode 130 may be electrically connected to the contact plug 103. The lower electrode 130 may include at least one of doped polysilicon, a conductive metal nitride (e.g., titanium nitride, tungsten nitride, etc.), a metal (e.g., ruthenium, iridium, titanium, tantalum, etc.), and a conductive metal oxide (e.g., iridium oxide, etc.).

[0036] The etch stop layer 105 may be provided on the interlayer insulating layer 102. The etch stop layer 105 may be provided to surround a portion of the sidewall of the lower electrode 130 formed adjacent to the upper surface of the interlayer insulating layer 102. The etch stop layer 105 may include a Figure 9 The first mold layer 151 and the second mold layer 152 include oxide and have an etch selectivity. The etch stop layer 105 may include, for example, silicon nitride (SiN), but the present disclosure is not limited thereto.

[0037] The plurality of support members 110 and 120 may support the lower electrode 130. For example, referring to Figures 1 to 2 As shown, the first support member 110 and the second support member 120 may have the same shape in a plan view and completely overlap each other, for example, so that the first support member 110 may have the same shape as Figure 1 The same shape as the second support member 120 in (and is completely covered by the second support member 120, so that Figure 1 not shown).

[0038] In detail, the first support member 110 as a lower support member may be provided on the substrate 101 to support the lower electrodes 130. The first support member 110 may include: an opening region R1 therethrough to expose a portion of the capacitor dielectric layer 135 provided on the sidewalls of the plurality of lower electrodes 130; and a support region to surround a portion of the other sidewalls of the plurality of lower electrodes 130. The first support member 110 may support the plurality of lower electrodes 130 by using the support region. Although Figure 1 The lower electrode 130 is illustrated in which the opening region R1 is not formed, but the present disclosure is not limited thereto.

[0039] The opening region R1 of the first support member 110 may have a circular shape. However, the present disclosure is not limited thereto. That is, in some other exemplary embodiments, the opening region R1 of the first support member 110 may have, for example, a rectangular shape or a parallelogram shape.

[0040] The second support member 120, serving as an upper support member, may be disposed on the first support member 110 to support the lower electrodes 130. The second support member 120 may include an opening region to expose a portion of the capacitor dielectric layer 135 disposed on the sidewalls of the plurality of lower electrodes 130, and a support region to surround a portion of the other sidewalls of the plurality of lower electrodes 130. The second support member 120 may support the plurality of lower electrodes 130 using the support region.

[0041] The opening region of the second support member 120 may have the same shape as the opening region R1 of the first support member 110 in a plan view and may completely overlap with the opening region R1 of the first support member 110. For example, the opening region of the second support member 120 and the opening region R1 of the first support member 110 may be fluidly connected to each other to define a combined single space ( Figure 10 ). The opening area of ​​the second support member 120 may have a circular shape. However, the present disclosure is not limited thereto. That is, in some other exemplary embodiments, the opening area of ​​the second support member 120 may have, for example, a rectangular shape or a parallelogram shape.

[0042] The first support member 110 and the second support member 120 may be disposed between adjacent lower electrodes 130. Figure 1 and Figure 2 As shown, the first support member 110 and the second support member 120 may not be disposed in the opening region R1. For example, the first support member 110 and the second support member 120 may directly contact the lower electrode 130. However, the present disclosure is not limited thereto.

[0043] The first support member 110 and the second support member 120 may be disposed to be spaced apart from each other. Specifically, the first support member 110 and the second support member 120 may be disposed to be spaced apart from each other in the fourth direction DR4 in which the lower electrode 130 extends. For example, the first support member 110 and the second support member 120 may be spaced apart from each other by the upper electrode 140. For example, the first support member 110 may be disposed closer to the upper surface of the substrate 101 than the second support member 120. That is, the distance between the first support member 110 and the upper surface of the substrate 101 along the fourth direction DR4 may be smaller than the distance between the second support member 120 and the upper surface of the substrate 101 along the fourth direction DR4.

[0044] The first support member 110 may include, for example, silicon oxycarbide (SiOC). However, the present disclosure is not limited thereto. The second support member 120 may include, for example, at least one of silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), and tantalum oxide (TaO).

[0045] For example, along the fourth direction DR4, the height from the upper surface of the substrate 101 to the upper surface of the lower electrode 130 may be equal to the height from the upper surface of the substrate 101 to the upper surface of the second support member 120. That is, the uppermost portion (e.g., surface) of the lower electrode 130 and the upper surface of the second support member 120 may be formed on the same plane, for example, flush with each other. However, the present disclosure is not limited thereto.

[0046] The capacitor dielectric layer 135 may be conformally disposed on the lower electrode 130, the first support member 110, the second support member 120, and the etch stop layer 105. Specifically, the capacitor dielectric layer 135 may be disposed along the sidewalls and upper surface of the lower electrode 130. The capacitor dielectric layer 135 may be disposed along the upper and lower surfaces of the first support member 110. The capacitor dielectric layer 135 may be disposed along the upper and lower surfaces of the second support member 120. The capacitor dielectric layer 135 may be disposed along the upper surface of the etch stop layer 105. The capacitor dielectric layer 135 may be formed of a single layer or multiple layers.

[0047] The capacitor dielectric layer 135 may include, for example, at least one of silicon oxide (SiO 2 ), silicon nitride (SiN), silicon oxynitride (SiON), and a high-k dielectric material. For example, the high-k dielectric material may include hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, but the present disclosure is not limited thereto.

[0048] The upper electrode 140 may be disposed on the capacitor dielectric layer 135. Specifically, the upper electrode 140 may be disposed between adjacent lower electrodes 130 (e.g., in the first direction DR1 and the second direction DR2), between the first support member 110 and the second support member 120 (e.g., in the fourth direction DR4), and between the first support member 110 and the etch stop layer 105 (e.g., in the fourth direction DR4). The upper electrode 140 may include, for example, at least one of doped polysilicon, a metal, a conductive metal nitride, and a metal silicide.

[0049] In the following, reference will be made to Figures 2 to 11 Methods of fabricating semiconductor devices according to some example embodiments are described. Figures 3 to 11 are diagrams showing intermediate stages of fabrication, provided to explain fabrication according to some exemplary embodiments. Figure 2 The method of the semiconductor device shown in FIG.

[0050] Reference Figure 3An interlayer insulating layer 102 and contact plugs 103 penetrating the interlayer insulating layer 102 in a fourth direction DR4 may be formed on the substrate 101. Subsequently, an etch stop layer 105, a first mold layer 151, and a first support layer 111 may be sequentially stacked on the interlayer insulating layer 102 and the contact plugs 103.

[0051] In detail, the etch stop layer 105 may be conformally formed on the interlayer insulating layer 102 and the contact plug 103. The etch stop layer 105 may be formed by using, for example, a chemical vapor deposition process, but the present disclosure is not limited thereto.

[0052] A first mold layer 151 may be formed on the etch stop layer 105. The first mold layer 151 may be formed by, for example, a chemical vapor deposition (CVD) process, but the present disclosure is not limited thereto. The first mold layer 151 may include silicon oxide (SiO2), and may include, for example, flowable oxide (FOX), toner silazene (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethyl orthosilicate (PE-TEOS), fluorinated silicate glass (FSG), high-density plasma (HDP), plasma-enhanced oxide (PEOX), flowable CVD (FCVD), or a combination thereof.

[0053] Despite Figure 3 , the first mold layer 151 is shown to be formed as a single layer, but the present disclosure is not limited thereto. That is, in some other exemplary embodiments, the first mold layer 151 may include two or more layers having different etching speeds.

[0054] The first support layer 111 may be formed on the first mold layer 151. The first support layer 111 may be formed by using, for example, a chemical vapor deposition (CVD) process, but the present disclosure is not limited thereto.

[0055] The first support layer 111 may include, for example, silicon oxycarbide (SiOC). Component materials of the first support layer 111 will be described in detail below.

[0056] Reference Figure 4 , can be achieved by Figure 3The first support layer 111 is etched to form a first support pattern 112 to expose at least a portion of the upper surface 151a of the first mold layer 151. For example, the first support pattern 112 may include a plurality of portions spaced apart from each other in a horizontal direction (e.g., along the first direction DR1 and / or the second direction DR2) such that a region between each two adjacent portions of the first support pattern 112 exposes a portion of the upper surface 151a of the first mold layer 151. At least a portion of the exposed upper surface 151a of the first mold layer 151 may be formed to overlap with the contact plug 103 (e.g., along the fourth direction DR4).

[0057] Reference Figure 5 The first insulating layer 160 may be formed to cover the exposed upper surface 151a of the first mold layer 151 and the first support pattern 112. The first insulating layer 160 may be formed using, for example, an atomic layer deposition process. Thus, the first insulating layer 160 may be conformally formed on the exposed upper surface 151a of the first mold layer 151 and the first support pattern 112.

[0058] A lower surface of the first insulating layer 160 may be formed on the same plane as a lower surface of the first support pattern 112. However, the present disclosure is not limited thereto.

[0059] The first insulating layer 160 may be formed to completely fill the region between the first support patterns 112. For example, the first insulating layer 160 may be formed to completely fill the region between adjacent portions of the first support pattern 112. For example, the first insulating layer 160 may be formed using an atomic layer deposition process to a thickness sufficient to exceed the thickness of the first support patterns 112 in the fourth direction DR4, for example, when measured from the upper surface 151a of the first mold layer 151, so as to completely fill the region between the first support patterns 112. Therefore, the formation of voids in the region between, for example, adjacent portions of the first support pattern 112 can be effectively prevented.

[0060] The first insulating layer 160 may include the same material as the first mold layer 151. The first insulating layer 160 may include, for example, silicon oxide (SiO2). However, the present disclosure is not limited thereto.

[0061] Reference Figure 6 , the second mold layer 152 and the second support layer 121 may be sequentially stacked on the first insulating layer 160. In detail, the second mold layer 152 may be formed on the first insulating layer 160, for example, such that the first insulating layer 160 separates the first mold layer 151 from the second mold layer 152.

[0062] The second mold layer 152 may be formed by using, for example, a chemical vapor deposition process. That is, the second mold layer 152 may be formed by a process different from that of the first insulating layer 160. However, the present disclosure is not limited thereto. That is, according to some other exemplary embodiments, the first insulating layer 160 and the second mold layer 152 may be formed by using the same process (e.g., a chemical vapor deposition process).

[0063] The second mold layer 152 may include the same material as that of the first insulating layer 160. The second mold layer 152 may include silicon oxide (SiO2), and for example, may include flowable oxide (FOX), toner silazane (TOSZ), undoped silica glass (USG), borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), plasma-enhanced tetraethylorthosilicate (PE-TEOS), fluorinated silicate glass (FSG), high-density plasma (HDP), plasma-enhanced oxide (PEOX), flowable CVD (FCVD), or a combination thereof.

[0064] Despite Figure 6 , the second mold layer 152 is shown to be formed as a single layer, but the present disclosure is not limited thereto. That is, in some other exemplary embodiments, the second mold layer 152 may include two or more layers having different etching speeds.

[0065] A second support layer 121 may be formed on the second mold layer 152. The second support layer 121 may be formed using, for example, a chemical vapor deposition (CVD) process, but the present disclosure is not limited thereto. The second support layer 121 may include, for example, at least one of silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), and tantalum oxide (TaO). The thickness of the second support layer 121 in the fourth direction DR4 may be formed to be greater than the thickness of the first support pattern 112 in the fourth direction DR4, but the present disclosure is not limited thereto.

[0066] Reference Figure 7 The first contact hole 171 and the second contact hole 172 can be formed by etching the second support layer 121, the second mold layer 152, the first insulating layer 160, at least a portion of the first support pattern 112, the first mold layer 151, and the etch stop layer 105 using the first mask pattern 10 formed on the second support layer 121 as a mask. The first contact hole 171 and the second contact hole 172 can be formed by, for example, a first dry etching process. The contact plug 103 can be exposed through the first contact hole 171 and the second contact hole 172.

[0067] The etching selectivities of the first support pattern 112 and the first insulating layer 160 relative to the first dry etching may be the same as each other. That is, a first dry etching rate of the first support pattern 112 relative to the first dry etching may be the same as a second dry etching rate of the first insulating layer 160 relative to the first dry etching. That is, when the first dry etching is performed, the first support pattern 112 and the first insulating layer 160 may be etched at the same speed.

[0068] Here, the term "same" refers to a substantially same level acceptable to those skilled in the art and includes slight errors that can be ignored by those skilled in the art. The same etching selectivity of the first support pattern 112 and the first insulating layer 160 relative to the first dry etching can be caused by the first support pattern 112 including silicon oxycarbide (SiOC) and the first insulating layer 160 including silicon oxide (SiO2).

[0069] The etching selectivities of the first support pattern 112 and the first mold layer 151 relative to the first dry etching may be the same. That is, a first dry etching rate of the first support pattern 112 relative to the first dry etching may be the same as a third dry etching rate of the first mold layer 151 relative to the first dry etching. That is, when the first dry etching is performed, the first support pattern 112 and the first mold layer 151 may be etched at the same speed.

[0070] Reference Figure 8 , a lower electrode layer 131 may be formed within each of the first and second contact holes 171 and 172 and over the first mask pattern 10. In detail, the lower electrode layer 131 may be formed to completely fill an inner portion of each of the first and second contact holes 171 and 172 and cover a sidewall and an upper surface of the first mask pattern 10.

[0071] Reference Figure 9 The first mask pattern 10 and a portion of the lower electrode layer 131 on the second support layer 121 may be removed by using a process including at least one of chemical mechanical polishing and etch back until the second support layer 121 is exposed. Through the above process, the lower electrode 130 electrically connected to the contact plug 103 may be formed in each of the first contact hole 171 and the second contact hole 172.

[0072] Reference Figure 10 , a second mask pattern 20 may be formed on a portion of the second support layer 121 and the lower electrode 130. In detail, the second support layer 121 and the lower electrode 130 (excluding the region disposed between the first contact hole 171 and the second contact hole 172 (i.e., Figure 1A second mask pattern 20 is formed on the second support layer 121) on the area corresponding to the opening area R1 shown in FIG.

[0073] Subsequently, the second support member layer 121, the second mold layer 152, the first insulating layer 160, the first support member pattern 112, and the first mold layer 151 can be etched using the second mask pattern 20 as a mask. Through the above process, the first support member 110 and the second support member 120 can be formed. In other words, the remaining portions of the first support member pattern 112 and the second support member layer 121 can be the first support member 110 and the second support member 120, respectively. For example, the opening region R1 can be formed by using a dry etching process.

[0074] Reference Figure 11 After removing the second mask pattern 20, the first mold layer 151, the second mold layer 152, and the first insulating layer 160 may be removed by a wet etching process. That is, by the wet etching process, a first cavity 151c may be formed in a region where the first mold layer 151 has been removed, and a second cavity 152c may be formed in a region where the second mold layer 152 and the first insulating layer 160 have been removed. Figure 11 As shown, the lower electrode 130 may be supported only by the first support member 110 and the second support member 120 .

[0075] Regarding the above-mentioned wet etching, the etching selectivities of the first mold layer 151, the second mold layer 152, and the first insulating layer 160 may be the same. That is, a first wet etching rate of the first insulating layer 160 with respect to the wet etching may be the same as a second wet etching rate of the first mold layer 151 with respect to the wet etching and a third wet etching rate of the second mold layer 152 with respect to the wet etching.

[0076] Reference Figure 2 , the capacitor dielectric layer 135 may be conformally formed on the lower electrode 130, the first support member 110, the second support member 120, and the etch stop layer 105. In detail, the capacitor dielectric layer 135 may be formed along the sidewall and upper surface of the lower electrode 130. The capacitor dielectric layer 135 may be formed along the upper and lower surfaces of the first support member 110. The capacitor dielectric layer 135 may be formed along the upper and lower surfaces of the second support member 120. The capacitor dielectric layer 135 may be formed along the upper surface of the etch stop layer 105.

[0077] Subsequently, the upper electrode 140 may be formed on the capacitor dielectric layer 135. Specifically, the upper electrode 140 may be formed between adjacent lower electrodes 130, between the first support member 110 and the second support member 120, and between the first support member 110 and the etching stop layer 105. Figure 2 The semiconductor device shown in .

[0078] The method of manufacturing a semiconductor device according to some exemplary embodiments may prevent voids from being formed between the first support patterns 112 by forming the first insulating layer 160 to cover the first support patterns 112 before forming the second mold layer 152. In other words, since the first insulating layer 160 is formed between portions of the first support patterns 112 to completely fill the space therebetween without a void, the second mold layer 152 may be subsequently formed without a void on the first support patterns 112 completely covered by the first insulating layer 160.

[0079] Furthermore, the method of manufacturing a semiconductor device according to some exemplary embodiments can prevent a tilting phenomenon in the profile of the sidewall in the contact hole 170 because there is no difference in the etch selectivity of the first insulating layer 160 relative to the first support pattern 112. That is, since there is no difference in the etch selectivity of the first insulating layer 160 relative to the first support pattern 112, potential tilting caused by a difference in the etch selectivity of different layers etched during the formation of the contact hole can be prevented, thereby performing etching at the same rate to have a substantially flat and uniform sidewall profile.

[0080] In the following, reference is made to Figure 12 and Figure 13 , a semiconductor device manufactured by a method of manufacturing a semiconductor device according to some other exemplary embodiments will be described. Figure 1 and Figure 2 The difference between the semiconductor devices shown in .

[0081] Figure 12 are diagrams provided to explain a semiconductor device manufactured by a method of manufacturing the semiconductor device according to some other exemplary embodiments. Figure 13 It is along Figure 12 A cross-sectional view taken along line AA.

[0082] Reference Figure 12 and Figure 13 In a semiconductor device manufactured by the method of manufacturing a semiconductor device according to some other exemplary embodiments, the lower electrode 230 may have a cylindrical shape, for example, a cylindrical shape having a U-shaped cross section. Specifically, the lower electrode 230 may be disposed along sidewalls and bottom surfaces of the first contact hole 171 and the second contact hole 172 (e.g., conformally).

[0083] The capacitor dielectric layer 235 may be conformally disposed on the lower electrode 230, the first support 110, the second support 120, and the etch stop layer 105. The capacitor dielectric layer 235 may be completely formed on the outer and inner walls of the lower electrode 230.

[0084] The upper electrode 240 may be disposed on the capacitor dielectric layer 235. Specifically, the upper electrode 240 may be disposed within the cylindrical lower electrode 230, between adjacent lower electrodes 230, between the first support 110 and the second support 120, and between the first support 110 and the etch stop layer 105.

[0085] In the following, reference will be made to Figure 14 and Figure 15 Methods for manufacturing semiconductor devices according to some other exemplary embodiments are described. Figures 3 to 11 The method of manufacturing a semiconductor device shown in FIG.

[0086] Figure 14 and Figure 15 are diagrams showing intermediate stages of fabrication, provided to explain fabrication according to some exemplary embodiments. Figure 13 The method of the semiconductor device shown in FIG.

[0087] Reference Figure 14 , after executing Figures 3 to 7 After the process described in , a lower electrode layer 231 may be formed within each of the first and second contact holes 171 and 172 and over the first mask pattern 10. In detail, the lower electrode layer 231 may be conformally formed to cover the sidewalls and bottom surface of the inner portion of each of the first and second contact holes 171 and 172 and the sidewalls and upper surface of the first mask pattern 10.

[0088] Reference Figure 15 , a sacrificial layer 245 may be formed to fill an inner portion of each of the first contact hole 171 and the second contact hole 172 on the lower electrode layer 231. Subsequently, the first mask pattern 10, the sacrificial layer 245, and at least a portion of the lower electrode layer 231 on the second support layer 121 may be removed by using a process including at least one of chemical mechanical polishing (CMP) and etch back until the second support layer 121 is exposed.

[0089] Through the above-described process, a lower electrode 230 electrically connected to the contact plug 103 and having a cylindrical shape can be formed in each of the first contact hole 171 and the second contact hole 172. Figure 10 and Figure 11 After the processing described in , the capacitor can be manufactured by removing the sacrificial layer 245 and forming the upper electrode 240 on the capacitor dielectric layer 235. Figure 13 The semiconductor device shown in .

[0090] In the following, reference will be made to Figure 16 and Figure 17Methods for manufacturing semiconductor devices according to some other exemplary embodiments are described. Figures 3 to 11 The method of manufacturing a semiconductor device shown in FIG.

[0091] Figure 16 and Figure 17 are diagrams illustrating intermediate stages of fabrication, which are provided to explain methods of fabricating semiconductor devices according to some other exemplary embodiments.

[0092] Reference Figure 16 , after executing Figure 3 After the processing described in Figure 3 The first support layer 111 is etched to form a first support pattern 112 to expose at least a portion of the upper surface 351a of the first mold layer 351. The exposed upper surface 351a of the first mold layer 351 may be formed to be recessed within the first mold layer 351.

[0093] Reference Figure 17 , an insulating layer 360 may be formed to cover the exposed upper surface 351a of the first mold layer 351 and the first support pattern 112. A lower surface 360a of the insulating layer 360 formed between the first support patterns 112 may be formed closer to the substrate 101 than a lower surface 112a of the first support pattern 112. Subsequently, the insulating layer 360 may be formed to cover the exposed upper surface 351a of the first mold layer 351 and the first support pattern 112. Figures 6 to 11 The process described in the Figure 2 The semiconductor device shown in FIG.

[0094] In the following, reference will be made to Figure 18 and Figure 19 Methods for manufacturing semiconductor devices according to some other exemplary embodiments are described. Figures 3 to 11 The method of manufacturing a semiconductor device shown in FIG.

[0095] Figure 18 and Figure 19 are diagrams illustrating intermediate stages of fabrication, which are provided to explain methods of fabricating semiconductor devices according to some other exemplary embodiments.

[0096] Reference Figure 18 ,exist Figure 3 and Figure 4 After the process described in , the second mold layer 452 and the second support layer 121 may be sequentially stacked on the exposed first mold layer 151 and the first support pattern 112. The second mold layer 152 may be formed by using, for example, a chemical vapor deposition process. However, the present disclosure is not limited thereto.

[0097] Reference Figure 19The first contact hole 171 and the second contact hole 172 can be formed by etching the second support layer 121, the second mold layer 452, at least a portion of the first support pattern 112, the first mold layer 151 and the etch stop layer 105 using the first mask pattern 10 formed on the second support layer 121 as a mask. Figures 8 to 11 The process described in the Figure 2 The semiconductor device shown in FIG.

[0098] In the following, reference is made to Figure 20 , a semiconductor device manufactured by a method of manufacturing a semiconductor device according to some other exemplary embodiments will be described. Figure 2 The difference between the semiconductor devices shown in .

[0099] Figure 20 are cross-sectional views provided to explain a semiconductor device manufactured by a method of manufacturing the semiconductor device according to some other exemplary embodiments.

[0100] Reference Figure 20 According to some other exemplary embodiments, a semiconductor device manufactured by a method of manufacturing a semiconductor device may include a first support member 110 as a lower support member, a second support member 520 as an intermediate support member, and a third support member 590 as an upper support member. Specifically, the second support members 520 may be arranged on the first support member 110 at intervals along the fourth direction DR4, and the third support members 590 may be arranged on the second support member 520 at intervals along the fourth direction DR4. The thickness of the third support member 590 in the fourth direction DR4 may be greater than the thickness of the first support member 110 in the fourth direction DR4 and the thickness of the second support member 520 in the fourth direction DR4. However, the present disclosure is not limited thereto.

[0101] Each of the first to third supports 110, 520, 590 may be disposed in contact with sidewalls of the first and second contact holes 571 and 572. The upper surface of the third support 590 may be formed on the same plane as the upper surface of the lower electrode 530. However, the present disclosure is not limited thereto.

[0102] The capacitor dielectric layer 535 may be conformally disposed on the lower electrode 530, the first support 110, the second support 520, the third support 590, and the etch stop layer 105. The upper electrode 540 may be disposed on the capacitor dielectric layer 535. Specifically, the upper electrode 540 may be disposed between adjacent lower electrodes 530, between the first support 110 and the second support 520, between the second support 520 and the third support 590, and between the first support 110 and the etch stop layer 105.

[0103] In the following, reference will be made to Figure 21 and Figure 22 Methods for manufacturing semiconductor devices according to some other exemplary embodiments are described. Figures 3 to 11 The method of manufacturing a semiconductor device shown in FIG.

[0104] Figure 21 and Figure 22 are diagrams showing intermediate stages of fabrication, provided to explain fabrication according to some other exemplary embodiments. Figure 20 The method of the semiconductor device shown in FIG.

[0105] Reference Figure 21 , after executing Figures 3 to 5 After the process described in , the second mold layer 152, the second support layer 521, the third mold layer 580, and the third support layer 591 may be sequentially stacked on the first insulating layer 160. Each of the second support layer 521 and the third support layer 591 may include, for example, at least one of silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), and tantalum oxide (TaO). The third mold layer 580 may include the same material as that of the second mold layer 152 and the first insulating layer 160, for example, silicon oxide (SiO2).

[0106] Reference Figure 22 , the first contact hole 571 and the second contact hole 572 can be formed by etching the third support layer 591, the third mold layer 580, the second support layer 521, the second mold layer 152, the first insulating layer 160, at least a portion of the first support pattern 112, the first mold layer 151 and the etch stop layer 105 using the third mask pattern 30 formed on the third support layer 591 as a mask. Figure 8 and Figure 9 After the processing described in Figure 11 The process of removing the third mold layer 580 is described to produce Figure 20 The semiconductor device shown in .

[0107] In the following, reference is made to Figure 23 , a semiconductor device manufactured by a method of manufacturing a semiconductor device according to some other exemplary embodiments will be described. Figure 2 The difference between the semiconductor devices shown in .

[0108] Figure 23 are cross-sectional views provided to explain a semiconductor device manufactured by a method of manufacturing the semiconductor device according to some other exemplary embodiments.

[0109] Reference Figure 23 According to some other exemplary embodiments, a semiconductor device manufactured by a method of manufacturing a semiconductor device may include a first support member 110 as a lower support member, a second support member 620 as an intermediate support member, and a third support member 690 as an upper support member. Specifically, the second support members 620 may be arranged spaced apart along the fourth direction DR4 on the first support member 110, and the third support members 690 may be arranged spaced apart along the fourth direction DR4 on the second support member 620. The thickness of the third support member 690 in the fourth direction DR4 may be greater than the thickness of the first support member 110 and the thickness of the second support member 620 in the fourth direction DR4. However, the present disclosure is not limited thereto.

[0110] Each of the first to third supports 110, 620, 690 may be disposed in contact with sidewalls of the first and second contact holes 671 and 672. The upper surface of the third support 690 may be formed on the same plane as the upper surface of the lower electrode 630. However, the present disclosure is not limited thereto.

[0111] The first support 110 and the second support 620 may include, for example, silicon oxycarbide (SiOC). The capacitor dielectric layer 635 may be conformally disposed on the lower electrode 630 , the first support 110 , the second support 620 , the third support 690 , and the etch stop layer 105 .

[0112] The upper electrode 640 may be disposed on the capacitor dielectric layer 635. Specifically, the upper electrode 640 may be disposed between adjacent lower electrodes 630, between the first support 110 and the second support 620, between the second support 620 and the third support 690, and between the first support 110 and the etch stop layer 105.

[0113] Reference Figure 24 , after executing Figures 3 to 5 After the process described in , a second mold layer 152 and a second support layer 621 may be sequentially stacked on the first insulating layer 160. The second support layer 621 may include, for example, silicon oxycarbide (SiOC).

[0114] Reference Figure 25 , can be achieved by Figure 24 The second supporter layer 621 is etched to form a second supporter pattern 622 to expose at least a portion of the upper surface 152a of the second mold layer 152. At least a portion of the exposed upper surface 152a of the second mold layer 152 may be formed to overlap the contact plug 103.

[0115] A second insulating layer 660 may be formed to cover the exposed upper surface 152a of the second mold layer 152 and the second support pattern 622. The second insulating layer 660 may be formed by, for example, an atomic layer deposition process. Thus, the second insulating layer 660 may be conformally formed on the exposed upper surface 152a of the second mold layer 152 and the second support pattern 622.

[0116] The lower surface of the second insulating layer 660 may be formed on the same plane as the lower surface of the second supporter pattern 622. However, the present disclosure is not limited thereto.

[0117] The second insulating layer 660 may be formed to completely fill the region between the second support patterns 622. For example, the second insulating layer 660 may be formed using an atomic layer deposition process with a thickness so as to completely fill the region between the second support patterns 622. Thus, the formation of voids in the region between the second support patterns 622 may be effectively prevented.

[0118] The second insulating layer 660 may include the same material as the second mold layer 152. The second insulating layer 660 may include, for example, silicon oxide (SiO2). However, the present disclosure is not limited thereto.

[0119] Reference Figure 26 , a third mold layer 680 and a third support layer 691 may be sequentially stacked on the second insulating layer 660. The third support layer 691 may include, for example, at least one of silicon oxynitride (SiON), silicon nitride (SiN), silicon carbonitride (SiCN), and tantalum oxide (TaO). The third mold layer 680 may include the same material as the second mold layer 152 and the second insulating layer 660, such as silicon oxide (SiO2).

[0120] Reference Figure 27 The first contact hole 671 and the second contact hole 672 can be formed by performing a second dry etching on the third support layer 691, the third mold layer 680, the second insulating layer 660, at least a portion of the second support pattern 622, the second mold layer 152, the first insulating layer 160, at least a portion of the first support pattern 112, the first mold layer 151 and the etch stop layer 105 using the fourth mask pattern 40 formed on the third support layer 691 as a mask.

[0121] The etching selectivities of the second support pattern 622 and the second insulating layer 660 relative to the second dry etching may be the same. That is, the third dry etching rate of the second support pattern 622 relative to the second dry etching may be the same as the fourth dry etching rate of the second insulating layer 660 relative to the second dry etching. That is, when the second dry etching is performed, the second support pattern 622 and the second insulating layer 660 may be etched at the same speed.

[0122] Afterwards, after executing Figure 8 and Figure 9 After the treatment described in Figure 11 The third mold layer 680 and the second insulating layer 660 are further removed in the process described in the above. Figure 23 The semiconductor device shown in .

[0123] In the following, reference is made to Figure 28 , a semiconductor device manufactured by a method of manufacturing a semiconductor device according to some other exemplary embodiments will be described. Figure 1 The difference between the semiconductor devices shown in .

[0124] Figure 28 are diagrams provided to explain a semiconductor device manufactured by a method of manufacturing the semiconductor device according to some other exemplary embodiments.

[0125] Reference Figure 28 The semiconductor device may include a plurality of contact holes 770 spaced apart from each other. For example, the second contact hole 772 may be spaced apart from the first contact hole 771 in the first direction DR1. In addition, the third contact hole 773 may be spaced apart from the first contact hole 771 in the third direction DR3.

[0126] An angle formed by the first direction DR1 and the third direction DR3 may be perpendicular. In this case, each of the plurality of contact holes 770 may be disposed on a vertex of a rectangle.

[0127] The opening region R2 of the second support member 720 may have a circular shape. However, the present disclosure is not limited thereto. That is, in some other exemplary embodiments, the opening region R2 of the second support member 720 may have, for example, a rectangular shape or a parallelogram shape. The lower electrode 730 may have a pillar shape to completely fill the inner portion of each of the plurality of contact holes 770.

[0128] In the following, reference is made to Figure 29 , a semiconductor device manufactured by a method of manufacturing a semiconductor device according to some other exemplary embodiments will be described. Figure 1 The difference between the semiconductor devices shown in .

[0129] Figure 29 are diagrams provided to explain a semiconductor device manufactured by a method of manufacturing the semiconductor device according to some other exemplary embodiments.

[0130] Reference Figure 29The semiconductor device may include a plurality of contact holes 870 spaced apart from each other. For example, the second contact hole 872 may be spaced apart from the first contact hole 871 in the first direction DR1. In addition, the third contact hole 873 may be spaced apart from the first contact hole 871 in the third direction DR3.

[0131] An angle formed by the first direction DR1 and the third direction DR3 may be perpendicular. In this case, each of the plurality of contact holes 870 may be disposed on a vertex of a rectangle.

[0132] The opening region R2 of the second support member 820 may have a circular shape. However, the present disclosure is not limited thereto. That is, in some other exemplary embodiments, the opening region R2 of the second support member 820 may have, for example, a rectangular shape or a parallelogram shape.

[0133] The lower electrode 830 may have a cylindrical shape conformally formed along a sidewall and a bottom surface of an inner portion of each of the plurality of contact holes 870 .

[0134] By way of summary and review, as the capacitance of semiconductor devices (eg, DRAM) increases, the aspect ratio of the cylindrical bottom electrode increases significantly. Therefore, the cylindrical bottom electrode may be tilted or broken before dielectric deposition.

[0135] In contrast, the present disclosure provides a method for manufacturing a semiconductor device, wherein an insulating layer and a mold layer are formed on a lower support pattern using separate processes, thereby preventing the formation of gaps between the lower support patterns. Furthermore, the present disclosure provides a method for manufacturing a semiconductor device, wherein an insulating layer having no dry etching selectivity difference relative to the lower support pattern is formed on the lower support pattern, thereby preventing a profile tilt phenomenon on the sidewall of the contact hole during an etching process for forming the contact hole.

[0136] Example embodiments have been disclosed herein, and although specific terms are employed, they are used and interpreted in a generic and descriptive sense only and not for purposes of limitation. In some examples, as will be apparent to one of ordinary skill in the art at the time of filing this application, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specifically noted. Therefore, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising the steps of: sequentially stacking a first mold layer and a first support layer on the substrate; forming a first support pattern by etching the first support layer to expose at least a portion of an upper surface of the first mold layer; forming an insulating layer to cover the exposed upper surface of the first mold layer and the first support member pattern; sequentially stacking a second mold layer and a second support layer on the insulating layer; dry-etching the second support layer, the second mold layer, the insulating layer, at least a portion of the first support pattern, and the first mold layer through a mask pattern to form a contact hole; forming a lower electrode in the contact hole; removing the first mold layer, the second mold layer and the insulating layer; as well as forming an upper electrode on the lower electrode and the first support pattern, During the dry etching, a dry etching rate of the first support pattern is the same as a dry etching rate of the insulating layer.

2. The method according to claim 1, wherein The first mold layer, the second mold layer, and the insulating layer are removed by wet etching, and a wet etching rate of the insulating layer is the same as a wet etching rate of the first mold layer.

3. The method according to claim 2, wherein: The insulating layer includes the same material as that of the first mold layer.

4. The method according to claim 1, wherein The insulating layer and the second mold layer are formed by processes different from each other.

5. The method according to claim 4, wherein: The insulating layer is formed by an atomic layer deposition process, and the second mold layer is formed by a chemical vapor deposition process.

6. The method of claim 1, wherein: The first support layer includes silicon oxycarbide (SiOC).

7. The method of claim 1, wherein: During the dry etching, a dry etching rate of the first support pattern is the same as a dry etching rate of the first mold layer.

8. The method of claim 1, wherein: The lower electrode is formed to completely fill an inner portion of the contact hole.

9. The method of claim 1, wherein: The lower electrode is formed along a sidewall and a bottom surface of the contact hole, and the upper electrode is formed to fill an inner portion of the contact hole on the lower electrode.

10. The method of claim 1, wherein: A lower surface of the insulating layer and a lower surface of the first support pattern are formed on the same plane.

11. A method for manufacturing a semiconductor device, the method comprising the steps of: sequentially stacking a first mold layer and a first support layer on the substrate; forming a first support pattern by etching the first support layer to expose at least a portion of an upper surface of the first mold layer; forming a first insulating layer to cover the exposed upper surface of the first mold layer and the first support member pattern; sequentially stacking a second mold layer, a second support layer, a third mold layer, and a third support layer on the first insulating layer; dry etching the third support layer, the third mold layer, the second support layer, the second mold layer, the first insulating layer, at least a portion of the first support pattern, and the first mold layer through a mask pattern to form a contact hole; forming a lower electrode in the contact hole; as well as removing the first mold layer, the second mold layer, the third mold layer and the first insulating layer, During the dry etching, a dry etching rate of the first support pattern is the same as a dry etching rate of the first insulating layer.

12. The method of claim 11, wherein: The step of sequentially stacking the second mold layer, the second support layer, the third mold layer, and the third support layer on the first insulating layer further includes: sequentially stacking the second mold layer and the second support layer on the first insulating layer; forming a second support member pattern by etching the second support member layer to expose at least a portion of the upper surface of the second mold layer; forming a second insulating layer to cover the exposed upper surface of the second mold layer and the second support pattern; and The third mold layer and the third support layer are formed on the second insulating layer.

13. The method of claim 12, wherein: The step of forming the contact hole further includes dry etching the second insulating layer, so that during the dry etching, a dry etching rate of the second support pattern is the same as a dry etching rate of the second insulating layer.

14. The method of claim 12, wherein: The second insulating layer includes the same material as that of the second mold layer.

15. The method of claim 12, wherein: The second support layer includes silicon oxycarbide (SiOC).

16. The method of claim 11, wherein: The first insulating layer and the second mold layer are formed by the same process.

17. The method of claim 11, wherein: A lower surface of the first insulating layer is formed closer to the substrate than a lower surface of the first supporter pattern.

18. A method for manufacturing a semiconductor device, the method comprising the steps of: sequentially stacking a first mold layer and a first support layer including silicon oxycarbide (SiOC) on a substrate; forming a first support pattern by etching the first support layer to expose at least a portion of an upper surface of the first mold layer; sequentially stacking a second mold layer and a second support member layer on the first support member pattern; dry-etching the second support layer, the second mold layer, at least a portion of the first support pattern, and the first mold layer through a mask pattern to form a contact hole; forming a lower electrode in the contact hole; as well as removing the first mold layer and the second mold layer, During the dry etching, a dry etching rate of the first support pattern is the same as a dry etching rate of the first mold layer.

19. The method according to claim 18, further comprising the steps of: forming an insulating layer to cover the exposed upper surface of the first mold layer and the first support pattern; and The second mold layer and the second support layer are sequentially stacked on the insulating layer.

20. The method of claim 19, wherein: The step of forming the contact hole further includes dry etching the insulating layer so that a dry etching rate of the first support pattern is the same as a dry etching rate of the insulating layer.

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