Chip Resistance Detection Device and Chip Device

Abstract

The present invention relates to a chip resistor detection device and a chip device. The device includes a current generation circuit, a voltage comparison circuit, and an output conversion circuit: The current generation circuit is used to connect an external resistor and generate a reference current; the reference current is the ratio of the bandgap reference voltage of the chip device under test to the resistance value of the external resistor. The current input terminal of the voltage comparison circuit is connected to the current output terminal of the current generation circuit, and is used to generate a test voltage corresponding to the reference current and output the comparison result between the test voltage and the bandgap reference voltage. The input terminal of the output conversion circuit is connected to the output terminal of the voltage comparison circuit, and is used to convert the comparison result into a digital signal and output it to the digital circuit of the chip device. Through the design of the current generation circuit, the voltage comparison circuit, and the output conversion circuit, the internal resistance detection process generates a reference current through the external resistor, and the detection process does not need to introduce the reference clock and register circuit inside the chip device, achieving the purpose of greatly reducing the detection power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of resistance detection, and particularly to a chip resistance detection device and a chip device. Background Art

[0002] Resistance detection technology is often applied to the detection of the actual resistance values of resistors on various chip devices, such as but not limited to chip devices such as ADC (Analog-to-digital converter) and PLL (Phase Locked Loop). Due to the limitations of chip production processes and the influence of temperature, the accuracy of passive components such as resistors on chips is relatively low. For example, the actual resistance value of a resistor usually varies by 20% or even more relative to its nominal value. Therefore, designers cannot accurately know the actual resistance value of the resistor inside the chip to make it equal to the nominal value, thereby ensuring the performance of the circuit on the chip.

[0003] In order to know the actual resistance value of the resistor inside the chip, the traditional resistance detection technology is to design a dedicated resistance detection device and use a reference resistor and introduce an internal reference clock and register circuit of the chip to test the internal resistance of the chip. However, in the process of implementing the invention, the inventor found that the traditional resistance detection technology has at least the problem of relatively high detection power consumption. Summary of the Invention

[0004] Based on this, it is necessary to provide a chip resistance detection device that can significantly reduce detection power consumption.

[0005] In order to achieve the above object, the embodiments of the present invention adopt the following technical solutions:

[0006] The embodiments of the present invention provide a chip resistance detection device, including:

[0007] A current generation circuit, configured to connect an external resistor and generate a reference current; the reference current is the ratio of the bandgap reference voltage of the chip device under test to the resistance value of the external resistor;

[0008] A voltage comparison circuit, with its current input terminal connected to the current output terminal of the current generation circuit, configured to generate a test voltage corresponding to the reference current and output a comparison result of the test voltage and the bandgap reference voltage;

[0009] An output conversion circuit, with its input terminal connected to the output terminal of the voltage comparison circuit, configured to convert the comparison result into a digital signal and output it to the digital circuit of the chip device.

[0010] In one of the embodiments, the voltage comparison circuit includes a resistor network unit and a comparator;

[0011] The input terminals of the resistor network unit are respectively connected to the current output terminal of the current generation circuit and the positive input terminal of the comparator. The output terminal of the resistor network unit is grounded. The negative input terminal of the comparator is used to connect the bandgap reference voltage, and the output terminal of the comparator is connected to the input terminal of the output conversion circuit.

[0012] In one embodiment, the resistor network unit includes a first resistor network and a first switch group. The first resistor network includes N resistors R0 connected in series in sequence. The first switch group includes N gating switches K1 corresponding to the resistors R0 one by one, where N is a positive integer greater than or equal to 2.

[0013] The input terminals of the first resistor network are respectively connected to the current output terminal of the current generation circuit and the positive input terminal of the comparator, and the output terminal of the first resistor network is grounded.

[0014] One end of each gating switch K1 is connected to the input terminal of the first resistor network, and the other end of each gating switch K1 is respectively connected to the output terminal of the corresponding resistor R0.

[0015] In one embodiment, the resistor network unit further includes a second resistor network and a second switch group. The second resistor network includes M sub-networks connected in series in sequence. Any one of the sub-networks includes a plurality of resistors R1 connected in parallel. The second switch group includes M gating switches K2 corresponding to the sub-networks one by one, where M is a positive integer greater than or equal to 1.

[0016] The input terminal of the second resistor network is connected to the output terminal of the first resistor network, the output terminal of the second resistor network is grounded, and each gating switch K2 is respectively connected in parallel with the resistor R1 of the corresponding sub-network.

[0017] In one embodiment, the resistor network unit further includes a grounding resistor R2, and the output terminal of the second resistor network is grounded through the grounding resistor R2. The number of resistors R1 connected in parallel in each sub-network is different. The gating switch K1 is a field effect transistor or a switching triode, and the gating switch K2 is a field effect transistor or a switching triode.

[0018] In one embodiment, the current generation circuit includes an operational amplifier, a current mirror MP0, a current mirror MP2, a current mirror MP1, a current mirror MP3, and an ESD protection circuit.

[0019] The negative input terminal of the operational amplifier is used to connect the bandgap reference voltage, and the output terminal of the operational amplifier is respectively connected to the gates of the current mirror MP0 and the current mirror MP2.

[0020] The sources of the current mirror MP0 and the current mirror MP2 are respectively used to connect to the power supply. The drain of the current mirror MP0 is connected to the source of the current mirror MP1, and the drain of the current mirror MP2 is connected to the source of the current mirror MP3.

[0021] The gates of current mirror MP1 and current mirror MP3 are respectively connected to the non-inverting input terminal of the operational amplifier. The drain of current mirror MP1 is used to connect an external resistor, and the drain of current mirror MP3 is connected to the current input terminal of the voltage comparison circuit;

[0022] The ESD protection circuit is connected in parallel between the gate and the drain of current mirror MP1, and is used for overvoltage protection of current mirror MP1.

[0023] In one embodiment, the ESD protection circuit includes a protection resistor Rs and a secondary ESD protection tube Q; the secondary ESD protection tube Q is a diode or a field effect transistor MN;

[0024] One end of the protection resistor Rs is connected to the gate of current mirror MP1, and the other end of the protection resistor Rs is connected to the drain of current mirror MP1;

[0025] The negative terminal of the secondary ESD protection tube Q is connected to one end of the protection resistor Rs, and the positive terminal of the secondary ESD protection tube Q is grounded.

[0026] In one embodiment, the output conversion circuit includes current mirror MP4, current mirror MP5, current mirror MP6, current mirror MN1, current mirror MN2, and current mirror MN3;

[0027] The collectors of current mirror MP4, current mirror MP5, and current mirror MP6 are respectively used to connect the digital-to-analog conversion reference voltage. The gates of current mirror MP4 and current mirror MN1 are connected and connected to the output terminal of the voltage comparison circuit. The drains of current mirror MP6 and current mirror MN3 are connected and used to connect the digital circuit of the chip under test;

[0028] The drains of current mirror MP4 and current mirror MN1 are connected, and are respectively connected to the gates of current mirror MP5 and current mirror MN2. The drains of current mirror MP5 and current mirror MN2 are connected, and are respectively connected to the gates of current mirror MP6 and current mirror MN3;

[0029] The sources of current mirror MN1, current mirror MN2, and current mirror MN3 are all grounded.

[0030] In one embodiment, the output conversion circuit further includes current mirror MN4;

[0031] The source of current mirror MN4 is respectively connected to the gates of current mirror MP4 and current mirror MN1. The gate of current mirror MN4 is connected to the output terminal of the voltage comparison circuit. The drain of current mirror MN4 is used to connect the digital-to-analog conversion reference voltage.

[0032] On the other hand, a chip device is also provided, including the above-mentioned chip resistance detection device.

[0033] One of the above technical solutions has the following advantages and beneficial effects:

[0034] The above chip resistor detection device and chip device, through the design of the current generation circuit, voltage comparison circuit and output conversion circuit, the reference current generated when the current generation circuit is externally connected to a resistor has eliminated the error influence brought by the parasitic resistor; after the reference current is input into the voltage comparison circuit, a corresponding test voltage is generated, and the voltage comparison circuit compares the test voltage with the bandgap reference voltage of the chip device to be measured. The output comparison result is digitally converted by the output conversion circuit and then output to the digital circuit of the chip device, so that the digital circuit can output the actual resistance value of the internal resistor of the chip device according to the digital signal corresponding to the comparison result. In this way, during the detection process of the internal resistor, the required reference current can be directly generated by externally connecting a resistor, and there is no longer a need to rely on the bandgap reference voltage inside the chip device to generate the reference current. The reference current has high precision and does not introduce the internal reference clock and register circuit of the chip device, which can minimize the detection cost and detection power consumption and achieve the purpose of significantly reducing the detection power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0036] Figure 1 It is a schematic structural diagram of a chip resistor detection device in an embodiment;

[0037] Figure 2 It is a schematic structural diagram of a chip resistor detection device in another embodiment;

[0038] Figure 3 It is a schematic structural diagram of a voltage comparison circuit in an embodiment;

[0039] Figure 4 It is a schematic structural diagram of a voltage comparison circuit in another embodiment;

[0040] Figure 5 It is a schematic structural diagram of a current generation circuit in an embodiment;

[0041] Figure 6 It is a schematic structural diagram of a current generation circuit in another embodiment;

[0042] Figure 7 It is a schematic structural diagram of an output conversion circuit in an embodiment;

[0043] Figure 8 It is a schematic structural diagram of an output conversion circuit in another embodiment. Detailed implementation manners

[0044] For ease of understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application is more thorough and comprehensive.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0046] It can be understood that the terms "first", "second", etc. used in this application can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first resistor can be called a second resistor, and similarly, a second resistor can be called a first resistor. Both the first resistor and the second resistor are resistors, but they are not the same resistor.

[0047] It can be understood that in the following embodiments, "connection", if there is an electrical signal or data transmission between the connected circuits, modules, units, etc., should be understood as "connection", "communication connection", etc.

[0048] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising", "including" or "having", etc. specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof.

[0049] As Figure 1 shown, in an embodiment, a chip resistor detection device 100 is provided, which includes a current generation circuit 12, a voltage comparison circuit 14, and an output conversion circuit 16. The current generation circuit 12 is used to connect an external resistor and generate a reference current; wherein, the reference current is the ratio of the bandgap reference voltage of the chip device under test to the resistance value of the external resistor. The current input terminal of the voltage comparison circuit 14 is connected to the current output terminal of the current generation circuit 12, and is used to generate a test voltage corresponding to the reference current and output the comparison result of the test voltage and the bandgap reference voltage. The input terminal of the output conversion circuit 16 is connected to the output terminal of the voltage comparison circuit 14, and is used to convert the comparison result into a digital signal and output it to the digital circuit of the chip device.

[0050] It can be understood that the external resistor is an external resistor used to detect the internal resistance value of the chip device, and the corresponding resistance value of the external resistor can be selected according to the nominal resistance value of the internal resistance of different chip devices. The connection method of the external resistor can be the same as that in the traditional resistor detection device and method. The voltage across the external resistor remains consistent with the bandgap reference voltage inside the chip device, and when the current generation circuit 12 is connected to the external resistor, it is used to generate a reference current across the external resistor according to Ohm's law.

[0051] In the bias current generation circuit 12 in the traditional resistor detection device and method, the non-inverting input terminal of the operational amplifier in the circuit is directly connected to the drain of the current mirror. Since there is a metal connection line between the connection point and the pin (PAD) of the chip device, when the metal connection line is long, the magnitude of the parasitic resistance Rp generated by it will reach the ohm level. Therefore, the reference current generated by the traditional bias current generation circuit 12 is actually the bandgap reference voltage VREF divided by the sum of the resistance value of the parasitic resistance and the resistance value of the external resistor, resulting in an error in the generated reference current. When the resistance value of the external resistor is smaller, this error is more obvious, and the error in detecting the resistance value of the internal resistance of the chip device is also larger. The connection method of the external resistor in this application can be the same as that in the traditional resistor detection device and method.

[0052] In this application, the influence of this parasitic resistance is considered in the designed current generation circuit 12 to ensure that the generated reference current is the ratio of the bandgap reference voltage of the chip device under test to the resistance value of the external resistor, avoiding the influence of the parasitic resistance. For example, through circuit design, the non-inverting input terminal of the operational amplifier in the circuit and the current mirror are directly connected at the PAD head of the chip device, so that the generated reference current is the ratio of the bandgap reference voltage VREF to the resistance value of the external resistor, and no longer contains the component of the parasitic resistance.

[0053] The reference voltage applied to the current generation circuit 12 is equal in magnitude to the bandgap reference voltage inside the chip device and can be directly provided by an external voltage source. The bandgap reference voltage connected to the voltage comparison circuit 14 is the bandgap reference voltage inside the chip device and can be directly connected from the chip device. The digital circuit of the chip device is the controller circuit of the chip device, which undertakes processor functions such as calculation, control, and input / output of the chip device. The specific functions implemented by the digital circuits of different types of chip devices are different and are not specifically limited in this specification.

[0054] Specifically, when it is necessary to detect the internal resistance of a chip device, an external resistor is connected to the current generation circuit 12 to generate a reference current from outside the chip device that does not rely on the bandgap reference voltage inside the chip device. After this reference current is input into the voltage comparison circuit 14, a corresponding voltage drop, i.e., the test voltage, is generated across the resistor inside the voltage comparison circuit 14. This test voltage will be compared by the voltage comparison circuit 14 with the bandgap reference voltage inside the chip device, and the comparison result is output in the form of an analog electrical signal. The analog electrical signal is converted into a corresponding digital signal by the output conversion circuit 16 and then sent to the digital circuit of the chip device. The digital circuit of the chip device can then determine the actual resistance value of the internal resistance of the chip device from this digital signal and determine the difference between the actual resistance value of the internal resistance of the chip device and its nominal value. At the same time, due to the signal conversion and output of the output conversion circuit 16, it can also prevent the influence of the subsequent circuit on the previous circuit, thus playing a good signal isolation role.

[0055] For the above-mentioned voltage comparison circuit 14, the resistor inside it can be a fixed value or a variable resistance value. When an external resistor with a certain resistance value is connected, the resistance value of the internal resistor of the voltage comparison circuit 14 can be adjusted so that the voltage comparison circuit 14 outputs different comparison results accordingly, until the output comparison result corresponds to the test voltage being equal to the bandgap reference voltage inside the chip device. The digital circuit of the chip device can then correspondingly detect the actual resistance value of the internal resistance of the chip device. Correspondingly, the resistance value of the internal resistor of the voltage comparison circuit 14 can be fixed, and by replacing external resistors with different resistance values, it is also possible to make the voltage comparison circuit 14 output different comparison results accordingly, until the output comparison result corresponds to the test voltage being equal to the bandgap reference voltage inside the chip device. The digital circuit of the chip device can then correspondingly detect the actual resistance value of the internal resistance of the chip device. In this way, for the above two detection operation methods, the first detection method can quickly obtain the deviation between the actual resistance value of the internal resistance of the chip device and its nominal value, and the second detection method can also screen external resistors in reverse. Thus, based on the principle of using an external resistor and generating a corresponding reference current, the above-mentioned chip resistance detection device 100 synchronously generates the current bias required by the device and also has the function of resistor selection. During the above detection process, the accuracy of the reference current generated externally is guaranteed, and the internal reference clock and register circuit of the chip device are not introduced, achieving the effects of low cost and low power consumption for the detection.

[0056] The above chip resistor detection device 100, through the design of the current generation circuit 12, the voltage comparison circuit 14, and the output conversion circuit 16, the reference current generated when the current generation circuit 12 is externally connected to a resistor has eliminated the error influence brought by the parasitic resistor; after the reference current is input into the voltage comparison circuit 14, a corresponding test voltage is generated. The voltage comparison circuit 14 compares the test voltage with the bandgap reference voltage of the chip device to be measured, and the output comparison result is digitally converted by the output conversion circuit 16 and then output to the digital circuit of the chip device, so that the digital circuit can output the actual resistance value of the internal resistance of the chip device according to the digital signal corresponding to the comparison result. In this way, during the detection process of the internal resistance, the required reference current can be directly generated by externally connecting a resistor, and there is no longer a need to rely on the bandgap reference voltage inside the chip device to generate the reference current. The reference current has high precision and does not introduce the internal reference clock and register circuit of the chip device, which can minimize the detection cost and detection power consumption, achieving the purpose of significantly reducing the detection power consumption.

[0057] As Figure 2 shown, in one embodiment, the voltage comparison circuit 14 includes a resistor network unit 142 and a comparator 144. The input terminals of the resistor network unit 142 are respectively connected to the current output terminal of the current generation circuit 12 and the positive input terminal of the comparator 144, and the output terminal of the resistor network unit 142 is grounded. The negative input terminal of the comparator 144 is used to access the bandgap reference voltage, and the output terminal of the comparator 144 is connected to the input terminal of the output conversion circuit 16.

[0058] It can be understood that the voltage comparison circuit 14 internally includes two circuit components. Among them, the resistor network unit 142 is a resistor network composed of several resistors in series and / or parallel. The resistor network unit 142 is used to generate a corresponding voltage drop after accessing the reference current generated by the current generation circuit 12, that is, to generate a corresponding test voltage to be applied to the positive input terminal of the comparator 144. The resistance value of the resistor connected to the resistor network unit 142 can be fixed or adjustable in multiple steps. The total resistance value (or the maximum resistance value) of the resistor network unit 142 can be specifically determined according to the estimated situation of the actual resistance value of the internal resistance of the chip device to be measured, as long as it can meet the detection requirements of the internal resistance value of the chip device.

[0059] The comparator 144 is a voltage comparator CMP (comparator), and it can be various types of voltage comparators 144 in the art. Specifically, it can be selected according to the detection requirements of the internal resistance value of the chip device and / or the design specifications of the chip resistor detection device 100 (such as cost and volume size, etc.).

[0060] Specifically, the reference current generated by the current generation circuit 12 passes through the resistor network unit 142 to generate a corresponding voltage drop, which is the test voltage input to the non-inverting input terminal of the comparator 144 and is compared with the bandgap reference voltage at the inverting input terminal of the comparator 144. When the test voltage is equal to the bandgap reference voltage, the output of the comparator 144 will flip to output the comparison result of the pair. This comparison result is level-converted by the output conversion circuit 16 and then sent to the digital circuit of the chip device for processing to determine the deviation between the actual resistance value and the nominal value of the internal resistance of the chip device.

[0061] By adopting the resistor network unit 142 and the comparator 144 and working in coordination with the current generation circuit 12 and the output conversion circuit 16, the comparison output of the test voltage and the bandgap reference voltage inside the chip device can be realized to obtain the accurate resistance value of the internal resistance of the chip device, without the need to introduce the internal reference clock and register circuit of the chip device. The circuit structure is simple and the detection power consumption is effectively reduced significantly.

[0062] As Figure 3 shown, in one embodiment, the resistor network unit 142 includes a first resistor network 1422 and a first switch group 1424. The first resistor network 1422 includes N resistors R0 connected in series in sequence, and the first switch group 1424 includes N gating switches K1 corresponding to the resistors R0 one by one; where N is a positive integer greater than or equal to 2. The input terminal of the first resistor network 1422 is respectively connected to the current output terminal of the current generation circuit 12 and the non-inverting input terminal of the comparator 144, and the output terminal of the first resistor network 1422 is grounded. One end of each gating switch K1 is connected to the input terminal of the first resistor network 1422, and the other end of each gating switch K1 is respectively connected to the output terminal of the corresponding resistor R0.

[0063] It should be noted that Figure 3 the circuit example shown in

[0064] Specifically, after the reference current IB is input, by selecting different gating switches K1, different test voltages can be generated and applied to the non-inverting input terminal of the comparator 144 for comparison with the bandgap reference voltage at the inverting input terminal of the comparator 144. When the test voltage is equal to the bandgap reference voltage, the comparator 144 flips and outputs the corresponding comparison result (output signal). The total resistance value of the resistor R0 connected through the gating switch K1 can be used to obtain the true resistance value deviation between the external resistor and the internal resistor of the chip device. At this time, the comparison result corresponding to the actual resistance value connected through the gating switch K1 on the external resistor and the first resistor network 1422 can accurately reflect the internal resistance of the chip device.

[0065] By adopting the above design of the voltage comparison circuit 14 composed of the first resistor network 1422 and the first switch group 1424, the accurate detection of the internal resistance of the chip device can be effectively realized, and the detection adaptability is relatively strong, which can support the detection of chip devices with different internal resistance sizes and the selection of external resistors with different resistance values.

[0066] As Figure 4 shown, in one embodiment, the resistor network unit 142 further includes a second resistor network 1426 and a second switch group 1428. The second resistor network 1426 includes M sub-networks connected in series in sequence, and any sub-network includes a plurality of resistors R1 connected in parallel. The second switch group 1428 includes M gating switches K2 corresponding to the sub-networks one by one, and M is a positive integer greater than or equal to 1. The input terminal of the second resistor network 1426 is connected to the output terminal of the first resistor network 1422, and the output terminal of the second resistor network 1426 is grounded. Each gating switch K2 is respectively connected in parallel with the resistor R1 of the corresponding sub-network.

[0067] It can be understood that in this embodiment, the resistor R1 can be the same as the resistor R0 (resistance value and / or type) used in the first resistor network 1422 (more efficient chip layout), or different from the resistor R0; the resistors R1 can be resistors with the same resistance value or resistors with different resistance values. The number of resistors R1 connected in parallel in each sub-network can be the same or different, and the specific number of resistors R1 connected in parallel in each sub-network can be determined according to the detection requirements of the internal resistance value of the chip device, as long as the test voltage can be made equal to the bandgap reference voltage of the chip device to be detected to obtain the accurate internal resistance value of the chip device. It should be noted that Figure 4 only shows a circuit example of one structure of the first resistor network 1422 and the second resistor network 1426, rather than the only circuit structure design. Those skilled in the art can appropriately expand or reduce the devices under the guidance of the design concept of this application to meet the detection requirements of chip devices with different internal resistance values.

[0068] The gating switch K2 can be a manually operated mechanical switch or an electrically controlled switch, which is used to respectively realize the access and short - circuit control of each corresponding sub - network, so as to change the total access resistance value of the second resistor network 1426 and cooperate with the first resistor network 1422 to realize the adjustment of the test voltage magnitude.

[0069] Specifically, in this embodiment, the above - mentioned first resistor network 1422 and the first switch group 1424 can be used as the coarse - adjustment part, while the second resistor network 1426 and the second switch group 1428 can be used as the fine - adjustment part. During the test, the gating switches K1 can be respectively gated first, and the actual resistance value range of the internal resistance of the chip device can be preliminarily determined from the output inversion of the comparator 144. When the total resistance value of the first resistor network 1422 corresponding to a certain gating switch K1 is the minimum deviation value between the external resistance value and the actual resistance value of the internal resistance of the chip device, the gating switches K2 are further respectively tried for fine - adjustment until the test voltage on the comparator 144 is equal to the bandgap reference voltage and an output inversion occurs; at this time, the total resistance values of the two resistor networks corresponding to the gated gating switch K1 and the gating switch K2 accurately reflect the true resistance deviation between the external resistance and the internal resistance of the chip device, and the corresponding comparison result is sent to the digital circuit of the chip device after level conversion, and the digital circuit can know the actual resistance value of the internal resistance of the chip device during the current detection.

[0070] By adopting the multi - stage design structure of the above - mentioned first resistor network 1422 and the first switch group 1424, as well as the second resistor network 1426 and the second switch group 1428, more accurate detection of the internal resistance of the chip device can be realized, and it can better adapt to the detection of the actual resistance value change of the internal resistance of the chip device at different usage times; when the total resistance value of the two resistor networks is fixed, on the contrary, accurate selection of external resistors with different resistance values can be realized.

[0071] As Figure 4 shown, in one embodiment, the resistor network unit 142 further includes a grounding resistor R2. The output end of the second resistor network 1426 is grounded through the grounding resistor R2. The number of parallel resistors R1 in each sub - network is different.

[0072] It can be understood that the resistance value of the grounding resistor R2 is greater than that of the resistor R0. Generally but not limited to, the resistance value of the grounding resistor R2 is selected to be 12 times that of R0, and reliable and safe grounding of the entire circuit can be achieved. Those skilled in the art can understand that the grounding resistor can also be set in the form of a resistor network. For example, a grounding resistor network is formed by several resistors in series and / or parallel, and can be specifically determined according to the grounding reliability requirements of the voltage comparison circuit 14, as long as it can effectively provide the required grounding protection. By setting the grounding resistor R2, the reliability and safety of the entire voltage comparison circuit 14 can be greatly improved, thereby achieving the effect of better improving the reliability of the entire chip resistance detection device 100.

[0073] In one embodiment, the resistance value R0 can be a 20KΩ resistor, and the resistance value R1 is the same as that of R0. It can be understood that in the above embodiment, the resistance value R0 is, for example, a 20KΩ resistor or a resistor with other resistance values, as long as it can achieve the effect of quickly detecting the internal resistance value. In this embodiment, the resistors in both resistor networks adopt the same resistance value resistor R0, and the circuit design and production are more efficient.

[0074] In one embodiment, as Figure 4 shown, the selection switch K1 is a field effect transistor or a switching triode. The selection switch K2 is a field effect transistor or a switching triode.

[0075] It can be understood that in this embodiment, the selection switch K1 and the selection switch K2 can adopt the same type of electric control switch. For example, they can both be field effect transistors, or they can both be switching triodes. As Figure 4 shown is an application example when field effect transistors are used as the selection switches K1 and K2. The gates (or bases) of these switching devices can be used to respectively access the control levels (such as 0 or 1) provided by an external register to achieve selection or cut-off control, thereby realizing the resistance value adjustment of the resistor network unit 142. As Figure 4 shown in the circuit, field effect transistors are taken as an example.

[0076] By applying the above-mentioned field effect transistor or switching triode, the resistance value regulation of the resistor network unit 142 can be conveniently realized, the response speed of the detection operation can be improved, and the detection efficiency can be enhanced.

[0077] As Figure 5As shown, in one embodiment, the current generation circuit 12 includes an operational amplifier, current mirrors MP0, MP2, MP1, and MP3, and an ESD protection circuit. The inverting input terminal of the operational amplifier is used to connect to a bandgap reference voltage, and the output terminal of the operational amplifier is respectively connected to the gates of current mirrors MP0 and MP2. The source terminals of current mirrors MP0 and MP2 are respectively used to connect to a power supply. The drain of current mirror MP0 is connected to the source of current mirror MP1, and the drain of current mirror MP2 is connected to the source of current mirror MP3. The gates of current mirrors MP1 and MP3 are respectively connected to the non-inverting input terminal of the operational amplifier. The drain of current mirror MP1 is used to connect to an external resistor. The drain of current mirror MP3 is connected to the current input terminal of the voltage comparison circuit 14. The ESD protection circuit is connected in parallel between the gate and the drain of current mirror MP1 for overvoltage protection of current mirror MP1.

[0078] Among them, the inverting input terminal of the operational amplifier (i.e., AMP) is used to connect to a reference voltage VREF, which can be provided by an external voltage source and is kept consistent with the bandgap reference voltage inside the chip device. The ESD protection circuit can be various types of ESD protection circuits commonly used in the art, and can be specifically selected according to the working environment of current mirror MP1, as long as it can provide the required effective protection to prevent current mirror MP1 from being broken down.

[0079] It can be understood that the non-inverting input terminal of the operational amplifier and current mirror MP0 are directly connected at the PAD head of the chip device, so that the parasitic resistance of the wire connection between current mirror MP0 and the PAD is so small that it can be ignored, thereby ensuring that the generated reference current is not affected by the error caused by the parasitic resistance and ensuring the accuracy of the resistance value detection of the internal resistor of the chip device. The power supply refers to each VDD, which can be the device power supply on the circuit board where the chip resistance detection device 100 is located, or the device power supply led out from the chip device to be measured. Its specific voltage value can be determined according to the working needs of each device.

[0080] Specifically, when it is necessary to detect the internal resistance of the chip device, an external resistor (i.e., resistor Rext) is connected to the current generation circuit 12, and through the control of the operational amplifier on each current mirror, a required high-precision reference current IB can be generated. The reference current IB is sent from the drain of current mirror MP3 to the voltage comparison circuit 14 for processing. Through the above-mentioned current generation circuit 12, the generation of a high-precision reference current can be achieved by connecting an external resistor, and different external resistors can be selected by using the chip resistance detection device 100 by replacing external resistors with different resistance values.

[0081] Such as Figure 6As shown, in one embodiment, the ESD protection circuit includes a protection resistor Rs and a secondary ESD protection transistor Q. One end of the protection resistor Rs is connected to the gate of the current mirror MP1, and the other end of the protection resistor Rs is connected to the drain of the current mirror MP1. The negative terminal of the secondary ESD protection transistor Q is connected to one end of the protection resistor Rs, and the positive terminal of the secondary ESD protection transistor Q is grounded.

[0082] It can be understood that in this embodiment, a specific ESD protection circuit is provided. Among them, the secondary ESD protection transistor Q can be various types of semiconductor transistors with a unidirectional conduction function in the art. The protection resistor Rs and the secondary ESD protection transistor Q together form a two-stage ESD protection circuit. Those skilled in the art can understand that the other end of the protection resistor Rs is indirectly connected to the drain of the current mirror MP1, that is, indirectly connected to the drain of the current mirror MP1 through the PAD pin of the chip device. The specific model and electrical parameters of the protection resistor Rs and the secondary ESD protection transistor Q can be determined according to the working environment requirements of each device in the current generation circuit 12.

[0083] Specifically, when the current generation circuit 12 is operating, if the voltage between the gate and drain of the current mirror MP1 is too high, double voltage discharge can be directly performed through the protection resistor Rs and the secondary ESD protection transistor Q to avoid breakdown of the current mirror MP1. Through the above two-stage protection circuit design, the device protection function of the current generation circuit 12 can be realized more reliably, thereby further improving the reliability of the chip resistance detection device 100.

[0084] As Figure 6 shown, in one embodiment, the secondary ESD protection transistor Q is a diode or a field effect transistor MN. Among them, the drain of the field effect transistor MN is connected to one end of the protection resistor Rs, and the gate and source of the field effect transistor MN are connected together and grounded.

[0085] Optionally, in this embodiment, a diode can be directly used as the required secondary ESD protection transistor Q, and the negative electrode of the diode is connected to one end of the protection resistor Rs, and the negative electrode of the diode is grounded. Or a field effect transistor MN can be used as the required secondary ESD protection transistor Q. Those skilled in the art can understand that in the current generation circuit 12 as Figure 6 described, an N-channel field effect transistor MN is used as an application example. In actual applications, a P-channel field effect transistor can also be used and the wiring polarity can be adjusted adaptively.

[0086] By applying a diode or a field effect transistor MN as the secondary ESD protection transistor Q, the circuit has good protection effect, high reliability and low cost, and can effectively achieve the device protection effect required by the current generation circuit 12.

[0087] As Figure 7As shown, in one embodiment, the output conversion circuit 16 includes current mirrors MP4, MP5, MP6, MN1, MN2, and MN3. The collectors of current mirrors MP4, MP5, and MP6 are respectively used to connect to the digital-to-analog conversion reference voltage. The gates of current mirrors MP4 and MN1 are connected and connected to the output terminal of the voltage comparison circuit 14. The drains of current mirrors MP6 and MN3 are connected and used to connect to the digital circuit of the chip under test. The drains of current mirrors MP4 and MN1 are connected and respectively connected to the gates of current mirrors MP5 and MN2. The drains of current mirrors MP5 and MN2 are connected and respectively connected to the gates of current mirrors MP6 and MN3. The sources of current mirrors MN1, MN2, and MN3 are all grounded.

[0088] Among them, the above-mentioned current mirrors MP4 and MN1 are high-voltage transistors, and current mirrors MP5, MP6, MN2, and MN3 are relatively low-voltage transistors, so as to ensure the reliable operation of the entire output conversion circuit 16 and realize the analog-to-digital conversion of the comparison result output by the voltage comparison circuit 14. The digital-to-analog conversion reference voltage refers to Figure 7 the voltage DVDD (i.e., Digital VDD, digital power supply) shown in, which can be directly obtained from the chip device under test or provided by an external device power supply. The specific voltage value can be determined according to the working requirements of each current mirror.

[0089] By adopting the above typical output conversion circuit 16 structure design, the analog-to-digital conversion output of the comparison result can be efficiently realized. The circuit structure is simple and the cost is not high, so that the production cost of the chip resistance detection device 100 can be reduced and the circuit volume can be reduced.

[0090] As Figure 8 shown, in one embodiment, the output conversion circuit 16 further includes a current mirror MN4. The source of the current mirror MN4 is respectively connected to the gates of the current mirrors MP4 and MN1. The gate of the current mirror MN4 is connected to the output terminal of the voltage comparison circuit 14. The drain of the current mirror MN4 is used to connect to the digital-to-analog conversion reference voltage.

[0091] It can be understood that the gates of the above-mentioned current mirrors MP4 and MN1 can be indirectly connected to the output terminal of the voltage comparison circuit 14 through the current mirror MN4. By adding the current mirror MN4, an initialization state can be provided when the entire chip detection device 100 is just powered on and started, and the circuit startup speed of the device can be accelerated, so as to further improve the chip resistance detection efficiency.

[0092] The above chip resistor detection device 100 can be applied to chip devices such as ADC chips or PLL chips. The chip resistor detection device 100 can be integrated inside the chip device for use, or can be separately integrated and packaged as an independent detection device. It can be used to detect the internal resistance values of one or more types of chip devices. The specific application setting method can be flexibly selected according to the requirements of the application scenario. It should be noted that the semiconductor device types shown in the drawings of the above embodiments are only illustrative and not the only limitation, such as each gating switch, current mirror, and ESD protection circuit, etc. Those skilled in the art can understand that semiconductor devices generally include two types: N-channel and P-channel. Therefore, under the guidance of the design concept of this application, devices of N-channel or P-channel can be selected according to needs, and the same or better effects can also be achieved.

[0093] In one embodiment, the present application also provides a chip device, which includes the above chip resistor detection device 100.

[0094] It can be understood that the chip device in this embodiment can be, but is not limited to, chip devices such as ADC chips or PLL chips, and the above chip resistor detection device 100 is integrated in these chip devices. For the explanation of the chip resistor detection device 100 in this embodiment, it can be understood in the same way by referring to the explanations of the above embodiments of the chip resistor detection device 100, and will not be repeated here.

[0095] By applying the above chip resistor detection device 100, when the chip device performs internal resistance detection, only an external resistor needs to be connected to generate a reference current that depends on the reference clock and bandgap reference voltage of the chip device, eliminating the error caused by parasitic resistance; the reference current is input into the voltage comparison circuit 14 of the chip resistor detection device 100 to generate a corresponding test voltage. The voltage comparison circuit 14 compares the test voltage with the bandgap reference voltage of the chip device to be measured. The output comparison result is digitally converted by the output conversion circuit 16 and then output to the digital circuit of the chip device, so that the digital circuit can output the actual resistance value of the internal resistance of the chip device according to the digital signal corresponding to the comparison result.

[0096] In this way, during the detection process of the internal resistance, the required reference current can be directly generated through the external resistor, and it is no longer necessary to rely on the bandgap reference voltage inside the chip device to generate the reference current. The reference current has high precision and does not introduce the reference clock and register circuit inside the chip device, which can minimize the detection cost and detection power consumption, achieving the purpose of significantly reducing the detection power consumption, thereby greatly improving the stability and reliability of the entire controller system where the chip device is located.

[0097] In the description of this specification, the descriptions referring to terms such as "one embodiment", "another embodiment", "an embodiment", etc. mean that the specific features, structures, materials or characteristics described in connection with that embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0098] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as falling within the scope described in this specification.

[0099] The above-described embodiments only represent several implementation manners of the present invention. The descriptions are relatively specific and detailed, but should not be construed as limiting the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present invention, several modifications and improvements can still be made, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the appended claims.

Claims

1. A chip resistor detection device, characterized in that, Comprising: A current generation circuit for connecting an external resistor to generate a reference current; The reference current is the ratio of the bandgap reference voltage of the device under test chip to the resistance value of the external resistor; A voltage comparison circuit, the current input terminal of which is connected to the current output terminal of the current generation circuit, and which includes a resistor network unit and a comparator; The input terminals of the resistor network unit are respectively connected to the current output terminal of the current generation circuit and the non-inverting input terminal of the comparator, the output terminal of the resistor network unit is grounded, the inverting input terminal of the comparator is used to access the bandgap reference voltage, and the output terminal of the comparator is connected to the input terminal of the output conversion circuit; there is a cooperation relationship between the external resistor and the resistor network unit; the cooperation relationship indicates the common adjustment of the external resistor and the resistor network unit to the test voltage; the voltage comparison circuit is used to generate the test voltage corresponding to the reference current on the basis of the cooperation relationship and output the comparison result between the test voltage and the bandgap reference voltage; An output conversion circuit, the input terminal of which is connected to the output terminal of the voltage comparison circuit, and which is used to convert the comparison result into a digital signal and output it to the digital circuit of the chip device.

2. The chip resistor detection device according to claim 1, characterized in that, The resistor network unit includes a first resistor network and a first switch group; the first resistor network includes N resistors R0 connected in series in sequence, and the first switch group includes N selection switches K1 corresponding one-to-one to the resistor R0, where N is a positive integer greater than or equal to 2; The input terminals of the first resistor network are respectively connected to the current output terminal of the current generation circuit and the non-inverting input terminal of the comparator, and the output terminal of the first resistor network is grounded; One end of each of the selection switches K1 is connected to the input terminal of the first resistor network, and the other end of each of the selection switches K1 is respectively connected to the output terminal of the corresponding resistor R0.

3. The chip resistor detection device according to claim 2, wherein The resistor network unit further includes a second resistor network and a second switch group; the second resistor network includes M sub-networks connected in series in sequence, and any one of the sub-networks includes a plurality of resistors R1 connected in parallel, and the second switch group includes M selection switches K2 corresponding one-to-one to the sub-networks, where M is a positive integer greater than or equal to 1; The input terminal of the second resistor network is connected to the output terminal of the first resistor network, the output terminal of the second resistor network is grounded, and each of the selection switches K2 is connected in parallel with the resistor R1 of the corresponding sub-network.

4. The chip resistor detection device according to claim 3, characterized in that, The resistor network unit further includes a grounding resistor R2, and the output terminal of the second resistor network is grounded through the grounding resistor R2; the number of the resistors R1 connected in parallel in each of the sub-networks is different; the selection switch K1 is a field effect transistor or a switching triode, and the selection switch K2 is a field effect transistor or a switching triode.

5. The chip resistor detection device according to any one of claims 1 to 4, characterized in that, The current generation circuit includes an operational amplifier, a current mirror MP0, a current mirror MP2, a current mirror MP1, a current mirror MP3, and an ESD protection circuit; The inverting input terminal of the operational amplifier is used to access the bandgap reference voltage, and the output terminal of the operational amplifier is respectively connected to the gates of the current mirror MP0 and the current mirror MP2; The sources of the current mirror MP0 and the current mirror MP2 are respectively used to connect to a power supply. The drain of the current mirror MP0 is connected to the source of the current mirror MP1, and the drain of the current mirror MP2 is connected to the source of the current mirror MP3; The gates of the current mirror MP1 and the current mirror MP3 are respectively connected to the non-inverting input terminal of the operational amplifier. The drain of the current mirror MP1 is used to connect to the external resistor, and the drain of the current mirror MP3 is connected to the current input terminal of the voltage comparison circuit; The ESD protection circuit is connected in parallel between the gate and the drain of the current mirror MP1 and is used to protect the current mirror MP1 against overvoltage.

6. The chip resistor detection device according to claim 5, wherein, The ESD protection circuit includes a protection resistor Rs and a secondary ESD protection tube Q; the secondary ESD protection tube is a diode or a field effect transistor MN; One end of the protection resistor Rs is connected to the gate of the current mirror MP1, and the other end of the protection resistor Rs is connected to the drain of the current mirror MP1; The negative terminal of the secondary ESD protection tube Q is connected to one end of the protection resistor Rs, and the positive terminal of the secondary ESD protection tube Q is grounded.

7. The chip resistor detection device according to claim 5, characterized in that, The output conversion circuit includes a current mirror MP4, a current mirror MP5, a current mirror MP6, a current mirror MN1, a current mirror MN2, and a current mirror MN3; The collectors of the current mirror MP4, the current mirror MP5, and the current mirror MP6 are respectively used to connect to the digital-to-analog conversion reference voltage. The gates of the current mirror MP4 and the current mirror MN1 are connected and connected to the output terminal of the voltage comparison circuit. The drains of the current mirror MP6 and the current mirror MN3 are connected and used to connect to the digital circuit of the chip under test; The drains of the current mirror MP4 and the current mirror MN1 are connected and respectively connected to the gates of the current mirror MP5 and the current mirror MN2. The drains of the current mirror MP5 and the current mirror MN2 are connected and respectively connected to the gates of the current mirror MP6 and the current mirror MN3; The sources of the current mirror MN1, the current mirror MN2, and the current mirror MN3 are all grounded.

8. The chip resistor detection device according to claim 7, wherein, The output conversion circuit further includes a current mirror MN4; The source of the current mirror MN4 is respectively connected to the gates of the current mirror MP4 and the current mirror MN1. The gate of the current mirror MN4 is connected to the output terminal of the voltage comparison circuit. The drain of the current mirror MN4 is used to connect to the digital-to-analog conversion reference voltage.

9. A chip device, characterized in that, Including the chip resistance detection device according to any one of claims 1 to 8.

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