Fan-out system-level packaging structure and manufacturing method thereof

Abstract

The present invention provides a fan-out system-level packaging structure and a manufacturing method thereof, wherein the packaging structure comprises: a rewiring layer; a metal bump formed on the surface of the rewiring layer; a system-level chip and a power management chip electrically connected to the rewiring; a packaging layer having a connection groove with a connection solder ball in the connection groove; an intermediate substrate electrically connected to the connection solder ball; a storage chip and a passive component electrically connected to the intermediate substrate. The present invention can realize a variety of different system functional requirements and improve the performance of the packaging structure. The present invention effectively reduces the area of ​​the packaging structure and improves the integration of the packaging structure through three-dimensional vertical stacking packaging, effectively shortens the conduction path between chips, reduces the power consumption of the packaging structure, and greatly reduces the overall thickness of the packaging structure. The connection solder balls can be formed by a solder ball process, which can effectively increase the size of the connection solder balls and further improve the conduction capacity.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit packaging, and in particular relates to a fan-out system-level packaging structure and a manufacturing method thereof. Background Art

[0002] With the advent of the 5G communication and artificial intelligence (AI) era, the amount of data that chips used in such related fields need to transmit and process at high speed is very huge. Such chips usually have a huge number of pad pins (hundreds or even thousands), ultra-fine pin size and spacing (a few microns or even smaller). On the other hand, the demand for mobile Internet and the Internet of Things is becoming stronger and stronger, and the miniaturization and multi-functionality of electronic terminal products have become a major trend in industrial development. How to integrate and package multiple high-density chips of different types together to form a powerful system or subsystem with relatively small volume and power consumption has become a major challenge in the field of advanced packaging of semiconductor chips.

[0003] At present, for multi-chip integrated packaging of such high-density chips, the industry usually adopts through silicon vias (TSV) and silicon interposers to lead out the ultra-fine pins of the chip and effectively interconnect them to form a functional module or system, but the cost of this technology is relatively high, which greatly limits its scope of application. Fan-out packaging technology uses the method of reconstructing wafers and rewiring RDL to provide a good platform for realizing multi-chip integrated packaging. However, the existing fan-out packaging technology has limited wiring accuracy, resulting in a large package area and high thickness, and there are many problems such as numerous processes and low reliability.

[0004] In order to adapt to the development trend of multifunctional, miniaturized, portable, high-speed, low-power and high-reliability microelectronic packaging technology, the system-level packaging (SIP) technology, as an emerging heterogeneous integration technology, has become the packaging form of more and more chips. The system-level packaging is to integrate multiple functional chips and components in one package to achieve a complete function. The system-level packaging is a new packaging technology with the advantages of short development cycle, more functions, lower power consumption, better performance, lower cost, smaller size and lighter weight.

[0005] However, with the increasing demand for packaging components and functions, the existing system-level packaging will occupy an increasingly larger area and thickness, which is not conducive to improving the integration level.

[0006] In addition, as the degree of integration increases, the requirements for electrical conductivity between components are becoming increasingly higher. Summary of the invention

[0007] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a fan-out system-level packaging structure and a manufacturing method thereof, so as to solve the problem that the volume of the system-level packaging is difficult to reduce in the prior art.

[0008] To achieve the above-mentioned purpose and other related purposes, the present invention provides a fan-out system-level packaging structure, which includes: a rewiring layer, which includes a first surface and an opposite second surface; metal bumps, which are formed on the first surface of the rewiring layer to achieve electrical lead-out of the rewiring layer; a system-level chip and a power management chip, which are bonded to the second surface of the rewiring layer to achieve electrical connection with the rewiring layer; a packaging layer, which covers the system-level chip and the power management chip, and has a connecting groove in the packaging layer, which exposes the rewiring layer; a connecting solder ball, which is located in the connecting groove, and the connecting solder ball is electrically connected to the rewiring layer; an intermediate substrate, which is located on the packaging layer, and the intermediate substrate is electrically connected to the connecting solder ball; a memory chip and a passive component, which are bonded to the intermediate substrate, and the memory chip and the passive component are electrically connected to the intermediate substrate.

[0009] Optionally, the rewiring layer includes: a patterned first dielectric layer; a patterned first metal wiring layer, located on the patterned first dielectric layer, the first metal wiring layer is connected to the connecting solder balls, the system-level chip and the power management chip; a patterned second dielectric layer, located on the first metal wiring layer; and a patterned second metal wiring layer, located on the second dielectric layer.

[0010] Optionally, the material of the dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

[0011] Optionally, the top surface of the packaging layer exposes the system-level chip and the power management chip, and the top surfaces of the packaging layer, the system-level chip and the power management chip are also covered with a protective layer.

[0012] Optionally, the intermediate substrate is connected to the packaging layer, or there is a distance between the intermediate substrate and the packaging layer, and the distance is no greater than 30 micrometers.

[0013] Optionally, a metal wiring layer is exposed on the first surface of the rewiring layer, and the metal bump is directly formed on the metal wiring layer exposed by the rewiring layer.

[0014] Optionally, the material of the connecting solder balls includes tin or a tin-containing alloy.

[0015] Optionally, the memory chip includes an ePoP memory.

[0016] Optionally, the passive component includes a plurality of passive elements, and the passive element includes one of a resistor, a capacitor and an inductor.

[0017] Optionally, the interposer substrate comprises a silicon interposer, the silicon interposer comprises a silicon substrate, metal wiring layers located on the first and second surfaces of the silicon substrate, and silicon through vias, the silicon through vias connecting the metal wiring layers on the first and second surfaces of the silicon substrate.

[0018] Optionally, the thickness of the fan-out system-level packaging structure is no more than 1 mm.

[0019] The present invention also provides a method for manufacturing a fan-out system-level packaging structure, the manufacturing method comprising the steps of: 1) providing a supporting substrate and forming a separation layer on the supporting substrate; 2) providing a system-level chip and a power management chip, adhering the system-level chip and the power management chip to the separation layer, with the electrodes of the system-level chip and the power management chip facing upward; 3) using a packaging layer to package the system-level chip and the power management chip; 4) forming a rewiring layer on the packaging layer, the rewiring layer being electrically connected to the system-level chip and the power management chip; 5) forming a metal bump on the rewiring layer to realize the electrical lead-out of the rewiring layer; 6) providing a 7) peeling off the packaging layer and the supporting substrate based on the separation layer; 8) forming a connection groove in the packaging layer, wherein the connection groove exposes the rewiring layer; 9) making a connection solder ball in the connection groove, wherein the connection solder ball is electrically connected to the rewiring layer; 10) providing an intermediate substrate, bonding the first surface of the intermediate substrate to the connection solder ball, wherein the intermediate substrate is electrically connected to the connection solder ball; 11) providing a memory chip and a passive component, bonding the memory chip and the passive component to the second surface of the intermediate substrate, wherein the memory chip and the passive component are electrically connected to the intermediate substrate.

[0020] Optionally, the supporting substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate.

[0021] Optionally, the separation layer includes a light-to-heat conversion layer, and in step 7), laser is used to irradiate the light-to-heat conversion layer to separate the light-to-heat conversion layer from the encapsulation layer and the supporting substrate, thereby peeling off the encapsulation layer and the supporting substrate.

[0022] Optionally, step 4) of making the rewiring layer includes the steps of: 4-1) forming a first dielectric layer on the surface of the packaging layer, etching the first dielectric layer and the packaging layer to form a patterned first dielectric layer; 4-2) forming a first metal layer on the patterned through hole and the surface of the first dielectric layer by a sputtering process, and etching the metal layer to form a patterned first metal wiring layer, wherein the first metal wiring layer is electrically connected to the connecting solder ball, the system-level chip and the power management chip; 4-3) forming a second dielectric layer on the surface of the patterned first metal wiring layer, and etching the second dielectric layer to form a patterned second dielectric layer; 4-4) filling the patterned through hole with a conductive plug, and then forming a second metal layer on the surface of the second dielectric layer by a sputtering process, and etching the metal layer to form a patterned second metal wiring layer; 4-5) repeating steps 4-3) to 4-4) to form a multi-layer structured rewiring layer, wherein the metal wiring layer is exposed on the surface of the rewiring layer.

[0023] Optionally, the material of the dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

[0024] Optionally, the metal bump is directly made on the metal wiring layer exposed by the rewiring layer.

[0025] Optionally, a method for forming the encapsulation layer includes one of compression molding, transfer molding, liquid sealing molding, vacuum lamination and spin coating, and a material of the encapsulation layer includes one of polyimide, silicone and epoxy resin.

[0026] Optionally, the passive component includes a plurality of passive elements, and the passive element includes one of a resistor, a capacitor and an inductor.

[0027] Optionally, the interposer substrate comprises a silicon interposer, the silicon interposer comprises a silicon substrate, metal wiring layers located on the first and second surfaces of the silicon substrate, and silicon through vias, the silicon through vias connecting the metal wiring layers on the first and second surfaces of the silicon substrate.

[0028] Optionally, the intermediate substrate is connected to the packaging layer, or there is a distance between the intermediate substrate and the packaging layer, and the distance is no greater than 30 micrometers.

[0029] Optionally, step 1) further includes forming a protective layer on the separation layer, and after step 7) the packaging layer and the supporting substrate are peeled off based on the separation layer, the protective layer remains on the surface of the packaging layer, the system-level chip and the power management chip.

[0030] As described above, the fan-out system-level packaging structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0031] The present invention adopts a fan-out system-level package to integrate chips with multiple functions, including system-level chips, power management chips, storage chips and passive components, into one package structure, which can meet various system function requirements and improve the performance of the packaged system.

[0032] The present invention realizes three-dimensional vertical stacking packaging of system-level chips, power management chips, storage chips and passive components by rewiring layers and connecting solder balls, effectively reducing the area of ​​the packaging system and improving the integration of the packaging system.

[0033] The present invention realizes close connection between wiring layers by connecting solder balls, which can effectively shorten the conduction path between chips and reduce the power consumption of the packaging system. The connecting solder balls can be formed by solder ball process, and larger connecting solder balls can be obtained, further improving the conduction capacity.

[0034] The fan-out system-level packaging structure of the present invention can achieve a packaging thickness of less than 1 mm, which greatly reduces the overall thickness of the packaging system compared to the traditional SiP packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 to Figure 17 It is a schematic diagram showing the structure of each step of the method for manufacturing the fan-out system-level packaging structure of the present invention, wherein: Fig.16 It is a schematic diagram of the cross-sectional structure of the fan-out system-level packaging structure of this embodiment. Fig.17 Shown is a schematic plan layout diagram of the fan-out system-in-package structure of this embodiment.

[0036] Component number description

[0037] 101 Support base

[0038] 102 Separation Layer

[0039] 103 Film

[0040] 104 Connection slot

[0041] 105 metal bumps

[0042] 20 Rewiring Layer

[0043] 201 First dielectric layer

[0044] 202 First metal wiring layer

[0045] 203 Second dielectric layer

[0046] 204 Second metal wiring layer

[0047] 205 Third dielectric layer

[0048] 206 Third Metal Wiring Layer

[0049] 207 Fourth dielectric layer

[0050] 208 Fourth metal wiring layer

[0051] 301 Connecting solder balls

[0052] 401 System-on-Chip

[0053] 402 Power Management Chip

[0054] 403 Isolation protection layer

[0055] 404 Memory Chip

[0056] 405 Passive Components

[0057] 501 Encapsulation layer

[0058] 60 Intermediate substrate DETAILED DESCRIPTION

[0059] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0060] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0061] For ease of description, spatially relative terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship of one element or feature shown in the drawings to other elements or features. It will be understood that these spatially relative terms are intended to encompass other orientations of the device in use or operation in addition to the orientation depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0062] In the context of the present application, a structure in which a first feature is described as being "above" a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0063] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0064] This embodiment provides a method for manufacturing a fan-out system-in-package structure, the manufacturing method comprising the steps of:

[0065] like Figure 1 As shown, step 1) is first performed to provide a supporting substrate 101 and to form a separation layer 102 on the supporting substrate 101 .

[0066] As an example, the support substrate 101 includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate. In this embodiment, the support substrate 101 is selected as a glass substrate, which has a low cost, is easy to form a separation layer 102 on its surface, and can reduce the difficulty of the subsequent stripping process.

[0067] As an example, the separation layer 102 includes a light-to-heat conversion layer (LTHC), which is formed on the support substrate 101 by a spin coating process and then solidified by a curing process. The light-to-heat conversion layer (LTHC) has stable performance and a smooth surface, which is conducive to the subsequent preparation of the rewiring layer, and in the subsequent stripping process, the stripping difficulty is relatively low.

[0068] In a preferred implementation, Figure 2 As shown, step 1) also includes forming a protective layer 103 on the separation layer. In the subsequent step 7), after the packaging layer and the supporting substrate are peeled off based on the separation layer, the protective layer 103 remains on the surface of the packaging layer, the system-level chip and the power management chip to effectively protect the system-level chip and the power management chip and prevent damage to the system-level chip and the power management chip by corrosive gases, water vapor, etc.

[0069] like Figure 3As shown, then step 2) is performed to provide a system-level chip 401 and a power management chip 402, and the system-level chip 401 and the power management chip 402 are adhered to the separation layer 102, wherein the electrodes of the system-level chip 401 and the power management chip 402 face upward to facilitate the subsequent connection with the rewiring layer. If a protective layer 103 is first formed on the separation layer 102, the system-level chip 401 and the power management chip 402 are adhered to the protective layer 103.

[0070] For example, the system-on-chip 401 may be a GPU chip for a mobile phone, a tablet or other smart devices.

[0071] In this embodiment, the system-level chip 401 and the power management chip 402 can be directly bonded to the separation layer 102 or the protection layer 103 using insulating glue, which is simple in process and can effectively reduce costs.

[0072] like Figure 4-5 As shown, step 5 is then performed, in which the system-level chip 401 and the power management chip 402 are encapsulated using a packaging layer 501, and the packaging layer 501 is thinned. After thinning, the electrodes of the system-level chip 401 and the power management chip 402 can be exposed in the packaging layer, and a packaging layer of a certain thickness can also be retained to cover the electrodes of the system-level chip 401 and the power management chip 402.

[0073] For example, the method for forming the encapsulation layer 501 includes one of compression molding, transfer molding, liquid sealing molding, vacuum lamination and spin coating, and the material of the encapsulation layer 501 includes one of polyimide, silicone and epoxy resin.

[0074] like Figure 6 As shown, step 4 is then performed to form a rewiring layer 20 on the packaging layer 501 . The rewiring layer 20 is electrically connected to the system-on-chip 401 and the power management chip 402 .

[0075] Specifically, step 4) manufacturing the rewiring layer 20 comprises the following steps:

[0076] like Figure 6 As shown, step 4-1) is performed to form a first dielectric layer 201 on the surface of the packaging layer 501 by a chemical vapor deposition process or a physical vapor deposition process, and the first dielectric layer and the packaging layer are etched to form a patterned first dielectric layer; the material of the first dielectric layer 201 includes one or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass.

[0077] Preferably, the material of the first dielectric layer 201 is PI (polyimide) to further reduce the process difficulty and process cost.

[0078] like Figure 6 As shown, step 4-2) is performed to form a first metal layer on the surface of the patterned through hole and the first dielectric layer 201 by a sputtering process, and the metal layer is etched to form a patterned first metal wiring layer 202, and the first metal wiring layer 202 is electrically connected to the system-level chip 401 and the power management chip 402. The material of the first metal wiring layer 202 includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

[0079] like Figure 6 As shown, step 4-3) is performed to form a second dielectric layer 203 on the surface of the patterned first metal wiring layer 202 by a chemical vapor deposition process or a physical vapor deposition process, and the second dielectric layer 203 is etched to form a patterned second dielectric layer 203. The material of the second dielectric layer 203 includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass, and fluorine-containing glass.

[0080] Preferably, the material of the second dielectric layer 203 is PI (polyimide) to further reduce the process difficulty and process cost.

[0081] like Figure 6 As shown, step 4-4) is performed to fill the patterned through hole with a conductive plug, and then a second metal layer is formed on the surface of the second dielectric layer 203 by a sputtering process, and the metal layer is etched to form a patterned second metal wiring layer 204. The material of the second metal wiring layer 204 includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

[0082] Then, if Figure 6 As shown, the above steps 4-3) to 4-4) can be repeated to form a rewiring layer with a multi-layer stacking structure to achieve different wiring functions, wherein a metal wiring layer is exposed on the surface of the rewiring layer. For example, in this embodiment, the rewiring layer 20 also includes a patterned third dielectric layer 205, a patterned third metal wiring layer 206, a patterned fourth dielectric layer 207 and a patterned fourth metal wiring layer 208, and the fourth gold wiring layer 208 is exposed on the surface of the rewiring layer.

[0083] like Figure 7 As shown, step 5) is then performed to form metal bumps 105 on the rewiring layer to achieve electrical extraction of the rewiring layer.

[0084] In this embodiment, the metal bump 105 is directly made on the fourth metal wiring layer 208 exposed by the rewiring layer 20 , and the metal bump 105 can be one of tin solder, silver solder and gold-tin alloy solder.

[0085] like Figure 8 Then, step 6) is performed to provide a film 103 , and the side of the rewiring layer 20 having the metal bumps 105 is adhered to the film 103 .

[0086] like Fig. 9 As shown, step 7) is then performed to peel off the encapsulation layer 501 and the supporting substrate 101 based on the separation layer 102 .

[0087] For example, the light-to-heat conversion layer may be irradiated with a laser to separate the light-to-heat conversion layer from the encapsulation layer 501 and the supporting substrate 101 , thereby peeling off the encapsulation layer 501 and the supporting substrate 101 .

[0088] In this embodiment, a protective layer 103 is formed on the separation layer 102 . After the encapsulation layer 501 and the supporting substrate 101 are peeled off based on the separation layer 102 , the protective layer 103 remains on the surfaces of the encapsulation layer 501 , the system-level chip 401 and the power management chip 402 .

[0089] like Fig.10 Then, step 8 is performed to form a connection groove 104 in the packaging layer 501 , wherein the connection groove 104 exposes the rewiring layer 20 .

[0090] like Fig.11 As shown, step 9 is then performed to form a connecting solder ball 103 in the connecting groove, and the connecting solder ball 103 is electrically connected to the rewiring layer 20 .

[0091] For example, the connection solder ball 103 may be manufactured by ball planting and reflow process, and the material of the connection solder ball 103 may be tin or a tin-containing alloy, such as pure tin, tin-gold alloy, tin-lead alloy, etc.

[0092] like Fig.12 As shown, step 10 is then performed to provide an interposer substrate 60 , and the first surface of the interposer substrate 60 is bonded to the connecting solder balls 103 , so that the interposer substrate 60 and the connecting solder balls 103 are electrically connected.

[0093] For example, the interposer substrate may be a silicon interposer, which includes a silicon substrate, metal wiring layers located on the first and second surfaces of the silicon substrate, and through silicon vias, wherein the through silicon vias connect the metal wiring layers on the first and second surfaces of the silicon substrate. The silicon interposer has a relatively high hardness, and the metal wiring layer structure also has a relatively high precision, which can effectively improve the stability and yield of the packaging structure.

[0094] like Figure 13 to Figure 17 As shown, step 11 is finally performed to provide a memory chip 404 and a passive component 405 , and to bond the memory chip 404 and the passive component 405 to the interposer substrate 60 to achieve electrical connection with the interposer substrate 60 .

[0095] For example, the memory chip 404 may be bonded to the intermediate substrate 60 using a die bonding process. Fig.13 As shown, the passive component 405 is then bonded to the intermediate substrate 60 using a surface mount process, as shown in FIG. Fig.14 As shown, finally, a dispensing process is used to form an isolation protection layer 403 on the memory chip 404 and the intermediate substrate 60, as shown in FIG. Fig.15 shown.

[0096] In this embodiment, the passive component 405 includes a plurality of passive elements, and the plurality of passive elements may be arranged in a parallel array, such as Fig.17 As shown, the passive component may be one of a resistor, a capacitor and an inductor.

[0097] Finally, the package structure formed above is cut, and then the film 103 is peeled off to form the fan-out system-level package structure. Fig.16 As shown, the system-level chip 401 , the power management chip 402 , the memory chip 404 and the passive component 405 are interconnected through the rewiring layer 20 , the intermediate substrate 60 and the connecting solder balls 301 , and a fan-out package is implemented through the metal bumps 105 .

[0098] Fig.16 It is a schematic diagram of the cross-sectional structure of the fan-out system-level packaging structure of this embodiment. Fig.17 The schematic diagram of the plan layout of the fan-out system-level package structure of this embodiment is shown as follows: Figure 16-17As shown, in a specific implementation process, the overall size (length × width) of the fan-out system-level packaging structure can be 13mm × 16mm, the total height is 1mm, the size (length × width) of the system-level chip 401 can be 8.2×8.3mm, the size of the power management chip 402 can be 5.1mm × 4.8mm, the spacing between the system-level chip 401 and the power management chip 402 is 0.5mm, and the thickness of the storage chip 404 is 0.68mm.

[0099] The present invention uses a fan-out system-level package to integrate chips with multiple functions, including a system-level chip 401, a power management chip 402, a memory chip 404, and a passive component 405, into a package structure, which can realize a variety of different system function requirements and improve the performance of the package system. The present invention realizes a three-dimensional vertical stacking package of the system-level chip 401, the power management chip 402, the memory chip 404, and the passive component 405 through the rewiring layer and the connecting solder ball 301, effectively reducing the area of ​​the packaging system and improving the integration of the packaging system. The present invention realizes a close connection between the rewiring layers by connecting the solder balls 301, which can effectively shorten the conduction path between the chips and reduce the power consumption of the packaging system. The connecting solder balls can be formed by the solder ball process, and a larger size of connecting solder balls can be obtained, further improving the conduction capacity. The fan-out system-level package structure of the present invention can achieve a package thickness of less than 1 mm, which greatly reduces the overall thickness of the packaging system compared to the traditional SiP packaging structure.

[0100] like Fig.16 and Fig.17As shown, the present embodiment also provides a fan-out system-level packaging structure, the packaging structure comprising: a rewiring layer 20, the rewiring layer 20 comprising a first surface and an opposite second surface, the first surface of the rewiring layer 20 exposing a metal wiring layer; metal bumps 105, formed on the metal wiring layer on the first surface of the rewiring layer 20 to achieve electrical lead-out of the rewiring layer 20; a system-level chip 401 and a power management chip 402, the system-level chip 401 and the power management chip 402 being bonded to the second surface of the rewiring layer 20 to achieve electrical connection with the rewiring layer 20; a packaging structure; The packaging layer 501 covers the system-level chip 401 and the power management chip 402, and the packaging layer 501 has a connection groove 104, and the connection groove 104 exposes the rewiring layer 20; the connecting solder ball 103 is located in the connecting groove 104, and the connecting solder ball 103 is electrically connected to the rewiring layer 20; the intermediate substrate 60 is located on the packaging layer 501, and the intermediate substrate 60 is electrically connected to the connecting solder ball 301; the memory chip 404 and the passive component 405 are bonded to the intermediate substrate 60, and the memory chip 404 and the passive component 405 are electrically connected to the intermediate substrate 60.

[0101] The rewiring layer 20 includes: a patterned first dielectric layer 201; a patterned first metal wiring layer 202, located on the patterned first dielectric layer 201, the first metal wiring layer 202 is connected to the connection solder ball 301, the system-level chip 401 and the power management chip 402; a patterned second dielectric layer 203, located on the first metal wiring layer 202; and a patterned second metal wiring layer 204, located on the second dielectric layer 203. The material of the dielectric layer includes one or more combinations of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphorus silicon glass, and fluorine-containing glass, and the material of the metal wiring layer includes one or more combinations of copper, aluminum, nickel, gold, silver, and titanium. In this embodiment, the material of the first dielectric layer 201 and the second dielectric layer 203 is selected as PI (polyimide) to further reduce the process difficulty and process cost. The rewiring layer 20 can also include more dielectric layers and metal layers to achieve different wiring functions. For example, in this embodiment, the rewiring layer 20 also includes a patterned third dielectric layer 205, a patterned third metal wiring layer 206, a patterned fourth dielectric layer 207 and a patterned fourth metal wiring layer 208, and the patterned fourth metal wiring layer 208 is exposed on the surface of the rewiring layer 20.

[0102] The connecting solder ball 301 may be tin or a tin-containing alloy. The connecting solder ball 301 may be formed by a solder ball process, and a larger connecting solder ball 301 may be obtained, further improving the conduction capability. For example, the radial dimension of the connecting solder ball 301 may be more than 100 microns.

[0103] In this embodiment, the top surface of the packaging layer 501 exposes the system-on-chip 401 and the power management chip 402 . The top surfaces of the packaging layer 501 , the system-on-chip 401 , and the power management chip 402 are also covered with a protection layer 103 .

[0104] The intermediate substrate may be connected to the packaging layer, or there may be a gap between the intermediate substrate and the packaging layer, and the gap may be no greater than 30 microns. For example, the gap may be 10 microns, 20 microns, etc., and the gap may be filled with insulating glue using a dispensing process.

[0105] The system-level chip 401 may be a GPU chip for a mobile phone, a tablet or other smart devices, etc. The memory chip 404 includes an ePoP memory. An isolation protection layer 406 is also provided between the memory chip 404 and the intermediate substrate 60 .

[0106] The intermediate substrate 60 can be a silicon intermediate layer, which includes a silicon substrate, a metal wiring layer located on the first side and the second side of the silicon substrate, and a silicon through via. The silicon through via connects the metal wiring layer on the first side and the second side of the silicon substrate. The silicon intermediate layer has a high hardness, and the metal wiring layer structure also has a high precision, which can effectively improve the stability and yield of the packaging structure.

[0107] The material of the packaging layer 501 includes one of polyimide, silicone and epoxy resin. The metal bump 105 includes one of tin solder, silver solder and gold-tin alloy solder.

[0108] The thickness of the fan-out system-level packaging structure is no more than 1 mm.

[0109] like Fig.17 As shown, the passive component 405 includes a plurality of passive elements, and the passive element includes one of a resistor, a capacitor and an inductor.

[0110] Fig.16 It is a schematic diagram of the cross-sectional structure of the fan-out system-level packaging structure of this embodiment. Fig.17 The schematic diagram of the plan layout of the fan-out system-level package structure of this embodiment is shown as follows: Figure 16-17As shown, in a specific implementation process, the overall size (length × width) of the fan-out system-level packaging structure can be 13mm × 16mm, the total height is 1mm, the size (length × width) of the system-level chip 401 can be 8.2×8.3mm, the size of the power management chip 402 can be 5.1mm × 4.8mm, the spacing between the system-level chip 401 and the power management chip 402 is 0.5mm, and the thickness of the storage chip 404 is 0.68mm.

[0111] As described above, the fan-out system-level packaging structure and the manufacturing method thereof of the present invention have the following beneficial effects:

[0112] The present invention adopts a fan-out system-level package to integrate chips with multiple functions, including system-level chips, power management chips, storage chips and passive components, into one package structure, which can meet various system function requirements and improve the performance of the packaged system.

[0113] The present invention realizes three-dimensional vertical stacking packaging of system-level chips, power management chips, storage chips and passive components by rewiring layers and connecting solder balls, effectively reducing the area of ​​the packaging system and improving the integration of the packaging system.

[0114] The present invention realizes close connection between wiring layers by connecting solder balls, which can effectively shorten the conduction path between chips and reduce the power consumption of the packaging system. The connecting solder balls can be formed by solder ball process, and larger connecting solder balls can be obtained, further improving the conduction capacity.

[0115] The fan-out system-level packaging structure of the present invention can achieve a packaging thickness of less than 1 mm, which greatly reduces the overall thickness of the packaging system compared to the traditional SiP packaging structure.

[0116] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0117] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for manufacturing a fan-out system-level packaging structure, characterized in that: Includes steps: 1) providing a supporting substrate, and forming a separation layer on the supporting substrate; 2) providing a system-level chip and a power management chip, and adhering the system-level chip and the power management chip to the separation layer, with the electrodes of the system-level chip and the power management chip facing upward; 3) Encapsulating the system-on-chip and the power management chip using a packaging layer; 4) forming a rewiring layer on the packaging layer, wherein the rewiring layer is electrically connected to the system-on-chip and the power management chip; 5) forming metal bumps on the rewiring layer to realize electrical extraction of the rewiring layer; 6) providing a film, and adhering the side of the rewiring layer having the metal bumps to the film; 7) peeling off the encapsulation layer and the supporting substrate based on the separation layer; 8) forming a connection groove in the packaging layer, wherein the connection groove exposes the rewiring layer; 9) forming a connection solder ball in the connection groove, wherein the connection solder ball is electrically connected to the rewiring layer; 10) providing an intermediate substrate, bonding a first surface of the intermediate substrate to the connecting solder balls, wherein the intermediate substrate is electrically connected to the connecting solder balls; 11) Providing a memory chip and a passive component, bonding the memory chip and the passive component to the second surface of the intermediate substrate, and electrically connecting the memory chip and the passive component to the intermediate substrate; cutting the above-formed packaging structure, and then peeling off the film to form the fan-out system-level packaging structure.

2. The method for manufacturing a fan-out system-level packaging structure according to claim 1, wherein: The supporting substrate includes one of a glass substrate, a metal substrate, a semiconductor substrate, a polymer substrate and a ceramic substrate.

3. The method for manufacturing a fan-out system-level packaging structure according to claim 1, wherein: The separation layer includes a light-to-heat conversion layer. In step 7), laser is used to irradiate the light-to-heat conversion layer to separate the light-to-heat conversion layer from the encapsulation layer and the supporting substrate, thereby peeling off the encapsulation layer and the supporting substrate.

4. The method for manufacturing a fan-out system-level packaging structure according to claim 1, wherein: Step 4) Making the rewiring layer comprises the following steps: 4-1) forming a first dielectric layer on the surface of the packaging layer, and etching the first dielectric layer and the packaging layer to form a patterned first dielectric layer; 4-2) forming a first metal layer in the through hole formed by patterning the first dielectric layer and on the surface of the first dielectric layer by a sputtering process, and etching the metal layer to form a patterned first metal wiring layer, wherein the first metal wiring layer is electrically connected to the connecting solder balls, the system-level chip, and the power management chip; 4-3) forming a second dielectric layer on the surface of the patterned first metal wiring layer, and etching the second dielectric layer to form a patterned second dielectric layer; 4-4) filling a conductive plug in the through hole formed by patterning the second dielectric layer, then forming a second metal layer on the surface of the second dielectric layer by a sputtering process, and etching the metal layer to form a patterned second metal wiring layer; 4-5) Repeat steps 4-3) to 4-4) to form a multi-layered redistribution layer, wherein a metal wiring layer is exposed on the surface of the redistribution layer.

5. The method for manufacturing a fan-out system-level packaging structure according to claim 4, characterized in that: The material of the dielectric layer includes one or a combination of two or more of epoxy resin, silica gel, PI, PBO, BCB, silicon oxide, phosphosilicate glass, and fluorine-containing glass, and the material of the metal wiring layer includes one or a combination of two or more of copper, aluminum, nickel, gold, silver, and titanium.

6. The method for manufacturing a fan-out system-level package structure according to claim 4, characterized in that: The metal bump is directly made on the metal wiring layer exposed by the rewiring layer.

7. The method for manufacturing a fan-out system-level package structure according to claim 1, wherein: The method for forming the encapsulation layer includes one of compression molding, transfer molding, liquid sealing molding, vacuum lamination and spin coating, and the material of the encapsulation layer includes one of polyimide, silica gel and epoxy resin.

8. The method for manufacturing a fan-out system-level package structure according to claim 1, wherein: The passive component includes a plurality of passive elements, and the passive element includes one of a resistor, a capacitor and an inductor.

9. The method for manufacturing a fan-out system-level package structure according to claim 1, wherein: The interposer substrate includes a silicon interposer, which includes a silicon substrate, metal wiring layers located on a first surface and a second surface of the silicon substrate, and through silicon vias, wherein the through silicon vias connect the metal wiring layers on the first surface and the second surface of the silicon substrate.

10. The method for manufacturing a fan-out system-level package structure according to claim 1, characterized in that: The intermediate substrate is connected to the packaging layer, or there is a distance between the intermediate substrate and the packaging layer, and the distance is no greater than 30 micrometers.

11. The method for manufacturing a fan-out system-level package structure according to claim 1, characterized in that: Step 1) also includes forming a protective layer on the separation layer. Step 7) after peeling off the packaging layer and the supporting substrate based on the separation layer, the protective layer remains on the surface of the packaging layer, the system-level chip and the power management chip.

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