A slow start circuit and control method for an audio switch

Abstract

The present invention discloses a slow start circuit for an audio switch, which includes a first transistor circuit, a second transistor circuit, a high-side level conversion circuit, a low-side level conversion circuit, and a main switch drive circuit. The low-side and high-side level conversion circuits are used to receive a slow start enable signal or a slow start disable signal sent by a digital circuit. When the high-side level conversion circuit and the low-side level conversion circuit receive the slow start enable signal through the digital circuit, both the high-side level conversion circuit and the low-side level conversion circuit generate a low-level conversion signal according to the slow start enable signal, receive a first current sent by a first current source through the first transistor circuit, and then drive the main switch drive circuit to receive a slow start current sent by a slow start current source to generate a main switch drive signal, and the slow start circuit enters the slow start mode. The slow start function proposed by the present invention realizes flexible adjustment of the slow start time length through an analog method, effectively eliminating the Pop sound when the earphone or the speaker is turned on.

Description

Technical Field

[0001] The present invention relates to the field of analog audio switches, and in particular, to a slow start circuit and a control method for an audio switch. Background Art

[0002] In audio applications, a Pop sound often occurs instantaneously when a headphone or a speaker is turned on, which is a very troublesome problem. The sudden change of energy at the moment of power-on or startup is the root cause of the Pop sound. If the switch is turned on in a slow start manner, the slow change of energy is achieved, and the Pop sound can be effectively removed.

[0003] In the past, in many slow start technologies, the slope of the voltage change over time was relatively fast, so the human ear could still hear part of the Pop sound. And although some switches have a very low slow start slope, they require an external capacitor, which increases the complexity of the application and also increases the cost of the system.

[0004] Some traditional slow start controls cannot flexibly adjust the slow start time, which brings inconvenience to the application. Summary of the Invention

[0005] In view of the above problems, the present application proposes a slow start circuit for an audio switch to solve the problem that the existing slow start control cannot flexibly adjust the slow start time.

[0006] The present invention proposes a slow start circuit for an audio switch, and the slow start circuit includes:

[0007] A high-side level conversion circuit for receiving a slow start enable signal or a slow start disable signal sent by a digital circuit;

[0008] A first transistor circuit electrically connected to the high-side level conversion circuit;

[0009] A low-side level conversion circuit electrically connected to the high-side level conversion circuit, and the low-side level conversion circuit is used for receiving the slow start enable signal or the slow start disable signal;

[0010] A second transistor circuit electrically connected to the low-side level conversion circuit and the first transistor circuit;

[0011] The main switch driving circuit is electrically connected to the first node of the first transistor circuit and the second transistor circuit. When the high-side level conversion circuit and the low-side level conversion circuit receive the soft-start enable signal through the digital circuit, both the high-side level conversion circuit and the low-side level conversion circuit generate a low-level conversion signal according to the soft-start enable signal to receive the first current sent by the first current source through the first transistor circuit, and then drive the main switch driving circuit to receive the soft-start current sent by the soft-start current source to generate a main switch driving signal, and the soft-start circuit enters the soft-start mode.

[0012] Further, when the high-side level conversion circuit and the low-side level conversion circuit receive the soft-start disable signal through the digital circuit, the high-side level conversion circuit and the low-side level conversion circuit generate a high-level conversion signal according to the soft-start disable signal to drive the main switch driving circuit to generate a main switch disable signal through the second transistor circuit, and the soft-start circuit enters the normal working mode from the soft-start mode to receive and transmit audio signals through at least one select-low circuit.

[0013] Further, the first transistor circuit includes:

[0014] A first transistor, the source of the first transistor is electrically connected to the first current source and receives the first current, and the gate of the first transistor is electrically connected to the high-side level conversion circuit and receives a high-side level conversion signal;

[0015] A second transistor, the source of the second transistor is electrically connected to the drain of the first transistor, and the gate of the second transistor receives a BP voltage signal. When the high-side level conversion circuit and the low-side level conversion circuit receive the soft-start enable signal through the digital circuit, both the high-side level conversion circuit and the low-side level conversion circuit generate a low-level conversion signal according to the soft-start enable signal to turn on the first transistor and the second transistor to receive the first current sent by the first current source, and the soft-start circuit enters the soft-start mode.

[0016] Further, the second transistor circuit includes:

[0017] A third transistor, the drain of the third transistor is electrically connected to the first current source transistor circuit, and the gate of the third transistor receives a BN voltage signal;

[0018] A fourth transistor, the drain of the fourth transistor being electrically connected to the source of the third transistor, and the gate of the fourth transistor being electrically connected to the low-side level conversion circuit and receiving a low-voltage level conversion signal. Wherein, when the high-side level conversion circuit and the low-side level conversion circuit receive the soft-start disable signal through the digital circuit, the high-side level conversion circuit and the low-side level conversion circuit generate a high-level conversion signal according to the soft-start disable signal to turn on the third transistor and the fourth transistor, and the soft-start circuit enters the normal mode from the soft-start mode to transmit and receive audio signals through at least one select-low circuit.

[0019] Further, the main switch driving circuit includes:

[0020] A fifth transistor, the gate of the fifth transistor being electrically connected to the first transistor circuit and the second transistor circuit through the first node;

[0021] A sixth transistor, the gate of the sixth transistor being electrically connected to the gate of the fifth transistor and the first node. Wherein, after the first transistor circuit receives the first current sent by the first current source, the fifth transistor and the sixth transistor are started, and the soft-start current source sends a soft-start current to generate a main switch driving signal, and the soft-start circuit enters the soft-start mode.

[0022] Further, the soft-start circuit further includes:

[0023] A seventh transistor, the source of the seventh transistor being electrically connected to the drain of the fifth transistor;

[0024] An eighth transistor, the source of the eighth transistor being electrically connected to the gate and the drain of the seventh transistor;

[0025] A first resistor, one end of which is electrically connected to the gate and the drain of the eighth transistor;

[0026] A ninth transistor, the source of the ninth transistor being electrically connected to the drain of the sixth transistor;

[0027] A tenth transistor, the source of the tenth transistor being electrically connected to the gate and the drain of the ninth transistor;

[0028] A second resistor, one end of which is electrically connected to the gate and the drain of the tenth transistor, and the other end of which is electrically connected to the other end of the first transistor and the soft-start current source;

[0029] A third resistor, one end of which is electrically connected to the source of the fifth transistor. After the first node raises the voltage level to turn on the fifth transistor, the first resistor, the third resistor, the fifth transistor, the seventh transistor, the eighth transistor, and the first shunt of the slow start current source form a first path;

[0030] A fourth resistor, one end of which is electrically connected to the source of the sixth transistor. After the first node raises the voltage level to turn on the sixth transistor, the second resistor, the fourth resistor, the sixth transistor, the ninth transistor, the tenth transistor, and the second shunt of the slow start current source form a second path;

[0031] A main switch transistor, the drain of the main switch transistor is electrically connected to the other end of the third resistor, the source of the main switch transistor is electrically connected to the other end of the fourth resistor, and the gate of the main switch transistor is electrically connected to the other end of the first resistor and the other end of the second resistor. Wherein, the voltage difference between the gate and the source of the main switch transistor is equal to the voltage difference formed after the first shunt flows into the first resistor, the seventh transistor, and the eighth transistor. The voltage difference between the gate and the source of the main switch transistor continuously increases until the operating mode region of the main switch transistor jumps out of the saturation region into the linear region, and the slow start circuit enters the normal operating mode from the slow start mode;

[0032] A gate drive circuit is electrically connected to the gate of the main switch transistor, the other end of the first resistor, and the other end of the second resistor. Wherein, when the slow start circuit enters the normal operating mode from the slow start mode, after the main switch transistor enters the normal operating mode, the gate drive circuit is enabled;

[0033] An eleventh transistor, the gate and the drain of the eleventh transistor are electrically connected to the first node, the first transistor circuit, and the second transistor circuit;

[0034] A twelfth transistor, the gate and the drain of the twelfth transistor are electrically connected to the source of the eleventh transistor. When the slow start circuit receives the slow start enable signal, after the first transistor circuit receives the first current sent by the first current source and turns on the fifth transistor of the main switch drive circuit through the first node, the voltage difference between the gate and the source of the fifth transistor is equal to the cross voltage of the eleventh transistor and the twelfth transistor;

[0035] The first low-selection circuit, the first input terminal of the first low-selection circuit is electrically connected to the other end of the third resistor, the second input terminal of the first low-selection circuit is electrically connected to the other end of the fourth resistor, and the output terminal of the first low-selection circuit is electrically connected to the source electrode of the twelfth transistor;

[0036] The second low-selection circuit, the first input terminal of the second low-selection circuit is electrically connected to the first input terminal of the first low-selection circuit and the other end of the third resistor, and the second input terminal of the second low-selection circuit is electrically connected to the second input terminal of the first low-selection circuit and the other end of the fourth resistor;

[0037] The third low-selection circuit, the first input terminal of the third low-selection circuit is grounded, the second input terminal of the third low-selection circuit is electrically connected to the output terminal of the second low-selection circuit, and the output terminal of the third low-selection circuit is electrically connected to the second transistor circuit through a second node. Wherein, when the low-side level conversion signal output by the low-side level conversion circuit is at a high voltage level, the second transistor circuit is turned on, and the second node selects the low output of the audio input signal, the audio output signal, and GND, so that the voltage difference between the gate and the source of the fifth transistor is 0V or a negative voltage, turning off the fifth transistor and the sixth transistor, and the slow start mode ends.

[0038] Further, the slow start circuit further includes a slow start current source generation circuit, the slow start current source generation circuit:

[0039] The thirteenth transistor, the drain of the thirteenth transistor is electrically connected to the slow start current source and sends the slow start current source;

[0040] The fourteenth transistor, the source of the fourteenth transistor is electrically connected to the source of the thirteenth transistor, and the gate and the drain of the fourteenth transistor are electrically connected to the gate of the thirteenth transistor, wherein the size of the thirteenth transistor is the same as the size of the fourteenth transistor;

[0041] The fifteenth transistor, the drain of the fifteenth transistor is electrically connected to the gate and the drain of the fourteenth transistor and the gate of the thirteenth transistor;

[0042] The fifth resistor, one end is electrically connected to the source of the fifteenth transistor, and the other end is grounded;

[0043] The sixteenth transistor, the drain of the sixteenth transistor is electrically connected to one end of the fifth resistor, and the source of the sixteenth transistor is grounded;

[0044] Comparator, the positive input terminal of the comparator is electrically connected to one end of the fifth resistor and the drain of the sixteenth transistor and receives the CAP voltage signal, the negative input terminal of the comparator receives the REF voltage signal, and the output terminal of the comparator is electrically connected to the gate of the sixteenth transistor. Wherein, when the voltage level of the CAP voltage signal is greater than the voltage level of the REF voltage signal, the time range for the output terminal of the comparator to start the sixteenth transistor and then pull the voltage level of the CAP voltage signal to ground is the time range of the slow start mode;

[0045] Amplifier, the output terminal of the amplifier is electrically connected to the gate of the fifteenth transistor, the positive input terminal of the amplifier receives the SOFT voltage signal, and the negative input terminal of the amplifier is electrically connected to the source of the fifteenth transistor, one end of the fifth resistor, the drain of the sixteenth transistor, and the positive input terminal of the comparator. Wherein, the SOFT voltage signal and the CAP voltage signal are at the same potential, and the slow start current is the SOFT voltage signal divided by the fifth resistor, and the amplifier, the fifteenth transistor, and the fifth resistor form a negative feedback circuit;

[0046] Binary control circuit, one end is electrically connected to the positive input terminal of the amplifier and the second current source, and the other end is grounded. The second current source and the binary control circuit are used to control the voltage level of the SOFT voltage signal.

[0047] Further, the binary control circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor. The first switch is connected in series with the first capacitor, the second switch is connected in series with the second capacitor, the third switch is connected in series with the third capacitor, the fourth switch is connected in series with the fourth capacitor, the fifth switch is connected in series with the fifth capacitor, the sixth switch is connected in series with the sixth capacitor, the seventh switch is connected in series with the seventh capacitor, and the eighth switch is connected in series with the eighth capacitor and then are respectively connected in parallel, so as to dynamically control the voltage level of the SOFT voltage signal through the combined capacitance value of the second current source and each capacitor, thereby extending or shortening the time range of the quasi-slow start mode.

[0048] The present invention also provides a control method, which is applied to a slow start circuit of an audio switch. The slow start circuit includes a high-side level conversion circuit, a first transistor circuit, a low-side level conversion circuit, a second transistor circuit, and a main switch driving circuit. The first transistor circuit is electrically connected to the high-side level conversion circuit, the low-side level conversion circuit is electrically connected to the high-side level conversion circuit, the second transistor circuit is electrically connected to the low-side level conversion circuit and the first transistor circuit, and the main switch driving circuit is electrically connected to a first node of the first transistor circuit and the second transistor circuit. The control method includes:

[0049] The high-side level conversion circuit receives a slow start enable signal or a slow start disable signal sent by a digital circuit;

[0050] The low-side level conversion circuit receives the slow start enable signal or the slow start disable signal;

[0051] When the high-side level conversion circuit and the low-side level conversion circuit receive the slow start enable signal through the digital circuit, both the high-side level conversion circuit and the low-side level conversion circuit generate a low-level conversion signal according to the slow start enable signal, receive a first current sent by a first current source through the first transistor circuit, and then drive the main switch driving circuit to receive a slow start current sent by a slow start current source to generate a main switch driving signal, and the slow start circuit enters a slow start mode.

[0052] Further, when the high-side level conversion circuit and the low-side level conversion circuit receive the slow start disable signal through the digital circuit, the high-side level conversion circuit and the low-side level conversion circuit generate a high-level conversion signal according to the slow start disable signal to drive the main switch driving circuit to generate a main switch disable signal through the second transistor circuit, and the slow start circuit enters a normal working mode from the slow start mode to transmit and receive audio signals through at least one select-low circuit.

[0053] The technical solution of the present invention has the following beneficial effects:

[0054] The present invention provides a slow start circuit and a control method for an audio switch. The present invention proposes a fully internally integrated (without external capacitors) slow start solution. After the total internal capacitance value is built by the permutation and combination addition of multiple capacitors of a binary control circuit, the slow start current and its time range are dynamically adjusted. The slow start function can be completely realized by an analog method, and the digital circuit can flexibly adjust the slow start time length through digital control. By introducing the slow start function, the Pop sound when the earphone or the speaker is turned on is effectively eliminated. The present invention can not only achieve slow start with an ultra-low slope, optimize power consumption and sound quality, but also does not require external capacitors, reducing costs. Brief Description of the Drawings

[0055] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the embodiments of the present invention, and thus should not be regarded as limiting the scope of the embodiments of the present invention.

[0056] Figure 1 is a block diagram of the slow start circuit for the audio switch in Embodiment 1 of the present invention;

[0057] Figure 2 is a circuit diagram of the slow start circuit for the audio switch in Embodiment 2 of the present invention;

[0058] Figure 2a is a circuit diagram of the slow start current source generation circuit in Embodiment 2 of the present invention;

[0059] Figure 2b is a circuit diagram of the first low selection circuit in Embodiment 2 of the present invention;

[0060] Figure 2c is a circuit diagram of the second and third low selection circuits in Embodiment 2 of the present invention;

[0061] Figure 2d is a circuit diagram of the high-side level conversion circuit and the low-side level conversion circuit in Embodiment 2 of the present invention;

[0062] Figure 3 is a flowchart of the control method in Embodiment 3 of the present invention. Detailed Embodiments

[0063] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of the embodiments.

[0064] Therefore, the detailed description of the embodiments of the present invention provided in the drawings below is not intended to limit the scope of the claimed embodiments of the present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the embodiments of the present invention.

[0065] The embodiments of the present invention will be described in detail below with specific embodiments.

[0066] Embodiment 1

[0067] Please refer to Figure 1 , Figure 1It is a block diagram of the slow start circuit (hereinafter referred to as "slow start circuit") for an audio switch in Embodiment 1 of the present invention. The slow start circuit 1 includes a high-side level conversion circuit 203, a first transistor circuit 206', a low-side level conversion circuit 204, a second transistor circuit 208', and a main switch drive circuit 217'. The first transistor circuit 206' is electrically connected to the high-side level conversion circuit 203. The low-side level conversion circuit 204 is electrically connected to the high-side level conversion circuit 203. The second transistor circuit 208' is electrically connected to the low-side level conversion circuit 204 and the first transistor circuit 206'. The main switch drive circuit 217' is electrically connected to the first node 215' of the first transistor circuit 216' and the second transistor circuit 208'.

[0068] Furthermore, the high-side level conversion circuit 203 is used to receive a slow start enable signal or a slow start disable signal sent by a digital circuit, and the low-side level conversion circuit 204 is used to receive a slow start enable signal or a slow start disable signal. Among them, the slow start enable signal is used to start the slow start function mode of the slow start circuit 1, and the slow start disable signal is used to turn off the slow start function mode of the slow start circuit 1 and start the normal operation mode. When the high-side level conversion circuit 203 and the low-side level conversion circuit 204 receive the slow start enable signal STES through the digital circuit, both the high-side level conversion circuit 203 and the low-side level conversion circuit 204 generate a low-level conversion signal according to the slow start enable signal STES to receive the first current sent by the first current source 205 through the first transistor circuit 206' and then drive the main switch drive circuit 217' to receive the slow start current sent by the slow start current source to generate a main switch drive signal, and the slow start circuit 1 enters the slow start mode. Among them, the slow start enable signal STES is used to turn on the first transistor circuit 206' and turn off the second transistor circuit 208'.

[0069] In one embodiment, after multiple experiments, when the high-side level conversion circuit 203 and the low-side level conversion circuit 204 receive the slow start disable signal STDS through the digital circuit, the high-side level conversion circuit 203 and the low-side level conversion circuit 204 generate a high-level conversion signal according to the slow start disable signal STDS to drive the main switch drive circuit 217' to generate a main switch disable signal through the second transistor circuit 208', and the slow start circuit 1 enters the normal operation mode from the slow start mode to receive and transmit audio signals through at least one select-low circuit. For example, the select-low circuit can be set to receive audio signals within a certain range of levels to optimize the sound quality and enhance the user experience. The present invention proposes a fully internally integrated slow start solution that does not require external capacitors to reduce circuit costs, effectively optimize the circuit space, reduce the package space, and can flexibly adjust the time length of slow start in a way that can be controlled by a digital circuit to increase accuracy.

[0070] Embodiment 2

[0071] Please refer to Figure 2 , Figure 2a , Figure 2b , Figure 2c and Figure 2d . Figure 2 is the circuit diagram of the slow start circuit for the audio switch in Embodiment 2 of the present invention. Figure 2a is the circuit diagram of the slow start current source generation circuit in Embodiment 2 of the present invention. Figure 2b is the circuit diagram of the first low-selection circuit in Embodiment 2 of the present invention. Figure 2c is the circuit diagram of the second and third low-selection circuits in Embodiment 2 of the present invention. Figure 2d is the circuit diagram of the high-side level conversion circuit and the low-side level conversion circuit in Embodiment 2 of the present invention.

[0072] In one embodiment, the first transistor circuit 206' includes a first transistor 206 and a second transistor 207. For example, the first transistor 206 and the second transistor 207 can be PMOS. The source of the first transistor 206 is electrically connected to the first current source 205, and the first transistor 206 receives the first current sent by the first current source 205. The gate of the first transistor 206 is electrically connected to the high-side level conversion circuit 203, and the first transistor 206 receives the high-side level conversion signal PG sent by the high-side level conversion circuit 203. The source of the second transistor 207 is electrically connected to the drain of the first transistor 206, and the gate of the second transistor 207 receives the BP voltage signal VBP. When the high-side level conversion circuit 203 and the low-side level conversion circuit 204 receive the slow start enable signal STES through the digital circuit, both the high-side level conversion circuit 203 and the low-side level conversion circuit 204 generate low-level conversion signals according to the slow start enable signal STES to start the first transistor 206 and the second transistor 207 to receive the first current sent by the first current source 205, and the slow start circuit 1 enters the slow start mode.

[0073] In one embodiment, the second transistor circuit 208' includes a third transistor 208 and a fourth transistor 209. The drain of the third transistor 208 is electrically connected to the drain of the second transistor 207 of the first transistor circuit 206'. The gate of the third transistor 208 receives the BN voltage signal VBN. The drain of the fourth transistor 209 is electrically connected to the source of the third transistor 208. When the gate of the fourth transistor 209 is electrically connected to the low-side level conversion circuit 204 and receives the slow start disable signal STDS through the digital circuit, the high-side level conversion circuit 203 and the low-side level conversion circuit 204 generate a high-level conversion signal according to the slow start disable signal STDS to turn on the third transistor 208 and the fourth transistor 209 of the second transistor circuit 208'. The slow start circuit 1 enters the normal mode from the slow start mode to transmit the audio signal through at least one low-selection circuit.

[0074] In one embodiment, the main switch driving circuit 217' includes a fifth transistor 217 and a sixth transistor 222. The gate of the fifth transistor 217 is electrically connected to the drain of the second transistor 207 of the first transistor circuit 206' and the drain of the third transistor 208 of the second transistor circuit 208' through the first node 215'. The gate of the sixth transistor 222 is electrically connected to the gate of the fifth transistor 217 and the first node 215'. After the source of the first transistor 206 of the first transistor circuit 206' receives the first current sent by the first current source 205, the fifth transistor 217 and the sixth transistor 222 are started through the first node 215'. The slow start current source ISOFT sends the slow start current to generate the main switch driving signal, and the slow start circuit 1 enters the slow start mode. In other words, since the time range of the slow start function is controlled by the digital circuit, when the slow start function ends, the digital circuit will send an end signal to turn off the high-side level conversion circuit 203 and turn on the low-side level conversion circuit 204, connecting the first node 215' to the output of at least one low-selection circuit through the third transistor 208 and the fourth transistor 209, so that VGS of the fifth transistor 217 and the sixth transistor 222 is 0, and the fifth transistor 217 and the sixth transistor 222 can be turned off, and the slow start function ends.

[0075] In one embodiment, the soft start circuit 1 includes a seventh transistor 216, an eighth transistor 215, a first resistor 214, a ninth transistor 221, a tenth transistor 220, a second resistor 219, a third resistor 218, a fourth resistor 223, a main switch transistor 201, a gate drive circuit 200, an eleventh transistor 210, a twelfth transistor 211, a first low selection circuit 212, a second low selection circuit 225, and a third low selection circuit 226. The source of the seventh transistor 216 is electrically connected to the drain of the fifth transistor 217. The source of the eighth transistor 215 is electrically connected to the gate and drain of the seventh transistor 216. One end of the first resistor 214 is electrically connected to the gate and drain of the eighth transistor 215. The source of the ninth transistor 221 is electrically connected to the drain of the sixth transistor 222. The source of the tenth transistor 220 is electrically connected to the gate and drain of the ninth transistor 221. One end of the second resistor 219 is electrically connected to the gate and drain of the tenth transistor 220. The other end of the second resistor 219 is electrically connected to the other end of the first resistor 214, a third node 224, and a soft start current source ISOFT.

[0076] In one embodiment, one end of the third resistor 218 is electrically connected to the source of the fifth transistor 217. After the high-side level conversion circuit 203 raises the voltage level at the first node 215' through the first transistor circuit 206' to turn on the fifth transistor 217, the first shunt of the first resistor 214, the third resistor 218, the fifth transistor 217, the seventh transistor 216, the eighth transistor 215, and the soft start current source ISOFT forms a first path. One end of the fourth resistor 223 is electrically connected to the source of the sixth transistor 222. After the high-side level conversion circuit 203 raises the voltage level at the first node 215' through the first transistor circuit 206' to turn on the sixth transistor 222, the second shunt of the second resistor 219, the fourth resistor 223, the sixth transistor 222, the ninth transistor 221, the tenth transistor 220, and the soft start current source ISOFT forms a second path.

[0077] In one embodiment, the drain of the main switch transistor 201 is electrically connected to the other end of the third resistor 218, the source of the main switch transistor 201 is electrically connected to the other end of the fourth resistor 223, and the gate of the main switch transistor 201 is electrically connected to the other end of the first resistor 214 and the other end of the second resistor 219. The voltage difference between the gate and source of the main switch transistor 201 is equal to the voltage difference formed after the first shunt flows through the first resistor 214, the seventh transistor 216, and the eighth transistor 215. The voltage difference between the gate and source of the main switch transistor 201 continues to increase until the operating mode region of the main switch transistor 201 jumps out of the saturation region to the linear region, and the soft start circuit 1 enters the normal operating mode from the soft start mode.

[0078] In one embodiment, the gate driving circuit 200 is electrically connected to the gate of the main switch transistor 201, the other end of the first resistor 214, and the other end of the second resistor 219. When the soft-start circuit 1 enters the normal operating mode from the soft-start mode, after the main switch transistor 201 enters the normal operating mode, the gate driving circuit 200 is enabled. The gate and drain of the eleventh transistor 210 are electrically connected to the first node 215', the drain of the second transistor 207 of the first transistor circuit 206', and the drain of the third transistor 208 of the second transistor circuit 208'. The gate and drain of the twelfth transistor 211 are electrically connected to the source of the eleventh transistor 210. When the high-side level conversion circuit 203 of the soft-start circuit 1 receives the soft-start enable signal STES, the first transistor 206 and the second transistor 207 of the first transistor circuit 206' receive the first current sent by the first current source 205 and then turn on the fifth transistor 217 of the main switch driving circuit 217' through the first node 215'. The voltage difference between the gate and the source of the fifth transistor 217 is equal to the voltage across the eleventh transistor 210 and the twelfth transistor 211.

[0079] For example, the source of the main switch transistor 201 is the output terminal connected to the load RL to GND (not shown in the figure), and the drain of the main switch transistor 201 is the input terminal connected to the input signal with a positive amplitude. After the soft-start mode is turned on, the first current of the first current source 205 flows through the first transistor 206 and the second transistor 207, then into the eleventh transistor 210 and the twelfth transistor 211, then into at least one select-low circuit, and then into the source or drain of the main switch transistor 201. At this time, the voltage level of the first node 215' is greater than the voltage of two diodes at the source (regarded as the voltage difference across the eleventh transistor 210 and the twelfth transistor 211), and the fifth transistor 217 is turned on. At this time, the eighth transistor 215, the seventh transistor 216, and the first resistor 214 are connected in series across the source and the gate of the main switch transistor 201. The gate-source voltage difference of the main switch transistor 201 is equal to the voltage drop formed after the soft-start current ISOFT flows through the first resistor 214, the eighth transistor 215, and the seventh transistor 216. This voltage drop increases as the soft-start current ISOFT increases, controlling the VGS between the source and the gate of the main switch transistor 201 until the main switch transistor 201 jumps out of the saturation region into the linear region, and the soft-start process ends. In other words, after the soft start, the soft-start circuit 1 enters the normal operating mode, and at this time, the gate driving circuit 200 is turned on.

[0080] For example, when entering the slow start mode, the high-side level conversion circuit 203 is turned on. The first current source 205 flowing out of the charge pump flows through the first transistor 206 (PMOS) and the second transistor 207 (PMOS), and then into the eleventh transistor 210 (NMOS) connected in series diode to the twelfth transistor 211 (NMOS), and then flows into at least one low-selection circuit. When the voltage difference between the source and drain of the main switch transistor 201 (NMOS) is large, the low-selection circuit selects the one with the lower voltage value. When the voltage difference between the two is very small, the average value of the two voltages is selected.

[0081] In one embodiment, the first input terminal of the first low-selection circuit 212 is electrically connected to the other end of the third resistor 218. The second input terminal of the first low-selection circuit 212 is electrically connected to the other end of the fourth resistor 223. The output terminal of the first low-selection circuit 212 is electrically connected to the source of the twelfth transistor 211. The first input terminal of the second low-selection circuit 225 is electrically connected to the first input terminal of the first low-selection circuit 212 and the other end of the third resistor 218. The second input terminal of the second low-selection circuit 225 is electrically connected to the second input terminal of the first low-selection circuit 212 and the other end of the fourth resistor 223. The first input terminal of the third low-selection circuit 226 is grounded, and the second input terminal of the third low-selection circuit 226 is electrically connected to the output terminal of the second low-selection circuit 225. The output of the third low-selection circuit 226 is electrically connected to the second transistor circuit 208' through the second node 227.

[0082] For example, when the low-side level conversion signal output by the low-side level conversion circuit 204 is at a high voltage level, the second transistor circuit 208' is turned on. The second node 227 selects the lower output among the audio input signal, the audio output signal, and GND, so that the voltage difference between the gate and source of the fifth transistor 217 is 0V or a negative voltage, turning off the fifth transistor 217 and the sixth transistor 222, and the slow start mode ends. The charge pump is a high-voltage power supply, and the low-selection circuit is an audio signal with a voltage range of -3.6V to +3.6V. Both the second transistor 207 (PMOS) and the third transistor 208 (NMOS) use high-voltage LDMOS. In Figure 2b wherein, A and B can be respectively the first input terminal and the second input terminal of the first low-selection circuit 212, and Y can be the output terminal of the first low-selection circuit 212. In Figure 2c wherein, A and B can be respectively the first input terminal and the second input terminal of the second and third low-selection circuits 225 and 226, and Y can be the output terminals of the second and third low-selection circuits 225 and 226.

[0083] In one embodiment, when the output of the low-side level conversion circuit 204 is high and the output of the high-side level conversion circuit 203 is high, the third transistor 208 (NMOS) and the fourth transistor 209 (NMOS) are turned on, and the second node 227 outputs the lower one among the audio input signal, the audio output signal, and GND. That is to say, when the audio input signal and the audio output signal are positive voltages, the second node 227 is GND, and when the audio input signal and the audio output signal are negative voltages, the second node 227 is also a negative voltage. This makes the VGS of the fifth transistor 217 (NMOS) 0V or a negative voltage, turning off the fifth transistor 217 (NMOS) and the sixth transistor 222 (NMOS), and ending the soft-start mode. The Body terminal of the twelfth transistor 211 (NMOS) is connected to the source, and the Body of the eleventh transistor 210 (NMOS) is connected to the drain. The parasitic Body diodes of the two eleventh transistors 210 and the twelfth transistor 211 form a back-to-back structure. In this case, when the soft-start mode is turned off, even if the audio input signal is a positive voltage, the second node 227 is 0V, and the first node 215' is a positive voltage, the diode-like structure formed by the two eleventh transistors 210, the twelfth transistor 211, and their parasitic Body will not conduct. For example, the soft-start is implemented in an analog manner, but the control of the soft-start, including the soft-start turn-on, turn-off, and time length, is controlled by a digital circuit. In this case, several links need to work in coordination: it is necessary to select appropriate soft-start current ISOFT, and the values of the first resistor 214 and the second resistor 219 to ensure that the analog soft-start action has been completed when the digital soft-start end control signal arrives for audio signals in the range of -3.6V to +3.6V.

[0084] In Figure 2aAmong them, the soft start circuit 1 further includes a soft start current source generation circuit 1'. The soft start current source generation circuit 1' includes a thirteenth transistor 103, a fourteenth transistor 104, a fifteenth transistor 105, a fifth resistor 107, a sixteenth transistor 106, a comparator 108, an amplifier 102, and a binary control circuit I2C. The drain of the thirteenth transistor 103 is electrically connected to the soft start current source ISOFT and transmits the soft start current. The source of the fourteenth transistor 104 is electrically connected to the source of the thirteenth transistor 103. The gate and drain of the fourteenth transistor 104 are electrically connected to the gate of the thirteenth transistor 103. The size of the thirteenth transistor 103 is the same as that of the fourteenth transistor 104. The drain of the fifteenth transistor 105 is electrically connected to the gate and drain of the fourteenth transistor 104 and the gate of the thirteenth transistor 103. One end of the fifth resistor 107 is electrically connected to the source of the fifteenth transistor 105, and the other end of the fifth resistor 107 is grounded. The drain of the sixteenth transistor 106 is electrically connected to one end of the fifth resistor 107, and the source of the sixteenth transistor 106 is grounded.

[0085] In an embodiment, the positive input terminal of the comparator 108 is electrically connected to one end of the fifth resistor 107 and the drain of the sixteenth transistor 106 and receives the CAP voltage signal VCAP. The negative input terminal of the comparator 108 receives the REF voltage signal VREF. The output terminal of the comparator 108 is electrically connected to the gate of the sixteenth transistor 106. When the voltage level of the CAP voltage signal VCAP is greater than the voltage level of the REF voltage signal VREF, the time range for the output terminal of the comparator 108 to start the sixteenth transistor 106 and then pull the voltage level of the CAP voltage signal VCAP to ground is the time range of the soft start mode. The output terminal of the amplifier 102 is electrically connected to the gate of the fifteenth transistor 105, and the positive input terminal of the amplifier 102 receives the SOFT voltage signal VSOFT. The negative input terminal of the amplifier 102 is electrically connected to the source of the fifteenth transistor 105, one end of the fifth resistor 107, the drain of the sixteenth transistor 106, and the positive input terminal of the comparator 108. The SOFT voltage signal VSOFT and the CAP voltage signal VCAP are at the same potential, and the soft start current is the SOFT voltage signal VSOFT divided by the fifth resistor 107. The amplifier 102, the fifteenth transistor 105, and the fifth resistor 107 form a negative feedback circuit.

[0086] In one embodiment, one end of the binary control circuit I2C is electrically connected to the positive input terminal of the amplifier 102 and the second current source 101, and the other end of the binary control circuit I2C is grounded. The second current source 101 and the binary control circuit I2C can be used to control the voltage level of the SOFT voltage signal VSOFT and the time range of the soft start mode. The binary control circuit I2C includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a fifth switch S5, a sixth switch S6, a seventh switch S7, an eighth switch S8, a first capacitor C1, a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a sixth capacitor C6, a seventh capacitor C7, and an eighth capacitor C8. The first switch S1 is connected in series with the first capacitor C1, the second switch S2 is connected in series with the second capacitor C2, the third switch S3 is connected in series with the third capacitor C3, the fourth switch S4 is connected in series with the fourth capacitor C4, the fifth switch S5 is connected in series with the fifth capacitor C5, the sixth switch S6 is connected in series with the sixth capacitor C6, the seventh switch S7 is connected in series with the seventh capacitor C7, and the eighth switch S8 is connected in series with the eighth capacitor C8 and then are respectively connected in parallel, so as to dynamically control the voltage level of the SOFT voltage signal VSOFT through the combined capacitance value of the second current source 101 and each capacitor, thereby extending or shortening the time range of the quasi slow start mode. Among them, the switches S1 to S8 are controlled by digital logic. When the system is applied, different slow start times can be obtained by rewriting through the interface. The present invention adopts I2C interface control. On the premise of ensuring that the slow start slope is slow enough, no external capacitor is required, which greatly reduces the cost of system manufacturers and improves the integration of the system.

[0087] For example, in this embodiment, the capacitance values C1 to C8 are 64 pF, 32 pF, 16 pF, 8 pF, 4 pF, 2 pF, 1 pF, and 0.5 pF in sequence, arranged in binary. It can be set that a small current source 101 (for example, 10 nA) flows into the capacitors C1 to C8 through the switches S1 to S8, forming a linearly slowly rising voltage VCAP. The amplifier 102, the fifteenth transistor 105 (NMOS), and the fifth resistor 107 form a stable negative feedback. The voltage values at the two input terminals of the negative feedback amplifier 102 are equal, that is, VSOFT = VCAP, and the current value flowing through the fifteenth transistor 105 (NMOS) and the fifth resistor 107 is equal to the ratio of VSOFT and the fifth resistor 107. It is also equal to the current of the thirteenth transistor 103 (PMOS). In this embodiment, the thirteenth transistor 103 (PMOS) and the fourteenth transistor 104 (PMOS) have the same size. Therefore, the following formula can be finally obtained:

[0088] ISOFT = VSOFT / R107 = VCAP / R107;

[0089] VCAP = I*t / C = 10 nA*t / C;

[0090] ISOFT = 10nA * t / C * R107;

[0091] When the VSOFT voltage is greater than VREF, the output of comparator 108 becomes high level, which will turn on the sixteenth transistor 106 (NMOS) and pull VSOFT to GND. This ends the current soft-start mode process. The VREF voltage should be selected as high as possible so that VCAP can reach the target voltage more slowly and the soft-start function is better. For example, the VREF received by the negative input terminal of comparator 108 can be generated internally by the soft-start circuit 1, so it is usually lower than the power supply voltage. In this embodiment, since the minimum power supply voltage VCC is 2.7V, VREF = 2.4V is selected. That is to say, after the soft start is enabled, the VCAP voltage linearly rises from 0V to 2.4V, and the maximum soft-start time is:

[0092] TSOFT = V * C / I = 2.4V * 127.5pF / 10nA = 30.6mS;

[0093] The minimum soft-start time and the digital control value of each step are both:

[0094] TSOFT = V * C / I = 2.4V * 0.5pF / 10nA = 120μS;

[0095] In this embodiment, see Figure 2 and Figure 2a , generally 5V NMOS and PMOS are used. Since the charge pump voltage is a high voltage, the fifteenth transistor 105 (NMOS), the thirteenth transistor 103 (PMOS), and the fourteenth transistor 104 (PMOS) use high-voltage LDMOS devices. At the same time, because the audio signal range spans from -3.6V to +3.6V, and the signal range itself is greater than 5V, it is more required that the thirteenth transistor 103 (PMOS) and the fourteenth transistor 104 (PMOS) need to use high-voltage devices. In addition, the soft-start mode requires a small current (regarded as the second current source 101) to flow into a large capacitor (regarded as the binary control circuit I2C) to form a slowly rising voltage (regarded as VSOFT).

[0096] In Figure 2dIn this case, the high-side level conversion circuit 203 and the low-side level conversion circuit 204 adopted by the present invention are controlled by the same control signal "slow start enable signal or slow start disable signal", and the power supply domain of the control signal is the power supply of the IC: VCC~VSS. The power supply domain of the low-side level conversion circuit is: VLDO~VLVSS, where VLDO is the 2V power supply output generated inside the IC, and VLVSS is the lower value selected from the audio signal and ground, that is, 0V or negative voltage (the lowest negative voltage is -3.6V). This structure can ensure that the withstand voltage of the low-side level conversion circuit 204 basically does not exceed 5V, and the withstand voltage of the 5.5V MOS reaches 5.5V. The power supply voltage of the high-side level conversion circuit 203 is the output VCP of the charge pump, which is a high voltage. Therefore, NMOS 307 and 308 adopt high-voltage LDMOS, and the negative power supply of the high-side level conversion circuit is GND. Among them, VBN is about 5V voltage, which can be the output voltage of a certain stage in the middle of the charge pump, and VBP is about 5V lower than the charge pump voltage, that is, VCP is -5V.

[0097] Embodiment 3

[0098] Please refer to Figure 3 , Figure 3 which is the flowchart of the control method of Embodiment 3 of the present invention. The control method is applied to the slow start circuit of the audio switch. The slow start circuit includes a high-side level conversion circuit, a first transistor circuit, a low-side level conversion circuit, a second transistor circuit, and a main switch drive circuit. The first transistor circuit is electrically connected to the high-side level conversion circuit, the low-side level conversion circuit is electrically connected to the high-side level conversion circuit, the second transistor circuit is electrically connected to the low-side level conversion circuit and the first transistor circuit, and the main switch drive circuit is electrically connected to the first node of the first transistor circuit and the second transistor circuit. The control method includes:

[0099] S310. The high-side level conversion circuit receives the slow start enable signal or slow start disable signal sent by the digital circuit;

[0100] S320. The low-side level conversion circuit receives the slow start enable signal or slow start disable signal;

[0101] S330. When the high-side level conversion circuit and the low-side level conversion circuit receive the slow start enable signal through the digital circuit, both the high-side level conversion circuit and the low-side level conversion circuit generate a low-level conversion signal according to the slow start enable signal, receive the first current sent by the first current source through the first transistor circuit, drive the main switch drive circuit to receive the slow start current sent by the slow start current source, generate a main switch drive signal, and the slow start circuit enters the slow start mode.

[0102] In one embodiment, when the high-side level conversion circuit and the low-side level conversion circuit receive a soft-start disable signal through a digital circuit, the high-side level conversion circuit and the low-side level conversion circuit generate a high-level conversion signal according to the soft-start disable signal to drive the main switch drive circuit through the second transistor circuit to generate a main switch disable signal, and the soft-start circuit enters the normal working mode from the soft-start mode to receive and transmit audio signals through at least one low-selection circuit.

[0103] As described above, it is only the specific implementation manner of the embodiments of the present invention, but the protection scope of the embodiments of the present invention is not limited thereto. Any person skilled in the art within the technical scope disclosed by the embodiments of the present invention can easily think of changes or substitutions, which should all be covered within the protection scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention should be subject to the protection scope of the claims.

Claims

1. A slow start circuit for an audio switch, characterized in that, The slow start circuit includes: A high-side level conversion circuit for receiving a slow start enable signal or a slow start disable signal sent by a digital circuit; A first transistor circuit electrically connected to the high-side level conversion circuit; A low-side level conversion circuit electrically connected to the high-side level conversion circuit, the low-side level conversion circuit being configured to receive the slow start enable signal or the slow start disable signal; A second transistor circuit electrically connected to the low-side level conversion circuit and the first transistor circuit; A main switch drive circuit electrically connected to a first node of the first transistor circuit and the second transistor circuit. Wherein, when the high-side level conversion circuit and the low-side level conversion circuit receive the slow start enable signal through the digital circuit, both the high-side level conversion circuit and the low-side level conversion circuit generate a low-level conversion signal according to the slow start enable signal to receive a first current sent by a first current source through the first transistor circuit, and then drive the main switch drive circuit to receive a slow start current sent by a slow start current source to generate a main switch drive signal, and the slow start circuit enters the slow start mode; The slow start circuit further includes a slow start current source generation circuit, and the slow start current source generation circuit: A thirteenth transistor, the drain of the thirteenth transistor is electrically connected to the slow start current source and sends the slow start current; A fourteenth transistor, the source of the fourteenth transistor is electrically connected to the source of the thirteenth transistor, and the gate and drain of the fourteenth transistor are electrically connected to the gate of the thirteenth transistor. Wherein, the size of the thirteenth transistor is the same as that of the fourteenth transistor; A fifteenth transistor, the drain of the fifteenth transistor is electrically connected to the gate and drain of the fourteenth transistor and the gate of the thirteenth transistor; A fifth resistor, one end of which is electrically connected to the source of the fifteenth transistor and the other end is grounded; A sixteenth transistor, the drain of the sixteenth transistor is electrically connected to one end of the fifth resistor, and the source of the sixteenth transistor is grounded; A comparator, the positive input terminal of the comparator is electrically connected to one end of the fifth resistor and the drain of the sixteenth transistor and receives a CAP voltage signal, the negative input terminal of the comparator receives a REF voltage signal, and the output terminal of the comparator is electrically connected to the gate of the sixteenth transistor. Wherein, when the voltage level of the CAP voltage signal is greater than the voltage level of the REF voltage signal, the output terminal of the comparator activates the sixteenth transistor and then pulls the voltage level of the CAP voltage signal to ground within the time range of the slow start mode; An amplifier, the output terminal of the amplifier is electrically connected to the gate of the fifteenth transistor. The positive input terminal of the amplifier receives a SOFT voltage signal. The negative input terminal of the amplifier is electrically connected to the source of the fifteenth transistor, one end of the fifth resistor, the drain of the sixteenth transistor, and the positive input terminal of the comparator. Among them, the SOFT voltage signal and the CAP voltage signal are at the same potential. The soft start current is the SOFT voltage signal divided by the fifth resistor. Among them, the amplifier, the fifteenth transistor, and the fifth resistor form a negative feedback circuit; A binary control circuit, one end is electrically connected to the positive input terminal of the amplifier and the second current source, and the other end is grounded. The second current source and the binary control circuit are used to control the voltage level of the SOFT voltage signal; The binary control circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, an eighth switch, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, a fifth capacitor, a sixth capacitor, a seventh capacitor, and an eighth capacitor. The first switch is connected in series with the first capacitor, the second switch is connected in series with the second capacitor, the third switch is connected in series with the third capacitor, the fourth switch is connected in series with the fourth capacitor, the fifth switch is connected in series with the fifth capacitor, the sixth switch is connected in series with the sixth capacitor, the seventh switch is connected in series with the seventh capacitor, and the eighth switch is connected in series with the eighth capacitor and then are respectively connected in parallel, so as to dynamically control the voltage level of the SOFT voltage signal through the combined capacitance value of the second current source and each capacitor, thereby extending or shortening the time range of the quasi-soft start mode; The main switch drive circuit includes: A fifth transistor, the gate of the fifth transistor is electrically connected to the first transistor circuit and the second transistor circuit through the first node; A sixth transistor, the gate of the sixth transistor is electrically connected to the gate of the fifth transistor and the first node. Among them, after the first transistor circuit receives the first current sent by the first current source, it starts the fifth transistor and the sixth transistor receives the soft start current sent by the soft start current source to generate a main switch drive signal, and the soft start circuit enters the soft start mode.

2. The slow start circuit according to claim 1, wherein When the high-side level conversion circuit and the low-side level conversion circuit receive the soft start disable signal through the digital circuit, the high-side level conversion circuit and the low-side level conversion circuit generate a high-level conversion signal according to the soft start disable signal to drive the main switch drive circuit through the second transistor circuit to generate a main switch disable signal, and the soft start circuit enters the normal working mode from the soft start mode to receive and transmit audio signals through at least one select-low circuit.

3. The slow start circuit according to claim 1, characterized in that, The first transistor circuit includes: A first transistor, the source of the first transistor is electrically connected to the first current source and receives the first current, and the gate of the first transistor is electrically connected to the high-side level conversion circuit and receives a high-side level conversion signal; A second transistor, the source of the second transistor being electrically connected to the drain of the first transistor, the gate of the second transistor receiving a BP voltage signal, wherein when the high-side level conversion circuit and the low-side level conversion circuit receive the soft-start enable signal through the digital circuit, the high-side level conversion circuit and the low-side level conversion circuit both generate a low-level conversion signal according to the soft-start enable signal to start the first transistor and the second transistor to receive the first current sent by the first current source, and the soft-start circuit enters the soft-start mode.

4. The slow start circuit according to claim 1, characterized in that, The second transistor circuit includes: A third transistor, the drain of the third transistor being electrically connected to the first current source transistor circuit, the gate of the third transistor receiving a BN voltage signal; A fourth transistor, the drain of the fourth transistor being electrically connected to the source of the third transistor, the gate of the fourth transistor being electrically connected to the low-side level conversion circuit and receiving a low-voltage level conversion signal, wherein when the high-side level conversion circuit and the low-side level conversion circuit receive the soft-start disable signal through the digital circuit, the high-side level conversion circuit and the low-side level conversion circuit generate a high-level conversion signal according to the soft-start disable signal to turn on the third transistor and the fourth transistor, and the soft-start circuit enters the normal mode from the soft-start mode to transmit and receive audio signals through at least one select-low circuit.

5. The slow start circuit according to claim 1, characterized in that The soft-start circuit further includes: A seventh transistor, the source of the seventh transistor being electrically connected to the drain of the fifth transistor; An eighth transistor, the source of the eighth transistor being electrically connected to the gate and the drain of the seventh transistor; A first resistor, one end being electrically connected to the gate and the drain of the eighth transistor; A ninth transistor, the source of the ninth transistor being electrically connected to the drain of the sixth transistor; A tenth transistor, the source of the tenth transistor being electrically connected to the gate and the drain of the ninth transistor; A second resistor, one end being electrically connected to the gate and the drain of the tenth transistor, and the other end being electrically connected to the other end of the first transistor and the soft-start current source; A third resistor, one end being electrically connected to the source of the fifth transistor, wherein after the first node raises the voltage level to start the fifth transistor, the first shunt of the first resistor, the third resistor, the fifth transistor, the seventh transistor, the eighth transistor and the soft-start current source is the first path; A fourth resistor, one end being electrically connected to the source of the sixth transistor, wherein after the first node raises the voltage level to start the sixth transistor, the second shunt of the second resistor, the fourth resistor, the sixth transistor, the ninth transistor, the tenth transistor and the soft-start current source is the second path; The main switching transistor, the drain of the main switching transistor is electrically connected to the other end of the third resistor, the source of the main switching transistor is electrically connected to the other end of the fourth resistor, and the gate of the main switching transistor is electrically connected to the other end of the first resistor and the other end of the second resistor. Wherein, the voltage difference between the gate and the source of the main switching transistor is equal to the voltage difference formed after the first shunt current flows into the first resistor, the seventh transistor, and the eighth transistor. The voltage difference between the gate and the source of the main switching transistor continues to increase until the operating mode region of the main switching transistor jumps out of the saturation region into the linear region, and the soft-start circuit enters the normal operating mode from the soft-start mode; The gate drive circuit is electrically connected to the gate of the main switching transistor, the other end of the first resistor, and the other end of the second resistor. Wherein, when the soft-start circuit enters the normal operating mode from the soft-start mode, after the main switching transistor enters the normal operating mode, the gate drive circuit is enabled; The eleventh transistor, the gate and the drain of the eleventh transistor are electrically connected to the first node, the first transistor circuit, and the second transistor circuit; The twelfth transistor, the gate and the drain of the twelfth transistor are electrically connected to the source of the eleventh transistor. Wherein, when the soft-start circuit receives the soft-start enable signal, after the first transistor circuit receives the first current sent by the first current source, the fifth transistor of the main switch drive circuit is turned on through the first node. The voltage difference between the gate and the source of the fifth transistor is equal to the voltage across the eleventh transistor and the twelfth transistor; The first low-selection circuit, the first input terminal of the first low-selection circuit is electrically connected to the other end of the third resistor, the second input terminal of the first low-selection circuit is electrically connected to the other end of the fourth resistor, and the output terminal of the first low-selection circuit is electrically connected to the source of the twelfth transistor; The second low-selection circuit, the first input terminal of the second low-selection circuit is electrically connected to the first input terminal of the first low-selection circuit and the other end of the third resistor, and the second input terminal of the second low-selection circuit is electrically connected to the second input terminal of the first low-selection circuit and the other end of the fourth resistor; The third low-selection circuit, the first input terminal of the third low-selection circuit is grounded, the second input terminal of the third low-selection circuit is electrically connected to the output terminal of the second low-selection circuit, and the output terminal of the third low-selection circuit is electrically connected to the second transistor circuit through the second node. Wherein, when the low-side level conversion signal output by the low-side level conversion circuit is at a high voltage level, the second transistor circuit is turned on, and the second node selects the lower output among the audio input signal, the audio output signal, and GND, so that the voltage difference between the gate and the source of the fifth transistor is 0V or a negative voltage, turning off the fifth transistor and the sixth transistor, and the soft-start mode ends.

6. A control method, characterized in that, The control method is applied to the slow start circuit of the audio switch described in any one of claims 1-5. The slow start circuit includes a high-side level conversion circuit, a first transistor circuit, a low-side level conversion circuit, a second transistor circuit, and a main switch drive circuit. The first transistor circuit is electrically connected to the high-side level conversion circuit, the low-side level conversion circuit is electrically connected to the high-side level conversion circuit, the second transistor circuit is electrically connected to the low-side level conversion circuit and the first transistor circuit, and the main switch drive circuit is electrically connected to the first node of the first transistor circuit and the second transistor circuit. The control method includes: The high-side level conversion circuit receives a slow start enable signal or a slow start disable signal sent by a digital circuit; The low-side level conversion circuit receives the slow start enable signal or the slow start disable signal; When the high-side level conversion circuit and the low-side level conversion circuit receive the slow start enable signal through the digital circuit, both the high-side level conversion circuit and the low-side level conversion circuit generate a low-level conversion signal according to the slow start enable signal to receive a first current sent by a first current source through the first transistor circuit, and then drive the main switch drive circuit to receive a slow start current sent by a slow start current source to generate a main switch drive signal, and the slow start circuit enters the slow start mode.

7. The control method according to claim 6, characterized in that When the high-side level conversion circuit and the low-side level conversion circuit receive the slow start disable signal through the digital circuit, the high-side level conversion circuit and the low-side level conversion circuit generate a high-level conversion signal according to the slow start disable signal to drive the main switch drive circuit to generate a main switch disable signal through the second transistor circuit, and the slow start circuit enters the normal operation mode from the slow start mode to transmit and receive audio signals through at least one select-low circuit.

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