System for page activation, computing system, and method for accessing memory

Abstract

A system for page activation, a computing system, and a method for accessing memory that effectively parallelizes dynamic random access memory operations with coherence operations to reduce memory access latency. The system may include a memory controller, an interconnect, and a processor. The interconnect may be coupled to the memory controller. The processor may be coupled to the memory controller via a first path and a second path, wherein the first path passes through the interconnect and the second path bypasses the interconnect. The processor may be configured to substantially concurrently send a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path, such that the dynamic random access memory access operation appears to be masked or hidden by the coherence operation.

Description

[0001] [CROSS-REFERENCE TO RELATED APPLICATIONS]

[0002] This patent application claims the benefit of priority to U.S. Provisional Patent Application No. 62 / 785,661, filed on December 27, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The subject matter disclosed herein generally relates to processing systems. More specifically, the subject matter disclosed herein relates to a system and method for providing speculative page activation for system memory. Background Art

[0004] Memory-access latency directly affects the performance of computing systems. Figure 1A A functional block diagram of a typical system on a chip (SoC) 100 is depicted. SoC 100 may include one or more processors 101a-101n, a coherent interconnect 102, one or more memory (dynamic random access memory (DRAM)) controllers 103a-103n, and one or more memories 104a-104n. Memories 104a-104n may be dynamic random access memories (DRAMs). In operation, a processor such as 101a-101n may send a memory access request to a memory controller such as 103a-103n via the coherent interconnect 102. The memory controller such as 103a-103n performs DRAM operations such as DRAM page close, DRAM page activate, and DRAM access, and the requested data is then returned to the processor such as 101a-101n via the interconnect 102.

[0005] The total memory access latency of SoC 100 may include latency associated with the requesting device (i.e., processors such as 101a-101n), clock-domain crossing (CDC) latency, latency associated with cache coherency components (i.e., cache and snoop filter (SF) lookups), latency of interconnect 102 (i.e., arbitration and serialization), and latency associated with DRAM page close, DRAM page activate, DRAM access, and data return.

[0006] Figure 1BMemory access delays associated with a typical memory controller such as 103a-103n and associated typical DRAM memories such as 104a-104n are depicted. Delays associated with DRAM access requests (entire request path) are represented at 111. Delays associated with DRAM activation are represented at 112. Delays associated with DRAM reads are represented at 113, and interconnect delays associated with providing a response to the requester are represented at 114. Summary of the invention

[0007] An exemplary embodiment provides a system for page activation, the system may include a memory controller, an interconnect, and a processor. The interconnect may be coupled to the memory controller, and the processor may be coupled to the memory controller via a first path and a second path, wherein the first path may pass through the interconnect, and the second path may bypass the interconnect. The processor may be configured to send a memory access request to the memory controller via the first path and send a page activation request or a hint request to the memory controller via the second path substantially concurrently. In one embodiment, the processor may be further configured to dynamically determine whether to send a memory access request via the second path based on the type of the memory access request or the current power / performance state of the system.

[0008] Another exemplary embodiment provides a computing system that may include a processor, a coherent interconnect, and a memory controller. The coherent interconnect may be coupled to the processor, and the memory controller may be coupled to the processor via a first path and a second path, wherein the first path may pass through the coherent interconnect and the second path may bypass the coherent interconnect. The memory controller may be configured to receive a memory access request from the processor via the first path and receive a page activation request or a hint request from the processor via the second path substantially concurrently. In one embodiment, the memory controller may be further configured to dynamically determine whether to respond to the memory access request via the second path based on the type of the memory access request or the current power / performance state of the computing system.

[0009] Another exemplary embodiment provides a method of accessing a memory, the method may include: receiving, at a memory controller, substantially concurrently via a first path, a page activation request or a hint request sent to the memory controller and receiving a memory access request via a second path, the first path bypassing an interconnect connected to the memory controller and the second path traversing the interconnect, the page activation request or the hint request including a page address; and if the memory controller determines that a page of the memory corresponding to the page activation request or the hint request is not yet opened, activating, by the memory controller, the page of the memory corresponding to the page address in response to the page activation request or the hint request before accessing the memory in response to the memory access request. In one embodiment, the method may further include dynamically determining by the memory controller, wherein the memory controller dynamically determines to respond to the memory access request via the second path based on the type of the memory access request or the current power / performance state of the memory controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In the following section, aspects of the subject matter disclosed herein will be explained with reference to exemplary embodiments shown in the drawings, in which:

[0011] Figure 1A Depicts the functional block diagram of a typical system-on-chip (SoC).

[0012] Figure 1B Depicted with Figure 1A Memory access latency associated with a typical memory controller of a typical SoC and the associated typical DRAM memory.

[0013] Figure 2A Depicted is a functional block diagram of an exemplary embodiment of a computing system in accordance with the subject matter disclosed herein.

[0014] Figure 2B Depicted are memory access latencies provided by a computing system utilizing a memory access technique that parallelizes DRAM operations with coherency operations in accordance with the subject matter disclosed herein.

[0015] Figure 3 Depicted is a flow chart of a memory access method that effectively parallelizes DRAM operations with coherency operations to reduce memory access latency in accordance with the subject matter disclosed herein.

[0016] Figure 4 Depicted is a functional block diagram of another exemplary embodiment of a computing system in accordance with the subject matter disclosed herein.

[0017] [Explanation of Symbols]

[0018] 100: Typical system-on-chip (SoC) / SoC;

[0019] 101a-101n, 201a-201n, 401a-401n: processor;

[0020] 102, 202: interconnection / coherent interconnection;

[0021] 103a-103n, 203a-203n, 403a-403n: memory (DRAM) controller;

[0022] 104a-104n, 204a-204n, 404a-404n: memory;

[0023] 111, 112, 113, 211, 212, 213: delay;

[0024] 114, 214: interconnection delay;

[0025] 200, 400: computing system;

[0026] 220a-220n, 420a-420n, 430a-430n, 440: out-of-band signaling lines;

[0027] 301, 302: steps;

[0028] 402: Interconnection. DETAILED DESCRIPTION

[0029] In the following detailed description, many specific details are set forth to provide a thorough understanding of the disclosure. However, those skilled in the art will appreciate that the disclosed aspects can be practiced without these specific details. In other cases, well-known methods, procedures, components, and circuits are not set forth in detail to avoid obscuring the subject matter disclosed herein.

[0030] References to "one embodiment" or "an embodiment" throughout this specification mean that a particular feature, structure, or characteristic described in conjunction with the embodiment may be included in at least one embodiment disclosed herein. Therefore, the phrases "in one embodiment" or "in an embodiment" or "according to one embodiment" (or other phrases with similar meanings) appearing throughout this specification may not necessarily refer to the same embodiment. In addition, in one or more embodiments, particular features, structures, or characteristics may be combined in any suitable manner. In this regard, the word "exemplary" used herein means "used as an example, instance, or illustration". Any embodiment described herein as "exemplary" should not be considered to be necessarily preferred or advantageous over other embodiments. In addition, depending on the context discussed herein, a singular term may include a corresponding plural form and a plural term may include a corresponding singular form. It should also be noted that the various figures (including component figures) shown and discussed herein are for illustrative purposes only and are not drawn to scale. Similarly, the various waveforms and timing diagrams shown are for illustrative purposes only. For example, for clarity, the size of some of the components may be exaggerated relative to other components. In addition, where appropriate, reference numerals are repeated in the figures to indicate corresponding components and / or similar components.

[0031] The terms used herein are only for the purpose of describing specific exemplary embodiments and are not intended to limit the claimed subject matter. Unless the context clearly indicates otherwise, the singular forms "a, an" and "the" used herein are intended to include the plural forms as well. It will also be understood that when the term "comprises and / or comprising" is used in this specification, it indicates the presence of the stated features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. The terms "first", "second", etc. used herein are used as labels for nouns following the terms, and unless clearly defined, the terms do not imply any type of order (e.g., space, time, logic, etc.). In addition, the same reference number may be used in two or more figures to refer to parts, components, blocks, circuits, units or modules having the same or similar functions. However, this usage is only for simplicity of illustration and ease of discussion; the usage does not imply that the construction details or architectural details of such components or units are the same in all embodiments or that these generally mentioned components / modules are the only way to implement the teachings of the specific embodiments disclosed herein.

[0032] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which the subject matter belongs. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted as having an idealized or overly formal meaning unless explicitly defined herein.

[0033] The term "module" as used herein refers to any combination of software, firmware, and / or hardware configured to provide the functionality described herein in conjunction with the module. Software may be implemented as a software package, code, and / or instruction set or instructions, and the term "hardware" used in any embodiment described herein may include, for example, hard-wired circuitry, programmable circuitry, state machine circuitry, and / or firmware storing instructions executed by programmable circuitry, either alone or in any combination. Modules may be implemented collectively or individually as circuitry that forms part of a larger system (e.g., but not limited to, an integrated circuit (IC), a system-on-chip (SoC), etc.).

[0034] The subject matter disclosed herein provides a memory access technique that effectively parallelizes DRAM operations with coherence operations to reduce memory access latency. In one embodiment, delays associated with DRAM access operations such as DRAM page close operations and / or DRAM page activations may occur concurrently with the coherence operations so that the DRAM access operations appear to be masked or hidden. By using out-of-band signaling that may, for example, initiate DRAM access operations in parallel with cache coherence operations, thereby masking or hiding delays associated with DRAM access operations through delays associated with cache coherence operations, clock domain crossings, and / or interconnect delays, reduced memory access latency may be achieved without overly complex techniques. Out-of-band signaling may include an "early" page activation request speculatively sent by a processor for a potential upcoming memory access request.

[0035] In one embodiment, a memory controller receiving out-of-band signaling may selectively not respond to the out-of-band signaling based on the workload experienced by the memory controller. That is, the memory controller may be configured to receive out-of-band signaling as a prompt, which may be selectively ignored based on the workload of the memory controller. If the memory controller chooses to respond to the prompt and access specific data in the DRAM, and if the accessed data is not required or is not the latest, the data may be discarded without affecting the system function. Therefore, the transmission mechanism may be damaged because some of the transmitted data may be discarded, but the overall system function will not be adversely affected. In another embodiment, the out-of-band signaling may include a priority indication associated with an early page activation request, and the memory controller may selectively ignore the priority indication based on the workload experienced by the memory controller, the access type (i.e., read or write, demand request or pre-fetch request), and / or the current power / performance state.

[0036] The subject matter disclosed herein also provides improved power efficiency for the processing system since the DRAM page is activated only if it is not already open. If such a command is actually required, the memory controller will send a memory page activation command to the DRAM at its discretion. Therefore, given the relatively slow rate involved in DRAM page activation compared to read requests, one page activation may be sufficient for multiple read accesses. Alternatively, if the performance / power tradeoff is acceptable, an out-of-band memory page activation request may be sent. Furthermore, an out-of-band memory page request provides routing efficiency since a full address bus is not required—only the DRAM page address is required.

[0037] Figure 2AA functional block diagram of an exemplary embodiment of a computing system 200 according to the subject matter disclosed herein is depicted. In one embodiment, the computing system 200 may be configured as a SoC. The computing system 200 may include one or more processors 201a-201n, an interconnect 202, one or more memory (DRAM) controllers 203a-203n, and one or more memories 204a-204n. The interconnect 202 may be a coherent interconnect or a non-coherent interconnect. The memories 204a-204n may be dynamic random access memories (DRAM). In one embodiment, memory controllers such as 203a-203n and corresponding memories such as 204a-204n may be implemented as memory modules.

[0038] In one mode of operation, computing system 200 may be similar to Figure 1A 100. More specifically, a processor such as 201a-201n may send a memory access request to a memory controller such as 203a-203n via coherent interconnect 202. The memory controller such as 203a-203n performs DRAM operations such as DRAM page close, DRAM page activate, and DRAM access to access the requested data, and the requested data is then returned to the processor such as 201a-201n via interconnect 202. In this mode of operation, the processor and the memory controller may communicate with each other through the coherent interconnect 202. Figure 1A Compared to the SoC 100 depicted in , reduced memory access latency may not be provided.

[0039] In another mode of operation, the computing system 200 utilizes memory access techniques that effectively parallelize DRAM operations with coherence operations to reduce memory access latency. Specifically, the computing system 200 includes out-of-band signaling lines 220a-220n, which bypass the interconnect 202 to provide early page activation requests directly from processors such as 201a-201n to memory controllers such as 203a-203n. The out-of-band signaling lines 220a-220n may also be referred to as speculative DRAM activation paths. In one embodiment, a separate out-of-band signaling line is provided from a processor such as 201a-201n to each memory controller 203a-203n. It should be understood that, although only the out-of-band signaling lines 220a-220n are depicted for the processor 201a, corresponding out-of-band signaling lines 220a-220n may also be provided for one or more processors 201b-201n. In one embodiment, the early page activation request may include an indication that the early page request is associated with a demand request or a prefetch request. In one embodiment, the processor may send the early page request via out-of-band signaling while querying the processor's internal cache if DRAM is to be accessed to further mask or hide memory access latency.

[0040] In one embodiment, processors such as 201a-201n may dynamically determine to send early page activation requests based on access type (i.e., read or write, demand request or pre-fetch request), current power / performance state. For example, if processors such as 201a-201n are in a high performance state, processors such as 201a-201n may determine to send early page activation requests more frequently than if processors such as 201a-201n are in a low power, low performance state. In one embodiment, if there are multiple accesses to the same DRAM page within a short period of time, processors such as 201a-201n may only need to send one early page activation request.

[0041] In one embodiment, a memory controller such as 203a-203n may be configured to respond to an early page activation request upon receipt of the early page activation request. In one embodiment, in response to receiving the early page activation request, a memory controller such as 203a-203n may selectively activate (i.e., open a new page) without any pre-charging (i.e., closing any other pages). In another embodiment, a memory controller such as 203a-203n may selectively pre-charge (i.e., close a page) in order to activate a page (i.e., open a new page). In yet another embodiment, a memory controller such as 203a-203n may selectively pre-charge (i.e., close a page) without performing page activation.

[0042] In another embodiment, a memory controller such as 203a-203n may be configured such that the out-of-band signaling is received by the memory controller such as 203a-203n as a hint, and the memory controller such as 203a-203n may selectively not respond to the out-of-band signaling based on, for example, the workload experienced by the memory controller. A memory controller such as 203a-203n may dynamically determine to respond to an early page activation request based on the workload experienced by the memory controller, the access type (i.e., read or write, demand request or prefetch request), and / or the current power / performance state.

[0043] Figure 2B Depicted are memory access latencies provided by computing system 200 utilizing memory access techniques that parallelize DRAM operations with coherency operations in accordance with the subject matter disclosed herein. The latency associated with coherent interconnect 202, represented at 211, is substantially simultaneous with the latency associated with an out-of-band DRAM page activation request, represented at 212. The latency associated with a DRAM read is represented at 213, and the interconnect latency associated with providing a response to the requestor is represented at 214. When Figure 1BWhen compared to the memory access latency depicted in Figure 2B The memory access latency depicted in has been reduced.

[0044] In one embodiment, the out-of-band signaling may additionally or alternatively include a page precharge request / hint. The memory controller may be configured to determine whether a precharge operation is required even if the corresponding page has not yet timed out. For example, an open page that is the target of an upcoming memory access may be close to timeout, and the memory controller may determine that it is advantageous to precharge the open page in advance along with an activate command.

[0045] Figure 3 A flow chart of a memory access method according to the subject matter disclosed herein is depicted, the memory access method effectively parallelizing DRAM operations with coherence operations to reduce memory access latency. At 301, a page activation request (or hint request) may be received via a first path by being received at a memory controller, such as memory controllers 203a-203n. The page activation request (or hint request) is sent to the memory controller substantially concurrently with a memory access request sent via a second path, wherein the first path bypasses an interconnect (e.g., interconnect 202) connected to the memory controller and the second path passes through the interconnect. In one embodiment, the page activation request (or hint request) may include, but is not limited to, a page address.

[0046] At 302, if the memory controller determines that the page of memory corresponding to the page activation request or the hint request is not already opened, the memory controller activates the page of memory corresponding to the page address in response to the page activation request (or the hint request) before accessing the memory in response to the memory access request.

[0047] In one embodiment, out-of-band requests may be prioritized for use in a decision process used by a memory controller to determine whether to precharge and / or activate a DRAM page for a particular request. For example, demand memory accesses may take precedence over prefetches, so if the controller is heavily loaded, the memory controller may determine to precharge and / or activate only the requesting DRAM page.

[0048] In another embodiment, early page activation may be dynamically enabled by a processor such as 201a-201n and / or by a memory controller such as 203a-203n based on a moving average of cycles between early page activation and corresponding demand requests. For example, if the average number of cycles between early page activation and corresponding demand requests exceeds a predetermined threshold, the early page activation function may be disabled because the average number of cycles indicates that the early page activation is premature and the precharge or activation caused by the early page activation may be in the wrong location in the DRAM.

[0049] In one embodiment, if the memory controller is heavily loaded, early page activation may be disabled to avoid thrashing of page activation.

[0050] In one embodiment, early page activation may be disabled by any of a processor such as 201a-201n and / or a memory controller such as 203a-203n for certain conditions or operations. For example, if the ratio of reads to writes is large, early page activation may be disabled for reads. Early page activation may also be disabled for a large hit rate occurring in the processor's last-level cache (LLC). For such a case, the cache controller may send the last-level cache (LLC) hit rate to the memory controller so that the memory controller may consider the LLC hit rate when determining whether to disable the early page activation function.

[0051] In one embodiment, if the number of early page activations exceeds a predetermined threshold during a predetermined time interval, early page activation may be disabled by a processor such as 201a-201n or by a memory controller such as 203a-203n because power may be wasted compared to any performance improvement that may be obtained through early page activation.

[0052] Another embodiment may provide system-level feedback (or feedback messages) from the interconnect and / or memory controller to the processor, which may be used to adjust the number of early page requests sent by the processor. The feedback may be provided as an out-of-band signal or provided via the interconnect. Additionally, feedback may be provided from the cache controller to the processor based on hits in the last level cache. In one embodiment, the memory controller may send feedback to the processor indicating that the memory controller did not respond to or act on an early page request.

[0053] Figure 4A functional block diagram of another exemplary embodiment of a computing system 400 according to the subject matter disclosed herein is depicted. In one embodiment, the computing system 400 may be configured as a SoC. The computing system 400 may include one or more processors 401a-401n, an interconnect 402, one or more memory (DRAM) controllers 403a-403n, and one or more memories 404a-404n. The interconnect 402 may be a coherent interconnect or a non-coherent interconnect. The memories 404a-404n may be dynamic random access memories (DRAM). In one embodiment, memory controllers such as 403a-403n and corresponding memories such as 404a-404n may be implemented as memory modules.

[0054] The computing system 400 may also include out-of-band signaling lines 420a-420n, which bypass the interconnect 402 to provide early page activation requests (or prompt requests) directly from processors such as 401a-401n to memory controllers such as 403a-403n. Feedback may be provided to processors such as 401a-401n from corresponding memory controllers such as 403a-403n via out-of-band signaling lines 430a-430n. It should be understood that although out-of-band signaling lines 420a-420n and 430a-430n are only depicted for processor 401a, corresponding out-of-band signaling lines 420a-420n and 430a-430n may be provided for one or more of the other processors 401b-401n. Feedback may also be provided by the interconnect 402 via out-of-band signaling lines 440.

[0055] As those skilled in the art will recognize, the innovative concepts described herein are susceptible to modification and variation over a wide range of applications. Accordingly, the scope of the claimed subject matter should not be limited to any specific exemplary teachings discussed above, but rather is defined by the appended claims.

Claims

1. A system for page activation, include: Memory controller; an interconnect coupled to the memory controller; as well as a processor coupled to the memory controller via a first path and a second path, the first path traversing the interconnect and the second path bypassing the interconnect, the processor being configured to concurrently send a memory access request to the memory controller via the first path and a page activate request or a hint request to the memory controller via the second path, Wherein the second path comprises a signaling line directly from the processor to the memory controller.

2. The system of claim 1, wherein the processor is further configured to dynamically determine whether to send the memory access request via the second path based on a type of memory access request or a current power or performance state of the system.

3. The system of claim 1 , further comprising a memory coupled to the memory controller, wherein the processor sends a page activation request via the second path, the page activation request including a page address, and The memory controller is configured to: determining whether a page of the memory corresponding to the memory access request has been opened, and If the memory controller determines that the page of the memory corresponding to the memory access request is not already open, then activating the page of the memory associated with the page address before accessing the memory in response to the memory access request.

4. The system of claim 1 , further comprising a memory coupled to the memory controller, wherein the processor sends a page activation request via the second path, the page activation request including a page address, and Wherein the memory controller is configured to ignore the page activation request before accessing the memory in response to the memory access request.

5. The system of claim 1 , further comprising a memory coupled to the memory controller, wherein the processor sends a prompt request via the second path, the prompt request including a page address, and The memory controller is configured to: determining whether a page of the memory corresponding to the memory access request has been opened, and If the memory controller determines that the page of the memory corresponding to the memory access request is not already open, then activating the page of the memory associated with the page address before accessing the memory in response to the memory access request.

6. The system of claim 1 , further comprising a memory coupled to the memory controller, wherein the processor sends a prompt request via the second path, the prompt request including a page address, and Wherein the memory controller is configured to ignore the hint request before accessing the memory in response to the memory access request. 7 . The system of claim 1 , wherein the memory access request sent to the memory controller via the first path comprises a coherent memory access request or a non-coherent memory access request.

8. The system of claim 1, wherein the memory controller or the interconnect is configured to send a feedback message to the processor as an indication not to send a page activate request or a hint request to the memory controller via the second path.

9. A computing system, include: processor; a coherent interconnect coupled to the processor; as well as a memory controller coupled to the processor via a first path and a second path, the first path passing through the coherent interconnect and the second path bypassing the coherent interconnect, the memory controller being configured to concurrently receive a memory access request from the processor via the first path and a page activate request or a hint request from the processor via the second path, Wherein the second path comprises a signaling line directly from the processor to the memory controller.

10. The computing system of claim 9, wherein the memory controller is further configured to dynamically determine whether to respond to the memory access request via the second path based on a type of the memory access request or a current power or performance state of the computing system.

11. The computing system of claim 9, wherein the memory controller receives a page activation request via the second path, the page activation request comprising a page address, and The memory controller is further configured to: determining whether a page of the memory corresponding to the memory access request has been opened, and If the memory controller determines that the page of the memory corresponding to the memory access request is not already open, then activating the page of the memory associated with the page address before accessing the memory in response to the memory access request.

12. The computing system of claim 9, wherein the memory controller receives a page activation request via the second path, the page activation request comprising a page address, and Wherein the memory controller is further configured to ignore the page activation request before accessing a memory in response to the memory access request.

13. The computing system of claim 9, wherein the memory controller further receives a hint request via the second path, the hint request comprising a page address, and The memory controller is further configured to: determining whether a page of the memory corresponding to the memory access request has been opened, and If the memory controller determines that the page of the memory corresponding to the memory access request is not already open, then activating the page of the memory associated with the page address before accessing the memory in response to the memory access request.

14. The computing system of claim 9, wherein the memory controller further receives a hint request via the second path, the hint request comprising a page address, and Wherein the memory controller is further configured to ignore the hint request before accessing memory in response to the memory access request. 15 . The computing system of claim 9 , wherein the memory controller or the coherent interconnect is configured to send a feedback message to the processor to not send a page activate request or a hint request to the memory controller via the second path.

16. A method of accessing a memory, include: concurrently receiving at a memory controller a page activation request or a hint request sent to the memory controller via a first path and a memory access request via a second path, the first path bypassing an interconnect connected to the memory controller and the second path traversing the interconnect, the page activation request or the hint request including a page address; as well as If the memory controller determines that the page of the memory corresponding to the page activation request or the hint request has not been opened, the memory controller activates the page of the memory corresponding to the page address in response to the page activation request or the hint request before accessing the memory in response to the memory access request.

17. The method of claim 16, further comprising dynamically determining, by the memory controller, whether to respond to the memory access request via the second path based on a type of the memory access request or a current power or performance state of the memory controller.

18. The method of claim 16, further comprising ignoring, by the memory controller, the page activation request or the hint request if the memory controller determines that the page activation request or the hint request is to be ignored.

19. The method of claim 16, wherein the interconnect is a coherent interconnect.

20. The method according to claim 16, wherein the page activation request or the prompt request is sent by a processor, The method further includes sending, by the memory controller, a feedback message to the processor to not send a page activate request or a hint request to the memory controller via the first path.

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