Semiconductor stack, semiconductor device, and method for manufacturing the same

Abstract

The present invention discloses a semiconductor stack, a semiconductor device, and a method for manufacturing the same. The semiconductor device includes a first semiconductor layer and a light-emitting structure. The first semiconductor layer includes a first III-V semiconductor material, a first dopant, and a second dopant. The light-emitting structure is located on the first semiconductor layer and includes an active structure. In the first semiconductor layer, the concentration of the second dopant is greater than that of the first dopant, the first dopant is carbon, and the second dopant is hydrogen.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a light-emitting device including a semiconductor stack. Background Art

[0002] With the rapid development of technology, semiconductor devices play a very important role in fields such as information transmission and energy conversion, and the research and development of related materials continue. For example, III-V semiconductor materials containing group III and group V elements can be applied to various optoelectronic devices such as light-emitting diodes (LEDs), laser diodes (LDs), solar cells, etc., and can also be applied to fields such as lighting, medical treatment, display, communication, sensing, and power systems. Light-emitting diode devices are suitable for solid-state lighting sources and have advantages such as low power consumption and long lifespan, and thus have gradually replaced traditional light sources and are widely used in traffic signals, backlight modules, various lighting, and medical devices, etc. Summary of the Invention

[0003] The present invention provides a semiconductor device, which includes a first semiconductor layer, a second semiconductor layer, a third semiconductor layer, and a light-emitting structure. The first semiconductor layer includes a first III-V semiconductor material, a first dopant, a second dopant, and a third dopant. The second semiconductor layer is located under the first semiconductor layer and includes a second III-V semiconductor material. The light-emitting structure is located on the first semiconductor layer and includes an active structure. The third semiconductor layer is located between the first semiconductor layer and the light-emitting structure, and includes a third III-V semiconductor material and a third dopant. In the first semiconductor layer, the concentration of the second dopant is greater than the concentration of the first dopant, the first dopant is carbon, the second dopant is hydrogen, and the concentration of the third dopant in the first semiconductor layer is lower than the concentration of the third dopant in the third semiconductor layer.

[0004] In an embodiment of the present invention, the second semiconductor layer includes a third dopant, and the concentration of the third dopant in the second semiconductor layer is greater than the concentration of the third dopant in the first semiconductor layer.

[0005] In an embodiment of the present invention, the second semiconductor layer further includes a first dopant and a second dopant.

[0006] In an embodiment of the present invention, the third semiconductor layer further includes a first dopant and a second dopant.

[0007] In an embodiment of the present invention, the first semiconductor layer has a first lattice constant, the second semiconductor layer has a second lattice constant, and the difference between the first lattice constant and the second lattice constant is 2% or more and 10% or less.

[0008] In one embodiment of the present invention, the first III-V semiconductor material is the same as the third III-V semiconductor material.

[0009] In one embodiment of the present invention, the first III-V semiconductor material is different from the second III-V semiconductor material.

[0010] In one embodiment of the present invention, the third dopant is silicon.

[0011] In one embodiment of the present invention, when the semiconductor device is operating, the active structure emits infrared light.

[0012] In one embodiment of the present invention, the infrared light has a peak wavelength between 800 nm and 1700 nm.

[0013] In one embodiment of the present invention, the concentration curve of the first dopant in the first semiconductor layer has a periodically varying pattern.

[0014] In one embodiment of the present invention, the concentration curve of the first dopant includes i local maxima and i local minima, where i is a positive integer greater than or equal to 5.

[0015] In one embodiment of the present invention, the light-emitting structure does not contain nitrogen.

[0016] In one embodiment of the present invention, the second III-V semiconductor material is a binary III-V semiconductor material.

[0017] The present invention further provides a method for manufacturing a semiconductor device, which includes: forming a first semiconductor layer, which includes a first III-V semiconductor material, a first dopant, a second dopant, and a third dopant; providing a second semiconductor layer, located under the first semiconductor layer and including a second III-V semiconductor material; forming a light-emitting structure, located on the first semiconductor layer and including an active structure; and providing a third semiconductor layer, located between the first semiconductor layer and the light-emitting structure, and including a third III-V semiconductor material and a third dopant. In the first semiconductor layer, the concentration of the second dopant is greater than the concentration of the first dopant, the first dopant is carbon, the second dopant is hydrogen, and the concentration of the third dopant in the first semiconductor layer is lower than the concentration of the third dopant in the third semiconductor layer.

[0018] In one embodiment of the present invention, providing the first semiconductor layer further includes: a first step, including growing a part of the first semiconductor layer at a first temperature; a second step, including providing a second temperature higher than the first temperature, where the second temperature is not less than 750 °C; and repeating the first step and the second step.

[0019] In one embodiment of the present invention, the first step and the second step are repeated more than ten times.

[0020] In an embodiment of the present invention, the difference between the first temperature and the second temperature is not less than 300 °C.

[0021] In an embodiment of the present invention, the growth of the first semiconductor layer is not performed at the second temperature.

[0022] The present invention further provides a semiconductor stack, which includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a first III-V semiconductor material, a first dopant, and a second dopant. The second semiconductor layer is adjacent to the first semiconductor layer and includes a second III-V semiconductor material. In the first semiconductor layer, the concentration of the second dopant is greater than the concentration of the first dopant, the first dopant is carbon, the second dopant is hydrogen, and under X-ray diffraction analysis, the first semiconductor layer has a full width at half maximum of 300 arcsec or less.

[0023] In an embodiment of the present invention, the first semiconductor layer and the second semiconductor layer further include a third dopant, and the concentration of the third dopant in the first semiconductor layer is lower than the concentration of the third dopant in the second semiconductor layer.

[0024] In an embodiment of the present invention, each constituent element of the second III-V semiconductor material is different from each constituent element of the first III-V semiconductor material.

[0025] In an embodiment of the present invention, the first semiconductor layer has a first lattice constant, the second semiconductor layer has a second lattice constant, and the first lattice constant is greater than the second lattice constant.

[0026] In an embodiment of the present invention, the difference between the first lattice constant and the second lattice constant is 2% or more and 10% or less.

[0027] In an embodiment of the present invention, it further includes a light-emitting structure, which is located on the first semiconductor layer and includes an active structure.

[0028] In an embodiment of the present invention, it further includes a third semiconductor layer, which is located between the first semiconductor layer and the light-emitting structure, and the third semiconductor layer includes a third III-V semiconductor material.

[0029] In an embodiment of the present invention, the first semiconductor layer and the third semiconductor layer further include a third dopant, and the concentration of the third dopant in the first semiconductor layer is lower than the concentration of the third dopant in the third semiconductor layer.

[0030] In an embodiment of the present invention, the third dopant is silicon.

[0031] In an embodiment of the present invention, when the semiconductor device is operating, the active structure emits an infrared light.

[0032] In one embodiment of the present invention, the infrared light has a peak wavelength between 800 nm and 1700 nm.

[0033] In one embodiment of the present invention, the concentration curve of the first dopant in the first semiconductor layer has a periodically varying pattern.

[0034] In one embodiment of the present invention, the concentration curve of the first dopant includes i local maxima and i local minima, and i is a positive integer greater than or equal to 5.

[0035] In one embodiment of the present invention, the light-emitting structure does not contain nitrogen.

[0036] In one embodiment of the present invention, the second semiconductor layer contains the third dopant, and the concentration of the third dopant in the second semiconductor layer is greater than the concentration of the third dopant in the first semiconductor layer. Description of the Drawings

[0037] Figure 1 It is a schematic structural diagram of a semiconductor stack according to one embodiment of the present invention;

[0038] Figure 2A It is a partial structural schematic diagram of a semiconductor element according to one embodiment of the present invention;

[0039] Figure 2B It is a partial structural schematic diagram of a semiconductor element according to one embodiment of the present invention;

[0040] Figure 3 It is a structural schematic diagram of a semiconductor element according to one embodiment of the present invention;

[0041] Figure 4 It is a structural schematic diagram of a semiconductor element according to one embodiment of the present invention;

[0042] Figures 5A to 5D It is a schematic diagram of a manufacturing method of a semiconductor stack according to one embodiment of the present invention;

[0043] Figure 5E It is a graph showing the relationship between the concentration and depth of elements in a partial range of a semiconductor element according to one embodiment of the present invention;

[0044] Figure 5F It is Figure 5E a partially enlarged schematic diagram showing the concentration curve of carbon (C) in;

[0045] Figure 6 It is a schematic diagram of a packaging structure of a semiconductor element according to one embodiment of the present invention.

[0046] Symbol Description

[0047] 10: Semiconductor stack

[0048] 20, 20', 30, 40, 60: Semiconductor components

[0049] 61: Encapsulation substrate

[0050] 62: Through-hole

[0051] 63: Carrier

[0052] 63a: First part

[0053] 63b: Second part

[0054] 65: Bonding wire

[0055] 66: Contact structure

[0056] 66a, 66b: Contact pads

[0057] 68: Encapsulation material

[0058] 100, 300, 400, 500: First semiconductor layer

[0059] 102, 402, 502: Second semiconductor layer

[0060] 204, 304, 404, 504: Third semiconductor layer

[0061] 206, 306, 406: Light-emitting structure

[0062] 208, 308, 408: Fourth semiconductor layer

[0063] 210, 310, 410: Active structure

[0064] 212, 312, 412: Fifth semiconductor layer

[0065] 414: Window layer

[0066] 416: Contact layer

[0067] 600: Encapsulation structure

[0068] 318, 418: First electrode

[0069] 320, 420: Second electrode

[0070] S510, S520, S530, S540: Steps

[0071] C1: First concentration

[0072] C2: Second concentration

[0073] C3: Second concentration

[0074] C L1 , CL2 , C Li , C M1 , C M2 , C Mi : Concentration Detailed implementation mode

[0075] The following embodiments will illustrate the concept of the present invention with accompanying drawings. In the drawings or the description, similar or identical components will be described using similar or identical reference numerals, and unless otherwise specified, the shapes or dimensions of the components in the drawings are only illustrative and are not actually limited thereto. It should be particularly noted that the components not shown or described in the drawings may be in forms known to those skilled in the art.

[0076] The general formula InGaAsP represents In x1 Ga 1-x1 As 1-y1 P y1 , where 0 < x1 < 1, 0 < y1 < 1; AlGaInAs represents (Al y2 Ga (1-y2) ) 1-x2 In x2 As, where 0 < x2 < 1, 0 < y2 < 1; the general formula AlGaInP represents (Al y3 Ga (1-y3) ) 1-x3 In x3 P, where 0 < x3 < 1, 0 < y3 < 1; the general formula InGaAs represents In x4 Ga 1-x4 As, where 0 < x4 < 1; the composition, additives, and dopants of each layer included in the semiconductor device of the present invention can be obtained by any suitable analysis method, such as a secondary ion mass spectrometer (SIMS), and the thickness of each layer can also be obtained by any suitable analysis method, such as a transmission electron microscope (TEM) or a scanning electron microscope (SEM). In addition, the dopants mentioned in the present invention can be intentionally added or unintentionally added. Intentional addition is, for example, by in-situ doping during epitaxial growth and / or by implanting with P-type or N-type dopants after epitaxial growth. Unintentional addition is, for example, caused by the design of the manufacturing process.

[0077] Those with ordinary knowledge in the relevant field should understand that other components can be added based on the embodiments described below. For example, without special specification, the description of "forming a second layer on the first layer" may include embodiments where the first layer and the second layer are in direct contact, and may also include embodiments where there are other layers between the first layer and the second layer and they are not in direct contact with each other. In addition, the up-and-down relationship of each layer may change depending on the operation or use of the structure or component in different orientations. Furthermore, in the present disclosure, the statement that a layer "substantially consists of X material" means that the main component of the layer is X material, but does not exclude the inclusion of dopants or inevitable impurities.

[0078] Figure 1 FIG. 4 is a schematic structural diagram of a semiconductor stack 10 according to an embodiment of the present disclosure. The semiconductor stack 10 includes a first semiconductor layer 100 and a second semiconductor layer 102. The second semiconductor layer 102 is adjacent to the first semiconductor layer 100. In this embodiment, a surface 100a of the first semiconductor layer 100 is in direct contact with a surface 102a of the second semiconductor layer 102. There is no other structure (such as a buffer layer, etc.) between the first semiconductor layer 100 and the second semiconductor layer 102.

[0079] In this embodiment, the first semiconductor layer 100 includes a first III-V semiconductor material. The first III-V semiconductor material is, for example, a binary III-V semiconductor material. The first III-V semiconductor material is a material composed of elements from groups III and V in the periodic table of chemical elements. The element in group III can be gallium (Ga) or indium (In). The element in group V can be arsenic (As) or phosphorus (P), and preferably does not include nitrogen (N). In one embodiment, the first semiconductor layer 100 substantially consists of the first III-V semiconductor material, for example, substantially consists of a binary III-V semiconductor material. In one embodiment, the first semiconductor layer 100 may include InP, and preferably the first semiconductor layer 100 substantially consists of InP. The first semiconductor layer 100 may include dopants. In one embodiment, the first semiconductor layer 100 includes a first dopant and a second dopant. In this embodiment, the concentration of the second dopant in the first semiconductor layer 100 is greater than the concentration of the first dopant. The first dopant is, for example, carbon (C), and the second dopant is, for example, hydrogen (H). Thus, the first semiconductor layer 100 can have a surface with stable properties and fewer epitaxial defects, and can be used, for example, as a surface for epitaxial layer growth. In one embodiment, the first semiconductor layer 100 may include a third dopant. The third dopant is, for example, silicon (Si). In one embodiment, the dopants in the first semiconductor layer 100 may each independently have a doping concentration of about 1×10 16 / cm 3 to about 1×10 19 / cm 3 and, for example, have a doping concentration of about 5×1016 / cm 3 to about 5×10 17 / cm 3 of doping concentration, or about 6×10 17 / cm 3 to about 5×10 18 / cm 3 of doping concentration, etc. In one embodiment, the concentration of the third dopant in the first semiconductor layer 100 is less than 1×10 19 / cm 3 , for example, in the range of about 6×10 16 / cm 3 to about 1×10 17 / cm 3 . When the dopant in the first semiconductor layer 100 has an appropriate doping concentration, the first semiconductor layer 100 can have better conductive characteristics. In one embodiment, the conductive type of the first semiconductor layer 100 is N-type.

[0080] In this embodiment, the second semiconductor layer 102 comprises a second III-V semiconductor material. The second semiconductor layer 102 is, for example, a binary III-V semiconductor material. The second III-V semiconductor material is a material composed of elements from groups III and V of the periodic table of chemical elements. The group III element can be gallium (Ga) or indium (In). The group V element can be arsenic (As) or phosphorus (P), preferably not including nitrogen (N). The second III-V semiconductor material is different from the first III-V semiconductor material. In one embodiment, each constituent element of the second III-V semiconductor material is different from each constituent element of the first III-V semiconductor material. In one embodiment, the second semiconductor layer 102 consists essentially of the second III-V semiconductor material, for example, consists essentially of a binary III-V semiconductor material. In one embodiment, the second semiconductor layer 102 may comprise GaAs, preferably the second semiconductor layer 102 consists essentially of GaAs. The second semiconductor layer 102 may contain a plurality of dopants. The plurality of dopants in the second semiconductor layer 102 may each independently have a doping concentration of about 5×10 15 / cm 3 to about 1×10 20 / cm 3 , for example, having a doping concentration of about 1×10 17 / cm 3 to about 1×10 18 / cm 3 , about 1×10 18 / cm 3 to about 1×10 19 / cm 3 of doping concentration, or about 1×10 19 / cm 3 to about 1 × 10 20 / cm 3 of the doping concentration. When the dopants in the second semiconductor layer 102 have an appropriate doping concentration, the second semiconductor layer 102 can have better conductive characteristics. The dopants in the second semiconductor layer 102 can include silicon (Si), zinc (Zn), carbon (C), hydrogen (H), etc. In one embodiment, the conductive type of the second semiconductor layer 102 is N-type. In some embodiments, the first semiconductor layer 100 and the second semiconductor layer 102 have the same conductive type, for example, both are P-type or N-type. In one embodiment, the resistivity of the second semiconductor layer 102 is above 10 7 Ω·cm and below 10 9 Ω·cm, for example, above 10 8 Ω·cm.

[0081] In some embodiments, both the first semiconductor layer 100 and the second semiconductor layer 102 contain a first dopant, a second dopant, and a third dopant. In some embodiments, the concentration of the third dopant in the second semiconductor layer 102 is higher than the concentration of the third dopant in the first semiconductor layer 100. In some embodiments, the concentration of the second dopant in the second semiconductor layer 102 is higher than the concentration of the second dopant in the first semiconductor layer 100. In some embodiments, the concentration of the first dopant in the second semiconductor layer 102 is lower than the concentration of the first dopant in the first semiconductor layer 100. The above-mentioned first dopant is, for example, carbon (C), the second dopant is, for example, hydrogen (H), and the third dopant is, for example, silicon (Si). By containing specific dopants, the first semiconductor layer 100 and the second semiconductor layer 102 can obtain appropriate conductive characteristics and epitaxial quality.

[0082] On the other hand, the first semiconductor layer 100 has a first lattice constant L1, and the second semiconductor layer 102 has a second lattice constant L2. In this embodiment, the first lattice constant L1 is greater than the second lattice constant L2, and the difference ΔL% between the first lattice constant L1 and the second lattice constant L2 is 2% or more, preferably 2.5% or more or 3% or more, and 10% or less, preferably 5% or less. Specifically, the difference between the first lattice constant L1 and the second lattice constant L2 can be calculated by the following formula: ΔL% = (L1 - L2) / L2 * 100%. The above-mentioned lattice constant refers to the value obtained by measuring the X-ray diffraction pattern of the semiconductor material at a temperature of 300K. Here, only the lattice constants of several semiconductor compounds are listed as references, as shown in Table 1 below.

[0083] Table 1

[0084]

[0085] The first semiconductor layer 100 and the second semiconductor layer 102 can be formed by liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), metal organic chemical vapor deposition (MOCVD), or hydride vapor phase epitaxial (HVPE). In this embodiment, the first semiconductor layer 100 is directly formed on the second semiconductor layer 102 as a substrate. The thickness of the first semiconductor layer can be 20 μm or less, preferably 10 μm or less, more preferably 5 μm or less, and can be 1 μm or more. In one embodiment, the thickness of the first semiconductor layer is 2 μm. When the thickness of the first semiconductor layer 100 is within the above range, it can have better structural stability and can further reduce the influence caused by lattice mismatch. The thickness of the second semiconductor layer 102 can be in the range of about 50 μm to about 1000 μm, such as about 100 μm to about 400 μm or about 150 μm to about 350 μm, etc. Setting the thickness within the above range can make the subsequent grown semiconductor structure have a more stable structure. When observing the semiconductor stack 10 including the first semiconductor layer 100 and the second semiconductor layer 102 with an electron microscope, few epitaxial defects can be observed on the surface of the first semiconductor layer 100. In some embodiments, under X-ray diffraction analysis (XRD), the full width at half maximum (FWHM) of the XRD of the first semiconductor layer 100 can be 500 arcsec or less, preferably 350 arcsec or less, more preferably 300 arcsec or less, such as in the range of 100 arcsec or more to 200 arcsec or less. Thus, the surface of the first semiconductor layer 100 is more suitable for the growth of other epitaxial layers. Specifically, the first semiconductor layer 100 or the semiconductor stack 10 including the first semiconductor layer 100 and the second semiconductor layer 102 can be used as a growth substrate for semiconductor elements.

[0086] Figure 2AFIG. 0 is a partial structural schematic diagram of a semiconductor element 20 according to an embodiment of the present invention. In this embodiment, the semiconductor element 20 includes a first semiconductor layer 100, a third semiconductor layer 204, and a light-emitting structure 206. For the composition of the first semiconductor layer 100 and the like, reference may be made to the foregoing description of the first semiconductor layer 100, which will not be repeated here. In addition, the third semiconductor layer 204 and the light-emitting structure 206 can be sequentially formed on the first semiconductor layer 100 by liquid phase epitaxy (LPE), molecular beam epitaxy (MBE), chemical beam epitaxy (CBE), metal organic chemical vapor deposition (MOCVD), or hydride vapor phase epitaxial (HVPE). In some embodiments, the first semiconductor layer 100, the third semiconductor layer 204, and the light-emitting structure 206 are sequentially formed on the second semiconductor layer 102 as described in the previous embodiment, and then the second semiconductor layer 102 is removed to form a structure as shown in Figure 2A shown.

[0087] As Figure 2A shown, the third semiconductor layer 204 is located on the first semiconductor layer 100 and adjacent to the first semiconductor layer 100. In this embodiment, there is no other structure (such as a buffer layer, etc.) between the first semiconductor layer 100 and the third semiconductor layer 204. The third semiconductor layer 204 may include a third III-V semiconductor material. The third III-V semiconductor material is, for example, a binary III-V semiconductor material. The third III-V semiconductor material is a material composed of elements from groups III and V in the periodic table of chemical elements. The group III element may be gallium (Ga) or indium (In). The group V element may be arsenic (As) or phosphorus (P), preferably not including nitrogen (N). In some embodiments, the third III-V semiconductor material is the same as the foregoing first III-V semiconductor material. Specifically, in some embodiments, the third semiconductor layer 204 is substantially composed of a third III-V semiconductor material, for example, substantially composed of a binary III-V semiconductor material. In one embodiment, the third semiconductor layer 204 may include InP, preferably the third semiconductor layer 204 is substantially composed of InP. In addition, the third semiconductor layer 204 may also include a plurality of dopants. In some embodiments, the plurality of dopants in the third semiconductor layer 204 may each independently have about 5×10 16 / cm 3 to about 5×10 18 / cm 3doping concentration, for example having about 5×10 17 / cm 3 to about 2×10 18 / cm 3 doping concentration, or about 5×10 16 / cm 3 to about 5×10 17 / cm 3 doping concentration. In some embodiments, both the first semiconductor layer 100 and the third semiconductor layer 204 contain a first dopant, a second dopant, and a third dopant. The first dopant is, for example, carbon (C), the second dopant is, for example, hydrogen (H), and the third dopant is, for example, silicon (Si). In some embodiments, forming the third semiconductor layer 204 on the first semiconductor layer 100 helps to further stabilize the epitaxial surface quality. In some embodiments, the third semiconductor layer 204 can serve as a window layer to improve the light-emitting efficiency of the semiconductor device 20, and the third semiconductor layer 204 is transparent to the light emitted by the light-emitting structure 206. In addition, in one embodiment, the conductivity type of the third semiconductor layer 204 is N-type.

[0088] The light-emitting structure 206 includes an active structure 210, a fourth semiconductor layer 208, and a fifth semiconductor layer 212. The active structure 210 may include a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multiple quantum wells (MQW) structure. When the semiconductor device 20 is in operation, the active structure 210 emits a radiation. The above radiation is preferably infrared light, such as near-infrared light (Near Infrared, NIR). Specifically, when the radiation is near-infrared light, it may have a peak wavelength between 800 nm and 1700 nm, such as: 810 nm, 840 nm, 910 nm, 940 nm, 1050 nm, 1070 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1450 nm, 1550 nm, 1600 nm, 1650 nm, 1700 nm, etc. The active structure 110 may include a fourth III-V semiconductor material, preferably the active structure 110 is substantially composed of the fourth III-V semiconductor material. The fourth III-V semiconductor material is a material composed of elements from groups III and V in the periodic table of chemical elements. The group III element may be gallium (Ga) or indium (In). The group V element may be arsenic (As) or phosphorus (P), preferably not including nitrogen (N). The fourth III-V semiconductor material may be a quaternary III-V semiconductor material. In some embodiments, the active structure 110 may include a quaternary III-V semiconductor material (such as InGaAsP or AlGaInAs), preferably the active structure 110 is substantially composed of a quaternary III-V semiconductor material (such as InGaAsP or AlGaInAs).

[0089] The fourth semiconductor layer 208 and the fifth semiconductor layer 212 are respectively located on both sides of the active structure 210, and the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may have opposite conductivity types. For example, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may be an n-type semiconductor and a p-type semiconductor respectively, to provide electrons and holes respectively. Alternatively, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 may be a p-type semiconductor and an n-type semiconductor respectively, to provide holes and electrons respectively. The fourth semiconductor layer 208 and the third semiconductor layer 204 may have the same conductivity type, such as both being n-type semiconductor layers. In addition, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 respectively comprise a fifth III-V semiconductor material and a sixth III-V semiconductor material. The fifth III-V semiconductor material and the sixth III-V semiconductor material may be binary, ternary or quaternary III-V semiconductor materials respectively. The III-V semiconductor material refers to a material composed of elements from Group III and Group V of the periodic table of chemical elements. The Group III element may be gallium (Ga) or indium (In). The Group V element may be arsenic (As) or phosphorus (P), preferably not including nitrogen (N). In one embodiment, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 respectively comprise a quaternary semiconductor material (such as InGaAsP, AlGaInP or AlGaInAs), preferably the fourth semiconductor layer 208 and the fifth semiconductor layer 212 are substantially respectively composed of a quaternary semiconductor material (such as InGaAsP, AlGaInP or AlGaInAs).

[0090] The fourth semiconductor layer 208 and the fifth semiconductor layer 212 have different conductivity types by adding different dopants. Specifically, the dopants include magnesium (Mg), zinc (Zn), silicon (Si), tellurium (Te), etc., but are not limited thereto. In some embodiments, the fourth semiconductor layer 208 and the fifth semiconductor layer 212 can be doped by in-situ doping during epitaxial growth and / or by implanting with P-type or N-type dopants after epitaxial growth. In one embodiment, the dopants in the fourth semiconductor layer 208 and the fifth semiconductor layer 212 can each independently have a doping concentration of about 2×10 17 / cm 3 to about 1×10 20 / cm 3 , for example having a doping concentration of about 5×10 17 / cm 3 to about 5×10 19 / cm 3 .

[0091] In some embodiments, an etch stop layer may be further disposed between the first semiconductor layer 100 and the light-emitting structure 206. Please refer to Figure 2A , for example, the etch stop layer (not shown) may be located between the first semiconductor layer 100 and the third semiconductor layer 204. Then, the first semiconductor layer 100 may be removed according to the requirements of the device structure, so as to form a semiconductor device 20’ as shown in Figure 2B . By providing the etch stop layer, the third semiconductor layer 204 and the light-emitting structure 206 can be prevented from being damaged when the first semiconductor layer 100 is removed. Next, the semiconductor device 20’ may include a bonding layer (not shown), and is bonded to a support substrate through the bonding layer, and subsequent manufacturing processes are performed. In one embodiment, the semiconductor device 20’ only includes the structure as shown in Figure 2B without having a support substrate. In some embodiments, the etch stop layer includes a seventh III-V semiconductor material. The seventh III-V semiconductor material may be a ternary or quaternary III-V semiconductor material. The III-V semiconductor material is a material composed of elements from groups III and V in the periodic table of chemical elements. The group III element may be aluminum (Al), gallium (Ga), or indium (In). The group V element may be arsenic (As) or phosphorus (P), preferably not including nitrogen (N). The etch stop layer preferably includes a group V element different from the group V element in the composition of the first semiconductor layer 100. In one embodiment, the etch stop layer may include a ternary III-V semiconductor material (such as InGaAs), preferably the etch stop layer is substantially composed of a ternary semiconductor material (such as InGaAs).

[0092] Based on the above, since the first semiconductor layer 100 may have a surface with a lower defect density, it is more suitable as a base layer for growing a semiconductor epitaxial layer. Specifically, when the third semiconductor layer 204 and other semiconductor layers are further formed on the first semiconductor layer 100, each semiconductor layer can still have good epitaxial quality.

[0093] Figure 3 FIG. 13 is a schematic structural diagram of a semiconductor device according to an embodiment of the present disclosure. In this embodiment, the semiconductor device 30 includes a first semiconductor layer 300, a third semiconductor layer 304, a light-emitting structure 306, a window layer 314, a first electrode 318, and a second electrode 320. For the composition of the first semiconductor layer 300, the third semiconductor layer 304, and the light-emitting structure 306, etc., reference may be made to the foregoing descriptions of the first semiconductor layer 100, the third semiconductor layer 204, and the light-emitting structure 206 respectively, which will not be repeated here. Specifically, for the composition of the fourth semiconductor layer 308, the active structure 310, and the fifth semiconductor layer 312 in the light-emitting structure 306, etc., reference may be made to the foregoing descriptions of the fourth semiconductor layer 208, the active structure 210, and the fifth semiconductor layer 212 respectively.

[0094] In this embodiment, the window layer 314 is located on the light-emitting structure 306 and is adjacent to the fifth semiconductor layer 312 in the light-emitting structure 306. In addition, the conductivity type of the window layer 314 is opposite to that of the third semiconductor layer 304. For example, when the window layer 314 is a P-type semiconductor layer, the third semiconductor layer 304 is an N-type semiconductor layer. The window layer 314 can be used as a light extraction layer, thereby further improving the light-emitting efficiency of the semiconductor element 30. In addition, the window layer 314 is transparent to the light emitted by the light-emitting structure 306.

[0095] The first electrode 318 and the second electrode 320 can be used to electrically connect to an external power source, and the first electrode 318 and the second electrode 320 are electrically connected to the light-emitting structure 306. In this embodiment, the first electrode 320 is adjacent to the window layer 314, and the second electrode 318 is adjacent to the first semiconductor layer 300, but in fact, it is not limited thereto. In addition, the materials of the first electrode 318 and the second electrode 320 can be the same or different, and for example, include transparent conductive materials, metals or alloys. The transparent conductive materials include metal oxides, such as indium tin oxide (ITO), indium oxide (InO), tin oxide (SnO), cadmium tin oxide (CTO), antimony tin oxide (ATO), aluminum zinc oxide (AZO), zinc tin oxide (ZTO), gallium zinc oxide (GZO), indium tungsten oxide (IWO), zinc oxide (ZnO) or indium zinc oxide (IZO), etc. Metals can include, for example, gold (Au), platinum (Pt), titanium (Ti), aluminum (Al), copper (Cu) or nickel (Ni), etc. Alloys can include, for example, germanium gold nickel (GeAuNi), beryllium gold (BeAu), germanium gold (GeAu), zinc gold (ZnAu), etc.

[0096] Figure 4 It is a schematic structural diagram of a semiconductor element according to an embodiment of the present invention. In this embodiment, the semiconductor element 40 includes a first semiconductor layer 400, a second semiconductor layer 402, a third semiconductor layer 404, a light-emitting structure 406, a window layer 414, a contact layer 416, a first electrode 420, and a second electrode 418. The main difference between the semiconductor element 40 and the aforementioned semiconductor element 30 is that it further includes a second semiconductor layer 402 and a contact layer 416. Regarding the composition of the first semiconductor layer 400, the second semiconductor layer 402, the third semiconductor layer 404, the light-emitting structure 406, the window layer 414, the first electrode 420, and the second electrode 418, etc., reference can be made to the description of the foregoing embodiments, and details will not be repeated here. Specifically, regarding the composition of the fourth semiconductor layer 408, the active structure 410, and the fifth semiconductor layer 412 in the light-emitting structure 406, reference can be made to the descriptions of the fourth semiconductor layer 208, the active structure 210, and the fifth semiconductor layer 212, respectively.

[0097] The contact layer 416 is located between the first electrode 420 and the window layer 414 and is used to conduct current. The contact layer 416 may have the same conductivity type as the window layer 314, for example, it is a P-type semiconductor layer. In this embodiment, the contact layer 416 is adjacent to the first electrode 420. Specifically, the contact layer 416 is, for example, a doped or undoped semiconductor material layer and may include a group III-V semiconductor material. The group III-V semiconductor material may be a binary or ternary group III-V semiconductor material, such as GaAs or InGaAs. When the first electrode 420 includes a metal or an alloy, an ohmic contact may be formed between the first electrode 420 and the contact layer 416, enabling a good electrical contact to be formed between the first electrode 420 and the light-emitting structure 406.

[0098] Figures 5A to 5B It is a schematic cross-sectional view of a method for manufacturing a semiconductor stack according to an embodiment of the present disclosure. Figure 5C It is a flowchart of fabricating a semiconductor stack according to an embodiment. The above semiconductor stack is, for example, a partial structure of a semiconductor device. As Figure 5A and Figure 5B shown, first, a second semiconductor layer 502 is provided, and a first semiconductor layer 500 is formed on the second semiconductor layer 502. The relevant descriptions of the first semiconductor layer 500 and the second semiconductor layer 502 can refer to the descriptions of the first semiconductor layer 100 and the second semiconductor layer 102 in the foregoing embodiments, and will not be elaborated herein.

[0099] Referring to Figures 5A to 5C , step S510 is performed to grow a part of the first semiconductor layer 500 at a first temperature. The growth of the first semiconductor layer 500 is achieved, for example, by Liquid Phase Epitaxy (LPE), Molecular Beam Epitaxy (MBE), Chemical Beam Epitaxy (CBE), Metal Organic Chemical Vapor Deposition (MOCVD), or hydride vapor phase epitaxial (HVPE). The first temperature is, for example, below 650°C and above 400°C, preferably not greater than 520°C, and more preferably in the range of 450°C to 510°C or 420°C to 500°C. By growing the first semiconductor layer 500 within the above temperature range, better epitaxial quality can be further obtained.

[0100] Next, step S520 is performed to provide a second temperature higher than the first temperature. The second temperature is, for example, above 700°C and below 850°C, preferably greater than 750°C, and more preferably in the range of 760°C to 810°C or 780°C to 800°C. In step S520, for example, the epitaxial ambient temperature is adjusted from the first temperature to the second temperature. In some embodiments, the difference between the first temperature and the second temperature is not less than 300°C, thereby achieving a better epitaxial effect. In addition, at the second temperature, the growth of the first semiconductor layer 500 may not be carried out. In this step, high-temperature tempering is performed by adjusting the ambient temperature to the higher second temperature. Not continuing the growth of the first semiconductor layer 500 at the second temperature can adjust the stress in a part of the first semiconductor layer 500 grown previously at the first temperature and reduce epitaxial defects.

[0101] Then, step S530 is entered to confirm whether the thickness of the first semiconductor layer 500 has reached a predetermined thickness. When the first semiconductor layer 500 has reached the predetermined thickness, the preparation of the first semiconductor layer 500 and the second semiconductor layer 502 is completed. In some embodiments, the predetermined thickness may be 20μm or less, preferably 10μm or less, more preferably 5μm or less, and may be 1μm or more. When the first semiconductor layer 500 has not reached the predetermined thickness, step S540 is entered, and steps S510 and S520 are repeated, for example, at least two or more times. In some embodiments, steps S510 and S520 may be repeated ten or more times to obtain a semiconductor stack with an appropriate thickness and a more stable epitaxial quality. In addition, the number of times of repeating steps S510 and S520 may be 30 or less.

[0102] Based on the above, by the method of heating and cooling during the preparation of the first semiconductor layer 500, there is no need to use other buffer structures or manufacturing processes to adjust the stress problem caused by lattice mismatch between the first semiconductor layer 500 and the second semiconductor layer 502, and a structure with good epitaxial quality can be obtained.

[0103] In some embodiments, the stack of the first semiconductor layer 500 and the second semiconductor layer 502 can be used as a base layer, and subsequent epitaxial structures can be grown as needed. For example, a light-emitting structure can be directly formed on the stack of the first semiconductor layer 500 and the second semiconductor layer 502.

[0104] Such as Figure 5DAs shown, a third semiconductor layer 504 can be further formed on the first semiconductor layer 500 and the second semiconductor layer 502. For the related description of the third semiconductor layer 504, reference can be made to the description of the third semiconductor layer 204 in the foregoing embodiments, which will not be elaborated herein. As described above, a light-emitting structure can be formed on the third semiconductor layer 504. One side of the first semiconductor layer 500 is adjacent to the second semiconductor layer 502, and the other side is adjacent to the third semiconductor layer 504. The surface 500a of the first semiconductor layer 500 directly contacts the surface 502a of the second semiconductor layer 502, and the other surface 500b directly contacts the surface 504a of the third semiconductor layer 504.

[0105] Figure 5E It is a graph showing the relationship between the concentration and depth of elements in a partial range of a semiconductor device according to an embodiment of the present disclosure. Specifically, Figure 5E is for a semiconductor device including a structure as shown in Figure 5D The result of secondary ion mass spectrometry (SIMS) analysis of a partial region of the semiconductor device. As shown in Figure 5E As shown, according to the thickness and order of each layer in the semiconductor device, it can be roughly divided into a first region Z1, a second region Z2, and a third region Z3. Specifically, the first region Z1 corresponds to the second semiconductor layer 502, the second region Z2 corresponds to the first semiconductor layer 500, and the third region Z3 corresponds to the third semiconductor layer 504. And in this embodiment, both the first semiconductor layer 500 and the third semiconductor layer 504 contain a plurality of dopants and are substantially composed of InP, and the second semiconductor layer 502 contains a plurality of dopants and is substantially composed of GaAs. The above-mentioned dopants at least include a first dopant, a second dopant, and a third dopant. The first dopant is carbon (C) and is represented by C1, the second dopant is hydrogen (H) and is represented by C2, and the third dopant is silicon (Si) and is represented by C3. The concentrations of C1, C2, and C3 of the first, second, and third dopants are referred to the Figure 5E vertical axis on the left. In this embodiment, the first dopant and the second dopant are unintentionally doped, and the third dopant is intentionally doped.

[0106] By growing the first semiconductor layer 500 with a single-layer structure in the above manner, the unintentionally doped first dopant and second dopant have a doping concentration greater than 10 16 / cm 3 in the first semiconductor layer 500, and the concentration curve of carbon (C) has a pattern similar to a periodic change. As shown in Figure 5EAs shown, in the second region Z2, the concentration of the second dopant is higher than that of the first dopant, that is, the hydrogen (H) concentration in the first semiconductor layer 500 is greater than the carbon (C) concentration. In addition, the concentration of the third dopant in the second region Z2 is lower than that in the first region Z1 and also lower than that in the third region Z3. That is, the silicon (Si) concentration in the first semiconductor layer 500 is lower than that in the second semiconductor layer 502 or the third semiconductor layer 504. On the other hand, in the second region Z2, the concentration of the second dopant is higher than that of the third dopant, that is, the hydrogen (H) concentration in the first semiconductor layer 500 is greater than the silicon (Si) concentration.

[0107] Figure 5F For Figure 5E a partially enlarged schematic view of the concentration curve of the first dopant (carbon (C)) within the dashed box region in the second region Z2. As Figure 5F shown, in this embodiment, the concentration distribution of the first dopant (carbon (C)) includes at least i local maxima (such as the concentrations C L1 , C L2 , …, C Li ) and i local minima (such as the concentrations C M1 , C M2 , …, C Mi ), where i is a positive integer greater than or equal to 5. In the local region shown in Figure 5F , i = 8. The local maxima and local minima appear alternately, and any one of the local maxima is greater than any one of the local minima. As Figure 5E shown, at some depth positions in the second region Z2, the concentration of the third dopant is less than some of the local maxima; at some depth positions in the second region Z2, the concentration of the third dopant is greater than some of the local minima. That is, in the second region Z2, the concentration of the third dopant can be less than some of the local maxima and can be greater than some of the local minima.

[0108] As Figure 5E shown, in this embodiment, the doping concentration of silicon (Si) in the first semiconductor layer 500 is below 1×10 17 / cm 3 , and is in the range of about 5×10 16 / cm 3 to about 9×10 16 / cm 3 ; the carbon (C) concentration is in the range of about 4×10 16 / cm 3 to about 9×10 16 / cm 3 ; the hydrogen (H) concentration is in the range of about 1×10 17 / cm 3 to about 5×1017 / cm 3 On the other hand, in some embodiments, the first region Z1, the second region Z2, and the third region Z3 also contain inevitable impurities such as oxygen (O), etc. For the sake of simplicity, they are not shown here. In one embodiment, the oxygen (O) concentration distribution in the first region Z1, the second region Z2, and the third region Z3 is in the range of 3×10 15 / cm 3 to 2×10 16 / cm 3 , approaching the detection limit of secondary ion mass spectrometry (SIMS) analysis.

[0109] Figure 6 FIG. is a schematic diagram of a packaging structure of a semiconductor device according to an embodiment of the present invention. Please refer to Figure 6 , the packaging structure 600 includes a semiconductor device 60, a packaging substrate 61, a carrier 63, bonding wires 65, a contact structure 66, and a packaging material 68. The packaging substrate 61 may include a ceramic or glass material. The packaging substrate 61 has a plurality of through holes 62. The through holes 62 may be filled with a conductive material such as metal to facilitate conduction and / or heat dissipation. The carrier 63 is located on a surface of one side of the packaging substrate 61 and also includes a conductive material, such as metal. The contact structure 66 is located on a surface of the other side of the packaging substrate 61. In this embodiment, the contact structure 66 includes a contact pad 66a and a contact pad 66b, and the contact pad 66a and the contact pad 66b can be electrically connected to the carrier 63 through the through holes 62. In one embodiment, the contact structure 66 may further include a thermal pad (not shown), for example, located between the contact pad 66a and the contact pad 66b. The semiconductor device 60 is located on the carrier 63 and may be the semiconductor device described in any embodiment of the present invention. In this embodiment, the carrier 63 includes a first portion 63a and a second portion 63b, and the semiconductor device 60 is electrically connected to the second portion 63b of the carrier 63 through the bonding wires 65. The material of the bonding wires 65 may include metal, such as gold, silver, copper, aluminum, or an alloy containing at least any one of the above elements. The packaging material 68 covers the semiconductor device 60 and has the effect of protecting the semiconductor device 60. Specifically, the packaging material 68 may include a resin material such as epoxy resin, silicone resin, etc. The packaging material 68 may further include a plurality of wavelength conversion particles (not shown in the figure) to convert the first light emitted by the semiconductor device 60 into a second light. The wavelength of the second light is greater than the wavelength of the first light.

[0110] The semiconductor device of the present invention can be applied to products in the fields of lighting, medical treatment, display, communication, sensing, power supply system, etc., such as lamps, monitors, mobile phones, tablet computers, vehicle instrument panels, televisions, computers, wearable devices (such as watches, bracelets, necklaces, etc.), traffic signals, outdoor displays, medical devices, etc.

[0111] Based on the above, according to some embodiments of the content of the present invention, a semiconductor structure can be provided, which has good surface epitaxial quality, can be used as a substrate of a semiconductor device, for example, and is beneficial to further reducing the production cost of the semiconductor device. According to some embodiments of the content of the present invention, a semiconductor device and a manufacturing method thereof can be provided, which achieve excellent technical effects in adjusting the stress generated by lattice mismatch between heteroepitaxies, and can avoid the situation that defects appear at the interface of the epitaxial layer.

[0112] Although the present invention is disclosed in connection with the above embodiments, it is not intended to limit the present invention. Those of ordinary skill in the art should understand that some modifications or changes can be made without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be defined by the appended claims. In addition, the above embodiments can be combined or replaced with each other under appropriate circumstances, rather than being limited to the specific embodiments described. For example, the relevant parameters of a specific component or the connection relationship between a specific component and other components disclosed in one embodiment can also be applied to other embodiments, and all fall within the scope of the protection of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A first semiconductor layer comprising a first III-V semiconductor material, a first dopant, a second dopant, and a third dopant; A second semiconductor layer located under the first semiconductor layer and comprising a second III-V semiconductor material; A light-emitting structure located on the first semiconductor layer and comprising an active structure; And A third semiconductor layer located between the first semiconductor layer and the light-emitting structure and comprising a third III-V semiconductor material and the third dopant; Wherein, in the first semiconductor layer, the concentration of the second dopant is greater than the concentration of the first dopant, the first dopant is carbon, the second dopant is hydrogen, and the concentration of the third dopant in the first semiconductor layer is lower than the concentration of the third dopant in the third semiconductor layer.

2. The semiconductor device according to claim 1, wherein the second semiconductor layer comprises the third dopant, and the concentration of the third dopant in the second semiconductor layer is greater than the concentration of the third dopant in the first semiconductor layer.

3. The semiconductor device according to claim 1, wherein the second semiconductor layer further comprises the first dopant and the second dopant.

4. The semiconductor device according to claim 1, wherein the third semiconductor layer further comprises the first dopant and the second dopant.

5. The semiconductor device according to claim 1, wherein the first semiconductor layer has a first lattice constant, the second semiconductor layer has a second lattice constant, and the difference between the first lattice constant and the second lattice constant is 2% or more and 10% or less.

6. The semiconductor device according to claim 1, wherein the first III-V semiconductor material is the same as the third III-V semiconductor material.

7. The semiconductor device according to claim 1, wherein the first III-V semiconductor material is different from the second III-V semiconductor material.

8. The semiconductor device according to claim 1, wherein the third dopant is silicon.

9. The semiconductor device according to claim 1, wherein when the semiconductor device is operating, the active structure emits an infrared light.

10. The semiconductor device according to claim 9, wherein the infrared light has a peak wavelength between 800 nm and 1700 nm.

11. The semiconductor device according to claim 1, wherein the concentration curve of the first dopant in the first semiconductor layer has a periodically varying pattern.

12. The semiconductor device according to claim 11, wherein the concentration curve of the first dopant comprises i local maxima and i local minima, and i is a positive integer greater than or equal to 5.

13. The semiconductor device according to claim 1, wherein the light-emitting structure does not contain nitrogen.

14. The semiconductor device according to claim 1, wherein the second III-V semiconductor material is a binary III-V semiconductor material.

15. A method of manufacturing a semiconductor device, comprising: Providing a first semiconductor layer comprising a first III-V semiconductor material, a first dopant, a second dopant, and a third dopant; Providing a second semiconductor layer, located under the first semiconductor layer and containing a second III-V semiconductor material; Forming a light-emitting structure, located on the first semiconductor layer and containing an active structure; and Providing a third semiconductor layer, located between the first semiconductor layer and the light-emitting structure, and containing a third III-V semiconductor material and the third dopant; Among them, In the first semiconductor layer, the concentration of the second dopant is greater than the concentration of the first dopant, the first dopant is carbon, the second dopant is hydrogen, and the concentration of the third dopant in the first semiconductor layer is lower than the concentration of the third dopant in the third semiconductor layer.

16. The method of manufacturing a semiconductor device according to claim 15, wherein providing the first semiconductor layer further comprises: A first step, including growing a part of the first semiconductor layer at a first temperature; A second step, including providing a second temperature higher than the first temperature, wherein the second temperature is not less than 750 °C; and Repeating the first step and the second step.

17. The method of manufacturing a semiconductor device according to claim 16, wherein the first step and the second step are repeated more than ten times.

18. The method of manufacturing a semiconductor device according to claim 16, wherein the difference between the first temperature and the second temperature is not less than 300 °C.

19. The method of manufacturing a semiconductor device according to claim 16, wherein the first semiconductor layer is not grown at the second temperature.

20. A semiconductor stack, characterized in that, Comprising: A first semiconductor layer, containing a first III-V semiconductor material, a first dopant, and a second dopant; and A second semiconductor layer, adjacent to the first semiconductor layer and containing a second III-V semiconductor material; wherein, in the first semiconductor layer, the concentration of the second dopant is greater than the concentration of the first dopant, the first dopant is carbon, the second dopant is hydrogen, and under X-ray diffraction analysis, the first semiconductor layer has a full width at half maximum of 300 arcsec or less.

21. The semiconductor stack according to claim 20, wherein the first semiconductor layer and the second semiconductor layer further include a third dopant, and the concentration of the third dopant in the first semiconductor layer is lower than the concentration of the third dopant in the second semiconductor layer.

22. The semiconductor stack according to claim 20, wherein each constituent element of the second III-V semiconductor material is different from each constituent element of the first III-V semiconductor material.

23. The semiconductor stack according to claim 20, wherein the first semiconductor layer has a first lattice constant, the second semiconductor layer has a second lattice constant, and the first lattice constant is greater than the second lattice constant.

24. The semiconductor stack according to claim 23, wherein the difference between the first lattice constant and the second lattice constant is 2% or more and 10% or less.

25. The semiconductor stack according to claim 20, further comprising a light-emitting structure, located on the first semiconductor layer and containing an active structure.

26. The semiconductor stack as claimed in claim 25 further comprises a third semiconductor layer located between the first semiconductor layer and the light-emitting structure, and the third semiconductor layer comprises a third III-V semiconductor material.

27. The semiconductor stack as claimed in claim 26, wherein the first semiconductor layer and the third semiconductor layer further comprise a third dopant, and the concentration of the third dopant in the first semiconductor layer is lower than the concentration of the third dopant in the third semiconductor layer.

28. The semiconductor stack as claimed in claim 27, wherein the third dopant is silicon.

29. The semiconductor stack as claimed in claim 25, wherein when the semiconductor stack is in operation, the active structure emits an infrared light.

30. The semiconductor stack as claimed in claim 29, wherein the infrared light has a peak wavelength between 800 nm and 1700 nm.

31. The semiconductor stack as claimed in claim 20, wherein the concentration curve of the first dopant in the first semiconductor layer has a periodically varying pattern.

32. The semiconductor stack as claimed in claim 31, wherein the concentration curve of the first dopant comprises i local maxima and i local minima, and i is a positive integer greater than or equal to 5.

33. The semiconductor stack as claimed in claim 25, wherein the light-emitting structure does not contain nitrogen.

34. The semiconductor stack as claimed in claim 27, wherein the second semiconductor layer comprises the third dopant, and the concentration of the third dopant in the second semiconductor layer is greater than the concentration of the third dopant in the first semiconductor layer.

Images