Enhanced noise immunity latched logic state retention

Abstract

The present application discloses a method for enhancing the logic state retention of a latch for noise immunity. In the described example, a latch (see 260) includes a circuit (see 220) for latching input information. The circuit can be precharged in response to an indication of a first mode (see 210) and can latch the input information to an indication of a second mode (see 210). The latch can optionally also latch the input information in response to a node (see 290, 292) for storing the latched input information.

Description

Background Art

[0001] Electronic circuits are being designed to include increasingly smaller design features to achieve increased functionality and reduced power consumption. Such electronic circuits may be implemented as SoC (system on a chip) designs implemented using VLSI (very large scale integration) technology. Power management features for controlling power consumption may be included in such VLSI circuits. For example, power management features may monitor and control parameters such as the rate and amount of power consumption, operating temperature, component lifespan, and battery life of devices incorporating the VLSI circuits. However, reducing the rate of power consumption may result in data loss in such devices. Summary of the Invention

[0002] In the described example, the latch includes circuitry for latching input information. The circuitry may be precharged in response to an indication of a first mode and may latch the input information in response to an indication of a second mode. The latch may optionally further latch the input information in response to a node for storing the latched input information. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram of an example system including an example master-slave retention (MSR) latch.

[0004] Figure 2 is a schematic diagram of an example MSR latch.

[0005] Figure 3 is a waveform diagram of an example mode transition of an example MSR latch.

[0006] Figure 4 is a schematic diagram of example directly and indirectly coupled D latches. DETAILED DESCRIPTION

[0007] For example, various highly integrated systems (such as SoCs - systems on a chip) may be powered from dynamically selectable power domains to reduce power consumption. The highly integrated systems may include a power management control unit that may selectively control the application of power to circuits powered by independent or overlapping power domains. Circuits within at least one particular power domain may be activated (or deactivated) in response to selection of one of various power modes, such as a "sleep" mode in which performance is reduced by selectively removing some (or all) power from the system (which conserves power), or an "active" mode in which power is provided for increased processing speed and / or functionality.

[0008] Sometimes, circuits used to maintain logic states are powered down to avoid continued power consumption. Because powering down a circuit can result in the loss of data stored by the active circuit, various steps can be taken to preserve the data before powering down the circuit that includes the logic state. In one example, data stored in a latch (e.g., a "flip-flop") can be preserved by writing the stored data (e.g., the stored data is stored as a quantized voltage level in a node of the active circuit) to non-volatile memory. However, including local or networked non-volatile memory in a system can increase cost, increase power consumption, and slow system operation.

[0009] Figure 1 1 is a block diagram of an example system 100 including an example master-slave retention (MSR) latch. Example system 100 includes a substrate 101 that includes a processor 102, a clock generator 104, a memory 106, a power mode selector 108, a power supply 110, a user / system interface 112, and MSR latch circuits 150, 160, and 170.

[0010] In at least one embodiment, processor 102 is configured to execute instructions (e.g., software stored in memory 106) that, when executed by processor 102, transform processor 102 into a special-purpose machine configured to perform at least one specific function or task. Processor 102 may be a microprocessor, a microcontroller, a digital signal processor (DSP), or the like. Processor 102 may also be any programmable digital module or ad hoc circuit for processing signals or data. Processor 102 is configured to read selected latch data (including scan chain data) from MSR latch circuits 150, 160, and 170, and to write selected latch data (including scan chain data) to MSR latch circuits 150, 160, and 170.

[0011] In at least one embodiment, the clock generator 104 is arranged to generate one or more clock signals (clocks) (e.g., synthesize, synchronize, phase-lock, multiply, divide, shape, or regenerate one or more clock signals (clocks). The clock signals may be periodic waveforms that cycle (oscillate) at the same or different frequencies over time. The clock signals may be arranged as a clock distribution network and / or clock tree for clocking (and optionally synchronizing) components of the processor 102 and other components of the system 100. For example, the clock generator 104 is arranged to generate a clock signal CLK for clocking latch data through a scan chain including each of the MSR latch circuits 120, 130, and 140 (as described below with respect to Figure 2 description).

[0012] In at least one embodiment, memory 106 can be volatile (e.g., loses stored information when power is removed) and / or non-volatile (e.g., retains information when power is removed). Volatile memory can include static memory (SRAM, which can be based on active feedback circuits) and / or dynamic RAM memory (DRAM, which can be based on capacitors). Non-volatile memory can include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), flash memory, hard disks, solid-state drives, CD-ROMs (e.g., including programmable CD-ROMs), DVD-ROMs, "cloud" storage, memory "sticks," and / or any other suitable device for retaining information. Memory 106 can store information (e.g., code and operational data) that is accessed in the context of an execution environment in which one or more computer programs can implement (and / or be used by) the techniques described herein. Memory 106 can be a tangible medium.

[0013] In at least one embodiment, power mode selector 108 can be configured to selectively apply power to various components within system 100. The selective application of power can be determined in response to changes in operating conditions so that various operating parameters (e.g., speed, data retention, power consumption, "boot" time, and temperature) can be optimized or adjusted to efficiently operate system 100. Generally, selected components of system 100 can be powered on (or off) when the functionality provided by the selected components is needed (or no longer needed). In operation, power mode selector 108 is configured to selectively assert and deassert retention mode signals RET1, RET2, and RET3 to control the operation of MSR latch circuits 150, 160, and 170, respectively. Power mode selector 108 can also control the activation / deactivation of various power supplies (e.g., via VDD on / off signals). Powering on and off the various supply voltages of power supply 110 can provide power on an as-needed basis to conserve power.

[0014] In at least one embodiment, the power supply 110 component is arranged to generate power for powering the MSR latch circuit 150, the MSR latch circuit 160, and the MSR latch circuit 170. For example, the power supply 110 is arranged to generate power at a first voltage output VDD1 for powering the MSR latch circuit 150; the power supply 110 is arranged to generate power at a second voltage output VDD2 for powering the MSR latch circuit 160; and the power supply 110 is arranged to generate power at a third voltage output VDD3 for powering the MSR latch circuit 170, wherein each of the first voltage output, the second voltage output, and the third voltage output may be the same voltage as another voltage of the voltage output (e.g., a mutual inductance voltage nominally equivalent to the voltage of another voltage output).

[0015] The power supply 110 component is arranged to generate power at a voltage output VDDHVT for powering the retention circuit of the MSR latch circuit 150, wherein the voltage output VDDHVT is optionally a higher voltage than at least one of the voltage output VDD1, the voltage output VDD2, and the voltage output VDD3. Figure 2 As described, voltage output VDDHVT may include an example voltage that is high enough to drive a control terminal (eg, a gate) of a higher voltage threshold (HVT) transistor that generates lower leakage current than a lower voltage threshold LVT transistor.

[0016] For example, the voltage output VDDHVT may be used to drive active circuitry (e.g., for retaining logic states, e.g., as described below with respect to retention mode latch 128 of MSR latch 120, retention mode latch 138 of MSR latch 130, and retention mode latch 148 of MSR latch 140) Figure 2 Also, for example, voltage output VDD1 may be used to power active circuits of clock gate 122, master latch 124, and slave latch 126; voltage output VDD2 may be used to power active circuits of clock gate 132, master latch 134, and slave latch 136; and voltage output VDD3 may be used to power active circuits of clock gate 142, master latch 144, and slave latch 146.

[0017] When the voltage output VDDHVT is a higher voltage than the voltage output VDD1 (e.g., for powering the MSR latch circuit 150), the transistors of the active feedback circuit of the retention mode latch 128 may be (e.g., fabricated as) higher voltage threshold transistors having a higher voltage threshold than the lower voltage threshold transistors of the master latch 124 and the slave latch 126 of the same MSR latch 120. When the voltage output VDDHVT is a higher voltage than the voltage output VDD2 (e.g., for powering the MSR latch circuit 160), the transistors of the active feedback circuit of the retention mode latch 138 may be higher voltage threshold transistors than the transistors of the master latch 134 and the slave latch 136. When the voltage output VDDHVT is a higher voltage than the voltage output VDD3 (e.g., for powering the MSR latch circuit 170), the transistors of the active feedback circuit of the retention mode latch 148 may be higher voltage threshold transistors than the transistors of the master latch 144 and the slave latch 166.

[0018] When instances of the MSR latch circuit include similar corresponding components and when each of such instances is controlled by a common mode signal (e.g., a retention mode signal), voltages VDD1, VDD2, and VDD3 can be the same voltage (and can be generated by the same power supply of power supply 110).

[0019] Power can be saved by latching the existing electronic state of the slave latch into a retention mode latch, wherein the retention mode latch includes a higher voltage threshold transistor (e.g., compared to the lower voltage threshold transistor of the slave latch). The higher threshold voltage transistor of the active feedback circuit of the retention mode latch has a lower leakage current than the leakage current caused by the lower voltage threshold transistor of the slave latch (and the master latch). In comparison, the lower voltage threshold transistor can switch at a higher speed than the higher voltage transistor.

[0020] As described below in this article Figure 2As described, the retention mode latch can operate in a retention mode to retain latched data (e.g., for leaking relatively little power), while the master latch and the slave latch can operate in an active mode to retain latched data (e.g., for robust operation at higher speeds).

[0021] In addition, a clock gate (e.g., clock gate 122) can be configured to gate the clock signal CLK for input in response to an indication of retention mode (e.g., signal RET1). For example, gating the clock signal CLK saves power by limiting the switching of transistors that switch states in response to the gating clock. Additionally, power supply 110 can shut off the VDD1 power source during retention mode to save power.

[0022] In at least one embodiment, the system 100 can be controlled responsive to a user and / or responsive to measured system parameters received via the user / system interface 112. The user / system interface 112 may include hardware sensors and indicators for outputting information to a user and indicators during execution of software applications of the system 100, as well as for receiving information from a user and various sensors.

[0023] In addition, the user / system interface 112 may include input / output ports for networking (e.g., providing information to and / or receiving information from) networked devices. Networked devices may include any device capable of point-to-point and / or networked communication with the system 100 (including scan chain test equipment). Networked devices may include tangible, non-transitory media (such as flash memory) and / or wired or wireless media. These and other input and output devices may be selectively coupled to the system 100 via wireless or wired connections by external devices.

[0024] In at least one embodiment, MSR latches 120, 130, and 140 can be used to store data in a retention mode while consuming a relatively low amount of power. Some low-power retention latches include low-leakage retention latches (e.g., 128, 138, and 148), which include ultra-low leakage (ULL) transistors. The ULL transistors are arranged to couple logic signals for writing information to (or otherwise controlling) the low-leakage retention latches. The gate structures of such ULL transistors are manufactured to operate using a high (higher) voltage threshold (HVT). Compared to standard voltage threshold (SVT) transistors, HVT transistors (for a given process for manufacturing transistors of a given low-leakage retention latch) have higher dynamic power consumption (e.g., during switching), lower leakage current, and higher operational latency.

[0025] For example, including an HVT transistor in a low-leakage retention latch can increase the switching delay of the low-leakage retention latch due to the higher voltage threshold and the inductance of the HVT transistor's gate. When the HVT transistor is placed in a timing-critical path of the device, the increased delay can slow the performance of the device including the HVT transistor low-leakage retention latch.

[0026] Additionally, the HVT transistor of the low-leakage retention latch operates at a power rail voltage (e.g., VDDHVT) that is sufficiently high to drive the HVT transistor. The voltage sufficient to drive the control terminal (e.g., gate) of the HVT transistor can be significantly higher than the voltage sufficient to drive a standard voltage threshold (SVT) transistor. For example, the significantly higher gate voltage is a voltage sufficient to reliably switch an SVT transistor, rather than a voltage sufficient to reliably switch an HVT transistor. The higher power rail voltage can also result in higher dynamic power consumption when the HVT transistor is switched.

[0027] As referenced below Figure 2 As described, a preset signal (eg, PREZ) may be asserted asynchronously. Assertion of the PREZ signal may set the states of the master latch 230 and the slave latch 240 to known states (eg, for operational or testing purposes).

[0028] Figure 2 is a schematic diagram of an example MSR latch 200. The example MSR latch 200 can be a latch such as the MSR latch circuit 120, the MSR latch circuit 130, and the MSR latch circuit 140. The example MSR latch 200 includes a first latch 258 and a second latch 260. The first latch 258 includes a master / slave latch pair (e.g., the master latch 230 and the slave latch 240), which is activated during an active operating mode (active mode) and can be at least partially deactivated during a retention operating mode (retention mode).

[0029] During the active mode, the second latch 260 (e.g., the retention mode latch 260) can be at least partially deactivated during the active mode. For example, the retention mode (ret mode) latch 260 can be deactivated by performing a precharge or clear operation in which the same logic state is set or cleared in the complementary feedback node of the ret mode latch 260.

[0030] During the retention mode, the ret mode latch 260 may be activated during the retention mode (or near the activation of the retention mode) to input, latch, and retain the existing logic state latched by the first latch (e.g., latched by the slave latch 240). For example, the ret mode latch 260 is arranged to save power by not providing a quiescent current path and reducing leakage while operating during the retention mode.

[0031] The power domain 204 is selectively coupled to transistors (eg, including transistors for implementing the illustrated logic gates) for applying power to the first latch 258. The power domain 204 of the first MSR latch 200 may be configured as described above with respect to FIG. Figure 1 The power domain 204 may be selectively powered by a power signal (such as VDD1) as described (the second MSR latch may be selectively powered by VDD2, and the third MSR latch may be selectively powered by VDD3). Power domain 204 may be selectively powered in response to an operating mode. For example, a first voltage (e.g., VDD1 coupled to MSR latch 200) may be coupled to power domain 204 during an active operating mode (active mode) and may be at least partially decoupled from power domain 204 during a retention operating mode (retention mode). The first voltage (e.g., VDD1 coupled to power domain 204) may be a voltage selected to effectively drive lower voltage threshold transistors included in power domain 204 (e.g., compared to driving higher voltage threshold transistors included in power domain 202). Additionally, transistors 290 and 292 are arranged to level shift control signals from power domain 204 to power domain 202.

[0032] The power domain 202 is coupled to power transistors of a second latch of the MSR latch 200 (e.g., including transistors arranged within the illustrated logic gates). The second latch may be a retention mode latch (e.g., a ret mode latch 260). The ret mode latch 260 includes an active feedback circuit comprising a cross-coupled PMOS transistor 264 and a cross-coupled PMOS transistor 266. The active feedback circuit may be powered by a second voltage (e.g., VDDHVT coupled to the power domain 202), which may be selected to drive a higher voltage threshold transistor included in the power domain 202. The second voltage may be selected to drive a higher voltage threshold transistor included in the power domain 202. Coupling a higher voltage to the higher voltage threshold transistor helps ensure lower leakage current of the higher voltage threshold transistor (while also helping to ensure proper switching).

[0033] Other transistors of the second latch may be included within the power domain 202. For example, rail transistor 290 and rail transistor 292 are included in the power domain 204 and are arranged to level shift the indication (e.g., signal N7 and signal N8) for programming the active portion of the ret mode latch 260 across different power domains (e.g., which may operate at different voltage levels). Inverter 210 is also included by the power domain 202 and is arranged to generate an inverted retention mode (RETZ) signal.

[0034] In the example MSR latch 200, all SVT (standard voltage threshold) transistors can be powered by a first power rail 204 (e.g., VDD), while the HVT (e.g., higher voltage threshold) transistors of the retention mode latch are powered by a second power rail 202 (e.g., VDDHVT, which can be the same voltage as or a higher voltage than the first power rail). The first power rail 204 can supply a lower voltage than the voltage suitable for driving the HVT transistors, which reduces the dynamic power that would otherwise be consumed by the SVT transistors operating at a voltage suitable for driving the HVT transistors. Additionally, when SVT or LVT (e.g., lower voltage threshold) transistors are arranged in critical timing paths in a master / slave latch pair, low signal propagation delays can be achieved even at lower first rail voltages.

[0035] The master latch 230 and the slave latch 240 (of the example retention latch 200) may include transistors having a lower gate threshold voltage (the transistors being suitable for generating a delay that is reduced compared to the delay that would otherwise be generated for each such transistor), while the retention mode latch (ret mode latch) 260 may include transistors having a higher threshold voltage (the transistors being suitable for maintaining low leakage current in each such transistor). The example ret mode latch may be used to save power by retaining the latched logic state of the active feedback circuit from the slave latch 240 during a retention mode (e.g., during which power may be removed from the first power domain 204).

[0036] The master / slave latch pair (e.g., 230 and 240) includes lower voltage threshold transistors arranged in the critical timing path of the example MSR latch 200, which reduces the delay of the MSR latch 200 when operating in active mode. The active circuit of the master / slave latch pair includes the master latch 230 and the slave latch 240, each of which can be formed using lower voltage threshold transistors. In contrast, the active circuit of the ret mode latch 260 includes higher voltage threshold transistors (e.g., this reduces leakage during retention mode and, if not disputed, reduces the degree of delay of the master / slave latch pair during retention mode (e.g., for speed needs)).

[0037] In active mode operation, the master latch 230 is arranged to latch a logic state in response to external data (e.g., latch data) selected via the multiplexer 220. The latch data may be operational data (such as data generated under normal operation and coupled to the D input of the multiplexer 220) or scan data (such as data from other latches in the scan chain, where the latched data from the previous latch in the scan chain is coupled to the SD input of the multiplexer 220). The multiplexer 220 couples a selected one of the D and SD inputs to the multiplexer 220 output in response to the state of the scan signal.

[0038] The master latch 230 includes a transmission gate 222 that is arranged to be closed during the period when the clock signal CLK is low (as described below with respect to FIG. Figure 3 2 ), passes the logic value received from multiplexer 220 to the logic state input node of the active feedback circuit of master latch 230. Buffer 232 disables the feedback path of master latch 230 during the period when clock signal CLK is low, so that the output portion of the feedback loop does not conflict with the output of transmission gate 222, and allows the logic value passed by transmission gate 222 to set the logic state of the active feedback circuit (which includes NAND gate 234).

[0039] NAND gate 234 includes a first input coupled to the output of transmission gate 222 (e.g., a logic state input gate) and the output of tri-state inverting buffer 232 (e.g., a logic state feedback gate for latching input data). NAND gate 234 also includes a second input coupled to a PREZ_INT signal. The PREZ_INT signal is generated by NAND gate 214 and inverter 212 in response to the PREZ and RETZ signals, enabling a preset operation in response to assertion of the preset signal when the retention mode signal is not already asserted. When the PREZ_INT signal is high, the output signal of NAND gate 234 inverts the logic state of the logic state input node (which is the output of transmission gate 222).

[0040] When the clock signal CLK transitions high, the path through transmission gate 222 is closed, and (while PREZ_INT remains high) the tri-state buffer inverting buffer 232 is arranged to invert the output signal of NAND gate 234: the double inversion of the logic input state node helps ensure that (when the clock signal CLK is high) the logic input state node is actively driven with the same logic state previously input by transmission gate 222 (this establishes the active latching feedback state of the master latch 230). The NAND gate 234 output signal is also inverted by inverter 236 and passes through transmission gate 238 (when the clock signal CLK is high).

[0041] When the PREZ_INT signal is low, the active feedback loop established between NAND gate 234 and inverting tri-state buffer 232 is disconnected. Disconnecting the active feedback loop helps ensure that the latched state of master latch 234 is not toggled in response to a change in the input logic state selected by multiplexer 220 (e.g., this can save power).

[0042] The output of the activated transmission gate 238 (e.g., which outputs the logic state of the master latch 230) is arranged to drive the logic input node N7 of the slave latch 240 when the clock signal CLK is high. Node N7 is coupled to the output Q of the first latch 258 via inverter 250. The critical path through the master / slave latch pair (which traverses the inverting multiplexer 220, the NAND gate 234, the inverter 236, and the inverter 250) includes an even number of inversions such that the output of the master / slave latch pair (230 and 240) is a non-inverted Q output (e.g., with respect to the associated D and SD inputs).

[0043] When the clock signal CLK is high, the feedback inverting tri-state buffer 242 is tri-stated so that the output of the buffer 242 does not conflict with the output of the transmission gate 238. The gate voltage N8_XX (coupled to the gate of the rail transistor 246 during the active mode) is low and, when low, does not conflict with the output of the transmission gate 238. In a similar manner, the gate voltage N7_XX does not conflict with the output N8 of the NAND gate 244 when low.

[0044] When the clock signal CLK transitions low (and PREZ_INT remains high), the path through transmission gate 238 closes, and the tri-state buffer inverting buffer 242 is arranged to invert the output signal N8 of the NAND gate 244. The double inversion of the logic input state node N7 ensures that (when the clock signal CLK is low) the logic input state node N7 of the slave latch 240 is actively driven with the same logic state previously input by the transmission gate 238 (this establishes the active latch feedback state of the slave latch 240). The NAND gate 244 output signal N8 is also inverted by the inverter 250 for output as the output Q of the first latch 258 (e.g., a master / slave latch pair).

[0045] In the example, when the retention mode signal (inverted) RETZ is not asserted, the active mode is asserted. During the active mode, the ret mode latch 260 is precharged and maintained in a precharged state. Being in the precharged state contributes to a lower input signal hold time for latching the ret mode latch. The precharged state helps ensure that the ret mode latch 260 can quickly establish a latched logic state in response to the current input logic state of the slave latch 240 (e.g., via N7 and N8). Maintaining the precharged state during operation in the active mode saves power that would otherwise be consumed (e.g., because the transistors of the ret mode latch 260 do not trigger the state (in the active mode) as a function of the clock signal (e.g., direct function).

[0046] In order to precharge the ret mode latch in active mode, the retention mode signal RET remains low. When the retention mode signal is low (e.g., not asserted), NMOS transistor 280, NMOS transistor 284, and NMOS transistor 286 are all off, while PMOS precharge transistor 262 and PMOS precharge transistor 268 are on. When transistor 262 and transistor 268 are on, a channel is established through each of transistor 262 and transistor 268, so that each of the corresponding nodes N7_X and N8_X is precharged (e.g., precharged to a logic high state during active mode). Node N8_X (including the drain of transistor 266) is coupled to the gate of the first cross-coupled PMOS transistor 264 (so that PMOS transistor 264 is off during active mode), however, node N7_X is coupled to the gate of the second associated cross-coupled PMOS transistor 266 (so that PMOS transistor 266 is also off during active mode).

[0047] As referenced below Figure 3 As described above, when the clock signal CLK (310) is low, the retention mode signal RET (320) is asserted. Figure 2 , PMOS pre-charge transistor 262 and PMOS pre-charge transistor 268 are turned off in response to assertion of the retention mode signal, while NMOS transistor 280, NMOS transistor 284, and NMOS transistor 286 are turned on in response to assertion of the retention mode signal. When transistor 262 and transistor 268 are turned off, the channel through each of transistor 262 and transistor 268 collapses, decoupling each of the corresponding nodes N7_X and N8_X from the second power rail VDDHVT (e.g., with reference to the first power rail VDD).

[0048] Because of the delay in turning on at least one of transistor 264 and transistor 266, both nodes N7_X and N8_X remain high at least temporarily (one of nodes N7_X and N8_X is later forced low as described herein below), causing both transistor 282 and transistor 288 to initially remain on. The source of transistor 282 is selectively coupled to ground (e.g., a low power rail) via NMOS rail transistor 290 (which is controlled by node N7 of slave latch 240), while the source of transistor 288 is selectively coupled to ground via NMOS rail transistor 292 (which is controlled by node N8 of slave latch 240). Because nodes N7 and N8 of slave latch 240 are set to complementary states, only one (e.g., exactly one) of primary rail transistor 290 and rail transistor 292 is coupled to ground.

[0049] In a first example where node N7 of slave latch 240 is high (and node N8 is low), rail transistor 290 is turned on, causing the NMOS stack of transistors 280, 282, and 290 to be arranged to selectively couple the precharge of node N7_X to ground via a first path. In response to the transition of node N7_X to ground, inverter 270 drives node N7_XX high. When node N7_XX is driven high (while node N8_XX remains low), transistor 274 is turned on, while transistor 276 remains off.

[0050] When transistor 274 is on, transistor 274 couples a second path from node N7_X to ground via activated rail transistor 284 (activated rail transistor 284 is activated in response to asserted retention mode). In the event of a spurious triggering of node N7, the second path from node N7_X (via transistor 284) to ground maintains the active latching of cross-coupling transistors 264 and 266. (Such spurious triggering of nodes N7 and N8 can occur, for example, due to noise and / or when power is removed from domain 204, which in turn effectively tri-states output nodes N7 and N8.)

[0051] The cross-coupling of the active feedback circuit of transistors 274 and 276 via inverters 270 and 272 can be referred to as "indirect coupling" and enhances the immunity of the ret-mode latch 260 circuit to electrical effects caused by device mismatch (e.g., coupling an HVT transistor to an LVT or SVT transistor) and / or parameter skew of the manufacturing process used to form such different devices on a single substrate. Additionally, for example, the indirect coupling can increase the immunity of the active feedback circuit to noise or switching glitches occurring on nodes N7 and / or N8.

[0052] When node N7_X is pulled low (as described above, in response to node N7 being high when retention mode is asserted), PMOS transistor 266 turns on, which maintains node N8_X at a high level (e.g., regardless of the state of the retention mode signal). Keeping node N8_X at a high level helps ensure that inverter 271 continues to output a logic zero (low) state (on node N8_XX). In response to the low state of node N8_XX, transistor 276 remains off, so that transistor 276 does not actively transfer charge to ground (e.g., this masks a "glitch" input via node N8, which controls rail transistor 292). The high state of node N8_X helps ensure that cross-coupled transistor 264 remains off. When cross-coupled transistor 264 is off (and cross-coupled transistor 266 is on), the active circuit including cross-coupled transistor 264 and cross-coupled transistor 266 electronically latches the logic state asserted by input node N7 and input node N8.

[0053] Coupling charge from VDDHVT to node N8_X via PMOS transistor 266 helps maintain the off state of complementary cross-coupled transistor 264 (despite drain and gate leakage of the activation transistor coupled to node N8_X). Maintaining the off state of complementary transistor 264 (while maintaining the on state of transistor 266 itself) actively and selectively retains the latched state (e.g., where node N7_XX also retains the logic state of node N7 via a second path coupled to ground through transistor 284).

[0054] In a second example where node N7 of slave latch 240 is low (and node N8 is high), rail transistor 292 is turned on, causing the NMOS stack of transistors 286, 288, and 290 to be arranged to selectively couple the precharge of node N8_X to ground via a first path. In response to the transition of node N7_X to ground, inverter 272 drives node N8_XX high. When node N8_XX is driven high (while node N7_XX remains low), transistor 276 is turned on, while transistor 274 remains off.

[0055] When transistor 276 is on, transistor 276 couples a second path from node N8_X to ground via activated rail transistor 284 (activated rail transistor 284 is activated in response to asserted retention mode.) In the event that, for example, power is removed from domain 204 (which in turn effectively tri-states output node N7 and output node N8), the path from node N8_X to ground maintains the active latching of cross-coupling transistors 264 and 266.

[0056] When node N8_X is pulled low, PMOS transistor 264 turns on, which maintains node N7_X at a high level (e.g., regardless of the state of the hold mode signal). Keeping node N7_X at a high level helps ensure that inverter 270 continues to output a logic zero (low) state (on node N7_XX). In response to the low state of node N7_XX, transistor 274 remains off, so that transistor 274 does not actively transfer charge to ground (e.g., this masks a "glitch" input via node N7, which controls rail transistor 290). The high state of node N7_X helps ensure that cross-coupled transistor 266 remains off. When cross-coupled transistor 266 is off and cross-coupled transistor 264 is on, the active circuit including cross-coupled transistor 264 and cross-coupled transistor 266 electronically latches the logic state asserted by input node N7 and input node N8.

[0057] Coupling charge from VDDHVT to node N7_X via PMOS transistor 264 helps maintain the off state of complementary cross-coupled transistor 266 (despite drain and gate leakage of the activation transistor coupled to node N7_X). Maintaining the off state of complementary transistor 266 (while maintaining the on state of transistor 264 itself) actively and selectively retains the latched state (e.g., where node N8_XX also retains the logic state of node N8).

[0058] As referenced below Figure 3 As described, power (eg, VDD and VDDNW 330) is removed (eg, from power domain 204). Referring again to Figure 2 , removing power from power domain 204 effectively tri-states the outputs of the transistors driving respective nodes N7 and N8 (which may make rail transistors 290 and 292 more susceptible to false switching due to noise on nodes N7 and N8). For example, power mode selector 108 ( Figure 1 2 (as shown) can be arranged to signal the power supply 110 so that power is not consumed by the master latch 258 (e.g., at an operating rate) during the retention mode. Such a loss of power can cause the first latch 258 (including the master latch 230 and the slave latch 240) to lose information stored therein as a latched state. The power mode selector 108 can be arranged to assert a retention signal (e.g., RET1, RET2, and / or RET3) for decoupling power to the power domain 204 of the selected MSR latch 200. The power mode selector 108 can be arranged to assert the retention signal in response to a determination (e.g., made by the processor 102) that at least a portion of the system 100 is to be placed in a power conservation mode.

[0059] In response to a determination (e.g., made by processor 102) that at least a portion of system 100 is activated (e.g., placed in active mode), power selector 108 may signal power supply 110 to couple power to power domain 204 (and / or generate power for power domain 204). After power is reapplied to power domain 204, the state of slave latch 240 is set in response to the N7_XX and N8_XX nodes of ret mode latch 260. The N7_XX and N8_XX nodes (e.g., complementary signals) activate one of rail transistor 246 and rail transistor 248, thereby setting the state of slave latch 240 in response to information previously actively stored in slave latch 240 prior to assertion of the retain mode signal (and / or removal of power from power domain 204).

[0060] After the state of the slave latch 240 is set in response to the information previously actively stored in the slave latch, the retention mode signal (RET) is de-asserted and the clock signal (CLK) is transitioned high (as described below with respect to Figure 3 description).

[0061] Figure 3 3 is a waveform diagram of an example mode transition of an example MSR latch 200. Waveform diagram 300 includes waveforms of signals CLK (clock) 310, RET (retention mode signal) 320, VDD (lower voltage threshold power rail) 330, and VDDHVT (higher voltage threshold power rail) 340. Latch 258 (of MSR latch 200) is activated during active mode (e.g., when RET signal 320 is low), and latch 258 is at least partially deactivated during retention mode (e.g., when RET signal 330 is high).

[0062] In active mode, the CLK signal 310 oscillates at a clock frequency for transmitting data, for example, through at least one example MSR latch 200 (e.g., where multiple instances of the MSR latch 200 may be arranged in series as a scan chain). During active mode, the master latch 230 is arranged to receive a data input (e.g., via a D or SD input terminal) and latch the data input when the CLK signal 310 is low. When the CLK signal 310 transitions high, the latched data from the master latch 230 is input to the slave latch 240. For example, at transition 311 (during which the CLK signal transitions low), data received from the master latch 230 by the slave latch 240 is latched into the slave latch 240.

[0063] In response to the assertion of the retain mode, the active mode ends (eg, at transition 321 of signal RET). Figure 1The power mode selector 108 is depicted as determining which mode is selected to be asserted. When the signal RET 320 is asserted, the ret mode latch 260 (which is precharged during active mode in a manner similar to the precharge of a sense amplifier) ​​couples the control node of one of a pair of cross-coupled transistors (e.g., 264 and 266) to ground, so that the latched logic state of the slave latch 240 is latched by the ret mode latch 260. When the signal RET 320 is asserted, the CLK signal 310 is turned off, which reduces power consumption and reduces electrical noise during retention mode.

[0064] In response to the assertion of retention mode, at transition 331, the power rail (e.g., VDD 330) used to power the master latch 230 and the slave latch 240 is disconnected (or otherwise removed or powered off). The power supplied by the VDD rail 330 is disconnected, for example, to save power that would otherwise be dissipated by the circuits of the master latch 230 and the slave latch 240. The power rail (VDDHVT340) used to power the retention mode latch remains active (e.g., high) in both active mode and retention mode, so that (for example) the ret mode latch 260 can be precharged during active mode and so that the ret mode latch 260 can retain data latched from the slave latch 240 during retention mode. The MSR latch 200 remains in retention mode (e.g., indefinitely) until the power mode selector determines a transition to active mode.

[0065] In response to the determination of the transition to active mode, the master latch 230 is reactivated at the transition 332 of the VDD rail 330. Activating the VDD rail 330 activates the master latch 230 and the slave latch 240 so that the master latch 230 and the slave latch 240 can input and latch received data. Additionally, assertion of the PREZ signal (described above) can set the latched states of the master latch 230 and the slave latch 240 to known values ​​(e.g., for testing purposes). When the PREZ signal is de-asserted, the slave latch 240 is set in response to the value latched in the ret mode latch 260 during retention mode.

[0066] When the RET signal 320 is de-asserted at transition 322 (e.g., in response to a determination of a transition to active mode), the retention mode latch is disabled (e.g., by pre-charging the two control nodes of the cross-coupled transistors of the active feedback circuit of the ret mode latch 260). After transition 322, the CLK signal 310 is gated (e.g., in response to the de-assertion of the RET signal 320), which generates a transition 312 (e.g., a rising edge) of the CLK signal 310. The rising edge of the CLK signal 310 at transition 312 can be used to clock information recovered from the latch 240 (e.g., previously stored in the ret mode latch 260 during the retention mode) into an input (e.g., the S input or the SD input) of another instance of the MSR latch 200. Additional cycles of the CLK signal 310 may be used to clock data through other scan latches of the scan chain so that, for example, data stored in multiple instances of the MSR latch 200 during retention mode may be read (e.g., by the processor 102) for restoring the context of the execution environment and / or for testing purposes.

[0067] Thus, the ret mode latch 260 can be written in response to the rising edge of the RET signal 320 (e.g., transition 321). When writing to the retention mode latch (e.g., from the slave latch 240), the ret mode latch 260 is enabled so that when the ret mode latch 260 is in the retention mode (e.g., between transition 321 and transition 322), the ret mode latch 260 can retain the state of the written data. When the RET signal 320 is deasserted, the ret mode latch 260 exits the retention mode and the value stored by the ret mode latch 260 is written (e.g., written back) to the slave latch 240 (the slave latch 240 also transitions to the active mode). The ret mode latch 260 is disabled from latching during the active mode (e.g., by precharging the control node of the active feedback circuit), which saves power that would otherwise be dissipated by switching in response to the CLK signal 310 during the active mode.

[0068] Figure 4Schematic diagram of example D latches coupled directly (e.g., via the gates of transistors 264 and 266) and indirectly (e.g., via the gates of transistors 27 and 276). Example D latch 400 is structurally similar to ret-mode latch D 260, but, for example, D latch 400 can operate differently in response to differently timed control signals. D latch 400 can be integrated on substrate 410, which can include multiple instances of D latch 400 and other circuitry so that scan chains can be formed for programming and testing other circuitry included on a single substrate 410 (e.g., and modifications thereof) can be used to implement master latch 230 and slave latch 240 (e.g., by switching the polarity of the CLK signal for respective components of the latch).

[0069] In operation, the timing of D latch 400 is controlled by the CLK signal. The CLK signal can indicate the operation of D latch 400 in one of two modes: when the CLK signal is low, the first mode is indicated for precharging D latch 400 (D latch 400 is similar in architecture to a sense amplifier); and when the CLK signal is high, the second mode is indicated for latching input information. For example, when the CLK signal is low, PMOS transistor 262 and PMOS transistor 268 are arranged to precharge nodes N7_X and N8_X (this helps ensure that cross-coupled transistor 264 and cross-coupled transistor 266 are both off). In response to a high input from node N7_X, inverter 270 outputs a low signal at node N7_XX, which is used to turn off transistor 274 and / or maintain transistor 274 in the off state. Similarly, in response to a high input from node N8_X, inverter 272 outputs a low signal (N8_XX) for turning off and / or maintaining transistor 276 in an off state. Because the CLK signal is low, the first NMOS transistor “stack” coupled to node N7_X (the first NMOS transistor “stack” includes NMOS transistor 280, NMOS transistor 282, and NMOS transistor 290) does not pull down node N7_X, and the second NMOS transistor “stack” coupled to node N8_X (the second NMOS transistor “stack” includes NMOS transistor 286, NMOS transistor 288, and NMOS transistor 292) does not pull down node N8_X. When the CLK signal is low, both directly cross-coupled nodes N7_X and N8_X are precharged because, for example, the cross-coupled nodes N7_X and N8_X are respectively coupled to a high power rail (e.g., VDD) and the cross-coupled nodes N7_X and N8_X are not respectively coupled to a low power rail (e.g., ground).

[0070] When the CLK signal transitions high, PMOS transistor 262 and PMOS transistor 268 are turned off, while PMOS transistor 264 and PMOS transistor 266 are initially both off. Because the D and DZ inputs are complementary, only one of transistor 280 and transistor 286 is selectively activated in response to the corresponding input signal. The selective activation of only one of transistor 280 and transistor 286 causes the value of input D to be written to and latched by D latch 400.

[0071] In the first example, when the D input is high, NMOS transistor 280 is on (in response to the high state of input D). Additionally, in response to the CLK signal transitioning to high, NMOS transistor 290 is on (e.g., activated). NMOS transistor 282 is initially on because cross-coupling node N8_X (in addition to node N7_X) is precharged to a high state. In response to the on state (e.g., being activated) of each of transistors 280, 282, and 290 in the first NMOS stack, node N7_X is selectively coupled to a low power rail (e.g., pulled down to ground) (this is the first path to ground). When node N7_X is pulled down, cross-coupling transistor 266 is arranged to pull up node N8_X, which couples charge to node N8_X to actively maintain the high state of node N8_X. (As described above, cross-coupling transistors 264 and 266 are latched in response to being driven by gate signals of respective complementary active drivers that control each other.)

[0072] Additionally (e.g., in response to input D and CLK being high), the low state of node N7_X forces inverter 270 high, causing node N7_XX to turn on transistor 274. Because transistor 284 (cascode-coupled with transistor 274) is turned on in response to CLK being high, a second (e.g., delayed) path from node N7_X to ground is selectively controlled (e.g., opened) by the latched state of D latch 400 (e.g., compared to direct control by the D input). This delayed second path to ground helps ensure that the cross-coupled active feedback circuit (e.g., including cross-coupled transistors 264 and 266) latches correct data by masking "glitches" on the D input that might otherwise pull down node N7_X and erroneously shunt precharge charge from the complementary input to ground. These "glitches" can occur during a write operation (until CLK subsequently transitions low) due to noise and / or in response to transistor mismatch (e.g., transistor drive strength differences). A delayed second path to ground (e.g., a delayed second path to ground controlled by “indirect coupling” via inverter 270) can also help reduce the hold time of the D (and DZ) inputs, which helps increase the robustness of the circuit to noise and variations caused by design or manufacturing tolerances.

[0073] In a second example where the DZ input is high (and the D input is low), NMOS transistor 286 is on (in response to the high state of input DZ). Additionally, in response to the CLK signal transitioning to high, NMOS transistor 292 is on (e.g., activated). Because cross-coupling node N7_X (and N8_X) are precharged to a high state, NMOS transistor 288 is initially on. In response to the on state (e.g., activated) of each of transistors 286, 288, and 292 arranged as an NMOS stack, node N8_X is selectively coupled to the low power rail (e.g., pulled down) along a first path. When node N8_X is pulled down, cross-coupling transistor 264 is arranged to pull up node N7_X, which couples charge to node N7_X to actively maintain the high state of node N7_X.

[0074] Additionally (e.g., in response to input DZ and CLK being high), the low state of node N8_X forces inverter 270 to be high, causing node N8_XX to turn on transistor 276. Because transistor 284 (which is cascode-coupled with transistor 276) is turned on in response to CLK being high, a second (e.g., delayed) path from node N8_X to ground is selectively controlled (e.g., opened) by the latched state of D latch 400 (e.g., compared to being directly controlled by the D input). The delayed second path to ground helps ensure that the cross-coupled active feedback circuit (e.g., the cross-coupled active feedback circuit includes cross-coupled transistor 264 and cross-coupled transistor 266) latches the correct data by masking "glitches" on the D input that might otherwise pull down node N8_X and shunt precharge charge from the complementary input to ground.

[0075] As described above, the first complementary (e.g., cross-coupled) node and the second complementary (e.g., cross-coupled) node (e.g., N7_X and N8_X) are arranged to be precharged during active mode (e.g., so that both nodes include a logic 1 voltage). In response to a control signal derived from a selected one of the first complementary node and the second complementary node (e.g., wherein the selected node is pulled down), the selected one of the first complementary node and the second complementary node is also (e.g., subsequently) coupled to ground via a second path, the second path including the activated transistor 284 (activated in response to assertion of the retention mode signal).

[0076] In another example, a cross-coupled NAND gate (e.g., as opposed to just cross-coupled transistors) is arranged to latch a value derived in response to the logic states of N7_X and N8_X. The logic state of the cross-coupled NAND gate can be set in response to selection of one of the D input and the SD input, where the selection can be implemented as part of the NMOS stack as a "first path to ground."

[0077] Modifications are possible in the described examples, and other examples are possible, within the scope of the claims.

Claims

1. A device comprising: a first latch for providing input data; a second latch coupled to the first latch, wherein the second latch comprises circuitry for latching the input data in response to a retention signal indicating whether the apparatus is in the first mode or the second mode, the circuitry comprising: a first transistor comprising an output coupled to a first node, wherein the first transistor is adapted to couple the first node to a first power rail during the first mode; and a second transistor comprising an output coupled to a second node, wherein the second transistor is adapted to couple the second node with the first power rail during the first mode, wherein: the first transistor comprising a gate coupled to the second node; and the second transistor including a gate coupled to the first node; a first path comprising a first set of transistors coupled in series between the first node and a second power rail; and a second path comprising a second set of transistors coupled in series between the second node and the second power rail; The first latch includes a transistor having a first threshold voltage lower than a second threshold voltage of the first transistor and the second transistor of the second latch. 2 . The apparatus of claim 1 , wherein power consumption of the circuit is high during the first mode, and the power consumption of the circuit is low during the second mode.

3. The apparatus of claim 1 , wherein the first set of transistors of the first path comprises: The following cascode arrangement: a first NMOS transistor, the first NMOS transistor including a gate coupled to a first signal of the input data; a second NMOS transistor including a gate coupled to the second node; and a third NMOS transistor including a gate coupled to receive the retention signal. 4 . The apparatus of claim 1 , wherein the second latch is powered by a first power domain, and the first latch is powered by a second power domain. The apparatus of claim 4 , wherein the second power domain is powered down during the second mode. 6 . The apparatus of claim 1 , wherein the first latch is arranged to receive a latched logic state of the second latch in response to a transition from the second mode to the first mode. 7 . The apparatus of claim 1 , wherein the circuitry of the second latch comprises a transistor having leakage that is lower than leakage of the transistor of the first latch.

8. The apparatus of claim 1, wherein the second latch comprises a transistor having a switching time that is slower than a switching time of the transistor of the first latch.

9. The apparatus of claim 1 , wherein the first latch comprises a master latch arranged to latch a received logic state during a first portion of a clock cycle and comprises a slave latch arranged to latch the received logic state latched by the master latch during a second portion of a clock cycle.

10. The apparatus of claim 6, comprising a multiplexer for selecting a scan chain input as the input data.

11. A circuit comprising: a first latch comprising a first circuit arranged to retain a received logic state during an active mode and arranged to be at least partially deactivated during a retention mode; as well as a second latch comprising a second circuit including a first logic node and a second logic node, wherein a logic state of each of the first logic node and the second logic node of the second latch is the same during a portion of the active mode, wherein the second circuit is arranged to latch a received logic state of the first latch in response to an indication of a transition from the active mode to the retention mode, wherein the logic state of each of the first logic node and the second logic node of the second latch is different during a portion of the retention mode, and wherein the second latch is arranged to retain the latched logic state received from the first latch during the retention mode.

12. The circuit of claim 11 , wherein the first logic node of the second latch is coupled to a first power rail in response to the indication of the active mode, and wherein the second logic node of the second latch is coupled to the first power rail in response to the indication of the active mode.

13. The circuit of claim 12 , wherein the first logic node of the second latch is coupled to a second power rail in response to the indication of the retention mode and in response to the logic state of the first logic node of the first circuit, and wherein the second logic node of the second latch is coupled to the second power rail in response to the indication of the active mode and in response to the logic state of the second logic node of the first circuit.

14. The circuit of claim 11 , wherein the first logic node of the second latch is coupled to a second power rail in response to a logic state of the second logic node of the second circuit, and wherein the second logic node of the second latch is coupled to the second power rail in response to a logic state of the first logic node of the second circuit.

15. The circuit of claim 14, wherein in response to the indication of the retention mode, exactly one of the first logic node of the second latch and the second logic node of the second latch is coupled to the second power rail.

16. A method comprising: In the first circuit, retaining the received logic state during the active mode; at least partially deactivating the first circuit during a retention mode in response to decoupling at least one element in the first circuit from a first power rail; latching the received logic state retained in the first circuit in response to coupling one of a first node and a second node in the second circuit to a second power rail during the retention mode, wherein in response to assertion of the retention mode and in response to an indication of the retained logic state of one of the first node and the second node in the first circuit, the one of the first node and the second node in the second circuit is coupled to the second power rail, and wherein the indication of the retained logic state is a signal powered by the first power rail; as well as The latched logic state of the second circuit is retained during the retention mode.

17. The method of claim 16, comprising precharging the first node and the second node of the second circuit during the active mode.

18. The method according to claim 16, comprising: activating the first circuit during a transition from the retention mode to the active mode, wherein the first circuit is activated in response to coupling at least one element of the first circuit to the first power rail; as well as In the activated first circuit, the retained logic state of the second circuit is latched.

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