Display device

Abstract

An embodiment of the present invention discloses a display device, comprising: a substrate including a display area equipped with main pixels and an electronic component area equipped with auxiliary pixels and a transmission portion; and an electronic component transmitting a predetermined signal to the outside of the substrate through the transmission portion, a blocking layer blocking an entire semiconductor layer of the auxiliary thin film transistor in a plane is arranged between the electronic component and the auxiliary thin film transistor of the auxiliary pixel.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to a display device. BACKGROUND

[0002] Recently, the use of display devices is diversifying. Also, there is a tendency that the thickness of display devices is becoming thinner, the weight is becoming lighter, and thus the range of use is gradually becoming wider.

[0003] As display devices are used diversely, various methods can be employed to design the form of display devices, and the functions that can be grafted or associated to display devices are increasing. SUMMARY

[0004] Embodiments of the present application can provide a display device equipped with a sensor region in which components such as sensors are arranged, inside a display region. In particular, a display device in which the arrangement structure of a blocking layer that blocks damage to elements caused by components is improved can be provided. However, these problems are merely exemplary, and the scope of the present application is not limited thereto.

[0005] An embodiment of the present application provides a display device including a substrate including a display region equipped with a main pixel and an electronic component region equipped with an auxiliary pixel and a through portion, and an electronic component that transmits a predetermined signal to the outside of the substrate through the through portion, wherein the auxiliary pixel is equipped with an auxiliary thin film transistor including a semiconductor layer, and a blocking layer that blocks the entire semiconductor layer of the auxiliary thin film transistor in a planar view is arranged between the electronic component and the auxiliary thin film transistor.

[0006] The blocking layer can have the same pattern as that of the semiconductor layer of the auxiliary thin film transistor.

[0007] The width of the pattern of the blocking layer can be greater than that of the semiconductor layer of the auxiliary thin film transistor.

[0008] The blocking layer can include a pattern different from that of the semiconductor layer of the auxiliary thin film transistor.

[0009] The thickness of the blocking layer can be The above.

[0010] A buffer layer can be present between the auxiliary thin film transistor and the blocking layer and between the blocking layer and the substrate, respectively.

[0011] The auxiliary pixel can further include an organic light emitting element connected to the auxiliary thin film transistor.

[0012] The main pixel is provided with a main thin film transistor including a semiconductor layer, and a blocking layer that blocks the entire semiconductor layer of the main thin film transistor in a planar direction can be disposed between the electronic component and the main thin film transistor.

[0013] The main pixel can further include an organic light emitting element connected to the main thin film transistor.

[0014] The predetermined signal can include any one of a light signal and an acoustic signal.

[0015] Other features, advantages, and characteristics of the present application will become apparent from the following detailed description, the appended claims, and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0016] Figure 1 is a perspective view schematically showing a display device according to an embodiment of the present application.

[0017] Figure 2 is a cross-sectional view taken along line A-A' of Figure 1 .

[0018] Figure 3 is a plan view of Figure 1 .

[0019] Figure 4 is a plan view showing a schematic arrangement of a sub-pixel and a main pixel around a sensor region of the display panel shown in Figure 1 .

[0020] Figure 5 is a plan view showing magnification of the sub-pixel of Figure 4 .

[0021] Figure 6 is a plan view showing only a semiconductor layer and a blocking layer of Figure 5 .

[0022] Figure 7a is a cross-sectional view taken along line B-B' of Figure 6 .

[0023] Figure 7b as a comparative example of Figure 7a , is a cross-sectional view describing a disconnection condition in a case where the blocking layer is only under a part of the semiconductor layer.

[0024] Figure 8 is a cross-sectional view of Figure 4 .

[0025] Figures 9a to 9d is a plan view showing a deformable structure of the blocking layer shown in Figure 6 .

[0026] Figure 10 is a schematic cross-sectional view of a display panel according to another embodiment of the present application. DETAILED DESCRIPTION

[0027] The present application can be modified in various ways, and can have several embodiments, and a specific embodiment is shown in the drawings and is described in detail in the detailed description. Reference will now be made in detail to the embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. Figure 1 The effects and features of the present application and methods of achieving the effects and features can be apparent from the following embodiments described in detail in conjunction with the accompanying drawings. However, the present application is not limited to the following disclosed embodiments, and can be realized in various forms.

[0028] Hereinafter, embodiments of the present application will be described in detail with reference to the accompanying drawings, and in describing the embodiments, the same or similar components will be given the same reference numerals and their overlapping description will be omitted.

[0029] In the following embodiments, the singular expression includes the plural expression unless it is explicitly indicated otherwise in the context.

[0030] In the following embodiments, the inclusion or the having terms mean the presence of the features or components described in the specification, and do not exclude the possibility of adding one or more other features or components in advance.

[0031] For convenience of explanation, the size of the components in the drawings can be exaggerated or reduced. For example, the size and thickness of each component shown in the drawings are shown in an arbitrary size and thickness for convenience of explanation, and thus the present application is not necessarily limited to the contents shown in the drawings.

[0032] When an embodiment can be realized at different times, a specific procedure can be performed differently from the order described. For example, two procedures described in succession can be performed substantially simultaneously, or in the reverse order of the described order.

[0033] Figure 1 is a perspective view schematically showing a display device according to an embodiment of the present application.

[0034] Reference Figure 2 The display device 1 includes a display area DA in which an image is realized and a non-display area NDA in which an image is not realized. The display device 1 can provide a main image using light emitted from a plurality of main pixels Pm arranged in the display area DA.

[0035] The display device 1 includes a sensor area SA. The sensor area SA will be described in detail with reference to FIG. 2. Figure 1As will be described later, the sensor region SA can be a region in which a component 20 such as a sensor using an optical signal or an acoustic signal is arranged in a lower portion thereof. The sensor region SA can include a transmission portion TA through which an optical signal and / or an acoustic signal output from the component 20 to the outside or propagated from the outside to the component 20 can be transmitted. As an embodiment of the present application, in a case where infrared rays are transmitted through the sensor region SA, the transmittance can be approximately 10% or more, more preferably, 20% or more, or 25% or more, or 50% or more, or 85% or more, or 90% or more.

[0036] In the present embodiment, a plurality of auxiliary pixels Pa can be arranged in the sensor region SA, and a predetermined image can be provided using light emitted from the plurality of auxiliary pixels Pa. The image provided from the sensor region SA serves as an auxiliary image, and the resolution thereof can be lower than that of the image provided from the display region DA. That is, since the sensor region SA has the transmission portion TA through which an optical signal and / or an acoustic signal can be transmitted, the number of auxiliary pixels Pa per unit area arranged in the sensor region SA can be less than the number of main pixels Pm per unit area arranged in the display region DA.

[0037] The sensor region SA can be surrounded by the display region DA at least in part, as an embodiment,

[0038] Figure 1 A case where the sensor region SA is entirely surrounded by the display region DA is shown.

[0039] Hereinafter, although an organic light emitting display device will be described as an example of the display device 1 according to the embodiment of the present application, the display device of the present application is not limited thereto. As another embodiment, various types of display devices such as an inorganic light emitting display device, a quantum dot light emitting display device, and the like can be used.

[0040] Although Figure 2 A case where the sensor region SA is arranged at one side (the upper right side) of the display region DA in a quadrangular shape is shown in FIG. 1, but the present application is not limited thereto. The shape of the display region DA can be a circular shape, an elliptical shape, or a polygonal shape such as a triangular shape or a pentagonal shape, and the position and number of the sensor region SA can also be variously changed.

[0041] Figure 1 is a cross-sectional view schematically showing a display device according to the embodiment of the present application, and can correspond to a cross-section taken along the A-A' line of FIG. 1. Figure 2

[0042] Referring to Figure 2 ​The display device 1 can include a display panel 10 including display elements and an assembly 20 corresponding to a sensor area SA.

[0043] The display panel 10 can include a substrate 100, a display element layer 200 disposed on the substrate 100, and a thin film encapsulation layer 300 as a sealing member sealing the display element layer 200. Also, the display panel 10 can further include a lower protection film 175 disposed at a lower portion of the substrate 100.

[0044] The substrate 100 can include glass or a high molecular resin. The high molecular resin can include polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene napthalate (PEN), polyethyeleneterepthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), cellulose acetate propionate (CAP), or the like. The substrate 100 including the high molecular resin can have a flexible, rollable, or bendable characteristic. The substrate 100 can be a multi-layer structure including a layer including the aforementioned high molecular resin and an inorganic layer (not shown).

[0045] The display element layer 200 can include a circuit layer including a main thin film transistor TFT and an auxiliary thin film transistor TFT', an organic light-emitting element OLED as a display element, and insulating layers IL, IL' located at the periphery thereof.

[0046] A main pixel Pm including a main thin film transistor TFT and an organic light-emitting element (OLED: organic light-emitting diode) connected thereto can be disposed at a display area DA, and an auxiliary pixel Pa including an auxiliary thin film transistor TFT' and an organic light-emitting element (OLED: organic light-emitting diode) connected thereto and a wiring WL can be disposed at a sensor area SA.

[0047] Also, a transmission portion TA can be arranged in the sensor region SA, in which no auxiliary thin film transistor TFT' and display elements are arranged. The transmission portion TA can be understood as a region that transmits light signals and / or acoustic signals emitted from the component 20 or incident on the component 20.

[0048] The component 20 can be located in the sensor region SA. The component 20 can be an electronic element that utilizes light or sound. For example, the component 20 can be a sensor that receives light, such as an infrared sensor, a sensor that outputs and senses light or sound to detect a distance or recognize a fingerprint, a small light that emits light, or a speaker that outputs sound, etc. When the component 20 is an electronic element that utilizes light, it is obvious that light of various wavelength bands, such as visible light, infrared light, ultraviolet light, etc. can be utilized. The number of components 20 arranged in the sensor region SA can be plural. For example, a light emitting element and a light receiving element can be arranged together as the component 20 in one sensor region SA. Alternatively, a light emitting portion and a light receiving portion can be equipped in one component 20. Here, the component 20 can be not only an electronic element or a sensor that utilizes light or sound, but also other electronic elements (i.e., electronic components) that are not sensors. Also, since the component 20 is an electronic element (i.e., an electronic component), the sensor region SA can also be referred to as an electronic component region.

[0049] In the present embodiment, a blocking layer BSM can be arranged in the sensor region SA. The blocking layer BSM can be arranged corresponding to the wiring WL and the auxiliary thin film transistor TFT' at the lower portion of the wiring WL and the lower portion of the auxiliary thin film transistor TFT'. The blocking layer BSM can prevent external light from reaching the auxiliary pixel Pa including the wiring WL and the auxiliary thin film transistor TFT' and the like. For example, the blocking layer BSM can prevent light emitted from the component 20 from reaching the wiring WL and the auxiliary pixel Pa.

[0050] Further, a constant voltage or a signal is applied to the blocking layer BSM, so damage to the pixel circuit due to electrostatic discharge can be prevented. Also, the blocking layer BSM has a characteristic in the arrangement relationship on the plane with respect to the auxiliary pixel Pa, and this will be described in detail later.

[0051] The thin film encapsulation layer 300 can include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, Figure 3 A first inorganic encapsulation layer 310 and a second inorganic encapsulation layer 330 and an organic encapsulation layer 320 therebetween are shown.

[0052] The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 can include one or more inorganic insulators of aluminum oxide, titanium oxide, thallium oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, silicon oxynitride.

[0053] The organic encapsulation layer 320 can include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyvinyl sulfonate, polyformaldehyde, polyarylate, hexamethyldisiloxane, an acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.), or any combination thereof.

[0054] The lower protective film 175 is attached to the lower portion of the substrate 100, and can function to support and protect the substrate 100. The lower protective film 175 can be provided with an opening 175OP corresponding to the sensor area SA. The light transmittance of the sensor area SA can be improved by providing the lower protective film 175 with the opening 175OP. The lower protective film 175 can be provided to include polyethylene terephthalate (PET) or polyimide (PI).

[0055] The area of the sensor area SA can be provided to be greater than the area of the arrangement assembly 20. Accordingly, the area of the opening 175OP provided in the lower protective film 175 can not coincide with the area of the sensor area SA. For example, the area of the opening 175OP can be provided to be smaller than the area of the sensor area SA.

[0056] Although not shown, a configuration element such as an input sensing member that senses a touch input, an anti-reflection member including a polarizer and a retarder or a color filter and a black matrix, and a transparent window can also be arranged on the display panel 10.

[0057] Further, although the case where the thin film encapsulation layer 300 is used as an encapsulation member that seals the display element layer 200 is shown in the present embodiment, the present application is not limited thereto. For example, a sealing substrate that is adhered to the substrate 100 by means of a sealant or a frit can also be used as a member that seals the display element layer 200.

[0058] Figure 1 is a plan view that more specifically shows the wiring structure on the plane of Figure 3 .

[0059] Referring to Figure 2 , the display panel 10 includes a plurality of main pixels Pm arranged in the display area DA. The main pixels Pm can each include a display element such as an organic light emitting element. Each main pixel Pm can emit light of, for example, red, green, blue, or white by means of the organic light emitting element. The main pixel Pm in the present specification can be understood as a pixel that emits light of any one of red, green, blue, and white as described above. The display area DA is described in detail above with reference to Figure 3The illustrated package member covers and can protect against the effects of external gases or moisture and the like.

[0060] The sensor region SA can be arranged inside the display region DA, and a plurality of auxiliary pixels Pa can be arranged in the sensor region SA. Each of the auxiliary pixels Pa can include a display element such as an organic light emitting element. Each of the auxiliary pixels Pa can emit light of, for example, red, green, blue, or white through the organic light emitting element. In the present specification, the auxiliary pixels Pa can be understood as pixels that emit light of any one of red, green, blue, and white as described above. Further, the sensor region SA can be provided with a transmissive portion TA arranged between the auxiliary pixels Pa.

[0061] In one embodiment, one main pixel Pm and one auxiliary pixel Pa can include the same pixel circuit. However, the present application is not limited thereto. The pixel circuit included in the main pixel Pm and the pixel circuit included in the auxiliary pixel Pa can obviously be different from each other.

[0062] The sensor region SA is provided with the transmissive portion TA, and the resolution of the sensor region SA can be lower than that of the display region DA. For example, the resolution of the sensor region SA can be about 1 / 2 of that of the display region DA. In some embodiments, the resolution of the display region DA can be 400 ppi or more, and the resolution of the sensor region SA can be about 200 ppi.

[0063] Each of the pixels Pm, Pa can be electrically connected to an outer peripheral circuit arranged in the non-display region NDA. The first scan driving circuit 110, the second scan driving circuit 120, the terminal 140, the data driving circuit 150, the first power supply wiring 160, and the second power supply wiring 170 can be arranged in the non-display region NDA.

[0064] The first scan driving circuit 110 can supply a scan signal to each of the pixels Pm, Pa through a scan line SL. The first scan driving circuit 110 can supply an emission control signal to each of the pixels Pm, Pa through an emission control line EL. The second scan driving circuit 120 can be arranged side by side with the first scan driving circuit 110 across the display region DA. Some of the pixels Pm, Pa arranged in the display region DA can be electrically connected to the first scan driving circuit 110, and the rest can be connected to the second scan driving circuit 120. As another embodiment, the second scan driving circuit 120 can be omitted.

[0065] The terminal 140 can be disposed at one side of the substrate 100. The terminal 140 can be exposed without being covered by the insulating layer, so as to be electrically connected with a printed circuit board PCB. A terminal PCB-P of the printed circuit board PCB can be electrically connected with the terminal 140 of the display panel 10. The printed circuit board PCB can transmit a signal or a power from a control portion (not shown) to the display panel 10. A control signal generated from the control portion can be transmitted to the first scan driving circuit 110 and the second scan driving circuit 120, respectively, through the printed circuit board PCB. The control portion can supply a first power (ELVDD) and a second power (ELVSS) to the first power supply line 160 and the second power supply line 170, respectively, through the first connection wiring 161 and the second connection wiring 171. The first power voltage (ELVDD) can be supplied to each of the pixels Pm, Pa through a driving voltage line PL connected with the first power supply line 160, and the second power voltage (ELVSS) can be supplied to the opposite electrode of each of the pixels Pm, Pa connected with the second power supply line 170.

[0066] The data driving circuit 150 is electrically connected to the data line DL. A data signal of the data driving circuit 150 can be supplied to each of the pixels Pm, Pa through a connection wiring 151 connected with the terminal 140 and the data line DL connected with the connection wiring 151. Although Figure 4 Although the data driving circuit 150 is shown as being disposed at the printed circuit board PCB, as another embodiment, the data driving circuit 150 can be disposed at the substrate 100. For example, the data driving circuit 150 can be disposed between the terminal 140 and the first power supply line 160.

[0067] The first power supply line 160 can include a first sub-line 162 and a second sub-line 163 extending in parallel in the x direction across the display area DA. The second power supply line 170 can partially surround the display area DA in a ring shape with one side open.

[0068] Figure 5 is a plan view of only one of the auxiliary pixels Pa and the through portion TA existing in the sensor area SA and the main pixel Pm adjacent to the sensor area SA, and the semiconductor layer 1130 is disposed at each of the auxiliary pixel Pa and the main pixel Pm. The semiconductor layer 1130 is an element of the active layer of the auxiliary thin film transistor TFT' and the main thin film transistor TFT provided at each of the auxiliary pixel Pa and the main pixel Pm, respectively, and is formed in the same pattern at both sides thereof. Here, the reason why only the semiconductor layer 1130 of the auxiliary pixel Pa and the main pixel Pm is shown in a simplified manner is that, in the following description, the auxiliary thin film transistor TFT' and the main thin film transistor TFT are described as being formed in the same pattern at both sides of the semiconductor layer 1130. Figure 6Before the complicated wirings are described, the features of the present embodiment in which the blocking layer BSM is arranged in order to block the semiconductor layer 1130 from the optical and acoustic signals of the module 20 are briefly mentioned. That is, the present embodiment has the feature that the semiconductor layer 1130 is well shielded by the blocking layer BSM so that it does not become affected by the signals of the module 20 to cause a leakage current or the like. This feature will be described later in Figure 5 The description will be continued.

[0069] Figure 5 is a plan view showing the various wirings overlapped with the auxiliary pixel Pa including an auxiliary thin film transistor TFT' including seven auxiliary thin film transistors of the drive thin film transistor Tl, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization drive thin film transistor T4, the operation control thin film transistor T5, the light emission control thin film transistor T6, and the second initialization drive thin film transistor T7 provided with such a semiconductor layer 1130 as a constituent element. It can be considered that the main pixel Pm also has the same arrangement structure of the wirings.

[0070] As Figure 8 shown, the auxiliary thin film transistor TFT' is configured of the drive thin film transistor Tl, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization drive thin film transistor T4, the operation control thin film transistor T5, the light emission control thin film transistor T6, and the second initialization drive thin film transistor T7 arranged along the semiconductor layer 1130. The semiconductor layer 1130 is arranged on the substrate 100 on which the first buffer layer 111a (refer to Figure 8 ) formed of an inorganic insulating substance is formed.

[0071] A part of the semiconductor layer 1130 corresponds to the active layers of the drive thin film transistor Tl, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization drive thin film transistor T4, the operation control thin film transistor T5, the light emission control thin film transistor T6, and the second initialization drive thin film transistor T7. In other words, it can be understood that the active layers of the drive thin film transistor Tl, the switching thin film transistor T2, the compensation thin film transistor T3, the first initialization drive thin film transistor T4, the operation control thin film transistor T5, the light emission control thin film transistor T6, and the second initialization drive thin film transistor T7 are connected to each other and curved in various shapes. Hereinafter, the active layers will also be collectively referred to as the semiconductor layer.

[0072] The seven auxiliary thin film transistors TFT' will be briefly described below.

[0073] First, the driving thin film transistor T1 includes a driving gate electrode G1 overlapping with a driving channel region and a driving source electrode S1 and a driving drain electrode D1 arranged on both sides of the driving channel region. The driving channel region overlapping with the driving gate electrode G1 can be formed with a long channel length in a narrow space by having a shape with a bend such as an omega (Ω) shape. In the case where the length of the driving channel region is long, since the driving range of the gate voltage becomes wide, the color step of light emitted from the organic light emitting element OLED can be controlled more finely, and thus the display quality can be improved.

[0074] The switching thin film transistor T2 includes a switching gate electrode G2 overlapping with a switching channel region and a switching source electrode S2 and a switching drain electrode D2 arranged on both sides of the switching channel region. The switching drain electrode D2 can be connected with the driving source electrode S1.

[0075] The compensation thin film transistor T3, as a double thin film transistor, can be equipped with a compensation gate electrode G3 overlapping with two compensation channel regions, and can include a compensation source electrode S3 and a compensation drain electrode D3 arranged on both sides. The compensation thin film transistor T3 can be connected with the driving gate electrode G1 of the driving thin film transistor T1 through the node connection line 1174 described later.

[0076] The first initialization driving thin film transistor T4, as a double thin film transistor, can be equipped with a first initialization gate electrode G4 overlapping with two

[0077] The first initialization channel region overlapping with the first initialization gate electrode G4 can include a first initialization source electrode S4 and a first initialization drain electrode D4 arranged on both sides.

[0078] The operation control thin film transistor T5 can include an operation control gate electrode G5 overlapping with an operation control channel region and an operation control source electrode S5 and an operation control drain electrode D5 arranged on both sides. The operation control drain electrode D5 can be connected with the driving source electrode S1.

[0079] The light emission control thin film transistor T6 can include a light emission control gate electrode G6 overlapping with a light emission control channel region and a light emission control source electrode S6 and a light emission control drain electrode D6 arranged on both sides. The light emission control source electrode S6 can be connected with the driving drain electrode D1.

[0080] The second initialization driving thin film transistor T7 can include a second initialization gate electrode G7 overlapping with a second initialization channel region and a second initialization source electrode S7 and a second initialization drain electrode D7 arranged on both sides.

[0081] The aforementioned auxiliary thin film transistor TFT' can be connected to a signal line (a scan line SL), a previous scan line SL-1, a light emission control line EL, and a data line DL, an initialization voltage line VL, and a driving voltage line PL.

[0082] The scan line SL, the previous scan line SL-1, the light emission control line EL, and the drive gate electrode G1 can be arranged on the aforementioned semiconductor layer 1130 with the insulating layer(s) interposed therebetween.

[0083] The scan line SL can extend in the first direction. A region of the scan line SL can correspond to the switching gate electrode G2 and the compensation gate electrode G3. For example, regions of the scan line SL that overlap with the switching channel of the switching thin film transistor T2 and the two compensation channels of the compensation thin film transistor T3, respectively, can be the switching gate electrode G2 and the compensation gate electrode G3.

[0084] The previous scan line SL-1 extends in the first direction, and a part of a region thereof can correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively. For example, regions of the previous scan line SL-1 that overlap with the two first initialization channels of the first drive thin film transistor T4 and the second initialization channel of the second initialization drive thin film transistor T7, respectively, can be the first initialization gate electrode G4 and the second initialization gate electrode G7.

[0085] The light emission control line EL extends in the first direction. A region of the light emission control line EL can correspond to the operation control gate electrode G5 and the light emission control gate electrode G6, respectively. For example, regions of the light emission control line EL that overlap with the operation control channel of the operation control thin film transistor T5 and the light emission control channel of the light emission control thin film transistor T6, respectively, can be the operation control gate electrode G5 and the light emission control gate electrode G6.

[0086] The drive gate electrode G1, as a floating electrode, can be connected to the compensation thin film transistor T3 via the aforementioned node connection line 1174.

[0087] The electrode voltage line HL can be arranged on the aforementioned scan line SL, the previous scan line SL-1, the light emission control line EL, and the drive gate electrode G1 with the insulating layer(s) interposed therebetween.

[0088] The electrode voltage line HL can extend in the first direction in a manner that crosses the data line DL and the drive voltage line PL. A part of the electrode voltage line HL can cover at least a part of the drive gate electrode G1, and can form a storage capacitor Cst together with the drive gate electrode G1. For example, the drive gate electrode G1 can become a first storage condenser plate CE1 of the storage capacitor Cst, and a part of the electrode voltage line HL can become a second storage condenser plate CE2 of the storage capacitor Cst.

[0089] The second storage capacitor plate CE2 of the storage capacitor Cst is electrically connected to the drive voltage line PL. In connection therewith, the electrode voltage line HL can be connected to the drive voltage line PL arranged on the electrode voltage line HL by means of the contact hole CNT. Thus, the electrode voltage line HL can have the same voltage level (constant voltage) as the drive voltage line PL. For example, the electrode voltage line HL can have a constant voltage of +5 V. The electrode voltage line HL can be understood as a horizontal drive voltage line.

[0090] Since the drive voltage line PL extends in the second direction and the electrode voltage line HL, which is electrically connected to the drive voltage line PL, extends in the first direction, which is transverse to the second direction, the plurality of drive voltage lines PL and electrode voltage lines HL can form a mesh structure in the display area.

[0091] On the electrode voltage line HL, the data line DL, the drive voltage line PL, the initialization connection line 1173 and the node connection line 1174 can be arranged through the insulating layer(s).

[0092] The data line DL extends in the second direction and can be connected to the switch source electrode S2 of the switch thin film transistor T2 by means of the contact hole 1154. A part of the data line DL can be understood as a switch source electrode.

[0093] The drive voltage line PL extends in the second direction and, as previously described, is connected to the electrode voltage line HL by means of the contact hole CNT. Furthermore, the drive voltage line PL can be connected to the operation control thin film transistor T5 by means of the contact hole 1155. The drive voltage line PL can be connected to the operation control drain electrode D5 by means of the contact hole 1155.

[0094] One end of the initialization connection line 1173 can be connected to the first initialization drive thin film transistor T4 and the second initialization drive thin film transistor T7 by means of the contact hole 1152 and the other end can be connected to the initialization voltage line VL by means of the contact hole 1151.

[0095] One end of the node connection line 1174 can be connected to the compensation drain electrode D3 by means of the contact hole 1156 and the other end can be connected to the drive gate electrode G1 by means of the contact hole 1157.

[0096] On the data line DL, the drive voltage line PL, the initialization connection line 1173 and the node connection line 1174, the initialization voltage line VL can be arranged through the insulating layer(s).

[0097] The initialization voltage line VL extends along a first direction. The initialization voltage line VL can be connected to the first initialization driving thin-film transistor T4 and the second initialization driving thin-film transistor T7 via the initialization connection line 1173. The initialization voltage line VL can have a constant voltage (e.g., -2V, etc.).

[0098] The initialization voltage line VL can be arranged in conjunction with the organic light-emitting element OLED (OLED). Figure 6 The pixel electrode 210 is on the same layer as the light-emitting control thin-film transistor T6 and may include the same material. The pixel electrode 210 can be connected to the light-emitting control thin-film transistor T6. The pixel electrode 210 is connected to the connecting metal 1175 through the contact hole 1163, and the connecting metal 1175 can be connected to the light-emitting control drain electrode D6 through the contact hole 1153.

[0099] As observed above, the semiconductor layer 1130 of the auxiliary thin-film transistor TFT' is disposed on the substrate 100 to form the main layer of the plurality of thin-film transistors T1-T7. However, if the optical signal or audio signal of the component 20 is directly transmitted to the semiconductor layer 1130, leakage current will be generated in each thin-film transistor T1-T7, which will act as a factor that hinders proper operation.

[0100] Therefore, in order to prevent this problem, such as Figure 7a A blocking layer BSM is formed beneath the semiconductor layer 1130, as shown. This blocking layer BSM is disposed between the component 20 located below the substrate 100 and the semiconductor layer 1130 located above the substrate 100, thereby blocking optical or acoustic signals output from the component 20 from being directly transmitted to the semiconductor layer 1130. The blocking layer BSM is primarily formed of Mo material, and to fully perform this blocking function, its thickness t1 (refer to...) Figure 7a ) needs to That's all. However, if we consider this kind of... If the blocking layer BSM of the above thickness is only formed in a portion of the area beneath the semiconductor layer 1130, such as the location of thin-film transistors T1 to T7, the step difference will increase the risk of wire breakage in the semiconductor layer 1130. Therefore, to prevent this problem, in this embodiment, the blocking layer BSM is formed with the same pattern as the semiconductor layer 1130 to cover the entire area of ​​the semiconductor layer 1130. Of course, for a more stable blocking function, the width W2 of the blocking layer BSM is formed to be greater than the width W1 of the semiconductor layer 1130 (W1... <W2)。

[0101] Here, the wire breakage problem caused by the aforementioned step difference can be addressed as follows: Figure 7b and Figure 7a The same understanding applies. Figure 6 It is along Figure 7bthe structure of the present embodiment taken along the B-B' line, Figure 7a As a comparative example, a cross-sectional view showing a case where the blocking layer BSM is present only under a part of the semiconductor layer 1130 is shown.

[0102] First, Figure 7b The structure of the present embodiment, in which the blocking layer BSM is formed under the entire region of the semiconductor layer 1130, does not cause a disconnection problem due to a step difference caused by the blocking layer BSM because the semiconductor layer 1130 is present only above the blocking layer BSM without passing through the step difference.

[0103] However, if the blocking layer BSM is present only under a part of the semiconductor layer 1130 as described above, Figure 6 the semiconductor layer 1130 passes through a step difference caused by the blocking layer BSM, and the thicker the blocking layer BSM, the more serious the step difference, thus easily forming a disconnection site 1130a as shown in the figure. Therefore, in the present embodiment, the blocking layer BSM is formed in the same pattern as the semiconductor layer 1130 as shown above, thus shielding the entire region of the semiconductor layer 1130, thus eliminating the risk of disconnection due to a step difference from the root. Figure 8

[0104] Hereinafter, referring to Figure 2 a cross-sectional structure of the auxiliary pixel Pa and the main pixel Pm of the thin film transistor having the features described above will be observed. It can be considered that the layered structure on the substrate 100 shown schematically in Figure 6 will be further described in detail.

[0105] In other words, the substrate 100 can include glass or a high molecular resin. The high molecular resin can include polyethersulfone (PES), polyacrylate, polyetherimide (PEI), polyethylene napthalate (PEN), polyethyeleneterepthalate (PET), polyphenylene sulfide (PPS), polyarylate (PAR), polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP), or the like. The substrate 100 including the high molecular resin can have a flexible, rollable, or bendable characteristic. The substrate 100 can be a multi-layer structure including a layer including the aforementioned high molecular resin and an inorganic layer (not shown). ​

[0106] The buffer layer 111 is provided on the substrate 100, and can reduce or block penetration of foreign matter, moisture, or external air from the lower portion of the substrate 100, and can provide a flat surface on the substrate 100. The buffer layer 111 can be made of an inorganic substance such as an oxide or a nitride, an organic substance, or an organic and inorganic composite, and can be configured of a single layer or a multi-layer structure of an inorganic substance and an organic substance. A barrier layer (not shown) that blocks penetration of external air can also be included between the substrate 100 and the buffer layer 111. The buffer layer 111 can be provided as a stack of a first buffer layer 111a and a second buffer layer 111b.

[0107] The gate electrode G is disposed on the semiconductor layer 1130 with the first gate insulating layer 112 interposed therebetween. The gate electrode G can include molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and can be configured as a single layer or a multi-layer. As an example, the gate electrode G can be a single layer of Mo. The scan line SL, the previous scan line SL-1, and the emission control line EL can be formed in the same layer as the gate electrode G. That is, the gate electrode G, the scan line SL, the previous scan line SL-1, and the emission control line EL can be disposed on the first gate insulating layer 112.

[0108] The first gate insulating layer 112 can include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), or the like.

[0109] The second gate insulating layer 113 can be provided to cover the gate electrode G. The second gate insulating layer 113 can include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), or the like.

[0110] The active electrode S and the drain electrode D and the driving voltage line PL can be disposed on the interlayer insulating layer 115. The source electrode S and the drain electrode D and the driving voltage line PL can include a conductive substance including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), or the like, and can be formed as a single layer or a multi-layer including the material.

[0111] The drain electrode D is connected to the pixel electrode 210 of the organic light emitting element OLED.

[0112] The planarization layer 117 can be provided on the source electrode S and the drain electrode D and the driving voltage line PL, and the organic light emitting element OLED can be provided on the planarization layer 117.

[0113] The planarization layer 117 can have a flat upper surface so that the pixel electrode 210 can be formed flat. The planarization layer 117 can be formed in a single layer or multiple layers with a film composed of an organic substance. Such a planarization layer 117 can include benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or a general-purpose polymer such as polystyrene (PS), a polymer derivative having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorine polymer, a p-xylylene polymer, a vinyl alcohol polymer, and a composite thereof. The planarization layer 117 can include an inorganic substance. Such a planarization layer 117 can include silicon oxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2), or zinc oxide (ZnO2), etc. In the case where the planarization layer 117 is composed of an inorganic substance, chemical planarization polishing can be performed as appropriate. In addition, the planarization layer 117 can include both an organic substance and an inorganic substance.

[0114] The pixel electrode 210 can be a (semi-)transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode 210 can be provided with a reflective film formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and a compound thereof, etc., and a transparent or semi-transparent electrode layer formed on the reflective film. The transparent or semi-transparent electrode layer can be provided with at least one selected from the group of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 can be provided in a structure in which ITO / Ag / ITO are laminated.

[0115] A pixel defining film 119 can be disposed on the planarization layer 117, and an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), and phenol resin can be spin-coated to form.

[0116] The intermediate layer 220 of the organic light emitting element OLED can include an organic light emitting layer. The organic light emitting layer can include an organic material including a fluorescent or phosphorescent substance that emits red, green, blue, or white light. The organic light emitting layer can be a low molecular organic material or a high molecular organic material, and a functional layer such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and an electron injection layer (EIL) can be selectively disposed at the lower and upper portions of the organic light emitting layer. The intermediate layer 220 can be disposed to correspond to each of the plurality of pixel electrodes 210. However, the present embodiment is not limited thereto. The intermediate layer 220 can be variously modified, for example, to include a layer that is integrated across the plurality of pixel electrodes 210.

[0117] The counter electrode 230 can be a light-transmissive electrode or a reflective electrode. In some embodiments, the counter electrode 230 can be a transparent or semi-transparent electrode, and can be formed of a thin metal film having a small work function including Li, Ca, LiF / Ca, LiF / Al, Al, Ag, Mg, and compounds thereof. Further, a transparent conductive oxide (TCO) film of ITO, IZO, ZNO, or In2O3, or the like can be disposed on the thin metal film. The counter electrode 230 can be disposed across the display area DA and the sensor area SA, and can be disposed at the upper portion of the intermediate layer 220 and the pixel defining film 119. The counter electrode 230 can be integrally formed for the plurality of organic light emitting elements OLED, and thus can correspond to the plurality of pixel electrodes 210.

[0118] In a case where the pixel electrode 210 is configured as a reflective electrode and the counter electrode 230 is configured as a light-transmissive electrode, light emitted from the intermediate layer 220 is emitted toward the counter electrode 230, and thus the display device can be a front light emitting type. In a case where the pixel electrode 210 is configured as a transparent or semi-transparent electrode and the counter electrode 230 is configured as a reflective electrode, light emitted from the intermediate layer 220 is emitted toward the substrate 100, and thus the display device can be a back light emitting type. However, the present embodiment is not limited thereto. The display device of the present embodiment can be a double-sided light emitting type that emits light in both the front and back directions.

[0119] In the present embodiment, the blocking layer BSM is arranged between the substrate 100 and the semiconductor layer 1130 of the auxiliary pixel Pa, and between the substrate 100 and the wiring portion DW. More precisely, by arranging the blocking layer BSM between the component 20 and the semiconductor layer 1130, and between the component 20 and the wiring portion DW, the auxiliary thin film transistor TFT' and the wiring portion DW are protected from the optical signal or the acoustic signal of the component 20, especially the semiconductor layer 1130 of the auxiliary thin film transistor TFT' as shown in Figure 6 is shielded by the blocking layer BSM.

[0120] Therefore, according to this structure, the danger of the occurrence of a leakage current by the optical signal or the acoustic signal of the component 20 can be prevented by the blocking layer BSM. Especially, since the semiconductor layer 1130 of the auxiliary thin film transistor TFT' is more sensitive to the occurrence of a leakage current, in order to sufficiently prevent it, the thickness of the blocking layer BSM needs to be formed At this time, for the danger of the disconnection of the semiconductor layer 1130 due to the step difference caused by the thickness of the blocking layer BSM, as shown in Figures 9a to 9d can be eliminated by shielding the entire area of the semiconductor layer 1130 by the blocking layer BSM in the same pattern as the semiconductor layer 1130.

[0121] Therefore, the occurrence of a leakage current due to the signal of the component 20 can be sufficiently prevented by the blocking layer BSM, so that the operation and the image presentation of the component 20 can be smoothly performed also in the sensor area SA, and the disconnection problem of the semiconductor layer 1130 due to the step difference can also be eliminated from the root.

[0122] Further, in the present embodiment, the case where the blocking layer BSM is formed in the same pattern as the pattern of the semiconductor layer 1130 is shown, and it can also be formed in the form of a region having a partially different pattern as shown in Figure 8 . That is, as long as the entire area of the semiconductor layer 1130 can be shielded, even if the blocking layer BSM does not necessarily have the same pattern, the functions of preventing the occurrence of a leakage current and suppressing disconnection can be sufficiently performed.

[0123] Further, in the aforementioned embodiments, as explained in Figure 10 , the case where the blocking layer BSM is present only under the auxiliary thin film transistor TFT' in the sensor area SA is shown, but as shown in ​As shown, the same substance as the blocking layer BSM of the auxiliary thin film transistor TFT' can be used and the same pattern can be arranged for the blocking layer BSM under the main thin film transistor TFT of the main pixel Pm. That is, since the main pixel Pm is not located in the sensor area SA where the component 20 is located, there is no big problem even if there is no blocking layer BSM, but if it is intended to completely block the mixing of noise caused by external light other than the component 20, the blocking layer BSM can be arranged to shield the entire area of the semiconductor layer 1130 under the main thin film transistor TFT of the main pixel Pm.

[0124] Although the present application has been described with reference to an embodiment shown in the drawings, this is merely exemplary and, as can be understood by those having ordinary knowledge in the relevant technical field, various modifications and equivalent other embodiments can be made. Therefore, the true technical scope of the present application should be determined based on the technical idea of the recited claims.

Claims

1. A display device, comprising: The substrate includes a display area equipped with main pixels and an electronic component area equipped with auxiliary pixels and a transmissive portion; as well as Electronic components transmit or receive predetermined signals from or to the outside of the substrate through the transmitting portion, and are arranged correspondingly to the electronic component area. The auxiliary pixel is equipped with an auxiliary thin-film transistor including a semiconductor layer and an organic light-emitting element connected to the upper part of the auxiliary thin-film transistor. The auxiliary thin-film transistor constitutes a structure in which multiple thin-film transistors are arranged along the semiconductor layer. A blocking layer having a first blocking layer and a second blocking layer is disposed on the substrate. A first blocking layer for blocking signals transmitted and received through the electronic component is disposed between the electronic component and the auxiliary thin-film transistor. When the substrate is viewed from above, the first blocking layer overlaps with the entire semiconductor layer of the auxiliary thin-film transistor. The semiconductor layer is formed in a predetermined pattern by interconnecting the plurality of thin-film transistors. The electronic component area is also equipped with wiring located on one side of the auxiliary pixel in an area other than the transmissive portion. When viewed from above, the second blocking layer overlaps with at least a portion of the wiring and the spacing between the plurality of wirings.

2. The display device as claimed in claim 1, wherein, The first blocking layer has the same pattern as the semiconductor layer of the auxiliary thin-film transistor.

3. The display device as claimed in claim 2, wherein, The width of the pattern in the first blocking layer is greater than the width of the pattern in the semiconductor layer of the auxiliary thin-film transistor.

4. The display device as claimed in claim 1, wherein, The first blocking layer includes a pattern different from the pattern of the semiconductor layer of the auxiliary thin-film transistor.

5. The display device as claimed in claim 1, wherein, The thickness of the blocking layer is 800 Å or more.

6. The display device as claimed in claim 1, wherein, Buffer layers are present between the auxiliary thin-film transistor and the blocking layer, and between the blocking layer and the substrate, respectively.

7. The display device as claimed in claim 1, wherein, The main pixel is equipped with a main thin-film transistor including a semiconductor layer. A third blocking layer is disposed between the electronic component and the main thin-film transistor, which blocks the entire semiconductor layer of the main thin-film transistor in a plane.

8. The display device as claimed in claim 7, wherein, The main pixel also includes an organic light-emitting element connected to the main thin-film transistor.

9. The display device as claimed in claim 1, wherein, The predetermined signal includes either an optical signal or an audio signal.

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