Method and apparatus for optimizing nvm interface command execution order

Abstract

The application discloses a method and device for optimizing NVM interface command execution sequence. The method comprises the following steps: obtaining a first NVM interface command to be executed; identifying whether the first NVM interface command hits a page cache of an NVM chip; in response to the page cache hit, generating a command for accessing the page cache according to the first NVM interface command, and replacing the first NVM interface command with the command for accessing the page cache. The medium interface controller in the application comprises a message queue and an NVM command processing unit; the message queue is used for receiving messages of multiple planes of a logical unit accessing an NVM chip; the NVM command processing unit obtains information from the message queue, generates an NVM interface command according to the indication of the message, and sends the NVM interface command to the NVM chip; and the NVM command processing unit fuses the NVM interface command.

Description

Technical Field

[0001] This application relates to the field of storage device technology, and more particularly to scheduling commands for accessing the NVM chip in a storage device to improve the performance of the storage device. Background Technology

[0002] See Figure 1 This diagram illustrates a block diagram of a storage device. Storage device 102 is coupled to a host computer to provide storage capabilities. The host computer and storage device 102 can be coupled in various ways, including but not limited to connections via SATA, IDE, USB, PCIe, NVMe (NVM Express), SAS, Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device via the aforementioned methods, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 includes an interface 103, a control unit 104, one or more NVM (Non-Volatile Memory) chips 105, and optionally firmware storage 110. Interface 103 is adapted to exchange data with the host via, for example, SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, or Fibre Channel. The control unit 104 is used to control data transmission between the interface 103, the NVM chip 105, and the firmware memory 110. It is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control unit 104 can be implemented through software, hardware, firmware, or a combination thereof. The control unit 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control unit 104 may also include a processor or controller. During operation, the control unit 104 loads firmware from the firmware memory 110. The firmware memory 110 can be NOR flash memory, ROM, EEPROM, or a portion of the NVM chip 105.

[0003] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0004] A memory target is one or more logic units within a NAND flash memory package that share a chip enable (CE) signal. Each logic unit has a logic unit number (LUN). A NAND flash memory package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, while multiple logic units within a NAND flash memory chip can execute commands and report status independently of each other. The meanings of target, logic unit, LUN, and plane are provided in the "Open NAND Flash Interface Specification (Revision 3.0)" available at http: / / www.micron.com / ~ / media / Documents / Products / Other%20Documents / ON FI3_0Gold.ashx, which is part of the prior art.

[0005] Data is typically stored and retrieved in pages on storage media, while data is erased in blocks. A block (also called a physical block) contains multiple pages. Pages on a storage medium (called physical pages) have a fixed size, such as 17664 bytes. Physical pages can also have other sizes.

[0006] Chinese patent application CN1414468A discloses a scheme for processing CPU (Central Processing Unit) instructions by executing microinstruction sequences. When the CPU needs to process a specific instruction, a conversion logic circuit converts the specific instruction into a corresponding microinstruction sequence, and the function of the specific instruction is implemented by executing the microinstruction sequence. The microinstruction sequence or a template of the microinstruction sequence is stored in ROM (Read Only Memory). During the process of converting a specific instruction into a microinstruction sequence, the microinstruction sequence template can be filled to correspond to the specific instruction.

[0007] Chinese patent applications CN201610009789.6 and CN201510253428.1 disclose microinstruction execution methods and apparatus for flash memory interface controllers; Chinese patent application CN201610861793.5 discloses microinstruction sequence scheduling methods and apparatus; Chinese patent application CN201611213754.0 discloses I / O command processing methods and solid-state storage devices; and Chinese patent application CN201611213755.5 discloses a high-capacity NVM interface controller. The full text of these patent applications is incorporated herein by reference. Flash memory interface controllers are typically coupled to multiple NVM chips. NVM chips include multiple LUNs (Logic Units) or dies, and multiple LUNs and dies can respond to and access NVM commands in parallel. Since each LUN or die can have multiple NVM commands to be processed, the NVM controller needs to schedule the processing of multiple NVM commands in order to maintain multiple NVM commands that are being processed or pending, or to maintain the execution of multiple microinstruction sequences used to generate and process NVM commands. Summary of the Invention

[0008] According to a first aspect of this application, a first media interface controller according to the first aspect of this application is provided, comprising: a message queue and an NVM command processing unit, the message queue being coupled to the NVM command processing unit, and the NVM command processing unit being coupled to a plurality of NVM chips; the message queue being used to receive messages for accessing the NVM chips, the NVM command processing unit obtaining information from the message queue, generating NVM interface commands according to the instructions of the messages, and sending them to the NVM chips; the NVM command processing unit changing the order in which the NVM interface commands are sent.

[0009] According to the first media interface controller of the first aspect of this application, a second media interface controller according to the first aspect of this application is provided, wherein the messages for accessing the NVM chip include one or more of the following: a message indicating that data is read, a message indicating that data is written, a message indicating that the memory cell of the NVM chip is erased, a message indicating that the state of the NVM chip is read, a message indicating that the characteristics of the NVM chip are read or set, and a user-defined message.

[0010] According to the first or second media interface controller of the first aspect of this application, a third media interface controller according to the first aspect of this application is provided, wherein the message queue includes one or more message queues.

[0011] According to one of the first to third media interface controllers of the first aspect of this application, a fourth media interface controller according to the first aspect of this application is provided, wherein the NVM command processing unit is coupled to multiple NVM chips through multiple channels, and each NVM chip includes multiple logic units.

[0012] According to one of the first to fourth media interface controllers of the first aspect of this application, a fifth media interface controller according to the first aspect of this application is provided, wherein the NVM command processing unit includes multiple hardware instances or multiple threads, and each instance or thread processes NVM interface commands in parallel.

[0013] According to one of the first to fifth media interface controllers of the first aspect of this application, a sixth media interface controller according to the first aspect of this application is provided, and an NVM command processing unit schedules NVM interface commands by executing instructions or microinstruction sequences.

[0014] According to one of the first to sixth media interface controllers of the first aspect of this application, a seventh media interface controller according to the first aspect of this application is provided, which creates multiple threads based on the same instruction or microinstruction sequence.

[0015] According to the seventh media interface controller of the first aspect of this application, an eighth media interface controller according to the first aspect of this application is provided, wherein the NVM command processing unit stores the execution state for each thread.

[0016] According to one of the first to eighth media interface controllers of the first aspect of this application, a ninth media interface controller according to the first aspect of this application is provided, wherein when the NVM chip processing unit writes data to the NVM chip, the data is stored in the page cache of the NVM chip.

[0017] According to one of the first to ninth media interface controllers of the first aspect of this application, a tenth media interface controller according to the first aspect of this application is provided, and an NVM command processing unit executes an optimized NVM interface command execution order according to the second aspect of this application.

[0018] According to one of the first to tenth media interface controllers of the first aspect of this application, an eleventh media interface controller according to the first aspect of this application is provided, wherein the NVM command processing unit merges two or more NVM interface commands.

[0019] According to a second aspect of this application, a method for optimizing the execution order of NVM interface commands according to the second aspect of this application is provided, comprising: detecting whether the execution order of NVM interface commands can be optimized; in response to the execution order of NVM interface commands being optimized, identifying whether the offset value of the read pointer is greater than 0; in response to the offset value being greater than 0, incrementing the offset value; and obtaining the read pointer based on the sum of the base address and the offset value, and obtaining and processing the NVM interface command based on the read pointer.

[0020] According to the first method for optimizing the execution order of NVM interface commands according to the second aspect of this application, a second method for optimizing the execution order of NVM interface commands according to the second aspect of this application is provided, wherein when the offset value is greater than 0, its value indicates the number of times the execution order of NVM interface commands has been changed previously.

[0021] According to the first or second method for optimizing the execution order of NVM interface commands according to the second aspect of this application, a third method for optimizing the execution order of NVM interface commands according to the second aspect of this application is provided, wherein the form of the acquired NVM interface commands is changed in response to the optimizable NVM interface command execution order.

[0022] According to the third method for optimizing the execution order of NVM interface commands according to the second aspect of this application, a fourth method for optimizing the execution order of NVM interface commands according to the second aspect of this application is provided, which modifies the obtained read command into a read page cache command.

[0023] According to one of the first to fourth methods for optimizing the execution order of NVM interface commands according to the second aspect of this application, a fifth method for optimizing the execution order of NVM interface commands according to the second aspect of this application is provided, wherein in response to an offset value not being greater than 0, both the offset value and the base address are incremented.

[0024] According to one of the methods for optimizing the execution order of NVM interface commands according to the first to fifth aspects of the second aspect of this application, a method for optimizing the execution order of NVM interface commands according to the sixth aspect of the second aspect of this application is provided. In response to the inability to optimize the execution order of NVM interface commands, the method identifies whether the offset value of the read pointer is greater than 0; in response to the offset value being greater than 0, the method obtains and processes the NVM interface command based on the base address as the read pointer; the method increments the base address and sums it with the offset value to obtain a new value of the base address, and sets the offset value to 0; and the method obtains the read pointer based on the sum of the base address and the offset value, and obtains and processes the NVM interface command based on the read pointer.

[0025] According to the sixth method for optimizing the NVM interface command execution order of the second aspect of this application, a seventh method for optimizing the NVM interface command execution order according to the second aspect of this application is provided, wherein the base address is incremented in response to an offset value not being greater than 0.

[0026] According to one of the methods for optimizing the execution order of NVM interface commands according to the second aspect of this application (first to seventh), an eighth method for optimizing the execution order of NVM interface commands according to the second aspect of this application is provided. After executing the first NVM interface command, it is identified whether the execution order of the NVM interface commands can be optimized; the first NVM interface command is compared with the adjacent second NVM interface command to identify whether the optimization conditions are met; in response to the first NVM interface command and the second NVM interface command not meeting the optimization conditions, and the first NVM interface command and the non-adjacent third NVM interface command meeting the optimization conditions, the execution order of the NVM interface commands that can be optimized is identified.

[0027] According to the eighth method for optimizing the execution order of NVM interface commands according to the second aspect of this application, a ninth method for optimizing the execution order of NVM interface commands according to the second aspect of this application is provided, wherein a second NVM interface command is executed in response to identifying that the execution order of NVM interface commands cannot be optimized.

[0028] The method for optimizing the execution order of NVM interface commands according to the eighth or ninth method of the second aspect of this application provides a method for optimizing the execution order of NVM interface commands according to the second aspect of this application. The optimization conditions include: the third NVM interface command indicates reading the same or similar address as the first NVM interface command; or the data read by the third NVM interface command is located in the page cache of the NVM chip due to the execution of the first NVM interface command; or the first NVM interface command and the third NVM interface command access different planes of the same logical unit, and the first NVM interface command and the third NVM interface command can be replaced by a single multi-plane command; or the third NVM interface command has a higher processing priority; or the third NVM interface command has a higher processing priority and the NVM interface commands between the first NVM interface command and the third NVM interface command in the message queue have a longer processing time.

[0029] According to one of the methods for optimizing the execution order of NVM interface commands according to the first to seventh aspects of the second aspect of this application, an eleventh method for optimizing the execution order of NVM interface commands according to the second aspect of this application is provided. After the first NVM interface command is executed, it is identified whether the execution order of the NVM interface commands can be optimized; in response to the first NVM interface command and the adjacent second NVM interface command satisfying the optimization conditions, the value of the offset value is obtained; in response to the offset value being greater than 0, the execution order of the NVM interface commands that can be optimized is identified.

[0030] According to the eleventh method of optimizing the execution order of NVM interface commands according to the second aspect of this application, a twelfth method of optimizing the execution order of NVM interface commands according to the second aspect of this application is provided, wherein in response to an offset value being greater than 0, the offset value is incremented while the base address remains unchanged; and a read pointer is obtained based on the sum of the base address and the offset value, and an NVM interface command is obtained and processed based on the read pointer.

[0031] According to the twelfth method of optimizing the execution order of NVM interface commands according to the second aspect of this application, a thirteenth method of optimizing the execution order of NVM interface commands according to the second aspect of this application is provided, in response to an offset value not greater than 0, identifying an execution order that cannot be optimized.

[0032] According to one of the methods for optimizing the execution order of NVM interface commands according to the twelfth to fourteenth aspects of the second aspect of this application, a method for optimizing the execution order of NVM interface commands according to the fifteenth aspect of the second aspect of this application is provided. In response to the first NVM interface command and the adjacent second NVM interface command not satisfying the optimization conditions, it is further identified whether the first NVM interface command and the non-adjacent third NVM interface command satisfy the optimization conditions; in response to the first NVM interface command and the third NVM interface command satisfying the optimization conditions, the execution order of NVM interface commands that can be optimized is identified.

[0033] According to the fifteenth method of optimizing the execution order of NVM interface commands according to the second aspect of this application, a sixteenth method of optimizing the execution order of NVM interface commands according to the second aspect of this application is provided, in response to the first NVM interface command and the third NVM interface command not meeting the optimization conditions, identifying the execution order of NVM interface commands that cannot be optimized.

[0034] According to a third aspect of this application, a first media interface controller according to the third aspect of this application is provided, comprising: a message queue and an NVM command processing unit, wherein the message queue is coupled to the NVM command processing unit, and the NVM command processing unit is also coupled to a plurality of NVM chips; the message queue is used to receive messages from multiple planes of the logic units accessing the NVM chips; the NVM command processing unit obtains information from the message queue, generates NVM interface commands according to the instructions of the messages, and sends them to the NVM chips; the NVM command processing unit merges the NVM interface commands.

[0035] According to the first media interface controller of the third aspect of this application, a second media interface controller according to the third aspect of this application is provided, wherein the messages for accessing the NVM chip include one or more of the following: a message indicating that data is read, a message indicating that data is written, a message indicating that the memory cell of the NVM chip is erased, a message indicating that the state of the NVM chip is read, a message indicating that NVM chip features are read or set, and a user-defined message.

[0036] According to the first or second media interface controller of the third aspect of this application, a third media interface controller according to the third aspect of this application is provided, wherein the message queue includes one or more message queues.

[0037] According to one of the first to third media interface controllers of the third aspect of this application, a fourth media interface controller according to the third aspect of this application is provided, wherein the NVM command processing unit is coupled to multiple NVM chips through multiple channels, and each NVM chip includes multiple logic units.

[0038] According to one of the first to fourth media interface controllers of the third aspect of this application, a fifth media interface controller according to the third aspect of this application is provided, wherein the NVM command processing unit includes multiple hardware instances or multiple threads, and each instance or thread processes NVM interface commands in parallel.

[0039] According to one of the first to fifth media interface controllers of the third aspect of this application, a sixth media interface controller according to the third aspect of this application is provided, and an NVM command processing unit schedules NVM interface commands by executing instructions or microinstruction sequences.

[0040] According to one of the first to sixth media interface controllers of the third aspect of this application, a seventh media interface controller according to the third aspect of this application is provided, which creates multiple threads based on the same instruction or microinstruction sequence.

[0041] According to one of the first to seventh media interface controllers of the third aspect of this application, an eighth media interface controller according to the third aspect of this application is provided, wherein the NVM command processing unit stores the execution state for each thread.

[0042] According to one of the first to eighth media interface controllers of the third aspect of this application, a ninth media interface controller according to the third aspect of this application is provided, wherein when the NVM chip processing unit writes data to the NVM chip, the data is stored in the page cache of the NVM chip.

[0043] According to one of the first to ninth media interface controllers of the third aspect of this application, a tenth media interface controller according to the third aspect of this application is provided, wherein the NVM command processing unit merges two or more read commands in the message queue that access different planes of the same NVM chip into a single multi-plane read command.

[0044] According to the tenth media interface controller of the third aspect of this application, an eleventh media interface controller according to the third aspect of this application is provided, which, in response to recognizing that the data accessed by the first read command in the message queue is loaded into the page cache of the NVM chip as the single multiplane command is executed, also prioritizes the execution of the first read command.

[0045] According to the tenth or eleventh media interface controller of the third aspect of this application, a twelfth media interface controller according to the third aspect of this application is provided, which modifies the first read command into a read page cache command and executes the read page cache command.

[0046] According to one of the first to twelfth media interface controllers of the third aspect of this application, a thirteenth media interface controller according to the third aspect of this application is provided, and one method for the NVM command processing unit to execute the optimized NVM interface command execution order according to the fourth, fifth, sixth or seventh aspects of this application is provided.

[0047] According to a fourth aspect of this application, a method for optimizing the execution order of NVM interface commands according to the fourth aspect of this application is provided, comprising: detecting whether a first NVM interface command to be executed and a second NVM interface command that is adjacent to and follows it in a message queue can be merged; in response to the first NVM interface command and the second NVM interface command being mergeable, merging the first NVM interface command and the second NVM interface command; and executing the merged NVM interface command.

[0048] According to the first method for optimizing the execution order of NVM interface commands according to the fourth aspect of this application, a second method for optimizing the execution order of NVM interface commands according to the fourth aspect of this application is provided, wherein the first NVM interface command is executed in response to the incompatibility of the first NVM interface command and the second NVM interface command.

[0049] According to the first or second method for optimizing the execution order of NVM interface commands according to the fourth aspect of this application, a third method for optimizing the execution order of NVM interface commands according to the fourth aspect of this application is provided, wherein in response to the completion of the execution of the first NVM interface command, it is detected whether the execution order of NVM interface commands can be optimized; in response to the execution order of NVM interface commands being optimized, it is identified whether the offset value of the read pointer is greater than 0; in response to the offset value being greater than 0, the offset value is incremented; and the read pointer is obtained according to the sum of the base address and the offset value, and the NVM interface command is obtained and processed according to the read pointer.

[0050] According to the third method for optimizing the execution order of NVM interface commands according to the fourth aspect of this application, a fourth method for optimizing the execution order of NVM interface commands according to the fourth aspect of this application is provided, wherein when the offset value is greater than 0, its value indicates the number of times the execution order of NVM interface commands has been changed previously.

[0051] According to the third or fourth method for optimizing the execution order of NVM interface commands according to the fourth aspect of this application, a fifth method for optimizing the execution order of NVM interface commands according to the fourth aspect of this application is provided, wherein in response to an offset value not being greater than 0, both the offset value and the base address are incremented.

[0052] According to one of the methods for optimizing the execution order of NVM interface commands according to the third to fifth aspects of the fourth aspect of this application, a method for optimizing the execution order of NVM interface commands according to the sixth aspect of the fourth aspect of this application is provided. In response to the inability to optimize the execution order of NVM interface commands, the method identifies whether the offset value of the read pointer is greater than 0; in response to the offset value being greater than 0, the method obtains and processes the NVM interface command based on the base address as the read pointer; the method increments the base address and sums it with the offset value to obtain a new value of the base address, and sets the offset value to 0; and the method obtains the read pointer based on the sum of the base address and the offset value, and obtains and processes the NVM interface command based on the read pointer.

[0053] According to the sixth method for optimizing the NVM interface command execution order according to the fourth aspect of this application, a seventh method for optimizing the NVM interface command execution order according to the fourth aspect of this application is provided, wherein the base address is incremented in response to an offset value not being greater than 0.

[0054] According to a fifth aspect of this application, a method for optimizing the execution order of NVM interface commands according to the fifth aspect of this application is provided, comprising: obtaining a first NVM interface command to be executed; identifying whether the first NVM interface command hits the page cache of the NVM chip; in response to a page cache hit, generating a command to access the page cache according to the first NVM interface command, and replacing the first NVM interface command with the command to access the page cache.

[0055] According to the first method for optimizing the execution order of NVM interface commands according to the fifth aspect of this application, a second method for optimizing the execution order of NVM interface commands according to the fifth aspect of this application is provided to obtain the next NVM interface command to be executed.

[0056] According to the first method for optimizing the execution order of NVM interface commands according to the fifth aspect of this application, a third method for optimizing the execution order of NVM interface commands according to the fifth aspect of this application is provided. In response to a page cache miss, it is identified whether a first NVM interface command and a second NVM interface command that are adjacent to and follow it in the message queue can be merged; in response to the first NVM interface command and the second NVM interface command being mergeable, the first NVM interface command and the second NVM interface command are merged, and a merged multiplane command is generated and executed to replace the first NVM interface command and the second NVM interface command.

[0057] According to one of the first to third methods for optimizing the execution order of NVM interface commands according to the fifth aspect of this application, a fourth method for optimizing the execution order of NVM interface commands according to the fifth aspect of this application is provided, wherein the first NVM interface command is executed in response to the inability of the first NVM interface command and the second NVM interface command to be merged.

[0058] According to one of the first to fourth methods for optimizing the execution order of NVM interface commands according to the fifth aspect of this application, a fifth method for optimizing the execution order of NVM interface commands according to the fifth aspect of this application is provided, which records the address range of data in the page cache of each NVM chip to identify whether the NVM interface command hits the page cache.

[0059] According to one of the methods for optimizing the execution order of NVM interface commands according to the fifth aspect of this application, a sixth method for optimizing the execution order of NVM interface commands according to the fifth aspect of this application is provided. If the first NVM interface command processing unit is a read command, in response to the execution of the first NVM interface command, the address of the data in the page cache is also marked to identify whether subsequent NVM interface commands will hit the page cache.

[0060] According to one of the methods for optimizing the execution order of NVM interface commands according to the first to sixth aspects of the fifth aspect of this application, a method for optimizing the execution order of NVM interface commands according to the fifth aspect of this application is provided in the seventh aspect, wherein the NVM command processing unit merges two or more read commands in the message queue that access different planes of the same NVM chip into a single multi-plane read command.

[0061] According to one of the methods for optimizing the execution order of NVM interface commands according to the first to seventh aspects of the fifth aspect of this application, an eighth method for optimizing the execution order of NVM interface commands according to the fifth aspect of this application is provided, wherein the first NVM interface command is any command in the message queue.

[0062] According to a sixth aspect of this application, a method for optimizing the execution order of NVM interface commands according to the sixth aspect of this application is provided, comprising: in response to a first NVM interface command to be executed; identifying whether the first NVM interface command and a second NVM interface command that are adjacent to and follow it in the message queue can be merged; in response to the first NVM interface command and the second NVM interface command being mergeable, merging the first NVM interface command and the second NVM interface command, generating and executing a merged multiplane command to replace the first NVM interface command and the second NVM interface command.

[0063] According to the first method for optimizing the execution order of NVM interface commands according to the sixth aspect of this application, a second method for optimizing the execution order of NVM interface commands according to the sixth aspect of this application is provided to obtain the next NVM interface command to be executed.

[0064] According to the second method for optimizing the execution order of NVM interface commands according to the sixth aspect of this application, a third method for optimizing the execution order of NVM interface commands according to the sixth aspect of this application is provided. In response to the incompatibility between the first NVM interface command and the second NVM interface command, it is identified whether the first NVM interface command hits the page cache of the NVM chip; in response to the page cache hit, a command to access the page cache is generated according to the first NVM interface command, and the first NVM interface command is replaced by the command to access the page cache.

[0065] According to one of the first to third methods for optimizing the execution order of NVM interface commands according to the sixth aspect of this application, a fourth method for optimizing the execution order of NVM interface commands according to the sixth aspect of this application is provided, wherein a first NVM interface command is executed in response to a page cache miss.

[0066] According to one of the first to fourth methods for optimizing the execution order of NVM interface commands according to the sixth aspect of this application, a fifth method for optimizing the execution order of NVM interface commands according to the sixth aspect of this application is provided, wherein the NVM command processing unit merges two or more read commands in the message queue that access different planes of the same NVM chip into a single multi-plane read command.

[0067] According to one of the methods for optimizing the execution order of NVM interface commands according to the first to fifth aspects of the sixth aspect of this application, a method for optimizing the execution order of NVM interface commands according to the sixth aspect of the sixth application is provided, wherein the NVM command processing unit records the address range of data in the page cache of the NVM chip to identify whether the NVM interface command hits the page cache.

[0068] According to one of the methods for optimizing the execution order of NVM interface commands according to the sixth aspect of this application, a method for optimizing the execution order of NVM interface commands according to the sixth aspect of this application is provided in the form of a seventh method for optimizing the execution order of NVM interface commands. In response to a page cache hit, the first NVM interface command and the second NVM interface command are merged to generate and execute a merged multi-plane command for the page cache to replace the first NVM interface command and the second NVM interface command.

[0069] According to the seventh method of optimizing the execution order of NVM interface commands according to the sixth aspect of this application, an eighth method of optimizing the execution order of NVM interface commands according to the sixth aspect of this application is provided, in response to a page cache miss, fusing a first NVM interface command and a second NVM interface command, generating and executing a fused multiplane command to replace the first NVM interface command and the second NVM interface command.

[0070] According to a seventh aspect of this application, a method for optimizing the execution order of NVM interface commands according to the seventh aspect of this application is provided, comprising: in response to a first NVM interface command to be executed; identifying whether the first NVM interface command hits the page cache of the NVM chip; in response to the first NVM interface command hitting the page cache, generating and executing a command to access the page cache according to the first NVM interface command, and replacing the first NVM interface command with the command to access the page cache.

[0071] According to the first method for optimizing the execution order of NVM interface commands according to the seventh aspect of this application, a second method for optimizing the execution order of NVM interface commands according to the seventh aspect of this application is provided, which identifies whether one or more second NVM interface commands that are adjacent to and follow the first NVM interface command in the message queue hit the page cache; in response to one or more second NVM interface commands hitting the page cache, generates and executes a command to access the page cache according to the second NVM interface command, replaces each second NVM interface command that hit the page cache with the command to access the page cache; and removes the second NVM interface command.

[0072] The method for optimizing the execution order of NVM interface commands according to the first or second method of the seventh aspect of this application provides a method for optimizing the execution order of NVM interface commands according to the seventh aspect of this application, which identifies whether a first NVM interface command and one or more third NVM interface commands can be merged; in response to the first NVM interface command and the third NVM interface command being mergeable, the first NVM interface command and one or more third NVM interface commands are merged, and a multi-plane command is generated and executed to replace the merged first NVM interface command and one or more third NVM interface commands; and the first and third NVM interface commands are removed.

[0073] According to one of the first to third methods for optimizing the execution order of NVM interface commands according to the seventh aspect of this application, a fourth method for optimizing the execution order of NVM interface commands according to the seventh aspect of this application is provided, which identifies whether a first NVM interface command is a relatively more time-consuming and low-priority command, and whether one or more fourth NVM interface commands are relatively low-latency or high-priority commands; in response to the first NVM interface command having a higher priority than one or more second NVM interface commands, the first NVM interface command is executed.

[0074] According to one of the methods for optimizing the execution order of NVM interface commands according to the first to fourth aspects of the seventh aspect of this application, a method for optimizing the execution order of NVM interface commands according to the seventh aspect of this application is provided, wherein in response to the fact that the priority of the first NVM interface command is lower than the priority of one or more fourth NVM interface commands and the first NVM interface command is relatively more time-consuming, one or more fourth NVM interface commands are executed; and the fourth NVM interface command to be executed is removed.

[0075] According to the fifth method for optimizing the execution order of NVM interface commands according to the seventh aspect of this application, a sixth method for optimizing the execution order of NVM interface commands according to the seventh aspect of this application is provided to generate and execute a fifth NVM interface command, which is used to instruct the NVM chip to suspend the execution of the first NVM interface command.

[0076] According to an eighth aspect of this application, a program including program code is provided, which, when loaded into a storage device and executed on the storage device, causes the storage device to perform one of the methods for optimizing the execution order of NVM interface commands according to the second, fourth, fifth, sixth, or seventh aspect of this application. Attached Figure Description

[0077] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0078] Figure 1 A block diagram showing a storage device using existing technology;

[0079] Figure 2 This is a block diagram of a media interface controller for a control component according to an embodiment of this application;

[0080] Figure 3 This is a block diagram of a media interface controller for a control component according to an embodiment of this application;

[0081] Figure 4A This is a schematic diagram illustrating the optimized NVM interface command execution order according to an embodiment of this application;

[0082] Figure 4B This is a flowchart illustrating the optimized NVM interface command execution order according to yet another embodiment of this application;

[0083] Figure 5A This is a flowchart illustrating the process of identifying whether the NVM command execution order can be optimized, according to an embodiment of this application.

[0084] Figure 5B This is a flowchart illustrating the process of identifying whether the NVM command execution order can be optimized, according to yet another embodiment of this application.

[0085] Figure 6 This is a block diagram of a media interface controller for a control component according to another embodiment of this application;

[0086] Figure 7This is a flowchart illustrating the optimization of NVM command execution order according to another embodiment of this application;

[0087] Figure 8A This is a flowchart illustrating the optimization of the NVM command execution order according to an embodiment of this application;

[0088] Figure 8B This is a flowchart illustrating the optimization of the NVM command execution order according to yet another embodiment of this application;

[0089] Figure 8C This is a flowchart illustrating the optimization of the NVM command execution order according to another embodiment of this application;

[0090] Figure 9 This is a flowchart illustrating an embodiment of the present application for optimizing the NVM command execution order. Detailed Implementation

[0091] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0092] Figure 2 This is a block diagram of a media interface controller for a control component according to an embodiment of this application. Figure 2 The media interface controller includes a message queue 210 and an NVM command processing unit 220. Figure 2 In the embodiment, message queue 210 is used to receive messages from the control unit (see also...) Figure 1 The NVM command processing unit (NVM) receives messages from the message queue 210 to access the NVM chip. Messages from the control unit may include instructions to read, write, or delete the NVM chip, as well as instructions to read the NVM chip status, read or set NVM chip features, and may also include user-defined messages. The NVM command processing unit 220 obtains messages from the message queue 210 and, according to the instructions in the messages, sends NVM interface commands conforming to the NVM chip interface standard to the NVM chip or receives data or status from the NVM according to the NVM chip interface standard. For example, according to an embodiment of this application, the NVM command processing unit schedules NVM interface commands by, for example, executing instructions or microinstructions. The message queue 210 includes one or more message queues.

[0093] The NVM command processing unit 220 is coupled to multiple NVM chips. Figure 2In this embodiment, the NVM command processing unit 220 is coupled to four NVM chips via two channels (CH1 and CH2), each NVM chip including two LUNs. The NVM chips (NVM0 and NVM1) on channel CH1 each provide LUN 0 and LUN 1, and the NVM chips (NVM2 and NVM3) on channel CH2 each provide LUN0 and LUN1. It can be understood that the NVM interface controller can couple to more channels and access more NVM chips and more LUNs.

[0094] The media interface controller can process multiple messages from multiple message queues accessing the NVM chip in parallel. The NVM command processing unit may include multiple hardware instances or multiple threads, each instance or thread processing multiple NVM interface commands in parallel. Hardware instances or threads executing microinstruction sequences access their respective NVM chips. An executable microinstruction sequence is called a thread. Since the same microinstruction sequence has its own execution state each time it is executed, multiple threads can be created based on the same microinstruction sequence. The NVM command processing unit 220 also stores the execution state for each thread. According to embodiments of this application, threads are created or used based on the LUN to be accessed. For example, thread 1 is used to access LUN1, and / or thread 2 is used to access LUN2.

[0095] Figure 3 This is a block diagram of a media interface controller for a control component according to an embodiment of this application.

[0096] Figure 3 In this embodiment, the media interface controller includes a message queue 310 and an NVM command processing unit 320. The media interface controller is coupled to multiple NVM chips (shown as NVM 0, NVM 1, NVM 2, and NVM 3). Each NVM chip includes a page cache. To write data to an NVM chip, the media interface controller issues a programming command to the NVM chip and transmits the programmed data to the NVM chip. The NVM chip receives the data and stores it in the page cache, and also stores the data in the page cache in the NVM chip. To read data from an NVM chip, the media interface controller issues a read command or a read page cache command to the NVM chip, wherein the read page cache command reads the data from the NVM chip's page cache and transmits it to the media interface controller.

[0097] Figure 3The document also illustrates multiple NVM interface commands in the message queue. As indicated by the arrows, commands received earlier or added earlier to the message queue are listed below. For example, from message queue 310, commands to read NVM chip 0 physical address P0, write NVM chip 0 physical address P100, read NVM chip 0 physical address P1, and read NVM chip 0 physical address P50 are received sequentially. The NVM interface commands can be sent to the NVM chip in the order they are received, and the execution results can be obtained.

[0098] According to an embodiment of this application, after receiving and sending a command to read physical address P0 of NVM chip 0, the processing of a command to write physical address P100 of NVM chip 0 is temporarily suspended. In response to the data being read from physical address P0 of NVM chip 0, the data at physical address P0, and optionally adjacent data, are stored in the page cache. The NVM command processing unit 320 recognizes that a subsequent command to read physical address P1 of NVM chip 0 can be pre-scheduled and modifies the command to retrieve data from the page cache, thereby reducing the processing latency of the read command. Next, the NVM command processing unit 320 issues commands to write physical address P100 and read physical address P50 of NVM chip 0 to NVM chip 0. This optimizes the performance of processing NVM interface commands by changing the execution order of the NVM interface commands. The NVM command processing unit 320 identifies one or more NVM interface commands whose execution order can be changed, and, if necessary, changes the form of the NVM interface commands, for example, modifying a read command to a read page cache command, or merging two or more commands.

[0099] Figure 4A This is a schematic diagram illustrating the optimized NVM interface command execution order according to an embodiment of this application.

[0100] Figure 4A This demonstrates the process from a message queue (for example, see...). Figure 3 The message queue (310) receives NVM interface commands (also simply "NVM commands") and their receiving order. NVM command 0 is received first, followed by NVM command 1, NVM command 2, and NVM command 3. For example, it is optimized to execute NVM command 2 immediately after executing NVM command 0. The write pointer indicates the position where NVM commands are filled into the message queue. The read pointer (RP) indicates the position where NVM commands are retrieved from the NVM message queue. Let the read pointer RP = Base + Offset, where Base is called the base address and Offset is called the offset value.

[0101] Figure 4BThis is a flowchart illustrating the optimized NVM interface command execution order according to yet another embodiment of this application.

[0102] For example Figure 3 NVM command processing unit 320 implementation Figure 4B The processing flow is shown below. In response to the completion of an NVM command (referred to as the current NVM command) (410), it is checked whether there is an opportunity to optimize the execution order of NVM commands (412). For example, if the current NVM command reads the same or similar address as an NVM command that is not adjacent to it in the message queue, the non-adjacent NVM command is processed first.

[0103] Next, it is determined whether the value of the offset is greater than 0 (414). The offset can be provided by a register or a program variable. When the offset is greater than 0, its value indicates the number of times the execution order of NVM commands has been changed. At this point, the offset is incremented (416), and a read pointer is obtained based on the sum of the base address and the offset. The NVM command is then retrieved from the message queue and processed based on the read pointer (420). Optionally, the retrieved NVM command may also be modified, for example, by changing the read command to a command that reads the page cache.

[0104] In step 414, if the offset is not greater than 0, both the offset and the base address are incremented (418), and the NVM command is retrieved from the message queue and processed based on the sum of the base address and the offset (420).

[0105] After step 420 is executed, return to step 410 to begin processing the next NVM command.

[0106] In step 412, if it is determined that there is no further opportunity to optimize the NVM command execution order (412), it is further determined whether the offset value is greater than 0 (430) to identify whether the NVM command execution order has been optimized previously. If the offset value is greater than 0 (430), the NVM command is retrieved and processed based on the individual base address (Base) as a read pointer (432), and the base address (Base) is updated to a new value that is incremented by the base address (Base) and summed with the offset value (Offset), and the offset value (Offset) is set to 0 (434). Next, in step 420, the NVM command is retrieved from the message queue and processed based on the sum of the base address (Base) and the offset value (Offset) as a read pointer.

[0107] In step 430, if the offset value is not greater than 0 (430), the base address is incremented (436), and in step 420, the NVM command is retrieved from the message queue and processed based on the sum of the base address and the offset value as a read pointer.

[0108] As an example, see below. Figure 4A After the NVM command 0 indicated by (1) is executed, the process begins according to... Figure 4B In the processing flow, the base address (Base) is 0, and the offset value (Offset) is 0. In step 412, it is identified that the execution order can be optimized by executing NVM command 2 before NVM command 1. In step 414, the offset value (Offset) is 0, proceeding to step 418, where both the offset value (Offset) and the base address (Base) are modified to 1. In step 420, the read pointer is set to (Base + Offset) 2 to obtain and process NVM command 2. Figure 4A (As indicated by (2)). Optionally, the form of NVM command 2 can also be changed to optimize the execution of NVM command 2. For example, if NVM command 2 is a read command that hits the page cache, NVM command 2 can be replaced with a command that reads the page cache.

[0109] Next, through steps 410 and 412, it is determined that the execution order cannot be further optimized, and the process proceeds to steps 430 and 432 to process NVM command 1 based on the base address. Figure 4A In the middle, as indicated by (3). And update the base address (Base) to 3, set the offset value (Offset) to 0 (434), and obtain NVM command 3 and process it ( Figure 4A (as indicated by (4)).

[0110] Figure 5A This is a flowchart illustrating whether the execution order of NVM commands can be optimized, according to an embodiment of this application.

[0111] According to an embodiment of this application, after executing an NVM command, through... Figure 5A The processing flow identifies whether the execution order of NVM commands can be optimized. The NVM command that has just been executed is referred to as the first NVM command, for example, Figure 4A In the NVM command 0, the NVM command that is adjacent to the first NVM command in the message queue and follows the first NVM command is called the second NVM command, such as... Figure 4A In the context of NVM command 1, one or more commands in the message queue that are not adjacent to the first NVM command and follow the first NVM command are collectively referred to as the third NVM command. For example, Figure 4A The NVM command 2 or NVM command 3.

[0112] The first NVM command and the second NVM command are compared to determine whether they meet the optimization criteria (510). Meeting the optimization criteria means that the first and second NVM commands should be executed consecutively. For example, the second NVM command instructs the reading of an address that is the same as or close to the first NVM command; or the data read by the second NVM command is located in the page cache of the NVM chip due to the execution of the first NVM command; or the first and second NVM commands access different planes of the same logical unit, and the first and second NVM commands can be replaced by a single multiplane command; or the second NVM command has a higher processing priority; or the second NVM command has a higher processing priority and the NVM commands between the first and second NVM commands in the message queue have a longer processing time (e.g., erase command). The first and third NVM commands are then identified to determine whether they meet the optimization criteria using the same standard.

[0113] If the first NVM command and the second NVM command do not meet the optimization condition (510), but the first NVM command and the third NVM command meet the optimization condition (520), then the execution order of the NVM commands that can be optimized is identified (530). For the first NVM command that has just been executed, the execution order can be optimized, which means that the second NVM command that is adjacent to it will not be executed next, but the third NVM command that is not adjacent to the first NVM command will be executed first.

[0114] Figure 5B This is a flowchart illustrating whether the execution order of NVM commands can be optimized, according to yet another embodiment of this application.

[0115] according to Figure 5B In one embodiment, after executing an NVM command (the first NVM command), through... Figure 5B The processing flow identifies whether the execution order of NVM commands can be optimized. If the first NVM command and its adjacent second NVM command satisfy the optimization condition (540), the offset value is further obtained. If the offset value is greater than 0 (542), an optimized execution order is identified (544). This allows for optimization in... Figure 4B In this embodiment, the processing flow is executed via the path of steps 412, 414 and 416.

[0116] If the offset value is not greater than 0 in step 542 (542), an execution order that cannot be optimized is identified (544).

[0117] If step 540 identifies that the first NVM command and its adjacent second NVM command do not meet the optimization conditions, it further identifies whether the first NVM command and its non-adjacent third NVM command meet the optimization conditions (550). The third NVM command and the first NVM command may be separated by one or more NVM commands in the message queue. If the first NVM command and its non-adjacent third NVM command meet the optimization conditions (550), an optimizable execution order is identified (552); otherwise, a non-optimizable execution order is identified (554).

[0118] Figure 6 This is a block diagram of a media interface controller for a control component according to another embodiment of this application.

[0119] Figure 6 In this embodiment, the media interface controller includes a message queue 610 and an NVM command processing unit 620. The media interface controller is coupled to multiple NVM chips (shown as NVM 0, NVM 1, NVM 2, and NVM 3). Each NVM chip includes a page cache. The logical units of each NVM chip include multiple planes. Figure 6 In this context, the planes are represented as P0 and P1. The NVM chip provides a multi-plane command to access addresses from two or more planes in a single multi-plane command.

[0120] Figure 6 The document also illustrates multiple NVM interface commands in the message queue. As indicated by the arrows, commands received earlier or added earlier to the message queue are listed below. For example, from message queue 610, the following commands are received sequentially: read NVM chip plane 0 (PL0) physical address P0, write NVM chip plane 0 (PL0) physical address P100, read NVM chip plane 0 (PL1) physical address P0, read NVM chip plane 0 (PL0) physical address P50, and read NVM chip plane 0 (PL0) physical address P1.

[0121] According to an embodiment of this application, the command to read physical address P0 of NVM chip plane 0 (PL0) and the command to read physical address P0 of NVM chip plane 1 (PL1) are merged to generate a single multi-plane command to replace the aforementioned two commands, thereby reducing the number of NVM commands executed and improving the performance of the solid-state storage device. Furthermore, it is also identified that the data of the command to read physical address P1 of NVM chip plane 0 (PL0) is loaded into the page cache of NVM chip 0 along with the execution of the multi-plane command. The execution order is also optimized: the command to read physical address P1 of NVM chip plane 0 (PL0) is executed first, and this command is replaced by a command to read the page cache. Next, the commands to write physical address P100 of NVM chip plane 0 (PL0) and read physical address P50 of NVM chip plane 0 (PL0) are executed.

[0122] Figure 7 This is a flowchart illustrating the optimized NVM command execution order according to another embodiment of this application.

[0123] For example Figure 6 NVM command processing unit 620 implementation Figure 7 The processing flow is shown below. In response to an NVM command to be executed (referred to as the first NVM command) (710), it is determined whether the first NVM command and a second NVM command that is adjacent to and follows it in the message queue can be merged (712). For example, it is determined whether the first NVM command and the second NVM command can be replaced by a single multiplane command. If the first NVM command and the second NVM command can be merged (712), the first NVM command and the second NVM command are merged (715), for example, a multiplane command is generated to replace the first NVM command and the second NVM command. If the first NVM command and the second NVM command cannot be merged (712), the first NVM command is executed (714).

[0124] In response to the completion of the first NVM command, the subsequent processing flow is similar to... Figure 4B The processing flow begins with step 410.

[0125] The system checks if there is an opportunity to optimize the NVM command execution order (716). If there is an opportunity to optimize the NVM command execution order, it then checks if the value of the offset is greater than 0 (718). If the offset is greater than 0, the offset is incremented (720), while the base address remains unchanged. A read pointer is obtained based on the sum of the base address and the offset, and an NVM command is retrieved from the message queue and processed based on the read pointer (724). Optionally, the retrieved NVM command may also be modified, for example, by modifying the read command to read the page cache command.

[0126] In step 718, if the offset value is not greater than 0, both the offset value and the base address are incremented (722), and the NVM command is retrieved from the message queue and processed based on the sum of the base address and the offset value as a read pointer (724).

[0127] After step 724 is executed, return to step 710 to begin processing the next NVM command.

[0128] In step 716, if it is determined that there is no further opportunity to optimize the NVM command execution order, it is further determined whether the offset value is greater than 0 (730) to identify whether the NVM command execution order has been optimized previously. If the offset value is greater than 0 (730), the NVM command is retrieved and processed based on the individual base address (Base) as a read pointer (732), and the base address (Base) is updated to a new value that is incremented by the base address (Base) and summed with the offset value (Offset), and the offset value (Offset) is set to 0 (734). Next, in step 724, the NVM command is retrieved from the message queue and processed based on the sum of the base address (Base) and the offset value (Offset) as a read pointer.

[0129] In step 730, if the offset value is not greater than 0, the base address is incremented (736), and in step 724, the NVM command is retrieved from the message queue and processed based on the sum of the base address and the offset value as a read pointer.

[0130] Figures 8A-8C This is a flowchart illustrating the optimized NVM command execution order according to several embodiments of this application. For example... Figure 6 NVM command processing unit 620 implementation Figures 8A-8C The processing flow is shown below.

[0131] See Figure 8A In response to an NVM command to be executed (referred to as the first NVM command) (810), the unit identifies whether the first NVM command hits the page cache (812). According to an embodiment of this application, the NVM command processing unit records the address range of data in the page cache of each NVM chip to identify whether the NVM command can hit the page cache. If the page cache is hit (812), a command to access the page cache is generated according to the first NVM command, and the first NVM command is replaced by the command to access the page cache (814). Then, the process returns to step 810 to continue obtaining the next NVM command to be executed.

[0132] If a page cache miss occurs (812), it is determined whether the first NVM command and an adjacent NVM command can be merged (816). If the first NVM command and an adjacent NVM command can be merged (816), the first NVM command and the adjacent NVM command are merged, and a multi-plane command is generated and executed to replace the first NVM command and the adjacent NVM command (818). Then, the process returns to step 810 to continue obtaining the next NVM command to be executed.

[0133] If the first NVM command is identified as not being fused with the adjacent NVM command (816), the first NVM command is executed (820), and the process returns to step 810 to continue obtaining the next NVM command to be executed.

[0134] Optionally, if the first NVM command is a read command, in step 820, in response to the execution of the first NVM command, the address of the data in the page cache is also marked to identify whether subsequent NVM commands will hit the page cache.

[0135] See Figure 8B In response to an NVM command to be executed (referred to as the first NVM command) (830), it is determined whether the first NVM command can be merged with an adjacent NVM command (832). If the first NVM command can be merged with the adjacent NVM command (832), the first NVM command and the adjacent NVM command are merged, and a multi-plane command is generated and executed to replace the first NVM command and the adjacent NVM command (834), and the process returns to step 830 to continue obtaining the next NVM command to be executed.

[0136] If the first NVM command is identified as not being merging with an adjacent NVM command (832), then it is determined whether the first NVM command hits the page cache (836). If the page cache is hit (836), a command to access the page cache is generated based on the first NVM command, and the first NVM command is replaced with the command to access the page cache (838). Then, step 830 is returned to continue obtaining the next NVM command to be executed. If the page cache is not hit (836), the first NVM command is executed (840), and step 830 is returned to continue obtaining the next NVM command to be executed.

[0137] See Figure 8CIn response to an NVM command to be executed (referred to as the first NVM command) (860), if the first NVM command can be merged with an adjacent NVM command (862), it is further identified whether the first NVM command hits the page cache (864). If the page cache is hit (864), the first NVM command is merged with the adjacent NVM command, and a multi-plane command for page cache is generated and executed to replace the first NVM command and the adjacent NVM command (868), and the process returns to step 860 to continue obtaining the next NVM command to be executed. If the page cache is not hit (864), the first NVM command is merged with the adjacent NVM command, and a multi-plane command for page cache is generated and executed to replace the first NVM command and the adjacent NVM command (866), and the process returns to step 860.

[0138] If the first NVM command is identified as not being fused with an adjacent NVM command (862), it is determined whether the first NVM command hits the page cache (870). If the page cache is hit (870), a command to access the page cache is generated based on the first NVM command, and the first NVM command is replaced with the command to access the page cache (872). Then, the process returns to step 860. If the page cache is not hit (870), the first NVM command is executed (874), and the process returns to step 860 to continue obtaining the next NVM command to be executed.

[0139] Figure 9 This is a flowchart illustrating the optimization of NVM command execution order according to another embodiment of this application. For example... Figure 6 NVM command processing unit 620 implementation Figure 9 The processing flow is shown below.

[0140] Optionally, the NVM command processing unit 620 retrieves an NVM command from the message queue 610 and stores it in a cache. It then retrieves the NVM command to be executed (referred to as the first NVM command) (910). Optionally, it identifies whether the first NVM command hits the page cache (920). If the first NVM command hits the page cache (920), it generates a command to access the page cache based on the first NVM command and replaces the first NVM command with the command to access the page cache (925). Finally, it returns to step 910 to continue retrieving the next NVM command to be executed.

[0141] If the first NVM command misses the page cache (920), optionally, one or more second NVM commands may still be identified as having hit the page cache (930). The second NVM command is the NVM command that follows the first NVM command in the cache. If one or more second NVM commands hit the page cache (930), a command to access the page cache is generated based on the second NVM commands, and each second NVM command that hit the page cache is replaced with the command to access the page cache (935). The executed NVM command is also removed from the cache. Then, the process returns to step 910 to retrieve the next NVM command to be executed.

[0142] If the second NVM command misses the page cache (930), optionally, it is still possible to identify whether the first NVM command and one or more second NVM commands can be merged (940). If the first NVM command and one or more second NVM commands can be merged (940), the first NVM command and one or more second NVM commands are merged, and a multi-plane command, for example, is generated and executed to replace the merged first NVM command and one or more second NVM commands (945). The merged NVM command is also removed from the cache. And the process returns to step 910 to continue obtaining the next NVM command to be executed.

[0143] If the first NVM command cannot be merged with one or more second NVM commands (940), optionally, the first NVM command is identified as a relatively more time-consuming or lower-priority command, while one or more second NVM commands are identified as relatively low-latency or high-priority commands (950). If the result of step 950 is true, one or more second NVM commands are executed (955). The executed NVM command is also removed from the cache. And the process returns to step 910 to continue retrieving the next NVM command to be executed. If the result of step 950 is false, the first NVM command is executed (960), and the process returns to step 910 to continue retrieving the next NVM command to be executed.

[0144] Optionally, if the result identified in step 950 is true, a first NVM command is executed, followed by the generation and execution of a third NVM command to instruct the NVM chip to abort the execution of the first NVM command. One or more second NVM commands are also executed (955). The executed second NVM commands are also removed from the cache. The aborted first NVM command can be resumed.

[0145] Optionally, it is also ensured that the first NVM command does not take too long to be executed.

[0146] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for optimizing the execution order of NVM interface commands, characterized in that, include: The first NVM interface command to be executed is obtained from the command queue of the media interface controller. The first NVM interface command conforms to the NVM chip interface standard and carries the physical address of the NVM chip. Identify whether the first NVM interface command hits the NVM chip's page cache; In response to a page cache hit, a command to access the page cache is generated based on the first NVM interface command, and the first NVM interface command is replaced with the command to access the page cache. The condition for a page cache hit is that the first NVM interface command is a read command, and an NVM interface command is executed before the first NVM interface command, so that the data to be read by the first NVM interface command is retained in the page cache. This NVM interface command is either a write command or a read command, and this NVM interface command and the first NVM interface command are executed consecutively. In response to a page cache miss, determine whether the first NVM interface command and the second NVM interface command that are adjacent to and follow it in the message queue can be merged; In response to the possibility of merging the first NVM interface command and the second NVM interface command, the first NVM interface command and the second NVM interface command are merged to generate and execute the merged multiplane command to replace the first NVM interface command and the second NVM interface command; In response to the incompatibility between the first NVM interface command and the second NVM interface command, the first NVM interface command is executed. In response to the completion of the first NVM interface command, check whether the execution order of NVM interface commands can be optimized; If the execution order of NVM interface commands can be optimized, check if the offset value is greater than 0; if the offset value is greater than 0, increment the offset value; obtain a read pointer based on the sum of the base address and the offset value, and retrieve and process the NVM interface command from the message queue based on the read pointer; where the offset value indicates the number of times the execution order of NVM interface commands has been changed; if the offset value is not greater than 0, increment both the offset value and the base address, and use the sum of the base address and the offset value as the read pointer to retrieve and process the NVM interface command from the message queue. If the NVM interface command execution order cannot be optimized, check if the offset value is greater than 0; if the offset value is greater than 0, use the base address as a read pointer to obtain and process the NVM interface command; increment the base address and sum it with the offset value to obtain the new value of the base address, and set the offset value to 0; use the sum of the base address and the offset value as a read pointer to obtain and process the NVM interface command; if the offset value is not greater than 0, increment the base address and use the sum of the base address and the offset value as a read pointer to obtain and process the NVM interface command.

2. The method as described in claim 1, characterized in that, The method further includes: The NVM command processing unit merges two or more read commands from different planes of the same NVM chip in the message queue into a single multi-plane read command.

3. A method for optimizing the execution order of NVM interface commands, characterized in that, include: In response to the pending execution of a first NVM interface command, wherein the first NVM interface command is located in the command queue of the media interface controller, wherein the first NVM interface command conforms to the NVM chip interface standard and carries the physical address of the NVM chip; Identify whether the first NVM interface command and the second NVM interface command that are adjacent to and follow it in the message queue can be merged; In response to the fusion of the first NVM interface command and the second NVM interface command, the first NVM interface command and the second NVM interface command are fused together, and a fused multi-plane command is generated and executed to replace the first NVM interface command and the second NVM interface command. The first NVM interface command and the second NVM interface command access different planes of the same NVM chip. In response to the incompatibility between the first NVM interface command and the second NVM interface command, it is determined whether the first NVM interface command hits the page cache of the NVM chip; In response to a page cache hit, a command to access the page cache is generated based on the first NVM interface command, and the first NVM interface command is replaced with the command to access the page cache. The condition for a page cache hit is that the first NVM interface command is a read command, and an NVM interface command is executed before the first NVM interface command, so that the data to be read by the first NVM interface command is retained in the page cache. This NVM interface command is either a write command or a read command, and this NVM interface command and the first NVM interface command are executed consecutively. In response to a page cache miss, execute the first NVM interface command; In response to the completion of the first NVM interface command, check whether the execution order of NVM interface commands can be optimized; If the execution order of NVM interface commands can be optimized, check if the offset value is greater than 0; if the offset value is greater than 0, increment the offset value; obtain a read pointer based on the sum of the base address and the offset value, and retrieve and process the NVM interface command from the message queue based on the read pointer; where the offset value indicates the number of times the execution order of NVM interface commands has been changed; if the offset value is not greater than 0, increment both the offset value and the base address, and use the sum of the base address and the offset value as the read pointer to retrieve and process the NVM interface command from the message queue. If the NVM interface command execution order cannot be optimized, check if the offset value is greater than 0; if the offset value is greater than 0, use the base address as a read pointer to obtain and process the NVM interface command; increment the base address and sum it with the offset value to obtain the new value of the base address, and set the offset value to 0; use the sum of the base address and the offset value as a read pointer to obtain and process the NVM interface command; if the offset value is not greater than 0, increment the base address and use the sum of the base address and the offset value as a read pointer to obtain and process the NVM interface command.

4. The method as described in claim 3, characterized in that, The method further includes: The NVM command processing unit records the address range of data in the NVM chip's page cache to identify whether the NVM interface command hits the page cache.

5. A method for optimizing the execution order of NVM interface commands, characterized in that, include: In response to the pending execution of a first NVM interface command, wherein the first NVM interface command is located in the command queue of the media interface controller, the first NVM interface command conforms to the NVM chip interface standard, and carries the physical address of the NVM chip; Identify whether the first NVM interface command hits the NVM chip's page cache; In response to a page cache hit by a first NVM interface command, a command to access the page cache is generated and executed based on the first NVM interface command, replacing the first NVM interface command. The page cache hit condition is that the first NVM interface command is a read command, and an NVM interface command is executed before the first NVM interface command, so that the data to be read by the first NVM interface command is retained in the page cache. This NVM interface command is either a write command or a read command, and this NVM interface command and the first NVM interface command are executed consecutively. In response to a page cache miss, determine whether the first NVM interface command and the second NVM interface command that are adjacent to and follow it in the message queue can be merged; In response to the possibility of merging the first NVM interface command and the second NVM interface command, the first NVM interface command and the second NVM interface command are merged to generate and execute the merged multiplane command to replace the first NVM interface command and the second NVM interface command; In response to the incompatibility between the first NVM interface command and the second NVM interface command, the first NVM interface command is executed. In response to the completion of the first NVM interface command, check whether the execution order of NVM interface commands can be optimized; If the execution order of NVM interface commands can be optimized, check if the offset value is greater than 0; if the offset value is greater than 0, increment the offset value; obtain a read pointer based on the sum of the base address and the offset value, and retrieve and process the NVM interface command from the message queue based on the read pointer; where the offset value indicates the number of times the execution order of NVM interface commands has been changed; if the offset value is not greater than 0, increment both the offset value and the base address, and use the sum of the base address and the offset value as the read pointer to retrieve and process the NVM interface command from the message queue. If the NVM interface command execution order cannot be optimized, check if the offset value is greater than 0; if the offset value is greater than 0, use the base address as a read pointer to obtain and process the NVM interface command; increment the base address and sum it with the offset value to obtain the new value of the base address, and set the offset value to 0; use the sum of the base address and the offset value as a read pointer to obtain and process the NVM interface command; if the offset value is not greater than 0, increment the base address and use the sum of the base address and the offset value as a read pointer to obtain and process the NVM interface command.

6. The method as described in claim 5, characterized in that, The method further includes: Identify whether one or more second NVM interface commands that are adjacent to and follow the first NVM interface command in the message queue have hit the page cache; In response to one or more second NVM interface commands hitting the page cache, generate and execute commands to access the page cache based on the second NVM interface commands, replace each second NVM interface command that hit the page cache with the commands to access the page cache, and remove the second NVM interface commands.

7. A media interface controller, characterized in that, include: The message queue and the NVM command processing unit are coupled together. The NVM command processing unit is also coupled to multiple NVM chips. The message queue is used to receive messages from multiple planes of the logical units accessing the NVM chip. The NVM command processing unit obtains information from the message queue, generates NVM interface commands according to the instructions in the messages, and sends them to the NVM chip. The NVM command processing unit merges NVM interface commands. Merging NVM interface commands means merging two or more adjacent NVM interface commands from different planes in the message queue that access the same NVM chip into a multi-plane command. The NVM interface commands conform to the NVM chip interface standard and carry the physical address of the NVM chip. The NVM command processing unit responds to the incompatibility between the first NVM interface command and the second NVM interface command by identifying whether the first NVM interface command hits the page cache of the NVM chip. In response to a page cache hit, it generates a command to access the page cache based on the first NVM interface command, replacing the first NVM interface command with the page cache access command. The page cache hit condition is that the first NVM interface command is a read command, and before executing the first NVM interface command, an NVM interface command is executed, causing the data to be read by the first NVM interface command to be retained in the page cache. This NVM interface command is either a write command or a read command, and this NVM interface command and the first NVM interface command are executed consecutively. In response to a page cache miss, execute the first NVM interface command; In response to the completion of the first NVM interface command, check whether the execution order of NVM interface commands can be optimized; If the execution order of NVM interface commands can be optimized, check if the offset value is greater than 0; if the offset value is greater than 0, increment the offset value; obtain a read pointer based on the sum of the base address and the offset value, and retrieve and process the NVM interface command from the message queue based on the read pointer; where the offset value indicates the number of times the execution order of NVM interface commands has been changed; if the offset value is not greater than 0, increment both the offset value and the base address, and use the sum of the base address and the offset value as the read pointer to retrieve and process the NVM interface command from the message queue. If the NVM interface command execution order cannot be optimized, check if the offset value is greater than 0; if the offset value is greater than 0, use the base address as a read pointer to obtain and process the NVM interface command; increment the base address and sum it with the offset value to obtain the new value of the base address, and set the offset value to 0; use the sum of the base address and the offset value as a read pointer to obtain and process the NVM interface command; if the offset value is not greater than 0, increment the base address and use the sum of the base address and the offset value as a read pointer to obtain and process the NVM interface command.

8. The media interface controller as described in claim 7, characterized in that, The NVM command processing unit merges two or more read commands from different planes of the same NVM chip in the message queue into a single multi-plane read command.

9. The media interface controller as described in claim 8, characterized in that, In response to the recognition that the data accessed by the first read command in the message queue is loaded into the page cache of the NVM chip as the single multiplane read command is executed, the first read command is also executed first.

Images