Organic light emitting diode display device

Abstract

An organic light emitting diode display device is provided. The organic light emitting diode display device includes a substrate, a driving transistor, a switching transistor, a first light absorbing layer, an organic insulating layer and a sub-pixel structure. The substrate includes a first region and a second region. The driving transistor is arranged in the first region on the substrate. The switching transistor is arranged in the second region on the substrate and includes a metal oxide-based semiconductor. The first light absorbing layer is arranged on the driving transistor and the switching transistor. The organic insulating layer is directly arranged on the first light absorbing layer. The sub-pixel structure is arranged on the organic insulating layer.

Description

Technical Field

[0001] The exemplary embodiments generally relate to an organic light emitting diode display device and a method of manufacturing the same. More specifically, the exemplary embodiments relate to an organic light emitting diode display device including different types of transistors and a method of manufacturing the same. Background Art

[0002] Flat panel display devices are widely used as display devices for replacing cathode ray tube display devices due to their light weight and thin characteristics. Such flat panel display devices may include liquid crystal display devices and organic light emitting diode display devices.

[0003] Recently, an organic light emitting diode display device including both a silicon-based semiconductor element and a metal oxide-based semiconductor element is being developed. More specifically, for example, in a sub-pixel circuit of an organic light emitting diode display device, a silicon-based semiconductor can be used as a driving transistor, and a metal oxide-based semiconductor can be used as a switching transistor. Summary of the invention

[0004] In an organic light emitting diode display device in which a driving transistor includes a silicon-based semiconductor and a switching transistor includes a metal oxide-based semiconductor, light is incident on the metal oxide-based semiconductor. For example, external light penetrating into the organic light emitting diode display device may be transmitted through a sub-pixel circuit, or a portion of light emitted from a light emitting layer may be reflected from an upper electrode and transmitted through the sub-pixel circuit. Therefore, the transmitted light may be incident on the metal oxide-based semiconductor. When light is incident on the metal oxide-based semiconductor, the metal oxide-based semiconductor may be rapidly degraded, and the characteristics of the switching transistor including the metal oxide-based semiconductor may be changed.

[0005] An exemplary embodiment provides an organic light emitting diode display device including transistors of different types.

[0006] An exemplary embodiment provides a method of manufacturing an organic light emitting diode display device including transistors of different types.

[0007] According to an exemplary embodiment, an organic light emitting diode display device includes a substrate, a driving transistor, a switching transistor, a first light absorbing layer, an organic insulating layer and a sub-pixel structure. The substrate includes a first region and a second region. In such an embodiment, the driving transistor is arranged in the first region on the substrate. In such an embodiment, the switching transistor is arranged in the second region on the substrate and includes a metal oxide-based semiconductor. In such an embodiment, the first light absorbing layer is arranged on the driving transistor and the switching transistor. In such an embodiment, the organic insulating layer is directly arranged on the first light absorbing layer. In such an embodiment, the sub-pixel structure is arranged on the organic insulating layer.

[0008] In exemplary embodiments, each of the driving transistor and the switching transistor may have a top gate structure.

[0009] In an exemplary embodiment, the driving transistor may include: a first active layer including a first source region, a first drain region and a first channel region; a first gate electrode overlapping the first channel region on the first active layer; a first source electrode disposed on the first gate electrode and connected to the first source region; and a first drain electrode disposed on the first gate electrode and connected to the first drain region. In such an embodiment, the first active layer may include a silicon-based semiconductor.

[0010] In an exemplary embodiment, the switch transistor may include: a second active layer including a second source region, a second drain region, and a second channel region; a second gate electrode overlapping the second channel region on the second active layer; a second source electrode disposed on the second gate electrode and connected to the second source region; and a second drain electrode disposed on the second gate electrode and connected to the second drain region. In such an embodiment, the second active layer may include a metal oxide-based semiconductor.

[0011] In an exemplary embodiment, the organic light emitting diode display device may further include an insulating pattern disposed between the second active layer and the second gate electrode.

[0012] In an exemplary embodiment, the organic light emitting diode display device may further include: a first gate insulating layer disposed on the substrate to cover the first active layer in the first region; and a second gate insulating layer disposed on the first gate insulating layer to cover the first gate electrode in the first region.

[0013] In exemplary embodiments, the driving transistor may further include a gate electrode pattern overlapping the first gate electrode on the second gate insulating layer.

[0014] In an exemplary embodiment, the organic light emitting diode display device may further include: a first insulating interlayer disposed on the second gate insulating layer to cover the gate electrode pattern in the first region; and a second insulating interlayer disposed on the first insulating interlayer to cover the second active layer and the second gate electrode in the second region.

[0015] In exemplary embodiments, the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode may be disposed on the second insulating interlayer.

[0016] In an exemplary embodiment, the organic light emitting diode display device may further include a protective insulating layer disposed on the second insulating interlayer to cover the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode.

[0017] In an exemplary embodiment, the organic light emitting diode display device may further include a planarization layer disposed on the protective insulating layer.

[0018] In an exemplary embodiment, the organic light emitting diode display device may further include a second light absorbing layer disposed between the protective insulating layer and the planarization layer.

[0019] In an exemplary embodiment, the sub-pixel structure may include: a lower electrode; a light emitting layer disposed on the lower electrode; and an upper electrode disposed on the light emitting layer.

[0020] In an exemplary embodiment, the organic light emitting diode display device may further include a connection pattern disposed between the planarization layer and the first light absorbing layer. In such an embodiment, the connection pattern may be electrically connected to the lower electrode through a contact hole defined by a portion of the first light absorbing layer and a portion of the organic insulating layer.

[0021] In an exemplary embodiment, the substrate may include: a first organic layer; a barrier layer disposed on the first organic layer; and a second organic layer disposed on the barrier layer.

[0022] In an exemplary embodiment, the organic light emitting diode display device may further include a buffer layer disposed on the substrate between the substrate and the driving transistor and the switching transistor.

[0023] In an exemplary embodiment, the organic light emitting diode display device may further include a thin film encapsulation structure disposed on the sub-pixel structure. In such an embodiment, the thin film encapsulation structure may include a first thin film encapsulation layer, a second thin film encapsulation layer, and a third thin film encapsulation layer. In such an embodiment, the first thin film encapsulation layer may include a flexible inorganic material. In such an embodiment, the second thin film encapsulation layer may be disposed on the first thin film encapsulation layer and may include a flexible organic material. In such an embodiment, the third thin film encapsulation layer may be disposed on the second thin film encapsulation layer and may include a flexible inorganic material.

[0024] According to an exemplary embodiment, a method for manufacturing an organic light emitting diode display device includes: preparing a substrate including a first region and a second region; disposing a driving transistor in the first region on the substrate; disposing a switching transistor including a metal oxide-based semiconductor in the second region on the substrate; disposing a planarization layer on the driving transistor and the switching transistor; disposing a connection pattern on the planarization layer; disposing a light absorbing layer on the planarization layer to cover the connection pattern; disposing an organic insulating layer having a first thickness on the light absorbing layer; forming a first contact hole through the organic insulating layer by performing an exposure process using a mask, the first contact hole exposing a portion of a top surface of the light absorbing layer; forming a second contact hole through the light absorbing layer by performing a dry etching process, the second contact hole exposing a portion of a top surface of the connection pattern through the first contact hole; and disposing a sub-pixel structure on the light absorbing layer.

[0025] In exemplary embodiments, during the dry etching process, the first thickness of the organic insulating layer may be reduced to a second thickness.

[0026] In an exemplary embodiment, the sub-pixel structure may include: a lower electrode; a light emitting layer disposed on the lower electrode; and an upper electrode disposed on the light emitting layer. In such an embodiment, the connection pattern may be electrically connected to the lower electrode through the first contact hole and the second contact hole.

[0027] In an exemplary embodiment of the invention, the organic light emitting diode display device includes a light absorbing layer so that the organic light emitting diode display device can block light incident on the second active layer. Therefore, the organic light emitting diode display device can protect the second active layer including the oxide-based semiconductor and can maintain the characteristics of the switching transistor.

[0028] In an exemplary embodiment of a method of manufacturing an organic light emitting diode display device, by forming an organic insulating layer having a first contact hole on the light absorbing layer, a second contact hole can be formed in the light absorbing layer. Therefore, the organic light emitting diode display device includes a light absorbing layer so that light incident on the second active layer can be blocked. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The exemplary embodiments may be understood in more detail through the following description taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a plan view showing an organic light emitting diode display device according to an exemplary embodiment of the invention;

[0031] Figure 2 is shown electrically connected to Figure 1 A block diagram of external devices of an organic light emitting diode display device;

[0032] Figure 3 It shows that the setting Figure 1 a circuit diagram of a sub-pixel circuit and an organic light emitting diode in a sub-pixel circuit region;

[0033] Figure 4 yes Figure 1 A cross-sectional view of an organic light emitting diode display device taken along line II';

[0034] Figures 5 to 16 is a cross-sectional view illustrating a method of manufacturing an organic light emitting diode display device according to an exemplary embodiment of the invention; and

[0035] Fig.17 is a cross-sectional view showing an organic light emitting diode display device according to an alternative exemplary embodiment of the invention. DETAILED DESCRIPTION

[0036] The invention will now be described more fully hereinafter with reference to the accompanying drawings, in which various embodiments are shown. However, the invention may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art. The same reference numerals represent the same elements throughout.

[0037] It will be understood that when an element is referred to as being “on” another element, the element can be directly on the other element or intervening elements may be located therebetween. In contrast, when an element is referred to as being “directly on” another element, there are no intervening elements present.

[0038] It will be understood that, although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings herein, the first "element", "component", "region", "layer" or "part" discussed below may be named as the second element, component, region, layer or part.

[0039] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be limited. As used herein, unless the content clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "the (the)" are intended to include plural forms including "at least one (kind / person)". "Or (or)" means "and / or". "At least one (kind / person) of A and B" means "A and / or B". As used herein, the term "and / or" includes any combination and all combinations of one or more of the relevant listed items. It will also be understood that when the term "includes" and / or its variations or "includes" and / or its variations are used in this specification, it is explained that there are stated features, regions, wholes, steps, operations, elements and / or components, but it is not excluded that there are or add one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0040] In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used here to describe the relationship of one element to another element as shown in the figure. It will be understood that relative terms are intended to include different orientations of the device in addition to the orientation depicted in the figure. For example, if the device in a figure is turned over, the element described as being on the "lower" side of the other element will then be oriented to be on the "upper" side of the other element. Therefore, depending on the specific orientation of the figure, the exemplary term "lower" can include both "lower" and "upper" orientations. Similarly, if the device in a figure is turned over, the element described as being "below" or "under" the other element will then be oriented to be "above" the other element. Therefore, the exemplary terms "below..." or "under..." can include both upper and lower orientations.

[0041] As used herein, "about" or "approximately" is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art taking into account the measurements in question and errors associated with measurement of the particular quantity (i.e., limitations of the measurement system).

[0042] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that terms (such as those defined in common dictionaries) should be interpreted as having a meaning consistent with their meaning in the relevant art and the context of the disclosure, and will not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0043] Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of rationalized embodiments. As such, variations in the shapes of the illustrations, such as those caused by manufacturing techniques and / or tolerances, are to be expected. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions as shown herein, but will include shape deviations, such as those caused by manufacturing. For example, a region shown or described as flat may typically have rough features and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the regions, and are not intended to limit the scope of the claims.

[0044] Hereinafter, embodiments of the invention will be explained in detail with reference to the accompanying drawings.

[0045] Figure 1 is a plan view showing an organic light emitting diode display device according to an exemplary embodiment of the invention, Figure 2 is shown electrically connected to Figure 1 A block diagram of external devices of an organic light emitting diode display device.

[0046] Reference Figure 1 and Figure 2 , an organic light emitting diode ("OLED") display device 100 (eg, Figure 4 An exemplary embodiment of a substrate 110 of the OLED display device 100 may include a display area 10 and a pad (or "pad") area 60. The display area 10 may include a light-emitting area 30 including a plurality of sub-pixel circuit areas 20 and a peripheral area 40 surrounding the light-emitting area 30, wherein the plurality of sub-pixel circuit areas 20 may be arranged in the light-emitting area 30 in a first direction D1 and a second direction D2, wherein the first direction D1 is parallel to the top surface of the OLED display device 100, and the second direction D2 is orthogonal to the first direction D1. For example, in an exemplary embodiment, Figure 3 Sub-pixel circuits (e.g., Figure 4 The driving transistor 250 and the switching transistor 255 of the OLED may be provided in each of the sub-pixel circuit regions 20, and the OLED (eg, Figure 4 The sub-pixel structure 200 may be disposed on the sub-pixel circuit. An image may be displayed in the display area 10 through the sub-pixel circuit and the OLED.

[0047] For example, in one exemplary embodiment, a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit may be disposed in the sub-pixel circuit region 20. The first sub-pixel circuit may be connected to a first OLED for emitting red light, the second sub-pixel circuit may be connected to a second OLED for emitting green light, and the third sub-pixel circuit may be connected to a third OLED for emitting blue light.

[0048] In an exemplary embodiment, the first OLED may be overlapped with the first sub-pixel circuit, the second OLED may be overlapped with the second sub-pixel circuit, and the third OLED may be overlapped with the third sub-pixel circuit. Optionally, the first OLED may be overlapped with a portion of the first sub-pixel circuit and a portion of other sub-pixel circuits different from the first sub-pixel circuit, the second OLED may be overlapped with a portion of the second sub-pixel circuit and a portion of other sub-pixel circuits different from the second sub-pixel circuit, and the third OLED may be overlapped with a portion of the third sub-pixel circuit and a portion of other sub-pixel circuits different from the third sub-pixel circuit. Here, "overlapping" may mean "overlapping in the thickness direction of the OLED display device when viewed from a plan view". For example, in an exemplary embodiment, the first to third OLEDs may be arranged based on the following schemes: an RGB stripe scheme, in which red OLEDs, green OLEDs, and blue OLEDs having the same size are arranged in sequence; an S stripe scheme, including a blue OLED having a relatively large area; a WRGB scheme, further including a white OLED; a PenTile scheme, in which an RG-GB pattern is repeatedly arranged; and the like.

[0049] In such an embodiment, at least one drive transistor, at least one switch transistor, at least one capacitor, etc. may be disposed in each of the sub-pixel circuit regions 20. For example, in one exemplary embodiment, a single drive transistor (e.g., Figure 3 The first transistor TR1) and six switch transistors (eg, Figure 3 2 to 7 transistors TR2, TR3, TR4, TR5, TR6, and TR7), a single storage capacitor (eg, Figure 3 A storage capacitor CST) or the like may be provided in each of the sub-pixel circuit regions 20.

[0050] In an exemplary embodiment, if Figure 1 As shown in , each of the display region 10, the peripheral region 40, and the sub-pixel circuit region 20 may have a rectangular planar shape, but the shape is not limited thereto. For example, in an exemplary embodiment, when viewed from a top view or a plan view in the thickness direction of the OLED display device 100, each of the display region 10, the peripheral region 40, and the sub-pixel circuit region 20 may have a triangular shape, a diamond shape, a polygonal shape, a circular shape, a track shape, or an elliptical shape.

[0051] In such an embodiment, a plurality of wirings may be disposed in the peripheral region 40. For example, in one exemplary embodiment, the wirings may include data signal wirings, gate signal wirings, light emission control signal wirings, gate initialization signal wirings, initialization voltage wirings, power supply voltage wirings, etc. The wirings may extend from the peripheral region 40 to the light emission region 30 and may be electrically connected to the sub-pixel circuits and the OLED. In such an embodiment, a gate driver, a data driver, etc. may be disposed in the peripheral region 40.

[0052] The pad region 60 may be located on one side of the display region 10, and a pad electrode 470 electrically connected to the external device 101 may be provided in the pad region 60. In such an embodiment, the pad electrode 470 may electrically connect the external device 101 to the sub-pixel circuit. In an exemplary embodiment, the OLED display device 100 may have a constant width in a lateral direction (e.g., the second direction D2).

[0053] In an alternative exemplary embodiment, a bending region may be defined between the pad region 60 and the display region 10. The connection electrode may be disposed in the bending region, and the bending region may be bent with respect to an axis relative to the second direction D2 so that the pad region 60 is located on the bottom surface of the OLED display device 100. In such an embodiment, when the pad region 60 is located on the bottom surface of the OLED display device 100, the bending region may have a curved shape. In such an embodiment, the width of the bending region and the pad region 60 in the lateral direction may be smaller than the width of the display region 10 in the lateral direction.

[0054] In an exemplary embodiment, if Figure 1 As shown in , the peripheral region 40 surrounding the light emitting region 30 may have a constant width, but the configuration of the invention is not limited thereto. For example, in an exemplary embodiment, the peripheral region 40 may include a first peripheral region extending in the second direction D2 and a second peripheral region extending in the first direction D1. In such an embodiment, the first peripheral region of the peripheral region 40 may be adjacent to the top of the light emitting region 30 and the pad region 60, and the second peripheral region of the peripheral region 40 may be located on both sides of the light emitting region 30 (e.g., the left and right sides of the light emitting region 30). In such an embodiment, the width of the second peripheral region in the transverse direction may be relatively smaller than the width of the first peripheral region in the longitudinal direction (e.g., the first direction D1).

[0055] The external device 101 may be electrically connected to the OLED display device 100 through a flexible printed circuit board or a printed circuit board. For example, in an exemplary embodiment, one side of the flexible printed circuit board may be in direct contact with the pad electrode 470, and the opposite side of the flexible printed circuit board may be in direct contact with the external device 101. The external device 101 may provide a data signal, a gate signal, a light emission control signal, a gate initialization signal, an initialization voltage, a power supply voltage, etc. to the OLED display device 100. In such an embodiment, a driver integrated circuit may be mounted on the flexible printed circuit board. In an optional exemplary embodiment, the driver integrated circuit may be mounted on the OLED display device 100 adjacent to the pad electrode 470.

[0056] Figure 3 It shows that the setting Figure 1 Circuit diagram of sub-pixel circuit and OLED in the sub-pixel circuit area.

[0057] Reference Figure 3 , a sub-pixel circuit SPC and an organic light emitting diode OLED (eg, Figure 4 The sub-pixel structure 200) can be set in each of the sub-pixel circuit areas 20 of the organic light emitting diode display device 100, and one sub-pixel circuit SPC can include first to seventh transistors TR1, TR2, TR3, TR4, TR5, TR6 and TR7, a storage capacitor CST, wiring for a high power supply voltage ELVDD, wiring for a low power supply voltage ELVSS, wiring for an initialization voltage VINT, wiring for a data signal DATA, wiring for a gate signal GW, wiring for a gate initialization signal GI, wiring for a light emitting control signal EM, wiring for a diode initialization signal GB, and the like.

[0058] The organic light emitting diode OLED may output light based on the driving current ID. The organic light emitting diode OLED may include a first terminal and a second terminal. In an exemplary embodiment, the second terminal of the organic light emitting diode OLED may be supplied with a low power supply voltage ELVSS. For example, in an exemplary embodiment, the first terminal of the organic light emitting diode OLED may be an anode terminal, and the second terminal of the organic light emitting diode OLED may be a cathode terminal. Alternatively, the first terminal of the organic light emitting diode OLED may be a cathode terminal, and the second terminal of the organic light emitting diode OLED may be an anode terminal. In an exemplary embodiment, the anode terminal of the organic light emitting diode OLED may be connected to the cathode terminal. Figure 4 The cathode terminal of the organic light emitting diode OLED may correspond to the lower electrode 290 of Figure 4 Corresponding to the upper electrode 340.

[0059] The first transistor TR1 (eg, corresponding to Figure 4 The driving transistor 250 of the first transistor TR1 may include a gate terminal, a first terminal, and a second terminal. In an exemplary embodiment, the first terminal of the first transistor TR1 may be a source terminal, and the second terminal of the first transistor TR1 may be a drain terminal. Alternatively, the first terminal of the first transistor TR1 may be a drain terminal, and the second terminal of the first transistor TR1 may be a source terminal.

[0060] The first transistor TR1 may generate a driving current ID. In an exemplary embodiment, the first transistor TR1 may operate in a saturation region. In such an embodiment, the first transistor TR1 may generate a driving current ID based on a voltage difference between a gate terminal and a source terminal. In such an embodiment, a grayscale or grayscale level may be expressed based on the magnitude of the driving current ID supplied to the organic light emitting diode OLED. Alternatively, the first transistor TR1 may operate in a linear region. In such an embodiment, a grayscale may be expressed based on the sum of the time of a process of supplying the driving current ID to the organic light emitting diode OLED within one frame.

[0061] The second transistor TR2 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the second transistor TR2 may be supplied with a gate signal GW. The first terminal of the second transistor TR2 may be supplied with a data signal DATA. The second terminal of the second transistor TR2 may be connected to the first terminal of the first transistor TR1. For example, in an exemplary embodiment, a gate signal GW may be provided from a gate driver, and the gate signal GW may be applied to the gate terminal of the second transistor TR2 through wiring for the gate signal GW. In an exemplary embodiment, the first terminal of the second transistor TR2 may be a source terminal, and the second terminal of the second transistor TR2 may be a drain terminal. Alternatively, the first terminal of the second transistor TR2 may be a drain terminal, and the second terminal of the second transistor TR2 may be a source terminal.

[0062] During the activation period of the gate signal GW, the second transistor TR2 may supply the data signal DATA to the first terminal of the first transistor TR1. In such an embodiment, the second transistor TR2 may operate in a linear region.

[0063] The third transistor TR3 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the third transistor TR3 may be supplied with a gate signal GW. The first terminal of the third transistor TR3 may be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3 may be connected to the second terminal of the first transistor TR1. For example, in an exemplary embodiment, a gate signal GW may be provided from a gate driver, and the gate signal GW may be applied to the gate terminal of the third transistor TR3 through wiring for the gate signal GW. In an exemplary embodiment, the first terminal of the third transistor TR3 may be a source terminal, and the second terminal of the third transistor TR3 may be a drain terminal. Alternatively, the first terminal of the third transistor TR3 may be a drain terminal, and the second terminal of the third transistor TR3 may be a source terminal.

[0064] During the activation period of the gate signal GW, the third transistor TR3 may connect the gate terminal of the first transistor TR1 to the second terminal of the first transistor TR1. In such an embodiment, the third transistor TR3 may operate in a linear region. In such an embodiment, the third transistor TR3 may connect the first transistor TR1 in a diode form during the activation period of the gate signal GW. Because the first transistor TR1 is connected in a diode form, the voltage difference between the first terminal of the first transistor TR1 and the gate terminal of the first transistor TR1 may be substantially equal to the threshold voltage of the first transistor TR1. As a result, during the activation period of the gate signal GW, a voltage obtained by adding the voltage difference (i.e., the threshold voltage) to the voltage of the data signal DATA supplied to the first terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1. In such an embodiment, the data signal DATA may be compensated by the threshold voltage of the first transistor TR1, and the compensated data signal DATA may be supplied to the gate terminal of the first transistor TR1. Since the threshold voltage compensation is performed, the problem of non-uniform drive current caused by the threshold voltage deviation of the first transistor TR1 may be effectively prevented. In an exemplary embodiment, the third transistor TR3 may be connected to the gate terminal of the first transistor TR1. Figure 3 The switching transistor 255 corresponds to the switching transistor 255. In such an embodiment, the channel of the third transistor TR3 may include a metal oxide semiconductor.

[0065] An output terminal of the initialization voltage wiring to which the initialization voltage VINT is supplied may be connected to the first terminal of the fourth transistor TR4 and the first terminal of the seventh transistor TR7 , and an input terminal of the initialization voltage wiring may receive the initialization voltage VINT.

[0066] The fourth transistor TR4 may include a gate terminal, a first terminal, and a second terminal. The gate terminal of the fourth transistor TR4 may be supplied with a gate initialization signal GI. The first terminal of the fourth transistor TR4 may be supplied with an initialization voltage VINT. The second terminal of the fourth transistor TR4 may be connected to the gate terminal of the first transistor TR1. In an exemplary embodiment, the first terminal of the fourth transistor TR4 may be a source terminal, and the second terminal of the fourth transistor TR4 may be a drain terminal. Alternatively, the first terminal of the fourth transistor TR4 may be a drain terminal, and the second terminal of the fourth transistor TR4 may be a source terminal.

[0067] During the activation period of the gate initialization signal GI, the fourth transistor TR4 may supply the initialization voltage VINT to the gate terminal of the first transistor TR1. In such an embodiment, the fourth transistor TR4 may operate in a linear region. In such an embodiment, the fourth transistor TR4 may initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT during the activation period of the gate initialization signal GI. In an exemplary embodiment, the initialization voltage VINT may have a voltage level sufficiently lower than the voltage level of the data signal DATA held by the storage capacitor CST in the previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1 as a p-channel metal oxide semiconductor transistor (PMOS transistor). In an optional exemplary embodiment, the initialization voltage VINT may have a voltage level sufficiently higher than the voltage level of the data signal DATA held by the storage capacitor CST in the previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1 as an n-channel metal oxide semiconductor transistor (NMOS transistor).

[0068] In an exemplary embodiment, the gate initialization signal GI may be a signal substantially identical to the gate signal GW transmitted one horizontal time ago. For example, in an exemplary embodiment, the gate initialization signal GI supplied to the sub-pixel circuit in the nth row (where n is an integer of 2 or greater) of the sub-pixel circuit SPC included in the OLED display device 100 may be a signal substantially identical to the gate signal GW supplied to the sub-pixel circuit in the (n-1)th row of the sub-pixel circuit SPC. In such an embodiment, by supplying the activated gate signal GW to the sub-pixel circuit in the (n-1)th row of the sub-pixel circuit SPC, the activated gate initialization signal GI may be supplied to the sub-pixel circuit in the nth row of the sub-pixel circuit SPC. As a result, the data signal DATA may be supplied to the sub-pixel circuit in the (n-1)th row of the sub-pixel circuit SPC, and at the same time, the gate terminal of the first transistor TR1 included in the sub-pixel circuit in the nth row of the sub-pixel circuit SPC is initialized to the initialization voltage VINT. Optionally, the fourth transistor TR4 may be connected to the gate terminal of the first transistor TR1. Figure 4 The switching transistor 255 corresponds to the switching transistor 255. In such an embodiment, the channel of the fourth transistor TR4 may include a metal oxide semiconductor.

[0069] The fifth transistor TR5 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may be supplied with a light emitting control signal EM. The first terminal may be connected to a wiring for a high power supply voltage ELVDD. The second terminal may be connected to a first terminal of the first transistor TR1. For example, in an exemplary embodiment, a light emitting control signal EM may be provided from a light emitting control driver, and the light emitting control signal EM may be applied to the gate terminal of the fifth transistor TR5 through a wiring for the light emitting control signal EM. In an exemplary embodiment, the first terminal of the fifth transistor TR5 may be a source terminal, and the second terminal of the fifth transistor TR5 may be a drain terminal. Alternatively, the first terminal of the fifth transistor TR5 may be a drain terminal, and the second terminal of the fifth transistor TR5 may be a source terminal.

[0070] During the activation period of the light emitting control signal EM, the fifth transistor TR5 may supply the high power supply voltage ELVDD to the first terminal of the first transistor TR1. In such an embodiment, the fifth transistor TR5 may cut off the supply of the high power supply voltage ELVDD during the inactive period of the light emitting control signal EM. In this case, the fifth transistor TR5 may operate in a linear region. During the activation period of the light emitting control signal EM, the fifth transistor TR5 supplies the high power supply voltage ELVDD to the first terminal of the first transistor TR1, so that the first transistor TR1 may generate a driving current ID. In such an embodiment, during the inactive period of the light emitting control signal EM, the fifth transistor TR5 cuts off the supply of the high power supply voltage ELVDD, so that the data signal DATA supplied to the first terminal of the first transistor TR1 may be supplied to the gate terminal of the first transistor TR1.

[0071] The sixth transistor TR6 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may be supplied with a light emitting control signal EM. The first terminal may be connected to the second terminal of the first transistor TR1. The second terminal may be connected to the first terminal of the organic light emitting diode OLED. For example, in an exemplary embodiment, a light emitting control signal EM may be provided from a light emitting control driver, and the light emitting control signal EM may be applied to the gate terminal of the sixth transistor TR6 through wiring for the light emitting control signal EM. In an exemplary embodiment, the first terminal of the sixth transistor TR6 may be a source terminal, and the second terminal of the sixth transistor TR6 may be a drain terminal. Alternatively, the first terminal of the sixth transistor TR6 may be a drain terminal, and the second terminal of the sixth transistor TR6 may be a source terminal.

[0072] During the activation period of the light emitting control signal EM, the sixth transistor TR6 can supply the driving current ID generated by the first transistor TR1 to the organic light emitting diode OLED. In such an embodiment, the sixth transistor TR6 can operate in a linear region. In such an embodiment, during the activation period of the light emitting control signal EM, the sixth transistor TR6 supplies the driving current ID generated by the first transistor TR1 to the organic light emitting diode OLED, so that the organic light emitting diode OLED can output light. In such an embodiment, during the inactive period of the light emitting control signal EM, the sixth transistor TR6 electrically separates the first transistor TR1 from the organic light emitting diode OLED, so that the data signal DATA supplied to the first terminal of the first transistor TR1 (more specifically, the data signal that has been subjected to threshold voltage compensation) can be supplied to the gate terminal of the first transistor TR1.

[0073] The seventh transistor TR7 may include a gate terminal, a first terminal, and a second terminal. The gate terminal may be supplied with a diode initialization signal GB. The first terminal may be supplied with an initialization voltage VINT. The second terminal may be connected to a first terminal of the organic light emitting diode OLED. In an exemplary embodiment, the first terminal of the seventh transistor TR7 may be a source terminal, and the second terminal of the seventh transistor TR7 may be a drain terminal. Alternatively, the first terminal of the seventh transistor TR7 may be a drain terminal, and the second terminal of the seventh transistor TR7 may be a source terminal.

[0074] During the activation period of the diode initialization signal GB, the seventh transistor TR7 can supply the initialization voltage VINT to the first terminal of the organic light emitting diode OLED. In such an embodiment, the seventh transistor TR7 can operate in the linear region. In such an embodiment, the seventh transistor TR7 can initialize the first terminal of the organic light emitting diode OLED to the initialization voltage VINT during the activation period of the diode initialization signal GB.

[0075] Alternatively, the gate initialization signal GI and the diode initialization signal GB may be signals substantially identical to each other. The operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the organic light emitting diode OLED may not affect each other. In such an embodiment, the operation of initializing the gate terminal of the first transistor TR1 and the operation of initializing the first terminal of the organic light emitting diode OLED may be independent of each other. Therefore, the diode initialization signal GB is not generated separately, so that the efficiency of the process can be improved.

[0076] The storage capacitor CST may include a first terminal and a second terminal. The storage capacitor CST may be connected between the wiring for the high power supply voltage ELVDD and the gate terminal of the first transistor TR1. For example, in an exemplary embodiment, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the wiring for the high power supply voltage ELVDD. During the inactive period of the gate signal GW, the storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor TR1. The inactive period of the gate signal GW may include the active period of the light emitting control signal EM, and the drive current ID generated by the first transistor TR1 may be supplied to the organic light emitting diode OLED during the active period of the light emitting control signal EM. Therefore, based on the voltage level maintained by the storage capacitor CST, the drive current ID generated by the first transistor TR1 may be supplied to the organic light emitting diode OLED.

[0077] As described above, in an exemplary embodiment, the sub-pixel circuit SPC may include seven transistors and a single storage capacitor, but the configuration of the exemplary embodiment of the invention is not limited thereto. For example, in an exemplary embodiment, the sub-pixel circuit SPC may have a configuration including two or more transistors and two or more storage capacitors.

[0078] Figure 4 yes Figure 1 A cross-sectional view of an organic light emitting diode display device taken along line II'.

[0079] Reference Figure 4 , an exemplary embodiment of the OLED display device 100 may include a substrate 110, a buffer layer 115, a driving transistor 250, a switching transistor 255, a gate electrode pattern 180, a first gate insulating layer 150, a second gate insulating layer 155, a first insulating interlayer 190, an insulating pattern 160, a second insulating interlayer 195, a protective insulating layer 400, a planarization layer 270, a connection pattern 370, a light absorbing layer 350, an organic insulating layer 275, a sub-pixel structure 200, a pixel defining layer 310, a thin film encapsulation structure 450, etc. In such an embodiment, the substrate 110 may include a first organic layer 111, a barrier layer 112, and a second organic layer 113. Since the OLED display device 100 includes a pad region 60 and a display region 10 including a light emitting region 30 and a peripheral region 40, the substrate 110 may also be divided into the display region 10 and the pad region 60. The driving transistor 250 may include a first active layer 130, a first gate electrode 170, a first source electrode 210, and a first drain electrode 230, and the switching transistor 255 may include a second active layer 135, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235. In such an embodiment, the sub-pixel structure 200 may include a lower electrode 290, a light emitting layer 330, and an upper electrode 340, and the thin film encapsulation structure 450 may include a first thin film encapsulation layer 451, a second thin film encapsulation layer 452, and a third thin film encapsulation layer 453.

[0080] In such an embodiment where the OLED display device 100 includes a flexible substrate 110 and a thin film encapsulation structure 450 , the OLED display device 100 may be used as a flexible organic light emitting diode display device.

[0081] The OLED display device 100 includes a first organic layer 111. The first organic layer 111 may include a flexible organic material. For example, in an exemplary embodiment, the first organic layer 111 may include polyimide.

[0082] The barrier layer 112 may be disposed on the first organic layer 111. The barrier layer 112 may block moisture permeated through the first organic layer 111. The barrier layer 112 may include a flexible inorganic material. For example, in an exemplary embodiment, the barrier layer 112 may include silicon oxide or silicon nitride.

[0083] The second organic layer 113 may be disposed on the barrier layer 112. The second organic layer 113 may be disposed on the entire barrier layer 112. The second organic layer 113 may include a flexible organic material. For example, in an exemplary embodiment, the second organic layer 113 may include polyimide.

[0084] In such an embodiment, the first organic layer 111, the barrier layer 112, and the second organic layer 113 may collectively define the substrate 110. In an exemplary embodiment, the substrate 110 may have a first region 11 and a second region 12, wherein the first region 11 may be adjacent to the second region 12. For example, in an exemplary embodiment, the first region 11 may be a region where the driving transistor 250 is disposed, and the second region 12 may be a region where the switching transistor 255 is disposed.

[0085] In an exemplary embodiment, if Figure 4 As shown in , the substrate 110 may have a multi-layer structure including three layers, but is not limited thereto. For example, in one exemplary embodiment, the substrate 110 may include a single layer or at least two layers.

[0086] In an optional exemplary embodiment, the substrate 110 may include a transparent material or an opaque material. For example, in an exemplary embodiment, the substrate 110 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate (F-doped quartz substrate), a soda-lime glass substrate, or an alkali-free glass substrate.

[0087] The buffer layer 115 may be disposed in the first region 11 and the second region 12 on the substrate 110. For example, in one exemplary embodiment, the buffer layer 115 may be disposed on the substrate 110. The buffer layer 115 may effectively prevent metal atoms or impurities from diffusing from the substrate 110 into the driving transistor 250, the switching transistor 255, and the sub-pixel structure 200, and may control the heat transfer rate during the crystallization process for forming the first active layer 130 to obtain a substantially uniform first active layer 130. In such an embodiment, when the surface of the substrate 110 is uneven, the buffer layer 115 may be used to improve the flatness of the surface of the substrate 110. Depending on the type of the substrate 110, at least two buffer layers 115 may be disposed on the substrate 110, or no buffer layer 115 may be disposed on the substrate 110. For example, in one exemplary embodiment, the buffer layer 115 may include an organic material or an inorganic material. In an exemplary embodiment, the buffer layer 115 may include an inorganic material.

[0088] The first active layer 130 may be disposed in the first region 11 on the buffer layer 115. For example, in one exemplary embodiment, the first active layer 130 may include a metal oxide semiconductor, amorphous silicon, polycrystalline silicon, or an organic semiconductor. In an exemplary embodiment, the first active layer 130 may include a silicon-based semiconductor, such as amorphous silicon or polycrystalline silicon. In an exemplary embodiment, the first active layer 130 may have a first source region, a first drain region, and a first channel region between the first source region and the first drain region.

[0089] The first gate insulating layer 150 may be disposed in the first region 11 and the second region 12 on the buffer layer 115 and the first active layer 130. For example, in one exemplary embodiment, the first gate insulating layer 150 may be disposed on the entire buffer layer 115. The first gate insulating layer 150 may fully cover the first active layer 130 on the buffer layer 115, and may have a substantially flat top surface without a step defined around the first active layer 130. Alternatively, the first gate insulating layer 150 may cover the first active layer 130 on the buffer layer 115, and may be disposed with a substantially uniform thickness along the contour of the first active layer 130. For example, the first gate insulating layer 150 may include a silicon compound or a metal oxide. For example, in one exemplary embodiment, the first gate insulating layer 150 may include silicon oxide (SiO x ), Silicon Nitride (SiN x ), silicon oxynitride (SiO x N y ), Silicon Oxycarbide (SiO x C y ), Silicon Carbide Nitride (SiC x N y ), aluminum oxide (AlO x ), aluminum nitride (AlN x ), tantalum oxide (TaO x ), hafnium oxide (HfO x ), zirconium oxide (ZrO x ) or titanium oxide (TiO x ). Alternatively, the first gate insulating layer 150 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0090] The first gate electrode 170 may be disposed in the first region 11 on the first gate insulating layer 150. In such an embodiment, the first gate electrode 170 may be disposed on a portion of the first gate insulating layer 150 under which the first active layer 130 is located (e.g., the first channel region). For example, the first gate electrode 170 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, or a transparent conductive material. For example, in an exemplary embodiment, the first gate electrode 170 may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an aluminum alloy, aluminum nitride (AlN), or the like. x ), silver alloy, tungsten nitride (WN x ), copper-containing alloys, molybdenum-containing alloys, titanium nitride (TiN x ), chromium nitride (CrN x ), Tantalum Nitride (TaN x ), strontium ruthenium oxide (SrRu x O y ), zinc oxide (ZnO x ), indium tin oxide (“ITO”), tin oxide (SnO x ), indium oxide (InO x ), gallium oxide (GaO x ) or indium zinc oxide ("IZO"). Such materials may be used alone or in combination with each other. Alternatively, the first gate electrode 170 may have a multi-layer structure including a plurality of layers.

[0091] The second gate insulating layer 155 may be disposed in the first region 11 and the second region 12 on the first gate insulating layer 150 and the first gate electrode 170. For example, in one exemplary embodiment, the second gate insulating layer 155 may be disposed on the entire first gate insulating layer 150. The second gate insulating layer 155 may fully cover the first gate electrode 170 on the first gate insulating layer 150, and may have a substantially flat top surface without a step defined around the first gate electrode 170. Alternatively, the second gate insulating layer 155 may cover the first gate electrode 170 on the first gate insulating layer 150, and may be provided with a substantially uniform thickness along the contour of the first gate electrode 170. For example, the second gate insulating layer 155 may include a silicon compound or a metal oxide. Alternatively, the second gate insulating layer 155 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0092] The gate electrode pattern 180 may be disposed in the first region 11 on the second gate insulating layer 155. In such an embodiment, the gate electrode pattern 180 may be disposed on a portion of the second gate insulating layer 155 under which the first gate electrode 170 is positioned. In the cross-sectional view of the OLED display device 100, the first gate electrode 170 and the gate electrode pattern 180 may be used as Figure 3 The storage capacitor CST of the gate electrode pattern 180 may be formed by a plurality of layers. For example, the gate electrode pattern 180 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, or a transparent conductive material. Alternatively, the gate electrode pattern 180 may have a multilayer structure including a plurality of layers.

[0093] The first insulating interlayer 190 may be disposed in the first region 11 and the second region 12 on the second gate insulating layer 155 and the gate electrode pattern 180. For example, in one exemplary embodiment, the first insulating interlayer 190 may be disposed on the entire second gate insulating layer 155. The first insulating interlayer 190 may fully cover the gate electrode pattern 180 on the second gate insulating layer 155, and may have a substantially flat top surface without a step defined around the gate electrode pattern 180. Alternatively, the first insulating interlayer 190 may cover the gate electrode pattern 180 on the second gate insulating layer 155, and may be provided with a substantially uniform thickness along the contour of the gate electrode pattern 180. For example, the first insulating interlayer 190 may include a silicon compound or a metal oxide. Alternatively, the first insulating interlayer 190 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0094] The second active layer 135 may be disposed in the second region 12 on the first insulating interlayer 190. The second active layer 135 may include a metal oxide semiconductor. For example, in such an embodiment, the second active layer 135 may be a semiconductor oxide layer including a binary compound (AB) containing indium (In), zinc (Zn), gallium (Ga), tin (Sn), titanium (Ti), aluminum (Al), hafnium (Hf), zirconium (Zr), or magnesium (Mg). x ), ternary compounds (AB x C y ) or quaternary compound (AB x C y D z ) etc. For example, in one exemplary embodiment, the second active layer 135 may include zinc oxide (ZnO x ), gallium oxide (GaO x ), titanium oxide (TiO x ), tin oxide (SnO x ), indium oxide (InO x), indium gallium oxide (“IGO”), indium zinc oxide (“IZO”), indium tin oxide (“ITO”), gallium zinc oxide (“GZO”), zinc magnesium oxide (“ZMO”), zinc tin oxide (“ZTO”), zinc zirconium oxide (ZnZr x O y ), indium gallium zinc oxide ("IGZO"), indium zinc tin oxide ("IZTO"), indium gallium hafnium oxide ("IGHO"), tin aluminum zinc oxide ("TAZO"), or indium gallium tin oxide ("IGTO"). In an exemplary embodiment, the second active layer 135 may have a second source region, a second drain region, and a second channel region between the second source region and the second drain region.

[0095] The insulating pattern 160 may be disposed on the second channel region of the second active layer 135. In such an embodiment, the insulating pattern 160 may be disposed between the second active layer 135 and the second gate electrode 175, and may be spaced apart from the second source electrode 215 and the second drain electrode 235. For example, the insulating pattern 160 may include a silicon compound or a metal oxide. Alternatively, the insulating pattern 160 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0096] The second gate electrode 175 may be disposed on the insulating pattern 160. In such an embodiment, the second gate electrode 175 may be disposed on the insulating pattern 160 of the second channel region under which the second active layer 135 is located. For example, the second gate electrode 175 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, or a transparent conductive material. Such materials may be used alone or in combination with each other. Alternatively, the second gate electrode 175 may have a multilayer structure including a plurality of layers.

[0097] The second insulating interlayer 195 may be disposed in the first region 11 and the second region 12 on the first insulating interlayer 190, the second active layer 135, the insulating pattern 160, and the second gate electrode 175. For example, in one exemplary embodiment, the second insulating interlayer 195 may be disposed on the entire first insulating interlayer 190. The second insulating interlayer 195 may fully cover the second active layer 135, the insulating pattern 160, and the second gate electrode 175 on the first insulating interlayer 190, and may have a substantially flat top surface without a step defined around the second active layer 135, the insulating pattern 160, and the second gate electrode 175. Alternatively, the second insulating interlayer 195 may cover the second active layer 135, the insulating pattern 160, and the second gate electrode 175 on the first insulating interlayer 190, and may be disposed with a substantially uniform thickness along the contours of the second active layer 135, the insulating pattern 160, and the second gate electrode 175. For example, the second insulating interlayer 195 may include a silicon compound or a metal oxide. Alternatively, the second insulating interlayer 195 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0098] The first source electrode 210 and the first drain electrode 230 may be disposed in the first region 11 on the second insulating interlayer 195. The first source electrode 210 may be connected to the first source region of the first active layer 130 through a first contact hole defined by (e.g., formed by removing the first portion of the first gate insulating layer 150, the first portion of the second gate insulating layer 155, the first portion of the first insulating interlayer 190, and the first portion of the second insulating interlayer 195). In such an embodiment, the first drain electrode 230 may be connected to the first drain region of the first active layer 130 by passing through the second portion of the first gate insulating layer 150, the second portion of the second gate insulating layer 155, the second portion of the first insulating interlayer 190, and the second portion of the second insulating interlayer 195 (e.g., formed by removing the second portion of the first gate insulating layer 150, the second portion of the second gate insulating layer 155, the second portion of the first insulating interlayer 190, and the second portion of the second insulating interlayer 195). For example, each of the first source electrode 210 and the first drain electrode 230 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, or a transparent conductive material. Such materials may be used alone or in combination with each other. In an optional exemplary embodiment, each of the first source electrode 210 and the first drain electrode 230 may have a multilayer structure including a plurality of layers.

[0099] Thus, a driving transistor 250 including the first active layer 130, the first gate electrode 170, the first source electrode 210, and the first drain electrode 230 may be constructed. In such an embodiment, the driving transistor 250 may be used as a driving transistor including a silicon-based semiconductor. In such an embodiment, the driving transistor 250 may be used as a transistor having a top gate structure. For example, in an exemplary embodiment, the driving transistor 250 may be connected to Figure 3 The first transistor TR1 shown in FIG.

[0100] The second source electrode 215 and the second drain electrode 235 may be disposed in the second region 12 on the second insulating interlayer 195. The second source electrode 215 may be connected to the second source region of the second active layer 135 by passing through a third contact hole defined by a third portion of the second insulating interlayer 195 (e.g., formed by removing the third portion of the second insulating interlayer 195). In such an embodiment, the second drain electrode 235 may be connected to the second drain region of the second active layer 135 by passing through a fourth contact hole defined by a fourth portion of the second insulating interlayer 195 (e.g., formed by removing the fourth portion of the second insulating interlayer 195). For example, each of the second source electrode 215 and the second drain electrode 235 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, or a transparent conductive material. Such materials may be used alone or in combination with each other. In an optional exemplary embodiment, each of the second source electrode 215 and the second drain electrode 235 may have a multilayer structure including a plurality of layers.

[0101] Thus, a switching transistor 255 including the second active layer 135, the second gate electrode 175, the second source electrode 215, and the second drain electrode 235 may be constructed. In such an embodiment, the switching transistor 255 may be used as a switching transistor including an oxide-based semiconductor. In such an embodiment, the switching transistor 255 may be used as a transistor having a top gate structure. For example, in one exemplary embodiment, the switching transistor 255 may be connected to the Figure 3 In an exemplary embodiment, the switch transistor 255 may correspond to the third transistor TR3 and / or the fourth transistor TR4, and the second transistor TR2, the fifth transistor TR5, the sixth transistor TR6, and the seventh transistor TR7 may be used as a switch transistor including a silicon-based semiconductor.

[0102] In an exemplary embodiment, the OLED display device 100 may include two transistors (eg, a driving transistor 250 and a switching transistor 255), but is not limited thereto. For example, in an exemplary embodiment, the OLED display device 100 may have a configuration including at least two transistors and at least one capacitor.

[0103] The protective insulating layer 400 may be disposed in the first region 11 and the second region 12 on the second insulating interlayer 195, the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235. In such an embodiment, the protective insulating layer 400 may be disposed on the entire second insulating interlayer 195. For example, in one exemplary embodiment, the protective insulating layer 400 may fully cover the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235 on the second insulating interlayer 195, and may have a substantially flat top surface without a step defined around the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235. Alternatively, the protective insulating layer 400 may cover the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235 on the second insulating interlayer 195, and may be provided with a substantially uniform thickness along the contours of the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235. For example, the protective insulating layer 400 may include a silicon compound or a metal oxide. Alternatively, the protective insulating layer 400 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0104] The planarization layer 270 may be disposed on the protective insulating layer 400. In such an embodiment, the planarization layer 270 may be disposed on the entire protective insulating layer 400. For example, in an exemplary embodiment, the planarization layer 270 may have a relatively thick thickness to fully cover the protective insulating layer 400, and in such an embodiment, the planarization layer 270 may have a substantially flat top surface. In order to achieve such a flat top surface of the planarization layer 270, a planarization process may be additionally performed on the planarization layer 270. The planarization layer 270 may include an organic material or an inorganic material. In an exemplary embodiment, the planarization layer 270 may include an organic material.

[0105] The connection pattern 370 may be disposed on the planarization layer 270. A high power supply voltage (eg, Figure 3 The high power supply voltage ELVDD shown in FIG. 1 may be applied to the connection pattern 370. In such an embodiment, the connection pattern 370 may be connected to the Figure 3For example, in one exemplary embodiment, the first drain electrode 230 of the driving transistor 250 may transmit the high power supply voltage ELVDD to the connection pattern 370 (eg, Figure 3 The second terminal of the sixth transistor TR6 shown in FIG. 3 is connected to the connection pattern 370, and the high power supply voltage ELVDD transmitted to the connection pattern 370 can be applied to the lower electrode 290. For example, the connection pattern 370 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, or a transparent conductive material. Such materials may be used alone or in combination with each other. Optionally, the connection pattern 370 may have a multilayer structure including a plurality of layers.

[0106] The light absorbing layer 350 may be disposed on a portion of the connection pattern 370 and the planarization layer 270. The light absorbing layer 350 may cover both sides of the connection pattern 370 and have a contact hole for exposing a portion of the top surface of the connection pattern 370. In an exemplary embodiment, the light absorbing layer 350 may effectively prevent external light penetrating into the OLED display device 100 from being incident on the second active layer 135, and may effectively prevent a portion of the light emitted from the light emitting layer 330 from being reflected from the upper electrode 340 and incident on the second active layer 135. The light absorbing layer 350 may include an organic material such as a photoresist, a polyacryl resin, a polyimide resin, a polyamide resin, a siloxane resin, or an epoxy resin. In such an embodiment, the light absorbing layer 350 may be substantially opaque. For example, in an exemplary embodiment, the light absorbing layer 350 may also include a light shielding material for absorbing external light. For example, the light shielding material may include carbon black, titanium oxynitride, titanium black, phenylene black, aniline black, cyanine black, nigrosine acid black, or black resin.

[0107] In a conventional organic light emitting diode display device, a portion of external light penetrating therein and / or light emitted from its light emitting layer may penetrate into a portion thereof where a driving transistor and a switching transistor are disposed, and light (e.g., external light and light emitted from the light emitting layer) may be reflected from an interface between the insulating layer and the metal electrode and incident on a top surface of the second active layer. When light is incident on the second active layer, the second active layer including a metal oxide-based semiconductor may be rapidly degraded, and the characteristics of the switching transistor including the metal oxide-based semiconductor may be changed, so that the conventional OLED display device may be defective.

[0108] In an exemplary embodiment of the invention, the OLED display device 100 includes a light absorbing layer 350 for absorbing light, so that a portion of external light penetrating into the OLED display device 100 and light emitted from the light emitting layer 330 can be absorbed. In such an embodiment, the light absorbing layer 350 can absorb about 90% of the light incident thereon. Therefore, in such an embodiment, the OLED display device 100 can protect the second active layer 135 including the metal oxide-based semiconductor, and the characteristics of the switching transistor 255 including the second active layer 135 are not changed.

[0109] In an exemplary embodiment, an organic insulating layer 275 may be disposed on the light absorbing layer 350. The organic insulating layer 275 may have a contact hole for exposing a portion of the top surface of the connection pattern 370, and the contact hole of the organic insulating layer 275 may overlap the contact hole of the light absorbing layer 350. For example, in an exemplary embodiment, the organic insulating layer 275 may have a relatively thick thickness to fully cover the light absorbing layer 350, and in such an embodiment, the organic insulating layer 275 may have a substantially flat top surface. In an exemplary embodiment, a planarization process may be additionally performed on the organic insulating layer 275 to achieve such a flat top surface of the organic insulating layer 275. The organic insulating layer 275 may include an organic material or an inorganic material. In an exemplary embodiment, the organic insulating layer 275 may include an organic material.

[0110] The lower electrode 290 may be disposed on the organic insulating layer 275. The lower electrode 290 may be connected to the connection pattern 370 through the contact hole of the organic insulating layer 275 and the contact hole of the light absorbing layer 350. For example, the lower electrode 290 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, or a transparent conductive material. Such materials may be used alone or in combination with each other. Alternatively, the lower electrode 290 may have a multilayer structure including a plurality of layers.

[0111] The pixel defining layer 310 may be disposed on a portion of the lower electrode 290 and the organic insulating layer 275. The pixel defining layer 310 may cover both sides of the lower electrode 290 and may expose a portion of the top surface of the lower electrode 290. The pixel defining layer 310 may include an organic material or an inorganic material, or may be formed of an organic material or an inorganic material. In an exemplary embodiment, the pixel defining layer 310 may include an organic material.

[0112] The light-emitting layer 330 may be disposed on the lower electrode 290 exposed by the pixel defining layer 310. The light-emitting layer 330 may include at least one of the light-emitting materials for emitting different color lights (i.e., red light, green light, blue light, etc.) corresponding to the sub-pixels, or may be formed using at least one of the light-emitting materials for emitting different color lights (i.e., red light, green light, blue light, etc.) corresponding to the sub-pixels. Alternatively, the light-emitting layer 330 may be formed by stacking a plurality of light-emitting materials for emitting different color lights such as red light, green light, or blue light, thereby emitting white light as a whole. In such an embodiment, a color filter may be disposed on the light-emitting layer 330 (e.g., it may be disposed to overlap with the light-emitting layer 330 on the top surface of the thin film encapsulation structure 450). The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include a yellow color filter, a cyan color filter, or a magenta color filter. For example, the color filter may include a photosensitive resin or a colored photoresist.

[0113] The upper electrode 340 may be disposed on the pixel defining layer 310 and the light emitting layer 330. The upper electrode 340 may cover the light emitting layer 330 and the pixel defining layer 310, and may be disposed integrally on the light emitting layer 330 and the pixel defining layer 310. In an exemplary embodiment, a low power supply voltage (e.g., Figure 3 The low power supply voltage ELVSS shown in FIG. 1 may be applied to the upper electrode 340. For example, the upper electrode 340 may include a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, or a transparent conductive material. Such materials may be used alone or in combination with each other. Alternatively, the upper electrode 340 may have a multilayer structure including a plurality of layers.

[0114] In such an embodiment, the sub-pixel structure 200 including the lower electrode 290 , the light emitting layer 330 , and the upper electrode 340 may be constructed as described above.

[0115] The first thin film encapsulation layer 451 may be disposed on the upper electrode 340 in the light emitting region 30. The first thin film encapsulation layer 451 may cover the upper electrode 340 in the light emitting region 30, and may be disposed with a substantially uniform thickness along the contour of the upper electrode 340. The first thin film encapsulation layer 451 may effectively prevent the sub-pixel structure 200 from being degraded due to the penetration of moisture, oxygen, etc. In such an embodiment, the first thin film encapsulation layer 451 may be used to protect the sub-pixel structure 200 from external impact. The first thin film encapsulation layer 451 may include a flexible inorganic material.

[0116] The second thin film encapsulation layer 452 may be disposed in the light emitting region 30 on the first thin film encapsulation layer 451. The second thin film encapsulation layer 452 may improve the flatness of the OLED display device 100 and may protect the sub-pixel structure 200. The second thin film encapsulation layer 452 may include a flexible organic material.

[0117] The third thin film encapsulation layer 453 may be disposed in the light emitting region 30 on the second thin film encapsulation layer 452. The third thin film encapsulation layer 453 may cover the second thin film encapsulation layer 452 in the light emitting region 30, and may be provided with a substantially uniform thickness along the contour of the second thin film encapsulation layer 452. The third thin film encapsulation layer 453 may effectively prevent the sub-pixel structure 200 from being degraded due to the penetration of moisture, oxygen, etc. together with the first thin film encapsulation layer 451. In such an embodiment, the third thin film encapsulation layer 453 may be used together with the first thin film encapsulation layer 451 and the second thin film encapsulation layer 452 to protect the sub-pixel structure 200 from external impact. The third thin film encapsulation layer 453 may include a flexible inorganic material. Alternatively, an encapsulation substrate may be disposed on the upper electrode 340 instead of the thin film encapsulation structure 450. For example, the encapsulation substrate may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, or an alkali-free glass substrate.

[0118] Therefore, as described above, a thin film encapsulation structure 450 including a first thin film encapsulation layer 451, a second thin film encapsulation layer 452, and a third thin film encapsulation layer 453 may be constructed. Alternatively, the thin film encapsulation structure 450 may have a five-layer structure formed by stacking the first to fifth thin film encapsulation layers or a seven-layer structure formed by stacking the first to seventh thin film encapsulation layers.

[0119] In an exemplary embodiment of the invention, the OLED display device 100 includes the light absorbing layer 350 so that the OLED display device 100 can block light incident on the second active layer 135. Therefore, the OLED display device 100 can effectively protect the second active layer 135 including the oxide-based semiconductor, and can maintain the characteristics of the switching transistor 255.

[0120] Figures 5 to 16 is a cross-sectional view illustrating a method of manufacturing an organic light emitting diode display device according to an exemplary embodiment of the invention.

[0121] Reference Figure 5In an exemplary embodiment of a method for manufacturing an organic light emitting diode display device, a rigid glass substrate 105 may be prepared. A first organic layer 111 may be provided or formed on the glass substrate 105. A flexible organic material may be used to form the first organic layer 111. In an exemplary embodiment, the first organic layer 111 may include polyimide. For example, in an exemplary embodiment, the first organic layer 111 may include a random copolymer or a block copolymer. In such an embodiment, the first organic layer 111 may have high transparency, a low coefficient of thermal expansion, and a high glass transition temperature. In an exemplary embodiment, the first organic layer 111 includes an imide group so that the first organic layer 111 may have high heat resistance, chemical resistance, corrosion resistance, and electrical properties.

[0122] The barrier layer 112 may be disposed or formed on the entire first organic layer 111. The barrier layer 112 may block moisture permeated through the first organic layer 111. The barrier layer 112 may be formed using a flexible inorganic material.

[0123] The second organic layer 113 may be disposed or formed on the entire barrier layer 112. A flexible organic material may be used to form the second organic layer 113. In an exemplary embodiment, the second organic layer 113 may include polyimide. For example, in one exemplary embodiment, the second organic layer 113 may include a random copolymer or a block copolymer.

[0124] Thus, a substrate 110 including a first organic layer 111, a barrier layer 112, and a second organic layer 113 may be formed. In an exemplary embodiment, the substrate 110 may have a first region 11 and a second region 12, wherein the first region 11 may be adjacent to the second region 12. For example, in one exemplary embodiment, the first region 11 may be a region where a driving transistor is formed, and the second region 12 may be a region where a switching transistor is formed.

[0125] In an exemplary embodiment, the substrate 110 may have three layers, but is not limited thereto. For example, in an exemplary embodiment, the substrate 110 may include a single layer or at least two layers.

[0126] In such an embodiment, because the substrate 110 is thin and flexible, the substrate 110 can be disposed or formed on the rigid glass substrate 105 to support the formation of the upper structure (e.g., a driving transistor, a switching transistor, a sub-pixel structure, etc.). For example, in an exemplary embodiment, after the upper structure is disposed on the substrate 110, the glass substrate 105 can be removed. In such an embodiment, due to the flexible physical properties of the first organic layer 111, the barrier layer 112, and the second organic layer 113, it is not possible to effectively form the upper structure directly on the first organic layer 111, the barrier layer 112, and the second organic layer 113. Therefore, in an exemplary embodiment, the upper structure is formed using the glass substrate 105, and then the glass substrate 105 is removed, so that the first organic layer 111, the barrier layer 112, and the second organic layer 113 can be used as the substrate 110.

[0127] In an optional exemplary embodiment, the substrate 110 may include a transparent material or an opaque material. For example, in an exemplary embodiment, the substrate 110 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, or an alkali-free glass substrate. In such an embodiment, the glass substrate 105 may not be used.

[0128] A buffer layer 115 may be disposed or formed in the first region 11 and the second region 12 on the substrate 110. For example, in one exemplary embodiment, the buffer layer 115 may be disposed or formed on the entire substrate 110. The buffer layer 115 may effectively prevent metal atoms or impurities from diffusing from the substrate 110, and may control a heat transfer rate during a crystallization process for forming the first active layer 130 to obtain a substantially uniform first active layer 130. In such an embodiment, the buffer layer 115 may be used to improve the flatness of the surface of the substrate 110 when the surface of the substrate 110 is uneven. Depending on the type of the substrate 110, at least two buffer layers 115 may be disposed on the substrate 110, or no buffer layer 115 may be disposed on the substrate 110. The buffer layer 115 may be formed using an inorganic material.

[0129] A first active layer 130 may be disposed or formed in the first region 11 on the buffer layer 115. For example, in one exemplary embodiment, the first active layer 130 may include a metal oxide semiconductor, amorphous silicon, polycrystalline silicon, or an organic semiconductor. In an exemplary embodiment, a silicon-based semiconductor (e.g., amorphous silicon or polycrystalline silicon) may be used to form the first active layer 130. In an exemplary embodiment, the first active layer 130 may have a first source region, a first drain region, and a first channel region between the first source region and the first drain region.

[0130] The first gate insulating layer 150 may be disposed or formed in the first region 11 and the second region 12 on the buffer layer 115 and the first active layer 130. For example, in one exemplary embodiment, the first gate insulating layer 150 may be disposed or formed on the entire buffer layer 115. The first gate insulating layer 150 may fully cover the first active layer 130 on the buffer layer 115, and may have a substantially flat top surface without a step defined around the first active layer 130. Alternatively, the first gate insulating layer 150 may cover the first active layer 130 on the buffer layer 115, and may be formed along the contour of the first active layer 130 with a substantially uniform thickness. The first gate insulating layer 150 may be formed using a silicon compound, a metal oxide, or the like. For example, in one exemplary embodiment, the first gate insulating layer 150 may include SiO x 、SiN x 、SiO x N y 、SiO x C y 、SiC x N y 、AlO x 、AlN x 、TaO x , HfO x 、ZrO x or TiO x Alternatively, the first gate insulating layer 150 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0131] The first gate electrode 170 may be disposed or formed in the first region 11 on the first gate insulating layer 150. In such an embodiment, the first gate electrode 170 may be disposed or formed on a portion of the first gate insulating layer 150 under which the first active layer 130 is positioned (e.g., the first channel region). For example, the first gate electrode 170 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, or a transparent conductive material. For example, in an exemplary embodiment, the first gate electrode 170 may include Au, Ag, Al, Pt, Ni, Ti, Pd, Mg, Ca, Li, Cr, Ta, W, Cu, Mo, Sc, Nd, Ir, an aluminum alloy, AlN x , silver alloy, WN x , copper alloy, molybdenum alloy, TiN x CrN x 、TaN x 、SrRu x O y 、ZnO x 、ITO、SnO x 、InO x、GaO x Or IZO. These materials may be used alone or in combination with each other. Alternatively, the first gate electrode 170 may have a multilayer structure including a plurality of layers.

[0132] The second gate insulating layer 155 may be disposed or formed in the first region 11 and the second region 12 on the first gate insulating layer 150 and the first gate electrode 170. For example, in one exemplary embodiment, the second gate insulating layer 155 may be disposed or formed on the entire first gate insulating layer 150. The second gate insulating layer 155 may fully cover the first gate electrode 170 on the first gate insulating layer 150, and may have a substantially flat top surface without a step defined around the first gate electrode 170. Alternatively, the second gate insulating layer 155 may cover the first gate electrode 170 on the first gate insulating layer 150, and may be formed along the contour of the first gate electrode 170 with a substantially uniform thickness. For example, the second gate insulating layer 155 may be formed using a silicon compound or a metal oxide. Alternatively, the second gate insulating layer 155 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0133] A gate electrode pattern 180 may be disposed or formed in the first region 11 on the second gate insulating layer 155. In such an embodiment, the gate electrode pattern 180 may be disposed or formed on a portion of the second gate insulating layer 155 under which the first gate electrode 170 is positioned. For example, the gate electrode pattern 180 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, or a transparent conductive material. Alternatively, the gate electrode pattern 180 may have a multilayer structure including a plurality of layers.

[0134] Reference Figure 6 , a first insulating interlayer 190 may be disposed or formed in the first region 11 and the second region 12 on the second gate insulating layer 155 and the gate electrode pattern 180. For example, in one exemplary embodiment, the first insulating interlayer 190 may be disposed or formed on the entire second gate insulating layer 155. The first insulating interlayer 190 may fully cover the gate electrode pattern 180 on the second gate insulating layer 155, and may have a substantially flat top surface without a step defined around the gate electrode pattern 180. Alternatively, the first insulating interlayer 190 may cover the gate electrode pattern 180 on the second gate insulating layer 155, and may be formed along the contour of the gate electrode pattern 180 with a substantially uniform thickness. For example, the first insulating interlayer 190 may be formed using a silicon compound or a metal oxide. Alternatively, the first insulating interlayer 190 may have a multilayer structure having a plurality of insulating layers including materials different from each other.

[0135] The second active layer 135 may be disposed or formed in the second region 12 on the first insulating interlayer 190. The second active layer 135 may be formed using a metal oxide semiconductor. In such an embodiment, the second active layer 135 may be a semiconductor oxide layer including a binary compound, a ternary compound, or a quaternary compound including In, Zn, Ga, Sn, Ti, Al, Hf, Zr, Mg, etc. For example, in an exemplary embodiment, the second active layer 135 may include ZnO x 、GaO x 、TiO x SnO x 、InO x ,IGO,IZO,ITO,GZO,ZMO,ZTO,ZnZr x O y , IGZO, IZTO, IGHO, TAZO, or IGTO. In exemplary embodiments, the second active layer 135 may have a second source region, a second drain region, and a second channel region between the second source region and the second drain region.

[0136] The insulating pattern 160 may be disposed or formed on the second channel region of the second active layer 135. The insulating pattern 160 may be formed using silicon compounds, metal oxides, etc. Alternatively, the insulating pattern 160 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0137] The second gate electrode 175 may be disposed or formed on the insulating pattern 160. In such an embodiment, the second gate electrode 175 may be disposed or formed on the insulating pattern 160 of the second channel region under which the second active layer 135 is located. For example, the second gate electrode 175 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, or a transparent conductive material. Such materials may be used alone or in combination with each other. Alternatively, the second gate electrode 175 may have a multilayer structure including a plurality of layers.

[0138] Reference Figure 7, the second insulating interlayer 195 may be disposed or formed in the first region 11 and the second region 12 on the first insulating interlayer 190, the second active layer 135, the insulating pattern 160, and the second gate electrode 175. For example, in one exemplary embodiment, the second insulating interlayer 195 may be disposed or formed on the entire first insulating interlayer 190. The second insulating interlayer 195 may fully cover the second active layer 135, the insulating pattern 160, and the second gate electrode 175 on the first insulating interlayer 190, and may have a substantially flat top surface without forming a step around the second active layer 135, the insulating pattern 160, and the second gate electrode 175. Alternatively, the second insulating interlayer 195 may cover the second active layer 135, the insulating pattern 160, and the second gate electrode 175 on the first insulating interlayer 190, and may be formed along the contours of the second active layer 135, the insulating pattern 160, and the second gate electrode 175 with a substantially uniform thickness. For example, the second insulating interlayer 195 may be formed using a silicon compound or a metal oxide. Alternatively, the second insulating interlayer 195 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0139] A first source electrode 210 and a first drain electrode 230 may be disposed or formed in the first region 11 on the second insulating interlayer 195. The first source electrode 210 may be connected to the first source region of the first active layer 130 through a first contact hole formed by removing a first portion of the first gate insulating layer 150, a first portion of the second gate insulating layer 155, a first portion of the first insulating interlayer 190, and a first portion of the second insulating interlayer 195. In such an embodiment, the first drain electrode 230 may be connected to the first drain region of the first active layer 130 through a second contact hole formed by removing a second portion of the first gate insulating layer 150, a second portion of the second gate insulating layer 155, a second portion of the first insulating interlayer 190, and a second portion of the second insulating interlayer 195. For example, each of the first source electrode 210 and the first drain electrode 230 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, or a transparent conductive material. Such materials may be used alone or in combination with each other. In an alternative exemplary embodiment, each of the first source electrode 210 and the first drain electrode 230 may have a multi-layer structure including a plurality of layers.

[0140] Therefore, the driving transistor 250 including the first active layer 130, the first gate electrode 170, the first source electrode 210 and the first drain electrode 230 may be formed as described above. In such an embodiment, the driving transistor 250 may be used as a driving transistor including a silicon-based semiconductor. In such an embodiment, the driving transistor 250 may be used as a transistor having a top gate structure.

[0141] A second source electrode 215 and a second drain electrode 235 may be formed in the second region 12 on the second insulating interlayer 195. The second source electrode 215 may be connected to the second source region of the second active layer 135 by a third contact hole formed by removing a third portion of the second insulating interlayer 195. In such an embodiment, the second drain electrode 235 may be connected to the second drain region of the second active layer 135 by a fourth contact hole formed by removing a fourth portion of the second insulating interlayer 195. For example, each of the second source electrode 215 and the second drain electrode 235 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, or a transparent conductive material. Such materials may be used alone or in combination with one another. For example, in an exemplary embodiment, the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235 may be formed simultaneously using the same material. In an optional exemplary embodiment, each of the second source electrode 215 and the second drain electrode 235 may have a multilayer structure including a plurality of layers.

[0142] Thus, a switching transistor 255 including a second active layer 135, a second gate electrode 175, a second source electrode 215, and a second drain electrode 235 may be formed as described above. In such an embodiment, the switching transistor 255 may be used as a switching transistor including an oxide-based semiconductor. In such an embodiment, the switching transistor 255 may be used as a transistor having a top gate structure.

[0143] Reference Figure 8 , a protective insulating layer 400 may be disposed or formed in the first region 11 and the second region 12 on the second insulating interlayer 195, the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235. In such an embodiment, the protective insulating layer 400 may be disposed or formed on the entire second insulating interlayer 195. For example, in an exemplary embodiment, the protective insulating layer 400 may fully cover the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235 on the second insulating interlayer 195, and may have a substantially flat top surface without forming a step around the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235. Alternatively, the protective insulating layer 400 may cover the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235 on the second insulating interlayer 195, and may be formed to a substantially uniform thickness along the contours of the first source electrode 210, the first drain electrode 230, the second source electrode 215, and the second drain electrode 235. For example, a silicon compound or a metal oxide may be used to form the protective insulating layer 400. Alternatively, the protective insulating layer 400 may have a multi-layer structure having a plurality of insulating layers including materials different from each other.

[0144] The planarization layer 270 may be disposed or formed on the protective insulating layer 400. In such an embodiment, the planarization layer 270 may be disposed or formed on the entire protective insulating layer 400. For example, in one exemplary embodiment, the planarization layer 270 may have a relatively thick thickness to fully cover the protective insulating layer 400, and in such an embodiment, the planarization layer 270 may have a substantially flat top surface. In an exemplary embodiment, a planarization process may be additionally performed on the planarization layer 270 to achieve such a flat top surface of the planarization layer 270. The planarization layer 270 may be formed using an organic material.

[0145] The connection pattern 370 may be disposed or formed on the planarization layer 270. For example, the connection pattern 370 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. Such materials may be used alone or in combination with each other. Optionally, the connection pattern 370 may have a multilayer structure including a plurality of layers.

[0146] The light absorbing layer 350 may be disposed or formed on the planarization layer 270 and the connection pattern 370. In such an embodiment, the light absorbing layer 350 may be disposed or formed on the entire planarization layer 270. For example, in an exemplary embodiment, the light absorbing layer 350 may have a relatively thick thickness to fully cover the connection pattern 370. The light absorbing layer 350 may be formed using an organic material such as a photoresist, a polyacryl resin, a polyimide resin, a polyamide resin, a siloxane resin, or an epoxy resin. In such an embodiment, the light absorbing layer 350 may be substantially opaque. For example, in an exemplary embodiment, the light absorbing layer 350 may further include a light shielding material for absorbing external light. For example, the light shielding material may include carbon black, titanium oxynitride, titanium black, phenylene black, aniline black, cyanine black, nicroic acid black, or black resin.

[0147] Reference Fig. 9 , an organic insulating layer 275 may be disposed or formed on the light absorbing layer 350. For example, in one exemplary embodiment, the organic insulating layer 275 may have a relatively thick thickness (e.g., a first thickness T1) to fully cover the light absorbing layer 350, and in this case, the organic insulating layer 275 may have a substantially flat top surface. In an exemplary embodiment, a planarization process may be additionally performed on the organic insulating layer 275 to achieve such a flat top surface of the organic insulating layer 275. The organic insulating layer 275 may be formed using an organic material.

[0148] Reference Fig.10 and Fig.11, an exposure process using a mask may be performed. For example, in one exemplary embodiment, light may be irradiated to a first portion of the organic insulating layer 275 through an opening of the mask to form a first contact hole for exposing a portion of the top surface of the light absorbing layer 350, so that a first contact hole may be formed in the organic insulating layer 275. The first portion of the organic insulating layer 275 may overlap a portion of the light absorbing layer 350 where the connection pattern 370 is located.

[0149] Reference Fig.12 and Fig.13 , a dry etching process may be performed on the light absorbing layer 350. For example, in one exemplary embodiment, the second portion of the light absorbing layer 350 may be dry etched through the first contact hole to form a second contact hole for exposing a portion of the top surface of the connection pattern 370. In an exemplary embodiment, the second portion of the light absorbing layer 350 and the first portion of the organic insulating layer 275 may overlap each other, and the first contact hole and the second contact hole may overlap each other. In such an embodiment, during the dry etching process, the thickness of the organic insulating layer 275 may be reduced from the first thickness T1 to the second thickness T2.

[0150] In the method of manufacturing an organic light emitting diode display device, if the organic insulating layer 275 is not disposed or formed on the light absorbing layer 350, the second contact hole cannot be formed in the light absorbing layer 350. When an exposure process using a mask is performed to form the second contact hole, the light absorbing layer 350 including the light shielding material absorbs light, and thus the second contact hole cannot be formed in the light absorbing layer 350. Therefore, in an exemplary embodiment, after the organic insulating layer 275 having the first contact hole is formed on the light absorbing layer 350, a dry etching process is performed so that the second contact hole can be formed in the light absorbing layer 350.

[0151] Reference Fig.14 , a lower electrode 290 may be disposed or formed on the organic insulating layer 275. The lower electrode 290 may be connected to the connection pattern 370 through the first contact hole of the organic insulating layer 275 and the second contact hole of the light absorbing layer 350. For example, the lower electrode 290 may be formed using a metal, an alloy of a metal, a metal nitride, a conductive metal oxide, or a transparent conductive material. Such materials may be used alone or in combination with each other. Optionally, the lower electrode 290 may have a multilayer structure including a plurality of layers.

[0152] A pixel defining layer 310 may be formed on a portion of the lower electrode 290 and the organic insulating layer 275. The pixel defining layer 310 may cover both sides of the lower electrode 290 and may expose a portion of a top surface of the lower electrode 290. The pixel defining layer 310 may include an organic material or may be formed using an organic material.

[0153] The light-emitting layer 330 may be disposed or formed on the lower electrode 290 exposed by the pixel defining layer 310. The light-emitting layer 330 may be formed using at least one of the light-emitting materials for emitting different colors of light according to the sub-pixels. Alternatively, the light-emitting layer 330 may be formed by stacking a plurality of light-emitting materials for emitting different colors of light (such as red light, green light, or blue light), thereby emitting white light as a whole. In such an embodiment, a color filter may be disposed or formed on the light-emitting layer 330. The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may include a yellow color filter, a cyan color filter, and a magenta color filter. For example, a photosensitive resin or a colored photoresist may be used to form the color filter.

[0154] The upper electrode 340 may be disposed or formed on the pixel defining layer 310 and the light emitting layer 330. The upper electrode 340 may cover the light emitting layer 330 and the pixel defining layer 310, and may be integrally disposed or formed on the light emitting layer 330 and the pixel defining layer 310. For example, the upper electrode 340 may be formed using a metal, a metal alloy, a metal nitride, a conductive metal oxide, or a transparent conductive material. Such materials may be used alone or in combination with each other. Alternatively, the upper electrode 340 may have a multilayer structure including a plurality of layers.

[0155] Therefore, the sub-pixel structure 200 including the lower electrode 290 , the light emitting layer 330 , and the upper electrode 340 may be provided or formed as described above.

[0156] A first thin film encapsulation layer 451 may be disposed or formed on the upper electrode 340 in the light emitting region 30. The first thin film encapsulation layer 451 may cover the upper electrode 340 in the light emitting region 30, and may be formed along the contour of the upper electrode 340 with a uniform thickness. The first thin film encapsulation layer 451 may effectively prevent the sub-pixel structure 200 from being degraded due to the penetration of moisture, oxygen, etc. In such an embodiment, the first thin film encapsulation layer 451 may be used to protect the sub-pixel structure 200 from external impact. The first thin film encapsulation layer 451 may be formed using a flexible inorganic material.

[0157] A second thin film encapsulation layer 452 may be disposed or formed in the light emitting region 30 on the first thin film encapsulation layer 451. The second thin film encapsulation layer 452 may improve the flatness of the OLED display device 100 and may protect the sub-pixel structure 200. The second thin film encapsulation layer 452 may be formed using a flexible organic material.

[0158] A third thin film encapsulation layer 453 may be disposed or formed in the light emitting region 30 on the second thin film encapsulation layer 452. The third thin film encapsulation layer 453 may cover the second thin film encapsulation layer 452 in the light emitting region 30, and may be formed along the contour of the second thin film encapsulation layer 452 with a uniform thickness. The third thin film encapsulation layer 453 may effectively prevent the sub-pixel structure 200 from being degraded due to the penetration of moisture, oxygen, etc. together with the first thin film encapsulation layer 451. In such an embodiment, the third thin film encapsulation layer 453 may be used together with the first thin film encapsulation layer 451 and the second thin film encapsulation layer 452 to protect the sub-pixel structure 200 from external impact. A flexible inorganic material may be used to form the third thin film encapsulation layer 453. Alternatively, an encapsulation substrate may be disposed or formed on the upper electrode 340 instead of the thin film encapsulation structure 450. For example, a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped quartz substrate, a soda-lime glass substrate, or an alkali-free glass substrate may be used to form the encapsulation substrate.

[0159] Therefore, as described above, a thin film encapsulation structure 450 including a first thin film encapsulation layer 451, a second thin film encapsulation layer 452, and a third thin film encapsulation layer 453 may be provided or formed. Alternatively, the thin film encapsulation structure 450 may have a five-layer structure formed by stacking the first to fifth thin film encapsulation layers or a seven-layer structure formed by stacking the first to seventh thin film encapsulation layers.

[0160] After forming the thin film encapsulation structure 450, the glass substrate 105 may be removed from the substrate 110, and the Figure 4 The OLED display device 100 is shown in FIG.

[0161] In an exemplary embodiment of a method of manufacturing an organic light emitting diode display device according to the invention, a second contact hole may be formed in the light absorbing layer 350 by forming an organic insulating layer 275 having a first contact hole on the light absorbing layer 350. Therefore, the organic light emitting diode display device 100 includes the light absorbing layer 350, so that light incident on the second active layer 135 may be blocked.

[0162] In an alternative exemplary embodiment, when Fig. 9 When the first thickness T1 of the organic insulating layer 275 is relatively small, during the dry etching process, Fig.15 275 is completely removed from the light absorbing layer 350. In such an embodiment, Fig.16 As shown in , the organic light emitting diode display device may not include the organic insulating layer 275. In such an embodiment, the top surface of the light absorbing layer 350 may directly contact the bottom surface of the pixel defining layer 310 and the bottom surface of the lower electrode 290.

[0163] Fig.173 is a cross-sectional view showing an organic light emitting diode display device according to an alternative exemplary embodiment of the invention. In addition to the first light absorbing layer 355 and the second light absorbing layer 350, Fig.17 The OLED display device 500 shown in FIG. Figures 1 to 4 The configuration of the OLED display device 100 described above is substantially the same as or similar to that of the OLED display device 100. Figures 1 to 4 Any repetition of elements described is described in detail as being substantially the same or similar.

[0164] Reference Fig.17 An exemplary embodiment of an OLED display device 500 may include a substrate 110, a buffer layer 115, a driving transistor 250, a switching transistor 255, a gate electrode pattern 180, a first gate insulating layer 150, a second gate insulating layer 155, a first insulating interlayer 190, an insulating pattern 160, a second insulating interlayer 195, a protective insulating layer 400, a first light absorbing layer 355, a planarizing layer 270, a connecting pattern 370, a second light absorbing layer 350, an organic insulating layer 275, a sub-pixel structure 200, a pixel defining layer 310, a thin film encapsulation structure 450, and the like.

[0165] The first light absorbing layer 355 may be disposed on the protective insulating layer 400. In such an embodiment, the first light absorbing layer 355 may be disposed on the entire protective insulating layer 400. In an exemplary embodiment, the first light absorbing layer 355 may effectively prevent external light penetrating into the OLED display device 500 from being incident on the second active layer 135, and may prevent a portion of the light emitted from the light emitting layer 330 from being reflected from the upper electrode 340 and incident on the second active layer 135. The first light absorbing layer 355 may include an organic material such as a photoresist, a polyacryl resin, a polyimide resin, a polyamide resin, a siloxane resin, or an epoxy resin. In such an embodiment, the first light absorbing layer 355 may be substantially opaque. For example, in an exemplary embodiment, the first light absorbing layer 355 may also include a light shielding material for absorbing external light. For example, the light shielding material may include carbon black, titanium oxynitride, titanium black, phenylene black, aniline black, cyanine black, nicroic acid black, or black resin.

[0166] The planarization layer 270 may be disposed on the first light absorbing layer 355. In such an embodiment, the planarization layer 270 may be disposed on the entire first light absorbing layer 355. For example, in an exemplary embodiment, the planarization layer 270 may have a relatively thick thickness to fully cover the first light absorbing layer 355, and in such an embodiment, the planarization layer 270 may have a substantially flat top surface. In such an embodiment, a planarization process may be additionally performed on the planarization layer 270 to achieve such a flat top surface of the planarization layer 270. The planarization layer 270 may include an organic material or an inorganic material. In an exemplary embodiment, the planarization layer 270 may include an organic material.

[0167] The second light absorbing layer 350 may be disposed on a portion of the connection pattern 370 and the planarization layer 270. The second light absorbing layer 350 may cover both sides of the connection pattern 370, and may have a contact hole for exposing a portion of the top surface of the connection pattern 370. In an exemplary embodiment, the second light absorbing layer 350 may effectively prevent external light penetrating into the OLED display device 500 from being incident on the second active layer 135, and may prevent a portion of light emitted from the light emitting layer 330 from being reflected from the upper electrode 340 and incident on the second active layer 135. The second light absorbing layer 350 may include the same material as that of the first light absorbing layer 355.

[0168] An exemplary embodiment of the OLED display device 500 according to the invention includes a first light absorbing layer 355 and a second light absorbing layer 350 for absorbing light, so that a portion of external light penetrating into the OLED display device 500 and light emitted from the light emitting layer 330 can be effectively absorbed or substantially completely absorbed. In such an embodiment, Figure 4 A single light absorbing layer of the OLED display device 100 may absorb about 90% of light incident on the light absorbing layer. In an alternative exemplary embodiment, Fig.17 The OLED display device 500 including two light absorbing layers can absorb substantially all (e.g., about 100%) of the light incident on the light absorbing layer. Therefore, the OLED display device 500 can protect the second active layer 135 including the oxide-based semiconductor, and the characteristics of the switching transistor 255 including the second active layer 135 are not changed.

[0169] Exemplary embodiments of the invention may be applied to various display devices including an OLED display device, for example, a vehicle display device, a ship display device, an aircraft display device, a portable communication device, a display device for display or for information transmission, a medical display device, etc.

[0170] The invention should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

[0171] While the invention has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. An organic light emitting diode display device, comprising: a substrate comprising a first region and a second region; a driving transistor, disposed in the first region on the substrate; a switching transistor disposed in the second region on the substrate and comprising a metal oxide-based semiconductor; A planarization layer, disposed on the driving transistor and the switching transistor; A first light absorbing layer is directly disposed on the planarization layer; an organic insulating layer, directly disposed on the first light absorbing layer; as well as A sub-pixel structure is arranged on the organic insulating layer, The organic light emitting diode display device further includes a connection pattern disposed between the planarization layer and the first light absorbing layer and directly contacting the planarization layer and the first light absorbing layer, and The connection pattern is electrically connected to the lower electrode of the sub-pixel structure through a contact hole defined by passing through a portion of the first light absorbing layer and a portion of the organic insulating layer.

2. The organic light emitting diode display device according to claim 1, wherein: Each of the driving transistor and the switching transistor has a top gate structure.

3. The organic light emitting diode display device according to claim 1, wherein: The driving transistor comprises: A first active layer including a first source region, a first drain region and a first channel region; a first gate electrode, overlapping the first channel region on the first active layer; a first source electrode disposed on the first gate electrode and connected to the first source region; and a first drain electrode disposed on the first gate electrode and connected to the first drain region, and The first active layer includes a silicon-based semiconductor.

4. The organic light emitting diode display device according to claim 3, wherein: The switching transistor comprises: A second active layer including a second source region, a second drain region and a second channel region; a second gate electrode, overlapping the second channel region on the second active layer; a second source electrode disposed on the second gate electrode and connected to the second source region; and a second drain electrode disposed on the second gate electrode and connected to the second drain region, and The second active layer includes the metal oxide-based semiconductor.

5. The organic light emitting diode display device according to claim 4, further comprising: An insulating pattern is disposed between the second active layer and the second gate electrode.

6. The organic light emitting diode display device according to claim 4, further comprising: a first gate insulating layer, disposed on the substrate to cover the first active layer in the first region; as well as A second gate insulating layer is disposed on the first gate insulating layer to cover the first gate electrode in the first region.

7. The organic light emitting diode display device according to claim 6, wherein: The driving transistor further includes a gate electrode pattern overlapping the first gate electrode on the second gate insulating layer.

8. The organic light emitting diode display device according to claim 7, further comprising: a first insulating interlayer, disposed on the second gate insulating layer to cover the gate electrode pattern in the first region; as well as a second insulating interlayer, disposed on the first insulating interlayer to cover the second active layer and the second gate electrode in the second region, The first source electrode, the first drain electrode, the second source electrode and the second drain electrode are arranged on the second insulating intermediate layer.

9. The organic light emitting diode display device according to claim 8, further comprising: a protective insulating layer, disposed on the second insulating intermediate layer to cover the first source electrode, the first drain electrode, the second source electrode and the second drain electrode, Wherein, the planarization layer is arranged on the protective insulating layer.

10. The organic light emitting diode display device according to claim 9, wherein: The sub-pixel structure comprises: the lower electrode; a light-emitting layer, disposed on the lower electrode; and The upper electrode is arranged on the light-emitting layer.

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