Silicon carbide epitaxial wafer and processing method thereof in preparation of silicon carbide power device

Abstract

The present invention provides a silicon carbide epitaxial wafer and a processing method thereof in the preparation of a silicon carbide power device, wherein dielectric layers are deposited on the front and back of the silicon carbide epitaxial wafer respectively; the dielectric layer on the front of the silicon carbide epitaxial wafer is etched, and then the dielectric layer on the back of the silicon carbide epitaxial wafer is removed; and ion implantation is performed on the front of the etched silicon carbide epitaxial wafer. The present invention greatly reduces the warpage of the silicon carbide epitaxial wafer, reduces the rejection rate, improves the photolithography process accuracy and ion implantation processing accuracy, reduces the rejection rate and fragmentation rate of ion implantation, and greatly improves the accuracy and qualified rate of the silicon carbide epitaxial wafer; separate dielectric layers are formed step by step on the front and back of the silicon carbide epitaxial wafer, offsetting the material stress caused by the direct deposition of the dielectric layer on the front of the silicon carbide epitaxial wafer, and providing a basis for improving the warpage of the silicon carbide epitaxial wafer; the cost is low, the efficiency is high, and it is suitable for silicon carbide epitaxial wafers of various specifications.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to a silicon carbide epitaxial wafer and a processing method thereof in the preparation of a silicon carbide power device. Background Art

[0002] The electrical parameters of the third-generation semiconductor silicon carbide (SiC) material and the traditional silicon (Si)-based semiconductor substrate material are very different. SiC material has a large thermal conductivity, a wide band gap, a high electron saturation velocity and breakdown voltage, and a low dielectric constant. These characteristics determine its application potential in high-temperature, high-frequency, and high-power semiconductor devices. The current research and development focus in the semiconductor field has gradually shifted to silicon carbide materials. The physical parameters of silicon carbide materials and silicon materials are quite different. Since the diffusion coefficient of SiC materials themselves is very low, the traditional ion diffusion process does not cause a significant change in the concentration of silicon carbide materials after high-temperature doping. In actual processes, it is impossible to selectively dope SiC materials through thermal diffusion methods. Even if ion implantation is used, silicon carbide materials need to be implanted at high temperatures, which is conducive to obtaining a higher ionization rate and can also repair lattice damage. Therefore, high-temperature ion implantation has become the preferred means of selective doping on SiC.

[0003] In the preparation of SiC devices, the SiC element doping, i.e., ion implantation process, is as follows: a layer of SiO2 film is deposited on the surface of the SiC epitaxial wafer by the plasma enhanced chemical vapor deposition (PECVD) method, and then a mesa pattern is formed by photolithography, and the pattern is transferred to the SiO2 mask by etching. After removing the photoresist, the SiC epitaxial wafer is subjected to high-temperature ion implantation using the SiO2 pattern as a mask. The preparation of silicon carbide power devices by the above process requires the use of silicon carbide epitaxial wafers with thicker epitaxial layers and thicker dielectric films as masking layers. However, the thick mask has greater stress, which can easily cause the epitaxial wafer to warp, affecting the transfer and processing accuracy of the photolithography process; in addition, the high-temperature and high-energy ion implantation process can easily introduce stress, which in turn causes the epitaxial wafer to warp during the ion implantation process, resulting in reduced processing accuracy and the risk of fragmentation.

[0004] The prior art usually places the prepared silicon carbide epitaxial wafer into a reaction chamber, keeps it at 650-1050°C for 10-30 minutes, then cools it down to ≤300°C in 10-15 minutes, and takes the silicon epitaxial wafer out of the reaction chamber. In this way, the warpage of the silicon carbide epitaxial wafer is reduced by high-temperature annealing. However, the warpage of the silicon carbide epitaxial wafer is still large, and the rejection rate is high. Summary of the invention

[0005] In order to overcome the shortcomings of the silicon carbide epitaxial wafer in the prior art, such as large warpage and high rejection rate, the present invention provides a method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices, comprising:

[0006] Depositing dielectric layers on the front and back sides of the silicon carbide epitaxial wafer respectively;

[0007] Etching the dielectric layer on the front side of the silicon carbide epitaxial wafer, and then removing the dielectric layer on the back side of the silicon carbide epitaxial wafer;

[0008] Ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer.

[0009] The method of depositing dielectric layers on the front and back sides of the silicon carbide epitaxial wafer comprises:

[0010] Depositing a first dielectric layer on the front side of the silicon carbide epitaxial wafer;

[0011] After a preset time has passed since the first dielectric layer was formed, a second dielectric layer is deposited on the back of the silicon carbide epitaxial wafer;

[0012] A third dielectric layer is deposited on the front side of the silicon carbide epitaxial wafer a preset time after the first dielectric layer is formed.

[0013] The etching of the dielectric layer on the front side of the silicon carbide epitaxial wafer and then removing the dielectric layer on the back side of the silicon carbide epitaxial wafer comprises:

[0014] Coating a photoresist outside the third dielectric layer on the front side of the silicon carbide epitaxial wafer, and performing a patterning process on the photoresist;

[0015] Using the patterned photoresist as a mask, etching the front side of the silicon carbide epitaxial wafer, and removing the photoresist;

[0016] Coating a photoresist on the front side of the silicon carbide epitaxial wafer;

[0017] The second dielectric layer on the back side of the silicon carbide epitaxial wafer is wet-etched.

[0018] After removing the dielectric layer on the back side, the method further comprises:

[0019] Remove the photoresist on the front side of the silicon carbide epitaxial wafer.

[0020] The ion implantation into the front side of the etched silicon carbide epitaxial wafer comprises:

[0021] Determine the ion implantation dose and ion implantation temperature;

[0022] Based on the dosage and temperature, ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer.

[0023] After the ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer, the method further comprises:

[0024] The third dielectric layer and the first dielectric layer are removed.

[0025] The deposition adopts a plasma enhanced chemical vapor deposition method or a low pressure chemical vapor deposition method.

[0026] The first dielectric layer, the second dielectric layer and the third dielectric layer are all made of silicon dioxide, silicon nitride and polysilicon, or a combination of at least two of them.

[0027] The thickness of the first dielectric layer is 0.2 μm to 10 μm;

[0028] The thickness of the second dielectric layer is 0.2 μm to 10 μm;

[0029] The thickness of the third dielectric layer is 0.2 μm to 6 μm.

[0030] The ion implantation dose is 1E11cm -2 ~1E18cm -2 ;

[0031] The ion implantation temperature is 25°C to 600°C.

[0032] Before the dielectric layers are deposited on the front and back sides of the silicon carbide epitaxial wafer respectively, the method comprises:

[0033] The silicon carbide epitaxial wafer is cleaned by using an RCA standard cleaning method to remove metals, organic matter and pollutants on the surface of the silicon carbide epitaxial wafer.

[0034] The present invention also provides a silicon carbide epitaxial wafer in the preparation of a silicon carbide power device, comprising: a front side of the silicon carbide epitaxial wafer and a back side of the silicon carbide epitaxial wafer;

[0035] The front side of the silicon carbide epitaxial wafer and the back side of the silicon carbide epitaxial wafer are obtained according to the processing methods respectively.

[0036] Compared with the closest prior art, the technical solution provided by the present invention has the following beneficial effects:

[0037] In the method for processing a silicon carbide epitaxial wafer in the preparation of a silicon carbide power device provided by the present invention, dielectric layers are deposited on the front and back of the silicon carbide epitaxial wafer respectively; the dielectric layer on the front of the silicon carbide epitaxial wafer is etched, and then the dielectric layer on the back of the silicon carbide epitaxial wafer is removed; ion implantation is performed on the front of the etched silicon carbide epitaxial wafer, thereby greatly reducing the warpage of the silicon carbide epitaxial wafer and reducing the rejection rate;

[0038] The processing method provided by the present invention improves the photolithography process accuracy and ion implantation processing accuracy, reduces the rejection rate and fragmentation rate of ion implantation, and greatly improves the accuracy and qualified rate of silicon carbide epitaxial wafers;

[0039] The processing method provided by the present invention forms respective dielectric layers on the front and back of the silicon carbide epitaxial wafer in steps, that is, firstly depositing the first dielectric layer on the front of the silicon carbide epitaxial wafer, then depositing the second dielectric layer on the back of the silicon carbide epitaxial wafer, and finally depositing the third dielectric layer on the front of the silicon carbide epitaxial wafer, thereby offsetting the material stress caused by directly depositing the dielectric layer on the front, and providing a basis for improving the warpage of the silicon carbide epitaxial wafer;

[0040] After the third dielectric layer and the first dielectric layer are etched in the technical solution provided by the present invention, the stress on the front side of the silicon carbide epitaxial wafer is released, and the second dielectric layer on the back side becomes the main factor causing the warping of the silicon carbide epitaxial wafer. The front side of the silicon carbide epitaxial wafer is protected by coating photoresist on the front side of the silicon carbide epitaxial wafer to prevent the front side of the silicon carbide epitaxial wafer from being corroded, and the second dielectric layer on the back side of the silicon carbide epitaxial wafer is wet-etched, thereby effectively reducing the warping degree of the silicon carbide epitaxial wafer.

[0041] The invention provides low cost and high efficiency and is applicable to silicon carbide epitaxial wafers of various specifications. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a flow chart of a method for processing a silicon carbide epitaxial wafer in the preparation of a silicon carbide power device in an embodiment of the present invention;

[0043] Figure 2 is a schematic diagram of depositing a first dielectric layer on the front side of a silicon carbide epitaxial wafer in an embodiment of the present invention;

[0044] Figure 3 is a schematic diagram of depositing a second dielectric layer on the back side of a silicon carbide epitaxial wafer in an embodiment of the present invention;

[0045] Figure 4 is a schematic diagram of depositing a third dielectric layer on the front side of a silicon carbide epitaxial wafer in an embodiment of the present invention;

[0046] Figure 5 is a schematic diagram of coating photoresist on the front side of the third dielectric layer in an embodiment of the present invention;

[0047] Figure 6 is a schematic diagram of patterning photoresist in an embodiment of the present invention;

[0048] Figure 7 is a schematic diagram of etching the front side of a silicon carbide epitaxial wafer using a patterned photoresist as a mask in an embodiment of the present invention;

[0049] Figure 8Schematic diagram of removing photoresist after etching the front side of a silicon carbide epitaxial wafer in an embodiment of the present invention;

[0050] Fig. 9 is a schematic diagram of coating photoresist on the front side of a silicon carbide epitaxial wafer in an embodiment of the present invention;

[0051] Fig.10 is a schematic diagram of wet etching the second dielectric layer in an embodiment of the present invention;

[0052] Fig.11 is a schematic diagram of removing the photoresist after wet etching the second dielectric layer in an embodiment of the present invention;

[0053] Fig.12 is a schematic diagram of ion implantation into the front side of an etched silicon carbide epitaxial wafer in an embodiment of the present invention;

[0054] Fig.13 is a schematic diagram of a silicon carbide epitaxial wafer obtained after removing the third dielectric layer and the first dielectric layer in an embodiment of the present invention;

[0055] In the figure, 1, silicon carbide epitaxial wafer, 2, first dielectric layer, 3, sample obtained after coating the first dielectric layer, 4, second dielectric layer, 5, sample obtained after coating the second dielectric layer, 6, third dielectric layer, 7, sample obtained after coating the third dielectric layer, 8, photoresist coated on sample 7, 9, sample obtained after patterning photoresist 8, 10, sample obtained after etching the front side of the silicon carbide epitaxial wafer using the patterned photoresist as a mask, 11, sample obtained after removing photoresist 8, 12, photoresist coated on the front side of the silicon carbide epitaxial wafer before removing the dielectric layer on the back side, 13, sample after coating photoresist 12, 14, sample obtained by wet etching the second dielectric layer, 15, sample obtained by removing photoresist 12, 16, sample obtained by ion implantation into the front side of the etched silicon carbide epitaxial wafer. DETAILED DESCRIPTION

[0056] The present invention will be further described in detail below in conjunction with the accompanying drawings.

[0057] The embodiment of the present invention provides a method for processing a silicon carbide epitaxial wafer in the preparation of a silicon carbide power device. The specific flow chart is as follows: Figure 1 As shown, the specific process is as follows:

[0058] S101: depositing dielectric layers on the front and back sides of the silicon carbide epitaxial wafer 1 respectively;

[0059] S102: etching the dielectric layer on the front side of the silicon carbide epitaxial wafer 1, and then removing the dielectric layer on the back side of the silicon carbide epitaxial wafer 1;

[0060] S103: performing ion implantation on the front side of the etched silicon carbide epitaxial wafer 1.

[0061] Before the dielectric layers are deposited on the front and back sides of the silicon carbide epitaxial wafer 1, the silicon carbide epitaxial wafer 1 needs to be cleaned using the RCA standard cleaning method to remove metals, organic matter and pollutants on the surface of the silicon carbide epitaxial wafer 1. The specific cleaning process is as follows:

[0062] The silicon carbide epitaxial wafer 1 is immersed in the SC1 cleaning solution, and a hydrofluoric acid solution (HF:H2O=1:10) is prepared first, and then the sample holder is cleaned and blown dry, and the sample 3 is placed on the holder.

[0063] Prepare liquid 3# (sulfuric acid: H2O2=3:1). It should be noted that sulfuric acid should be added last, and water should be boiled in another container at the same time. After liquid 3# is prepared, put sample 3 into liquid 3# and boil it for about 15 minutes, then take it out; heat sample 3 to 250℃, pick up the bracket containing sample 3 and let it cool for a while, then put the bracket into hot water and rinse it.

[0064] Prepare liquid 1# (ammonia water: H2O2: H2O=1:1:5-1:1:7): ​​pour the first two into hot water and heat to 75-85°C for about 10-20 minutes; then put the bracket containing sample 3 into liquid 1# for about 15 minutes, then take out the bracket and put it into hot water for flushing.

[0065] Prepare liquid 2# (HCl: H2O2: H2O = 1:1:5): Pour the first two into hot water. After the preparation is completed, take out the bracket containing sample 3 and put it into liquid 2# for about 15 minutes. Then take out the bracket, put it into hot water and rinse it.

[0066] The sample 3 was rinsed with 10% hydrofluoric acid for about 5 to 30 seconds to remove the oxide layer on the surface of the sample 3. Then, the sample was rinsed with deionized water for about 20 minutes.

[0067] After the sample is cleaned by the RCA cleaning method, a dielectric layer is deposited on the front and back sides of the silicon carbide epitaxial wafer 1, respectively, which specifically includes:

[0068] A first dielectric layer 2 is deposited on the front side of the silicon carbide epitaxial wafer 1, such as Figure 2 As shown, we get Figure 2 In sample 3, the thickness of the first dielectric layer 2 is 0.2μm to 10μm; the first dielectric layer 2 deposited on the front side in the embodiment of the present invention is a 1.5μm SiO2 film; the first dielectric layer 2 deposited on the front side of the silicon carbide epitaxial wafer 1 can protect the front side of the silicon carbide epitaxial wafer 1 to prevent contamination and scratches and other effects on the epitaxy; and multiple film formations can avoid the stress influence of directly growing thick films, effectively controlling the warping of the silicon carbide epitaxial wafer 1.

[0069] After a preset time after the first dielectric layer 2 is formed, a second dielectric layer 4 is deposited on the back of the silicon carbide epitaxial wafer 1. Figure 3 As shown, we get Figure 3 Sample 5 in the sample; after the first dielectric layer 2 on the front side is formed, it is necessary to deposit the second dielectric layer 4 on the back side of the silicon carbide epitaxial wafer 1 as soon as possible. In this embodiment, within 15 minutes after the first dielectric layer 2 is formed, the second dielectric layer 4 is deposited on the back side of the silicon carbide epitaxial wafer 1. The thickness of the second dielectric layer 4 is 0.2 μm to 10 μm. In this embodiment of the present invention, the second dielectric layer 4 is a 2.5 μm SiO2 film;

[0070] After a preset time after the first dielectric layer 2 is formed, a third dielectric layer 6 is deposited on the front side of the silicon carbide epitaxial wafer 1. Figure 4 As shown, we get Figure 4 In sample 7, the thickness of the third dielectric layer 6 is 0.2 μm to 6 μm. In this embodiment, the third dielectric layer 6 is a 1 μm SiO2 film.

[0071] The above-mentioned deposited dielectric layer can be deposited by plasma enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD). The embodiment of the present invention uses PECVD to deposit the first dielectric layer 2, the second dielectric layer 4 and the third dielectric layer 6. The deposition of the third dielectric layer 6 meets the requirements of high temperature and high energy ion implantation thin film masking.

[0072] The above S101 forms two dielectric layers on the front side in two times. Alternatively, a thicker dielectric layer may be deposited on the front side and then another dielectric layer may be deposited on the back side. When a dielectric layer is deposited on the front side and the back side respectively, the thickness of the dielectric layer deposited on the front side may be 0.2 μm to 3 μm, and the thickness of the dielectric layer deposited on the back side may be 0.2 μm to 10 μm. Regardless of whether the dielectric layer on the front side is deposited once or twice, the dielectric layer deposited on the back side is used to balance the warpage of the silicon carbide wafer caused by the deposition of the dielectric layer on the front side.

[0073] The dielectric layer on the front side of the silicon carbide epitaxial wafer 1 is etched, and then the dielectric layer on the back side of the silicon carbide epitaxial wafer 1 is removed, including:

[0074] A photoresist 8 is coated on the third dielectric layer 6 on the front side of the silicon carbide epitaxial wafer 1. Figure 5 As shown; then the photoresist 8 is patterned, as shown Figure 6 As shown, we get Figure 6Sample 9 in the embodiment of the present invention; before coating the photoresist 8 on the front of the third dielectric layer 6, a layer of HMDS (i.e., hexamethyldisilazane) adhesion promoter is coated on the front of the sample, the model of the photoresist 8 is AZ703, and any other positive photoresist can also be used, and the photoresist 8 is coated by a fully automatic coating method or a manual coating method. The graphic processing process includes vapor phase base film (HMDS), coating, pre-baking, exposure, post-baking, development, hard film and development inspection.

[0075] The front side of the silicon carbide epitaxial wafer 1 is etched using the patterned photoresist as a mask. Figure 7 As shown, we get Figure 7 Sample 10 in the embodiment and remove the photoresist, as Figure 8 As shown, sample 11 is obtained; the front side of the silicon carbide epitaxial wafer 1 is dry-etched or wet-etched using the patterned photoresist as a mask to obtain an ion implantation masking pattern, while reducing the influence of the front dielectric layer stress on the warpage of the silicon carbide epitaxial wafer.

[0076] A photoresist 12 is coated on the front side of the silicon carbide epitaxial wafer 1, such as Fig. 9 As shown, sample 13 was obtained;

[0077] The second dielectric layer 4 on the back side of the silicon carbide epitaxial wafer 1 is wet-etched. Fig.10 As shown, a sample 14 is obtained, and then the photoresist 12 is removed, as shown in FIG. Fig.11 As shown, sample 15 is obtained. In the embodiment of the present invention, a layer of HMDS (i.e., hexamethyldisilazane) adhesion promoter is coated on the front of sample 11, and then photoresist 12 is coated on the front of silicon carbide epitaxial wafer 1. In the embodiment of the present invention, BOE etching solution is used to wet-etch the second dielectric layer 4, that is, BOE etching solution is used to remove the second dielectric layer 4 on the back.

[0078] Ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer 1, including:

[0079] Determine the ion implantation dose and ion implantation temperature;

[0080] Based on the dose and temperature, ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer 1, such as Fig.12 As shown, sample 16 was obtained; the ion implantation dose was 1E11cm -2 ~1E18cm -2 ; The ion implantation temperature is 25℃~600℃, and the type of implanted ions is not limited;

[0081] After ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer 1, the third dielectric layer 6 and the first dielectric layer 2 are removed to obtain the processed silicon carbide epitaxial wafer 1, as shown in FIG. Fig.13 shown.

[0082] The first dielectric layer 2 , the second dielectric layer 4 and the third dielectric layer 6 are all made of one or a combination of at least two of silicon dioxide, silicon nitride and polysilicon.

[0083] The diameter of the silicon carbide epitaxial wafer used in the embodiment of the present invention is 100 mm, 150 mm, 200 mm or more, and its thickness is 0 to 200 μm. The silicon carbide epitaxial wafer 1 is processed by the processing method of the silicon carbide epitaxial wafer 1 in the preparation of the silicon carbide power device provided in the embodiment of the present invention to obtain the front side of the silicon carbide epitaxial wafer and the back side of the silicon carbide epitaxial wafer; the warpage of the silicon carbide epitaxial wafer after processing is greatly reduced, and the rejection rate is low.

[0084] For the convenience of description, the various parts of the above device are divided into various modules or units according to their functions and described separately. Of course, when implementing the present application, the functions of each module or unit can be implemented in the same or multiple software or hardware.

[0085] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

[0086] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0087] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0088] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention rather than to limit it. Ordinary technicians in the relevant field can still modify or make equivalent substitutions to the specific implementation methods of the present invention with reference to the above embodiments. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention are within the protection scope of the present invention to be approved.

Claims

1. A method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices, characterized in that: include: Depositing dielectric layers on the front and back sides of the silicon carbide epitaxial wafer respectively; Etching the dielectric layer on the front side of the silicon carbide epitaxial wafer, and then removing the dielectric layer on the back side of the silicon carbide epitaxial wafer; Performing ion implantation on the front side of the etched silicon carbide epitaxial wafer; The method of depositing dielectric layers on the front and back sides of the silicon carbide epitaxial wafer comprises: Depositing a first dielectric layer on the front side of the silicon carbide epitaxial wafer; After a preset time has passed since the first dielectric layer was formed, a second dielectric layer is deposited on the back of the silicon carbide epitaxial wafer; After a preset time has passed since the first dielectric layer was formed, a third dielectric layer is deposited on the front side of the silicon carbide epitaxial wafer; The first dielectric layer, the second dielectric layer and the third dielectric layer are all made of silicon dioxide, silicon nitride and polysilicon, or a combination of at least two of them.

2. The method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices according to claim 1, characterized in that: The etching of the dielectric layer on the front side of the silicon carbide epitaxial wafer and then removing the dielectric layer on the back side of the silicon carbide epitaxial wafer comprises: Coating a photoresist outside the third dielectric layer on the front side of the silicon carbide epitaxial wafer, and performing a patterning process on the photoresist; Using the patterned photoresist as a mask, etching the front side of the silicon carbide epitaxial wafer, and removing the photoresist; Coating a photoresist on the front side of the silicon carbide epitaxial wafer; The second dielectric layer on the back side of the silicon carbide epitaxial wafer is wet-etched.

3. The method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices according to claim 2, characterized in that: After removing the dielectric layer on the back side, the method further comprises: Remove the photoresist on the front side of the silicon carbide epitaxial wafer.

4. The method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices according to claim 2, characterized in that: The ion implantation into the front side of the etched silicon carbide epitaxial wafer comprises: Determine the ion implantation dose and ion implantation temperature; Based on the dosage and temperature, ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer.

5. The method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices according to claim 4, characterized in that: After the ion implantation is performed on the front side of the etched silicon carbide epitaxial wafer, the method further comprises: The third dielectric layer and the first dielectric layer are removed.

6. The method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices according to claim 1, characterized in that: The deposition adopts a plasma enhanced chemical vapor deposition method or a low pressure chemical vapor deposition method.

7. The method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices according to claim 1, characterized in that: The thickness of the first dielectric layer is 0.2 μm to 10 μm; The thickness of the second dielectric layer is 0.2 μm to 10 μm; The thickness of the third dielectric layer is 0.2 μm to 6 μm.

8. The method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices according to claim 4, characterized in that: The ion implantation dose is 1E11cm -2 ~1E18cm -2 ; The ion implantation temperature is 25°C to 600°C.

9. The method for processing silicon carbide epitaxial wafers in the preparation of silicon carbide power devices according to claim 1, characterized in that: Before the dielectric layers are deposited on the front and back sides of the silicon carbide epitaxial wafer respectively, the method comprises: The silicon carbide epitaxial wafer is cleaned by using an RCA standard cleaning method to remove metals, organic matter and pollutants on the surface of the silicon carbide epitaxial wafer.

10. A silicon carbide epitaxial wafer in the preparation of a silicon carbide power device, characterized in that: include: The front side of silicon carbide epitaxial wafer and the back side of silicon carbide epitaxial wafer; The front side of the silicon carbide epitaxial wafer and the back side of the silicon carbide epitaxial wafer are obtained according to the processing method described in any one of claims 1 to 7.

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