Scan driver and display device including the same

Abstract

Disclosed are a scan driver and a display device including the scan driver. The scan driver includes two or more scan signal output circuits each coupled to a first scan line and a second scan line and including a drive circuit, a first buffer circuit, and a second buffer circuit. The drive circuit applies a first drive signal to a first drive node and a second drive signal to a second drive node based on an input signal, a clock signal, a display conduction signal, and a conduction level signal. The input signal is a scan start signal or a previous scan signal. The first buffer circuit outputs a sensing signal to the second scan line based on the first drive signal, the second drive signal, an off-level voltage, and a sensing clock signal. The second buffer circuit outputs a scan signal to the first scan line based on the first drive signal, the second drive signal, an off-level voltage, and a scan clock signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0014603, filed on February 7, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Example embodiments relate to a scan driver and a display device including the scan driver. Background Art

[0004] Generally, a display device may include a display panel, a scan driver, a data driver, a timing controller, etc. The scan driver may provide a scan signal (which may be composed of a scan start signal and a scan off signal) to the display panel through a scan line. For this operation, the scan driver may include and operate a scan signal output circuit, wherein the scan signal output circuits are sequentially coupled to each other and each is composed of a free oxide thin film transistor.

[0005] Some display devices can compensate for degradation of a pixel or a change in pixel characteristics (e.g., a change in characteristics depending on temperature, etc.) by sensing mobility information of a driving transistor included in a pixel circuit or degradation information of a light-emitting element. In this case, the scan driver can generate and output scan signals for a display operation, a mobility sensing operation, and an operation of sensing degradation of a light-emitting element.

[0006] The above information disclosed in this section is only for background understanding of the inventive concept and therefore it may contain information that does not form the prior art. Summary of the invention

[0007] Some example embodiments relate to a scan driver capable of accurately sensing mobility and degradation of a light emitting element, for example, when a display device is in a power-on state.

[0008] Additional aspects will be set forth in the detailed description which follows, and in part will be apparent from the disclosure, or may be learned by practice of the inventive concepts.

[0009] According to some exemplary embodiments, the scan driver includes a first scan signal output circuit to an nth scan signal output circuit, wherein "n" is a natural number of 2 or greater. Each of the first scan signal output circuit to the nth scan signal output circuit is coupled to a first scan line and a second scan line. Each of the first scan signal output circuit to the nth scan signal output circuit includes a drive circuit, a first buffer circuit, and a second buffer circuit. The drive circuit is configured to apply a first drive signal to a first drive node and a second drive signal to a second drive node based on an input signal, a clock signal, a display conduction signal, and an on-level voltage. The input signal is one of a scan start signal and a previous scan signal. The first buffer circuit is configured to output a sensing signal to the second scan line based on a first drive signal, a second drive signal, an off-level voltage, and a sensing clock signal. The second buffer circuit is configured to output a scan signal to the first scan line based on a first drive signal, a second drive signal, an off-level voltage, and a scan clock signal.

[0010] According to some exemplary embodiments, a display device includes a display unit, a data driver, a scan driver, and a timing controller. The display unit includes pixels. The data driver is configured to supply a data signal to the display unit. The scan driver is configured to supply a scan signal and a sensing signal to the display unit. The timing controller is configured to control the data driver and the scan driver. The scan driver includes a first scan signal output circuit to an nth scan signal output circuit, wherein n is a natural number of 2 or greater. Each of the first scan signal output circuit to the nth scan signal output circuit is coupled to a first scan line and a second scan line. Each of the first scan signal output circuit to the nth scan signal output circuit includes a drive circuit, a first buffer circuit, and a second buffer circuit. The drive circuit is configured to apply a first drive signal to a first drive node and a second drive signal to a second drive node based on an input signal, a clock signal, a display conduction signal, and a conduction level voltage. The input signal is one of a scan start signal and a previous scan signal. The first buffer circuit is configured to output a sensing signal to a second scan line based on a first drive signal, a second drive signal, an off-level voltage, and a sensing clock signal. The second buffer circuit is configured to output a scan signal to the first scan line based on the first drive signal, the second drive signal, the off-level voltage, and the scan clock signal.

[0011] Both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept.

[0013] Figure 1 is a block diagram illustrating a configuration of a display device according to some exemplary embodiments.

[0014] Figure 2 is a diagram showing a method according to some exemplary embodiments Figure 1 The structure of a pixel is shown in the diagram.

[0015] Figure 3 is a diagram illustrating a configuration of a scan driver according to some exemplary embodiments.

[0016] Figure 4 is a diagram showing a method according to some exemplary embodiments Figure 3 A diagram of the configuration of any one of the scan signal output circuits shown in FIG.

[0017] Figure 5 is used to explain some exemplary embodiments Figure 4 A waveform diagram showing an operation in which a scanning signal output circuit generates a scanning signal for a display operation.

[0018] Figure 6 1 is a waveform diagram for explaining an operation of a scan signal output circuit selecting a sensing target scan line that is a target of a sensing operation according to some example embodiments.

[0019] Figure 7 2 is a waveform diagram for explaining an operation of a scan signal output circuit generating a sensing signal for a mobility sensing operation according to some example embodiments.

[0020] Figure 8 1 is a waveform diagram for explaining an operation of generating a sensing signal for sensing degradation of a light emitting element by a scan signal output circuit according to some exemplary embodiments.

[0021] Fig. 9 is a block diagram illustrating a configuration of a scan driver according to some exemplary embodiments.

[0022] Fig.10 is a diagram showing a method according to some exemplary embodiments Fig. 9 A diagram of the configuration of any one of the scan signal output circuits shown in FIG.

[0023] Fig.11 is used to explain some exemplary embodiments Fig.10 2 is a waveform diagram of changes in the potential of the first drive node Q1N shown in FIG. DETAILED DESCRIPTION

[0024] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments. As used herein, the terms "embodiment" and "implementation" are used interchangeably and are non-limiting examples of one or more of the inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments may be practiced without specific details or with one or more equivalent arrangements. In other examples, known structures and devices are shown in block diagram form to avoid unnecessary confusion of various exemplary embodiments. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0025] Unless otherwise specified, the exemplary embodiments shown should be understood as providing exemplary features of different details of some exemplary embodiments. Therefore, unless otherwise specified, the various described features, components, modules, layers, films, panels, regions, aspects, etc. (hereinafter individually or collectively referred to as "elements" or "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the concept of the present invention.

[0026] In the accompanying drawings, for the purpose of clarity and / or description, the size and relative size of the elements may be exaggerated. Thus, the size and relative size of each element are not necessarily limited to the size and relative size shown in the drawings. When the exemplary embodiment can be implemented in different ways, the specific process sequence can be performed differently from the described sequence. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described order. In addition, similar reference numerals represent similar elements.

[0027] When an element (e.g., layer) is referred to as being "on", "connected to" or "coupled to" another element, the element may be directly on, connected to or coupled to another element, or there may be an intermediate element. However, when an element is referred to as being "directly" "on", "directly connected to" or "directly coupled to" another element, there is no intermediate element. Other expressions and / or phrases used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" and "directly between", "adjacent" and "directly adjacent", "on" and "directly on", etc.). In addition, the expression "connection" may be referred to as physical connection, electrical connection and / or fluid connection. For the purpose of this disclosure, "at least one of X, Y and Z" and "at least one selected from a cluster consisting of X, Y and Z" may be interpreted as any combination of only X, only Y, only Z or two or more of X, Y and Z, such as XYZ, XYY, YZ and ZZ. As used herein, the expression "and / or" includes any and all combinations of one or more of the relevant listed items.

[0028] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0029] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein for descriptive purposes, and thus, to describe the relationship of one element to another element as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as being "below" or "beneath" other elements or features would subsequently be oriented to be "above" the other elements or features. Thus, the exemplary term "below" may include both orientations of above and below. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatially relative descriptors used herein are interpreted accordingly.

[0030] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" as used herein are also intended to include the plural forms. In addition, when the words "comprise", "comprising", "include" and / or "including" are used in this specification, the existence of the stated features, integers, steps, operations, elements, parts and / or clusters thereof is indicated, but the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or clusters thereof is not excluded. It is also noted that, as used herein, the words "substantially", "about" and similar words are used as approximate words rather than words of degree, and thus, are used to take into account the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0031] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and will not be interpreted in an idealized or overly formal sense.

[0032] As is customary in the art, in terms of functional blocks, units and / or modules, some exemplary embodiments are shown and described in the accompanying drawings. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be selectively driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware and processors (e.g., one or more programmed microprocessors and associated circuits) that perform some functions to perform other functions. Moreover, without departing from the concept of the present invention, each block, unit and / or module of some exemplary embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the concept of the present invention.

[0033] Hereinafter, various exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0034] Figure 1 is a diagram illustrating a configuration of a display device according to some exemplary embodiments.

[0035] Reference Figure 1 , a display device according to some exemplary embodiments may include a display unit 100 including a plurality of pixels PX, a scan driver 210 , a data driver 220 , a sensing unit 230 , and a timing controller 240 .

[0036] The timing controller 240 may generate a scan driving control signal and a data driving control signal based on an input signal (eg, an external input signal). The scan driving control signal generated by the timing controller 240 may be supplied to the scan driver 210 , and the data driving control signal may be supplied to the data driver 220 .

[0037] The scan driving control signal may include a plurality of clock signals CLK1 to CLK4, CLK1_SC to CLK4_SC, and CLK1_SS to CLK4_SS, and a scan start signal SSP. The scan start signal SSP may control an output timing of the first scan signal.

[0038] The plurality of clock signals CLK1 to CLK4, CLK1_SC to CLK4_SC, and CLK1_SS to CLK4_SS supplied to the scan driver 210 may include first clock signals CLK1 to fourth clock signals CLK4, first scan clock signals CLK1_SC to fourth scan clock signals CLK4_SC, and first sensing clock signals CLK1_SS to fourth sensing clock signals CLK4_SS. The first clock signals CLK1 to fourth clock signals CLK4 may be used to shift the scan start signal SSP. Each of the first scan clock signals CLK1_SC to fourth scan clock signals CLK4_SC may be used to output a scan signal in response to at least one of the scan start signal SSP and the first clock signals CLK1 to fourth clock signals CLK4. Each of the first sensing clock signals CLK1_SS to fourth sensing clock signals CLK4_SS may be used to output a sensing signal in response to at least one of the scan start signal SSP and the first clock signals CLK1 to fourth clock signals CLK4. The scan driver 210 may also receive other clock signals in addition to the above-mentioned clock signals CLK1 to CLK4 , CLK1_SC to CLK4_SC, and CLK1_SS to CLK4_SS.

[0039] In some exemplary embodiments, the data driving control signal may include a source start pulse and a clock signal. The source start pulse may control a sampling start time point of the data, and the clock signal may be used to control the sampling operation.

[0040] The scan driver 210 may output a scan signal in response to the scan drive control signal. The scan driver 210 may sequentially supply the scan signal to the first scan lines SC1 to SCn, where "n" is a natural number. The scan signal may be set to a gate-on voltage (e.g., a high-level voltage) so that a transistor included in the pixel PX may be turned on.

[0041] The scan driver 210 may output a sensing signal in response to the scan drive control signal. The scan driver 210 may supply the sensing signal to at least one of the second scan lines SS1 to SSn. Here, the sensing signal may be set to a gate-on voltage (e.g., a high level voltage) so that a transistor included in the pixel PX may be turned on.

[0042] The data driver 220 may supply data signals to the data lines D1 to Dm in response to the data driving control signal, where "m" is a natural number. The data signals supplied to the data lines D1 to Dm may be provided to the pixels PX supplied with the scan signals. For this operation, the data driver 220 may supply data signals to the data lines D1 to Dm in synchronization with the scan signals.

[0043] The sensing unit 230 may supply initialization power to the pixels supplied with the sensing signals through the sensing lines SL1 to SLm, and may measure (or otherwise determine) information about degradation of the pixels. Figure 1 The sensing unit 230 is shown as a separate component, but the sensing unit 230 may also be included in the data driver 220 or any other suitable component of the display device.

[0044] The display unit 100 may include a plurality of pixels PX coupled to data lines D1 to Dm, first scan lines SC1 to SCn, second scan lines SS1 to SSn, and sensing lines SL1 to SLm. The pixels PX may be supplied with first and second power sources ELVDD and ELVSS from an external device.

[0045] When or in response to a scan signal supplied to the first scan lines SC1 to SCn coupled to the corresponding pixel PX, the corresponding pixel PX may be supplied with a data signal from the data lines D1 to Dm. Each pixel PX supplied with a corresponding data signal may control the amount of current flowing from the first power source ELVDD to the second power source ELVSS via a light emitting element (not shown) in response to the data signal. The light emitting element may generate light with a predetermined brightness according to the amount of current. In addition, the voltage of the first power source ELVDD may be set to a voltage higher than the second power source ELVSS.

[0046] Although in Figure 1 , each pixel PX is shown as being coupled to a single first scan line SCi and a single data line Dj, but exemplary embodiments are not limited thereto. For example, depending on the circuit structure of the pixel PX, a plurality of first scan lines SC1 to SCn may be coupled to the pixel PX. Furthermore, in some cases, in addition to the first scan lines SC1 to SCn and the data lines D1 to Dm, each pixel PX may also be coupled to an emission control line (not shown). In this case, the display device may further include an emission driver configured to output an emission control signal.

[0047] Figure 2 is a diagram showing a method according to some exemplary embodiments Figure 1 For the convenience of description, Figure 2 , a pixel PX coupled to an i-th first scan line SCi and a j-th data line Dj is shown, where “i” is a natural number less than or equal to “n”, and “j” is a natural number less than or equal to “m”.

[0048] The pixel PX may include a driving transistor M1, a switching transistor M2, a sensing transistor M3, a storage capacitor Cst, and a light emitting element (eg, a light emitting diode such as an organic light emitting diode) LED.

[0049] The switching transistor M2 may include a first electrode coupled to the j-th data line Dj, a gate electrode coupled to the i-th first scan line SCi, and a second electrode coupled to the first node Na. When a scan signal is supplied from the i-th first scan line SCi, the switching transistor M2 is turned on and then may supply a data signal received from the j-th data line Dj to the storage capacitor Cst. Alternatively, the switching transistor M2 may control the potential of the first node Na.

[0050] The storage capacitor Cst including a first electrode coupled to the first node Na and a second electrode coupled to the second node Nb may charge a voltage corresponding to the data signal.

[0051] The driving transistor M1 may include a first electrode coupled to the first power source ELVDD, a second electrode coupled to the light emitting element LED, and a gate electrode coupled to the first node Na. The driving transistor M1 may control the amount of current flowing through the light emitting element LED according to a gate-source voltage of the driving transistor M1.

[0052] The sensing transistor M3 may include a first electrode coupled to the j-th sensing line SLj, a second electrode coupled to the second node Nb, and a gate electrode coupled to the i-th second scan line SSi. When a sensing signal is supplied to the i-th second scan line SSi, the sensing transistor M3 may be turned on to control the potential of the second node Nb. Alternatively, when a sensing signal is supplied to the i-th second scan line SSi, the sensing transistor M3 may be turned on, and then the current flowing through the light emitting element LED may be measured.

[0053] The light emitting element LED may include a first electrode (eg, an anode electrode) coupled to the second electrode of the driving transistor M1 and a second electrode (eg, a cathode electrode) coupled to the second power source ELVSS. The light emitting element LED may generate light corresponding to the amount of current supplied from the driving transistor M1.

[0054] exist Figure 2 In the embodiment, the first electrode of each of the transistors M1 to M3 may be set as one of the source electrode and the drain electrode, and the second electrode of each of the transistors M1 to M3 may be set as the remaining electrode different from the first electrode. For example, when the first electrode is set as the source electrode, the second electrode may be set as the drain electrode.

[0055] In addition, if Figure 2 As shown in FIG. 1 , the transistors M1 to M3 may be n-type metal oxide semiconductor (NMOS) transistors, but example embodiments are not limited thereto.

[0056] During the sensing of the mobility of the driving transistor M1, an activated scanning signal is supplied to the i-th first scanning line SCi, and an activated sensing signal is supplied to the i-th second scanning line SSi. However, in order to sense the current flowing through the light-emitting element LED and obtain degradation information, the driving transistor M1 should be turned off and the sensing transistor M3 should be turned on. That is, during the sensing of the current flowing through the light-emitting element LED, a disabled signal should be applied to the i-th first scanning line SCi, and an activated signal should be applied to the i-th second scanning line SSi. Therefore, the scanning signal to be supplied to the i-th first scanning line SCi and the sensing signal to be supplied to the i-th second scanning line SSi can be separately supplied via the i-th first scanning line SCi and the i-th second scanning line SSi, respectively.

[0057] Figure 3 is a diagram illustrating a configuration of a scan driver according to some exemplary embodiments.

[0058] Reference Figure 3, the scan driver 210 may include a plurality of scan signal output circuits SSC1 to SSCn. The scan driver 210 may supply scan signals to the first scan lines SC1 to SCn so that the display device may display an image. In addition, the scan driver 210 may supply sensing signals to the second scan lines SS1 to SSn so that the display device may perform an operation of sensing mobility and an operation of sensing degradation of the light emitting element LED.

[0059] The scan signal output circuits SSC1 to SSCn may be sequentially coupled to each other, and a single first scan line and a single second scan line may be coupled to each of the scan signal output circuits SSC1 to SSCn. Each of the scan signal output circuits SSC1 to SSCn may receive at least two of the first to fourth clock signals CLK1 to CLK4, receive at least one of the first to fourth scan clock signals CLK1_SC to CLK4_SC, and receive at least one of the first to fourth sense clock signals CLK1_SS to CLK4_SS.

[0060] The first scan signal output circuit SSC1 may receive the first and third clock signals CLK1 and CLK3, the first scan clock signal CLK1_SC, the first sensing clock signal CLK1_SS, and the scan start signal SSP. The first scan signal output circuit SSC1 may be coupled to the first first scan line SC1 and the first second scan line SS1. The second scan signal output circuit SSC2 may be coupled to the first scan signal output circuit SSC1 to receive the scan signal output from the first scan signal output circuit SSC1, and may receive the second and fourth clock signals CLK2 and CLK4, the second scan clock signal CLK2_SC, and the second sensing clock signal CLK2_SS. Furthermore, the second scan signal output circuit SSC2 may be coupled to the second first scan line SC2 and the second second scan line SS2. Moreover, the nth scan signal output circuit SSCn may be coupled to the (n-1)th scan signal output circuit SSCn-1 to receive the scan signal outputted from the (n-1)th scan signal output circuit SSCn-1, and may receive the second clock signal CLK2 and the fourth clock signal CLK4, the fourth scan clock signal CLK4_SC, and the fourth sensing clock signal CLK4_SS. Furthermore, the nth scan signal output circuit SSCn may be coupled to the nth first scan line SCn and the nth second scan line SSn.

[0061] When the display device performs an operation of displaying an image, the scan driver 210 may sequentially apply scan signals to the first to n-th first scan lines SC1 to SCn in response to the scan start signal SSP. For example, after the first scan signal output circuit SSC1 has output the scan signal, the second scan signal output circuit SSC2 may output the scan signal. After the second scan signal output circuit SSC2 has output the scan signal, the third scan signal output circuit SSC3 may output the scan signal. After the n-1-th scan signal output circuit SSCn-1 has output the scan signal, the n-th scan signal output circuit SSCn may output the scan signal.

[0062] When the display device performs an operation of sensing mobility or degradation of the light emitting element LED, the scan driver 210 may select a sensing target scan line on which the sensing operation is to be performed, and may output a sensing signal to the selected sensing target scan line.

[0063] In various exemplary embodiments, the scan driver 210 may sequentially apply scan signals to the first scan lines SC1 to SCn during a display period of one frame, and may apply a sensing signal to at least one of the second scan lines SS1 to SSn during a porch period of one frame.

[0064] Figure 4 is a diagram showing a method according to some exemplary embodiments Figure 3 For the convenience of description, in Figure 4 The configuration of the m-th scanning signal output circuit SSCm is shown in FIG.

[0065] Reference Figure 4 The m-th scan signal output circuit SSCm may include a driving circuit 211 , a first buffer circuit 213 , and a second buffer circuit 215 .

[0066] The driving circuit 211 may include third to thirteenth transistors T3 to T13 and first and second capacitors C1 and C2.

[0067] The third transistor T3 may include a first electrode configured to receive the first clock signal CLK1 , a second electrode coupled to the second node N2 , and a gate electrode coupled to the first node N1 .

[0068] The fourth transistor T4 may include a first electrode coupled to the on-level voltage VGH, a second electrode coupled to the first node N1, and a gate electrode configured to receive the (m-1)th scan signal SCAN[m-1] (ie, the input signal). Figure 4, a configuration in which the (m-1)th scan signal SCAN[m-1] is input to the gate electrode of the fourth transistor T4 is shown, but the scan start signal SSP may be input as an input signal to the gate electrode of the fourth transistor T4 included in the first scan signal output circuit SSC1.

[0069] The fifth transistor T5 may include a first electrode coupled to the second node N2 , a second electrode coupled to the on-level voltage VGH, and a gate electrode configured to receive the first clock signal CLK1 .

[0070] The sixth transistor T6 may include a first electrode coupled to the second node N2 , a second electrode coupled to the on-level voltage VGH, and a gate electrode coupled to the second node N2 .

[0071] The seventh transistor T7 may include a first electrode coupled to the first node N1 , a second electrode coupled to the first electrode of the eighth transistor T8 , and a gate electrode configured to receive the third clock signal CLK3 .

[0072] The eighth transistor T8 may include a first electrode coupled to the second electrode of the seventh transistor T7 , a second electrode coupled to the carry signal output node LN, and a gate electrode coupled to the second node N2 .

[0073] The ninth transistor T9 may include a first electrode coupled to the first node N1, a second electrode coupled to the carry signal output node LN, and a gate electrode configured to receive the next carry signal L[m+2]. Figure 4 The next carry signal L[m+2] is illustrated as a carry signal output from the (m+2)th scan signal output circuit SSCm+2, but according to an exemplary embodiment the next carry signal L[m+2] may be a carry signal output from an additional scan signal output circuit.

[0074] The first capacitor C1 may include a first electrode coupled to the first node N1 and a second electrode coupled to the carry signal output node LN.

[0075] The tenth transistor T10 may include a first electrode configured to receive the third clock signal CLK3 , a second electrode coupled to the carry signal output node LN, and a gate electrode coupled to the first node N1 .

[0076] The eleventh transistor T11 may include a first electrode coupled to the carry signal output node LN, a second electrode coupled to a sub off-level voltage VGL1 having a voltage level lower than that of the off-level voltage VGL, and a gate electrode coupled to the second node N2.

[0077] The second capacitor C2 may include a first electrode coupled to the second node N2 and a second electrode coupled to the sub-off level voltage VGL1 .

[0078] The twelfth transistor T12 may include a first electrode coupled to the first node N1, a second electrode coupled to the first driving node Q1N, and a gate electrode configured to receive the display-on signal DIS_ON.

[0079] The thirteenth transistor T13 may include a first electrode coupled to the second node N2, a second electrode coupled to the second driving node Q2N, and a gate electrode configured to receive the display-on signal DIS_ON.

[0080] The first buffer circuit 213 may include a first transistor T1 , a second transistor T2 , fourteenth to seventeenth transistors T14 to T17 , and third to fifth capacitors C3 to C5 .

[0081] The fourteenth transistor T14 may include a first electrode configured to receive the next carry signal L[m+2], a second electrode coupled to the sampling node SN, and a gate electrode configured to receive the sensing-on signal SEN_ON.

[0082] The third capacitor C3 may include a first electrode coupled to the sampling node SN and a second electrode coupled to the sub off-level voltage VGL1. According to some example embodiments, the second electrode of the third capacitor C3 may be coupled to the off-level voltage VGL.

[0083] The fourth capacitor C4 may include a first electrode coupled to the sampling node SN and a second electrode coupled to the gate electrode of the fourteenth transistor T14 receiving the sensing-on signal SEN_ON.

[0084] The fifteenth transistor T15 may include a first electrode configured to receive the sensing mode enabling clock signal S_CLK, a second electrode coupled to the first driving node Q1N, and a gate electrode coupled to the sampling node SN.

[0085] The sixteenth transistor T16 may include a first electrode coupled to the second driving node Q2N, a second electrode coupled to the first electrode of the seventeenth transistor T17 , and a gate electrode configured to receive the sensing mode enabling clock signal S_CLK.

[0086] The seventeenth transistor T17 may include a first electrode coupled to the second electrode of the sixteenth transistor T16 , a second electrode coupled to the off level voltage VGL, and a gate electrode coupled to the sampling node SN.

[0087] The first transistor T1 may include a first electrode configured to receive the third sensing clock signal CLK3_SS, a second electrode coupled to the sensing signal output node ON_SS, and a gate electrode coupled to the first driving node Q1N.

[0088] The second transistor T2 may include a first electrode coupled to the sensing signal output node ON_SS, a second electrode coupled to the off level voltage VGL, and a gate electrode coupled to the second driving node Q2N.

[0089] According to some exemplary embodiments, the first buffer circuit 213 may further include a capacitor, wherein the capacitor includes a first electrode configured to receive the sensing on signal SEN_ON and a second electrode coupled to the sampling node SN. In addition, according to some exemplary embodiments, the first buffer circuit 213 may further include a capacitor, wherein the capacitor includes a first electrode coupled to the second driving node Q2N and a second electrode coupled to the off-level voltage VGL.

[0090] The second buffer circuit 215 may include an eighteenth transistor T18 , a nineteenth transistor T19 , and a sixth capacitor C6 .

[0091] The eighteenth transistor T18 may include a first electrode configured to receive the third scan clock signal CLK3_SC, a second electrode coupled to the scan signal output node ON_SC, and a gate electrode coupled to the first node N1.

[0092] The nineteenth transistor T19 may include a first electrode coupled to the scan signal output node ON_SC, a second electrode coupled to the off level voltage VGL, and a gate electrode coupled to the second node N2.

[0093] The sixth capacitor C6 may include a first electrode coupled to the first node N1 and a second electrode coupled to the scan signal output node ON_SC.

[0094] According to various exemplary embodiments, each of the scan signal output circuits SSC1 to SSCn may receive a plurality of clock signals, a scan clock signal, and a sensing clock signal, and may output a scan signal and a sensing signal based on the received clock signals.

[0095] For example, the mth scan signal output circuit SSCm may receive the first clock signal CLK1 , the third clock signal CLK3 , the third scan clock signal CLK3_SC, and the third sensing clock signal CLK3_SS.

[0096] The rising edge of the third clock signal CLK3 may be arranged adjacent to the falling edge of the first clock signal CLK1, the rising edge of the first clock signal CLK1 may be arranged adjacent to the falling edge of the third clock signal CLK3, and the activation interval of the first clock signal CLK1 and the activation interval of the third clock signal CLK3 may not overlap with each other.

[0097] When the display device is in a power-on state, one frame may include a display period and a porch period. During the display period, the display-on signal DIS_ON may be activated and the sensing mode enabling clock signal S_CLK may be disabled, and during the inactive interval of the display-on signal DIS_ON in the porch period, the sensing mode enabling clock signal S_CLK may be activated.

[0098] In addition, during the activation interval of the next carry signal L[m+2] within the display period, the sense-on signal SEN_ON may be activated or disabled. For example, when the sense-on signal SEN_ON is activated during the activation interval of the next carry signal L[m+2] within the display period, the sampled voltage may be stored at the sampling node SN of the m-th scan signal output circuit SSCm. When the sense-on signal SEN_ON is not activated during the activation interval of the next carry signal L[m+2] within the display period, the sampled voltage may not be stored in the m-th scan signal output circuit SSCm.

[0099] Figure 5 is used to explain some exemplary embodiments Figure 4 A waveform diagram showing an operation in which a scanning signal output circuit generates a scanning signal for a display operation.

[0100] Although in Figure 5 1 to 4 are shown in the figure, but will be described under the assumption that the m-th scan signal output circuit SSCm receives the first clock signal CLK1 and the third clock signal CLK3. In this case, the (m+1)-th scan signal output circuit SSCm+1 may receive the second clock signal CLK2 and the fourth clock signal CLK4.

[0101] Reference Figure 5 During a display period of one frame, the sensing mode enable clock signal S_CLK may be maintained in an inactive state (ie, a logic low level), and the display on signal DIS_ON may be maintained in an active state (ie, a logic high level).

[0102] When the (m-1)th scan signal SCAN[m-1] is input and the fourth transistor T4 is turned on, the first node N1 and the first driving node Q1N are charged to the on-level voltage VGH, and thus, the signal applied to the first node N1 and the first driving signal Q1 applied to the first driving node Q1N may have the on-level voltage VGH.

[0103] When the (m-1)th scan signal SCAN[m-1] is input and then the fourth transistor T4 is turned on, the second node N2 and the second driving node Q2N are discharged to the inactive voltage of the first clock signal CLK1 in response to the disabled first clock signal CLK1, and thus, a signal applied to the second node N2 and a second driving signal Q2 applied to the second driving node Q2N may have the inactive voltage of the first clock signal CLK1.

[0104] As a result, the eighteenth transistor T18 and the tenth transistor T10 may be turned on, and the nineteenth transistor T19 and the eleventh transistor T11 may be turned off.

[0105] Therefore, as the third scan clock signal CLK3_SC is activated, a scan signal SCAN[m] having an activation voltage of the third scan clock signal CLK3_SC, that is, a scan on signal, may be output through the scan signal output node ON_SC. In addition, as the third clock signal CLK3 is activated, a carry signal L[m] having an activation voltage of the third clock signal CLK3 may be output through the carry signal output node LN.

[0106] Thereafter, as the third scan clock signal CLK3_SC is disabled again, a scan off signal having an inactive voltage of the third scan clock signal CLK3_SC may be output through the scan signal output node ON_SC. In addition, as the third clock signal CLK3 is disabled again, a carry signal L[m] having an inactive voltage of the third clock signal CLK3 may be output through the carry signal output node LN.

[0107] According to various exemplary embodiments, when the (m-1)th scan signal SCAN[m-1] is input and then the fourth transistor T4 is turned on, the first drive node Q1N is charged to the on-level voltage VGH, and therefore, the first transistor T1 may also be turned on. However, during the display period, the third sensing clock signal CLK3_SS having an inactive voltage may be supplied so that the sensing signal is not output. In this case, the remaining sensing clock signals CLK1_SS, CLK2_SS, and CLK4_SS supplied to the other scan signal output circuits may also be maintained in an inactive state. In this way, during the display period of one frame of the display device, the scan signal output circuits SSC1 to SSCn sequentially coupled to each other may sequentially output scan signals having an active voltage.

[0108] Figure 6 1 is a waveform diagram for explaining an operation of a scan signal output circuit selecting a sensing target scan line that is a target of a sensing operation according to some example embodiments.

[0109] Reference Figure 6 When the first clock signal CLK1 is activated, the second node N2 is charged to the turn-on level voltage VGH, and thus, the eleventh transistor T11 is turned on. When the next carry signal L[m+2] is activated, the sub turn-off level voltage VGL1 can reset the first node N1 and the first driving node Q1N via the eleventh transistor T11 and the ninth transistor T9.

[0110] Thereafter, as the sensing on signal SEN_ON is activated in a state where the next carry signal L[m+2] is activated, the fourteenth transistor T14 is turned on, and thus, the sampling node SN may be charged to the activation voltage of the next carry signal L[m+2]. As a result, the sampling node SN may store and hold the sampling voltage using the third capacitor C3. That is, among the plurality of scan signal output circuits SSC1 to SSCn, the sensing start signal SEN_ON may be activated only for the scan signal output circuit coupled to the scan line selected as the sensing target.

[0111] Although the next carry signal L[m+2] is shown as a carry signal output from the (m+2)th scan signal output circuit SSCm+2, the next carry signal L[m+2] may be a carry signal output from an additional scan signal output circuit according to an exemplary embodiment. In addition, since the operation of selecting the sensing target scan line is performed during the display period, the sensing mode enable clock signal S_CLK and the sensing clock signals CLK1_SS to CLK4_SS may be maintained in an inactive state.

[0112] Figure 7 2 is a waveform diagram for explaining an operation of a scan signal output circuit generating a sensing signal for a mobility sensing operation according to some example embodiments.

[0113] Reference Figure 7 During the edge period of one frame, the fifteenth transistor T15 in the scan signal output circuit SSCm in which the sampling node SN maintains the sampling voltage using the third capacitor C3 may be turned on by the sampling voltage.

[0114] When the sensing mode enabling clock signal S_CLK is activated in a state in which the fifteenth transistor T15 is in a turned-on state, the first driving node Q1N may be charged to an activated voltage of the sensing mode enabling clock signal S_CLK.

[0115] Accordingly, the first driving signal Q1 applied to the first driving node Q1N may have an activation voltage of the sensing mode enabling clock signal S_CLK. As a result, the first transistor T1 may be turned on, and the sensing signal SENS[m] having an activation voltage of the third sensing clock signal CLK3_SS may be output through the sensing signal output node ON_SS. At this time, the remaining sensing clock signals CLK1_SS, CLK2_SS, and CLK4_SS except the third sensing clock signal CLK3_SS may have a non-activation voltage, but exemplary embodiments are not limited thereto, and the remaining sensing clock signals CLK1_SS, CLK2_SS, and CLK4_SS may also have an activation voltage.

[0116] At the same time, during the period when the display on signal DIS_ON is disabled in the edge period, the twelfth transistor T12 and the thirteenth transistor T13 are turned off, and the first drive node Q1N is charged to the activation voltage of the sensing mode enabling clock signal S_CLK, and therefore, the eighteenth transistor T18 can be turned on. That is, the scan signal SCAN[m] (i.e., the scan on signal) having the activation voltage of the third scan clock signal CLK3_SC can be output through the scan signal output node ON_SC. At this time, the remaining scan clock signals CLK1_SC, CLK2_SC, and CLK4_SC except the third scan clock signal CLK3_SC may have a non-activation voltage, but the exemplary embodiment is not limited thereto, and the remaining scan clock signals CLK1_SC, CLK2_SC, and CLK4_SC may have an activation voltage. In addition, during at least a portion of the edge period, the first clock signal CLK1 to the fourth clock signal CLK4 may have an activation voltage or may be maintained in a non-activation state.

[0117] On the contrary, during the edge period of one frame, the fifteenth transistor T15 in each of the scan signal output circuits SSC1 to SSCm-1 and SSCm+1 to SSCn in which the sampling voltage is not stored is not turned on, and therefore, the sensing signal having the activation voltage of the third sensing clock signal CLK3_SS and the scanning signal having the activation voltage of the third scanning clock signal CLK3_SC will not be output.

[0118] Figure 8 1 is a waveform diagram for explaining an operation of generating a sensing signal for sensing degradation of a light emitting element by a scan signal output circuit according to some exemplary embodiments.

[0119] Reference Figure 8 During the edge period of one frame, the fifteenth transistor T15 in the scan signal output circuit SSCm in which the sampling node SN maintains the sampling voltage using the third capacitor C3 may be turned on by the sampling voltage.

[0120] If the sensing mode enabling clock signal S_CLK is activated when the fifteenth transistor T15 is in the on-state, the first driving node Q1N may be charged to an activated voltage of the sensing mode enabling clock signal S_CLK.

[0121] Accordingly, the first drive signal Q1 applied to the first drive node Q1N may have an activation voltage of the sensing mode enabling clock signal S_CLK. As a result, the first transistor T1 may be turned on, and the sensing signal SENS[m] having an activation voltage of the third sensing clock signal CLK3_SS may be output through the sensing signal output node ON_SC. The remaining sensing clock signals CLK1_SS, CLK2_SS, and CLK4_SS except the third sensing clock signal CLK3_SS may have a non-activation voltage, but exemplary embodiments are not limited thereto, and the remaining sensing clock signals CLK1_SS, CLK2_SS, and CLK4_SS may have an activation voltage.

[0122] At the same time, during the edge period when the display on signal DIS_ON is disabled, the twelfth transistor T12 and the thirteenth transistor T13 may be turned off, and the first drive node Q1N may be charged to the activation voltage of the sensing mode enabling clock signal S_CLK, and therefore, the eighteenth transistor T18 may be turned on. That is, the scan signal SCAN[m] (i.e., the scan off signal) having the inactive voltage of the third scan clock signal CLK3_SC may be output through the scan signal output node ON_SC. At this time, the remaining scan clock signals CLK1_SC, CLK2_SC, and CLK4_SC except the third scan clock signal CLK3_SC may also have an inactive voltage. In addition, during at least a portion of the edge period, the first clock signal CLK1 to the fourth clock signal CLK4 may have an active voltage or may remain in an inactive state.

[0123] During the porch period of one frame, the fifteenth transistor T15 in each of the scan signal output circuits SSC1 to SSCm-1 and SSCm+1 to SSCn not storing the sampling voltage is not turned on, and therefore, the sensing signal having the activation voltage of the third sensing clock signal CLK3_SS will not be output.

[0124] Fig. 9 FIG. 1 is a diagram showing a configuration of a scan driver according to some exemplary embodiments. Fig. 9 The description will be mainly based on the changed parts, and the description of the repeated parts will be mainly omitted. Accordingly, the coupling relationship between the scan signal output circuits SSC1' to SSCn' will be mainly described below.

[0125] Reference Fig. 9 , the scan driver 210 ′ may include a plurality of scan signal output circuits SSC1 ′ to SSCn′, and two or more of the scan signal output circuits SSC1 ′ to SSCn′ may be coupled to each other.

[0126] For example, the first scan signal output circuit SSC1' may receive the scan start signal SSP', and may be coupled to the first first scan line SC1 and the first second scan line SS1. The second scan signal output circuit SSC2' may receive the scan start signal SSP', and may be coupled to the second first scan line SC2 and the second second scan line SS2. The third scan signal output circuit SSC3' may be coupled to the first scan signal output circuit SSC1' to receive the scan signal output from the first scan signal output circuit SSC1', and may be coupled to the third first scan line SC3 and the third second scan line SS3. The fourth scan signal output circuit SSC4' may be coupled to the second scan signal output circuit SSC2' to receive the scan signal output from the second scan signal output circuit SSC2', and may be coupled to the fourth first scan line SC4 and the fourth second scan line SS4. The nth scan signal output circuit SSCn' can be coupled to the (n-2)th scan signal output circuit SSCn-2' to receive the scan signal output from the (n-2)th scan signal output circuit SSCn-2', and can be coupled to the nth first scan line SCn and the nth second scan line SSn.

[0127] Fig.10 is a diagram showing a method according to some exemplary embodiments Fig. 9 For the convenience of description, in Fig.10 The configuration of the m-th scan signal output circuit SSCm′ is shown and described in FIG. 2 . Furthermore, compared with the previously described exemplary embodiment, the description will be mainly based on the changed parts, and the description of the repeated parts will be mainly omitted.

[0128] Reference Fig.10 The fourth transistor T4 included in the driving circuit 211 may include a first electrode coupled to the turn-on level voltage VGH, a second electrode coupled to the first node N1, and a gate electrode configured to receive the (m-2)th scan signal SCAN[m-2].

[0129] Compared with the case where the (m-1)th scan signal SCAN[m-1] is input to the gate electrode of the fourth transistor T4, when the (m-2)th scan signal SCAN[m-2] is input to the gate electrode of the fourth transistor T4, the precharge time of the first drive node Q1N in the process for generating a scan signal for a display operation can be extended.

[0130] Fig.11 is used to explain some exemplary embodiments Fig.10 2 is a waveform diagram of changes in the potential of the first drive node Q1N shown in FIG.

[0131] As described above, when the activation signal is input to the gate electrode of the fourth transistor T4 , the first driving node Q1N starts to be charged to the on-level voltage VGH.

[0132] Therefore, if Fig.11 As shown in FIG. 1 , when the (m-2)th scan signal SCAN[m-2] is input to the gate electrode of the fourth transistor T4 , the first driving node Q1N may be precharged during the first period P1 .

[0133] On the contrary, when the (m-1)th scan signal SCAN[m-1] is input to the gate electrode of the fourth transistor T4, the first driving node Q1N may be precharged in the second period P2 shorter than the first period P1. That is, in the case of the scan driver 210' according to some exemplary embodiments, a more accurate scan signal may be output by extending the precharge period of the first driving node Q1N.

[0134] As mentioned above Figures 9 to 11 As described, according to some exemplary embodiments, not only the first scan signal output circuit SSC1 but also the second scan signal output circuit SSC2 may receive the scan start signal SSP as an input signal. The period during which the scan start signal SSP' is activated may be set to a period longer than the period from the time point when the first clock signal CLK1 starts to be activated (e.g., the time point corresponding to the rising edge of the first clock signal CLK1) to the time point when the second clock signal CLK2 starts to be disabled (e.g., the time point corresponding to the falling edge of the second clock signal CLK2).

[0135] According to various exemplary embodiments, a scan driver is provided that can separate a scan signal for supplying a data signal from a sensing signal for sensing mobility and degradation of a light-emitting element and can separately output the scan signal and the sensing signal, thereby accurately sensing the mobility and degradation of the light-emitting element when the display device is in a power-on state.

[0136] Although certain exemplary embodiments and implementations have been described herein, other embodiments and variations will be apparent from this description. Accordingly, it will be apparent to those skilled in the art that the inventive concept is not limited to these embodiments, but to the broader scope of the appended claims and various obvious variations and equivalent arrangements.

Claims

1. Scan the drive, include: a first scan signal output circuit to an nth scan signal output circuit, each of which is coupled to a first scan line and a second scan line, wherein n is a natural number of 2 or more, Wherein, each of the first scanning signal output circuit to the nth scanning signal output circuit comprises: a driving circuit configured to apply a first driving signal to a first driving node and a second driving signal to a second driving node based on an input signal, a clock signal, a display turn-on signal, and a turn-on level voltage, wherein the input signal is one of a scanning start signal and a previous scanning signal; a first buffer circuit configured to output a sensing signal to the second scan line based on the first drive signal, the second drive signal, an off-level voltage, and a sensing clock signal; and a second buffer circuit configured to output a scan signal to the first scan line based on the first drive signal, the second drive signal, the off-level voltage, and a scan clock signal, and The scan driver is configured to perform an operation of selecting a sensing target scan line among the second scan lines of the first scan signal output circuit to the nth scan signal output circuit during a display period, and output the sensing signal to the selected sensing target scan line.

2. The scanning driver according to claim 1, in, One frame includes the display period and the edge period; and Each of the first to nth scan signal output circuits is configured to output the scan signal via the first scan line during the display period.

3. The scanning driver according to claim 2, in, During the edge period, at least one of the first to nth scan signal output circuits is configured to output the sensing signal via the second scan line.

4. The scanning driver according to claim 1, in, The clock signal includes a first clock signal to a fourth clock signal; The scanning clock signal includes a first scanning clock signal to a fourth scanning clock signal; as well as The sensing clock signals include first to fourth sensing clock signals.

5. The scanning driver according to claim 4, in, Each of the first to nth scan signal output circuits is configured to receive at least two of the first to fourth clock signals, at least one of the first to fourth scan clock signals, and at least one of the first to fourth sensing clock signals.

6. The scan driver according to claim 3, in, When the sensing signal is output via the second scan line coupled to at least one of the first to nth scan signal output circuits, the scan signal is output via the first scan line.

7. The scan driver according to claim 3, in, When the sensing signal is output via the second scan line coupled to at least one of the first to nth scan signal output circuits, the scan-off signal is output via the first scan line.

8. The scan driver according to claim 5, in, The driving circuit in the m-th scanning signal output circuit comprises: a third transistor including a first electrode configured to receive the first clock signal, a second electrode coupled to the second node, and a gate electrode coupled to the first node; a fourth transistor including a first electrode configured to receive the on-level voltage, a second electrode coupled to the first node, and a gate electrode configured to receive the input signal; a fifth transistor including a first electrode coupled to the second node, a second electrode configured to receive the on-level voltage, and a gate electrode configured to receive the first clock signal; a sixth transistor including a first electrode coupled to the second node, a second electrode configured to receive the on-level voltage, and a gate electrode coupled to the second node; a seventh transistor including a first electrode coupled to the first node, a second electrode, and a gate electrode configured to receive the third clock signal; an eighth transistor including a first electrode coupled to the second electrode of the seventh transistor, a second electrode coupled to a carry signal output node, and a gate electrode coupled to the second node; a ninth transistor including a first electrode coupled to the first node, a second electrode coupled to the carry signal output node, and a gate electrode configured to receive a next carry signal; a first capacitor including a first electrode coupled to the first node and a second electrode coupled to the carry signal output node; a tenth transistor including a first electrode configured to receive the third clock signal, a second electrode coupled to the carry signal output node, and a gate electrode coupled to the first node; an eleventh transistor, the eleventh transistor comprising a first electrode coupled to the carry signal output node, a second electrode configured to receive a sub-off level voltage, and a gate electrode coupled to the second node; a second capacitor including a first electrode coupled to the second node and a second electrode configured to receive the sub-off level voltage; a twelfth transistor including a first electrode coupled to the first node, a second electrode coupled to the first driving node, and a gate electrode configured to receive the display-on signal; and a thirteenth transistor, the thirteenth transistor comprising a first electrode coupled to the second node, a second electrode coupled to the second driving node, and a gate electrode configured to receive the display-on signal, Where m is a natural number less than n, and The sub-off level voltage is a voltage lower than the off level voltage.

9. The scan driver according to claim 8, in, The gate electrode of the fourth transistor is configured to receive the scan signal or the scan start signal output from the (m-1)th scan signal output circuit as the input signal.

10. The scan driver according to claim 8, in, The gate electrode of the fourth transistor is configured to receive the scan signal or the scan start signal output from the (m-2)th scan signal output circuit as the input signal.

11. The scan driver according to claim 8, in, The first buffer circuit in the mth scanning signal output circuit comprises: a fourteenth transistor, the fourteenth transistor comprising a first electrode configured to receive the next carry signal, a second electrode coupled to the sampling node, and a gate electrode configured to receive a sense-on signal; a third capacitor including a first electrode coupled to the sampling node and a second electrode configured to receive the sub-off level voltage; a fifteenth transistor including a first electrode configured to receive a sensing mode enabling clock signal, a second electrode coupled to the first driving node, and a gate electrode coupled to the sampling node; a sixteenth transistor including a first electrode coupled to the second driving node, a second electrode, and a gate electrode configured to receive the sensing mode enabling clock signal; a seventeenth transistor, the seventeenth transistor comprising a first electrode coupled to the second electrode of the sixteenth transistor, a second electrode configured to receive the off-level voltage, and a gate electrode coupled to the sampling node; a first transistor including a first electrode configured to receive a third sensing clock signal, a second electrode coupled to a sensing signal output node, and a gate electrode coupled to the first driving node; a fourth capacitor including a first electrode coupled to the sampling node and a second electrode coupled to the gate electrode of the fourteenth transistor configured to receive the sensing turn-on signal; a fifth capacitor including a first electrode coupled to the first driving node and a second electrode coupled to the sensing signal output node; and A second transistor includes a first electrode coupled to the sensing signal output node, a second electrode configured to receive the off-level voltage, and a gate electrode coupled to the second driving node.

12. The scan driver according to claim 11, in, The second buffer circuit in the mth scanning signal output circuit comprises: an eighteenth transistor, the eighteenth transistor comprising a first electrode configured to receive a third scan clock signal, a second electrode coupled to a scan signal output node, and a gate electrode coupled to the first node; a sixth capacitor including a first electrode coupled to the first node and a second electrode coupled to the scan signal output node; and A nineteenth transistor includes a first electrode coupled to the scan signal output node, a second electrode configured to receive the off-level voltage, and a gate electrode coupled to the second node.

13. The scan driver according to claim 12, in, The scan signal output node is coupled to the first scan line; and The sensing signal output node is coupled to the second scan line.

14. The scan driver according to claim 12, in, One frame includes the display period and the edge period; During the edge period, the display-on signal is disabled, and the sensing mode enable clock signal, the third scanning clock signal, and the third sensing clock signal are activated.

15. The scan driver according to claim 12, in, One frame includes the display period and the edge period; as well as During the edge period, the display-on signal and the third scan clock signal are disabled, and the sensing mode enable clock signal and the third sensing clock signal are activated.

16. The scan driver according to claim 12, in, One frame includes the display period and the edge period; and During the display period, the display-on signal, the first clock signal, the third clock signal, and the third scanning clock signal are activated, and the sensing mode enable clock signal and the third sensing clock signal are disabled.

17. The scan driver according to claim 16, in, During an activation interval of the next carry signal within the display period, the sense-on signal is activated or disabled.

18. Display device, include: A display unit, the display unit comprising pixels; a data driver configured to supply a data signal to the display unit; a scan driver configured to supply a scan signal and a sensing signal to the display unit; as well as a timing controller configured to control the data driver and the scan driver, The scan driver includes a first scan signal output circuit to an nth scan signal output circuit, each of the first scan signal output circuit to the nth scan signal output circuit is coupled to a first scan line and a second scan line, wherein n is a natural number of 2 or more, Wherein, each of the first scanning signal output circuit to the nth scanning signal output circuit comprises: a driving circuit configured to apply a first driving signal to a first driving node and a second driving signal to a second driving node based on an input signal, a clock signal, a display turn-on signal, and a turn-on level voltage, wherein the input signal is one of a scanning start signal and a previous scanning signal; a first buffer circuit configured to output the sensing signal to the second scan line based on the first driving signal, the second driving signal, an off-level voltage, and a sensing clock signal; and a second buffer circuit configured to output the scan signal to the first scan line based on the first drive signal, the second drive signal, the off-level voltage, and a scan clock signal, and The scan driver is configured to perform an operation of selecting a sensing target scan line among the second scan lines of the first scan signal output circuit to the nth scan signal output circuit during a display period, and output the sensing signal to the selected sensing target scan line.

19. The display device according to claim 18, in, One frame includes the display period and the edge period; as well as During the porch period, the display device is configured to perform an operation of sensing at least one of mobility of a driving transistor in at least one of the pixels and degradation of a light emitting element in at least one of the pixels.

20. The display device according to claim 19, in, During the display period, each of the first to nth scan signal output circuits is configured to output the scan signal via the first scan line.

21. The display device according to claim 19, in, During the edge period, at least one of the first to nth scan signal output circuits is configured to output the sensing signal via the second scan line.

22. The display device according to claim 18, in, The timing controller is configured to supply the clock signals including first to fourth clock signals, the scan clock signals including first to fourth scan clock signals, and the sensing clock signals including first to fourth sensing clock signals to the scan driver.

23. The display device according to claim 22, in, Each of the first to nth scan signal output circuits is configured to receive at least two of the first to fourth clock signals, at least one of the first to fourth scan clock signals, and at least one of the first to fourth sensing clock signals.

24. The display device according to claim 19, in, Each of the pixels comprises: Light emitting element; a driving transistor configured to control an amount of current flowing through the light emitting element in response to the data signal; a switching transistor including a gate electrode coupled to the first scan line and configured to receive the data signal; and A sensing transistor includes a gate electrode coupled to the second scan line, and the sensing transistor is coupled to the first electrode of the light emitting element.

25. The display device according to claim 24, in, As part of the operation of sensing the mobility of the drive transistor, the scan signal is supplied through the first scan line, and the sensing signal is supplied through the second scan line.

26. The display device according to claim 24, in, As part of the operation of sensing degradation of the light emitting element, a scan-off signal is supplied through the first scan line, and the sensing signal is supplied through the second scan line.

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