Non-volatile memory device and method of operating the same

Abstract

The present disclosure provides an operation method of a page buffer circuit, a non-volatile memory device, and an operation method thereof. A non-volatile memory device includes: a memory cell array including a plurality of memory cells, a page buffer circuit, and a control logic circuit. The page buffer circuit includes a plurality of first page buffers and a plurality of second page buffers, each of which includes a sense latch, a data latch, and a cache latch. The sense latch senses data stored in the memory cell array and dumps the sensed data to the data latch, the data latch dumps the data dumped by the sense latch to the cache latch, and the cache latch sends the data dumped by the data latch to a data I / O circuit. While the cache latch included in at least one of the plurality of first page buffers performs a data sending operation, the data latch included in at least one of the plurality of second page buffers performs a data dumping operation.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority of Korean Patent Application No. 10 - 2019 - 0015557, filed on February 11, 2019, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Exemplary embodiments of the inventive concept relate to a non - volatile memory device and an operation method thereof, and more particularly, to a non - volatile memory device including a page buffer for sensing and reading data of memory cells and a method of operating the non - volatile memory device. Background Art

[0004] A semiconductor memory device is a storage device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), or indium phosphide (InP). The semiconductor memory device can be roughly classified into a volatile memory device and a non - volatile memory device.

[0005] A non - volatile memory device is a memory device capable of retaining stored information even when the power is turned off. Examples of non - volatile memory devices include read - only memory (ROM), programmable read - only memory (PROM), erasable programmable read - only memory (EPROM), electrically erasable programmable read - only memory (EEPROM), flash memory, phase - change random access memory (PRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FRAM). Flash memory devices can be roughly classified into NOR flash and NAND flash. Summary of the Invention

[0006] According to an exemplary embodiment of the inventive concept, a non - volatile memory device includes a memory cell array, a page buffer circuit, and a control logic circuit. The memory cell array includes a plurality of memory cells. The page buffer circuit includes a plurality of first page buffers and a plurality of second page buffers. Each of the plurality of first page buffers and the plurality of second page buffers includes a sense latch, a data latch, and a cache latch. The sense latch senses data stored in the memory cell array and dumps the sensed data to the data latch. The data latch dumps the data dumped by the sense latch to the cache latch. The cache latch sends the data dumped by the data latch to a data input / output (I / O) circuit. The control logic circuit is configured to control the page buffer circuit such that while a cache latch included in at least one of the plurality of first page buffers performs a data sending operation, a data latch included in at least one of the plurality of second page buffers performs a data dumping operation.

[0007] According to an exemplary embodiment of the inventive concept, a non-volatile memory device configured to perform a random read operation includes a memory cell array, a page buffer circuit, and a control logic circuit. The memory cell array includes pages, and each page includes memory cells connected to the same word line. The page buffer circuit includes a first page buffer and a second page buffer, and each of the first page buffer and the second page buffer includes a sense latch, a data latch, and a cache latch. The sense latch senses data from the memory cell array and dumps the sensed data. The data latch selectively dumps the data dumped by the sense latch. The cache latch sends the data dumped by the data latch to a data input / output (I / O) circuit. The control logic circuit is configured to, in response to receiving a command and an address indicating a random read operation, control the data latch of the first page buffer to dump first data to the cache latch of the first page buffer, and control the data latch of the second page buffer not to dump second data to the cache latch of the second page buffer.

[0008] According to an exemplary embodiment of the inventive concept, an operation method of a page buffer circuit for outputting data sensed from a plurality of bit lines to a data input / output (I / O) circuit includes: sensing first data and second data from the plurality of bit lines using a plurality of first sense latches and a plurality of second sense latches, respectively; dumping the first data from the plurality of first sense latches to a plurality of first data latches, and dumping the second data from the plurality of second sense latches to a plurality of second data latches; dumping the first data from the plurality of first data latches to a plurality of first cache latches; and maintaining the second data without dumping the second data during at least a part of a time period in which the first data is dumped to the plurality of first cache latches, wherein the maintaining of the second data is performed by the plurality of second data latches. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other features of the inventive concept will be more clearly understood by describing exemplary embodiments of the inventive concept in detail with reference to the accompanying drawings.

[0010] Figure 1 is a block diagram of a non-volatile memory device according to an exemplary embodiment of the inventive concept.

[0011] Figure 2A is a block diagram showing a plane included in a memory cell array according to an exemplary embodiment of the inventive concept.

[0012] Figure 2B is a circuit diagram showing a memory block included in a memory cell array according to an exemplary embodiment of the inventive concept.

[0013] Figure 2Cof an exemplary embodiment according to the inventive concept Figure 2B A perspective view of a memory block

[0014] Figure 2D A block diagram of a plane according to an exemplary embodiment of the inventive concept

[0015] Figure 3 A block diagram of a page buffer circuit according to an exemplary embodiment of the inventive concept

[0016] Figure 4 A data flow diagram for explaining a method of sensing and outputting data of multiple pages according to an exemplary embodiment of the inventive concept

[0017] Figure 5 of an exemplary embodiment according to the inventive concept Figure 3 of a page buffer circuit Figure 6 for explaining an exemplary embodiment according to the inventive concept Figure 5 of the operation of a page buffer circuit

[0018] Figure 7 A block diagram of a page buffer according to an exemplary embodiment of the inventive concept

[0019] Figure 8 A data flow diagram for explaining the operation of a page buffer according to an exemplary embodiment of the inventive concept

[0020] Figure 9 A data flow diagram for explaining the operation of a page buffer according to an exemplary embodiment of the inventive concept

[0021] Figure 10 A block diagram of a page buffer including a first page buffer and a second page buffer according to an exemplary embodiment of the inventive concept Figure 11 for explaining an exemplary embodiment according to the inventive concept Figure 10 of the operation of the first page buffer and the second page buffer

[0022] Figure 12A A block diagram of a page buffer according to an exemplary embodiment of the inventive concept

[0023] Figure 12B A block diagram of a page buffer according to an exemplary embodiment of the inventive concept

[0024] Figure 13 and Figure 14 A data flow diagram for explaining the operation of the first page buffer and the second page buffer according to an exemplary embodiment of the inventive concept

[0025] Figure 15AIt is a block diagram of a page buffer circuit according to an exemplary embodiment of the inventive concept.

[0026] Figure 15B It is for explaining a Figure 15A block diagram of a page buffer included in a page buffer circuit according to an exemplary embodiment of the inventive concept.

[0027] Figure 15C It is for explaining a Figure 15B data flow diagram of the operation of a page buffer according to an exemplary embodiment of the inventive concept.

[0028] Figure 16 It is a block diagram of a non-volatile memory device for explaining an exemplary embodiment of the inventive concept.

[0029] Figure 17 It is a block diagram for explaining a first page buffer and a second page buffer according to an exemplary embodiment of the inventive concept, Figure 18 It is for explaining a Figure 17 data flow diagram of the operations of the first page buffer and the second page buffer according to an exemplary embodiment of the inventive concept.

[0030] Figure 19 It is a diagram for explaining an address queuing operation performed by a control logic unit according to an exemplary embodiment of the inventive concept.

[0031] Figure 20 It is a flowchart of the operation of a page buffer circuit according to an exemplary embodiment of the inventive concept.

[0032] Figure 21 It is a flowchart of the operation of a page buffer circuit according to an exemplary embodiment of the inventive concept.

[0033] Figure 22 It is a flowchart of the operation of a page buffer circuit according to an exemplary embodiment of the inventive concept.

[0034] Figure 23 It is a block diagram of a solid state drive (SSD) system for explaining an exemplary embodiment of the inventive concept. Detailed Description

[0035] Exemplary embodiments of the inventive concept provide an advancement of a next sensing time point while reading data from memory cells via a page buffer of a non-volatile memory device, and provide a reduction in a time period from a sensing time point to a data output time point.

[0036] Hereinafter, exemplary embodiments of the inventive concept will be described more fully with reference to the accompanying drawings. Throughout the present application, the same reference numerals may denote the same elements.

[0037] Figure 1 is a block diagram of a non-volatile memory device according to an exemplary embodiment of the inventive concept.

[0038] Referring to Figure 1 , the non-volatile memory device 10 may include: a page buffer circuit 110 including a plurality of page buffers PB1 to PBm; a memory cell array 120 including a plurality of memory cells MC0 to MCm-1; a row decoder 130; and a control logic unit 140. The control logic unit 140 may also be referred to as a control logic circuit. Although the non-volatile memory device 10 is shown as a flash memory, the inventive concept is not limited to flash memories and is applicable to all types of non-volatile memory devices (e.g., read-only memory (ROM), programmable ROM (PROM), electrically erasable programmable ROM (EEPROM), flash memory, phase change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), and ferroelectric RAM (FRAM)).

[0039] The page buffer circuit 110 may operate as a write driver or a read amplifier according to an operation mode. During a programming operation, the page buffer circuit 110 may send a bit line voltage corresponding to data to be programmed to the bit lines BL of the memory cell array 120. During a read operation including a sequential read operation and a random read operation, the page buffer circuit 110 may sense data stored in selected memory cells via the bit lines BL. The page buffer circuit 110 may latch the sensed data and output the latched data to the outside.

[0040] Each of the plurality of page buffers PB1 to PBm included in the page buffer circuit 110 may include a sense latch, a data latch, and a cache latch. This will be described later with reference to Figure 2B etc. For convenience of explanation, some of the plurality of page buffers PB1 to PBm are referred to as first page buffers, and some of the other of the plurality of page buffers PB1 to PBm are referred to as second page buffers. This will be described later with reference to Figure 2A etc.

[0041] The memory cell array 120 may be connected to the row decoder 130 via word lines WL0 to WLn-1, cell string selection lines SSL, and ground selection lines GSL. The memory cell array 120 may be connected to the page buffer circuit 110 via bit lines BL0 to BLm-1. The memory cell array 120 may include a plurality of NAND cell strings SR. Each NAND cell string SR may be connected to a bit line BL (e.g., one of the bit lines BL0 to BLm-1) via a cell string selection transistor SST.

[0042] Figure 1The memory cell array 120 may be planar. Planar means a memory cell array 120 connected to a single page buffer circuit 110 that operates independently. Data in page units received from a memory controller may be stored in respective planes. Data read from a plane may be output to the memory controller via the page buffer circuit 110 corresponding to the plane. The non-volatile memory device 10 may perform read operations and write operations in page units, and may perform erase operations in memory block units. As will be described later Figure 2D As shown, each plane includes a plurality of memory blocks. As Figure 2A shown, each memory block may include a plurality of pages.

[0043] According to an exemplary embodiment of the inventive concept, a two-dimensional (2D) memory cell array or a three-dimensional (3D) memory cell array is provided. A 3D memory cell array is monolithically formed at a physical level of at least one memory cell array having a circuit formed on or in a silicon (Si) substrate as a circuit related to the operation of memory cells, and active regions are arranged on the Si substrate. The term "monolithic" means that layers of respective horizontal heights constituting a cell array are directly stacked on a layer of a lower horizontal height included in the cell array.

[0044] U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, and 8,559,235 and U.S. Patent Publication No. 2011 / 0233648 disclose suitable features of 3D memory arrays including multiple layers sharing word lines and / or bit lines, and are hereby incorporated by reference in their entirety. The memory cell array 120 will be described in detail later.

[0045] The row decoder 130 may select one of the memory blocks of the memory cell array 120 in response to a row address X-ADDR. The row decoder 130 may select one of the word lines WL0 to WL(n - 1) of the selected memory block. The row decoder 130 may send a word line voltage from a voltage generator to the word line WL (e.g., one of the word lines WL0 to WL(n - 1)) of the selected memory block.

[0046] The control logic unit 140 may receive a command CMD and an address ADDR, and in response to the command CMD and the address ADDR, output various control signals for controlling the page buffer circuit 110 and the row decoder 130 to perform a programming operation or a read operation.

[0047] According to an exemplary embodiment of the inventive concept, the control logic unit 140 may send a control signal CTRL_PB to the page buffer circuit 110 such that while cache latches included in at least one first page buffer output data to the data I / O circuit 150, data latches included in at least one second page buffer dump data.

[0048] The control signal CTRL_PB may include a sense latch control signal LTCH_S, a data latch control signal LTCH_D, and a cache latch control signal LTCH_C. This will be described in detail below with reference to Figure 7 the detailed description.

[0049] According to an exemplary embodiment of the inventive concept, the control logic unit 140 may read data from the memory cell MC according to a command CMD indicating a random read operation. In this case, the control logic unit 140 may send the control signal CTRL_PB to the page buffer circuit 110 such that the data latch included in the first page buffer dumps the first data to the cache latch of the first page buffer and does not dump the second data to the respective cache latches of the second page buffer.

[0050] The data I / O circuit 150 may be connected to the page buffer circuit 110 via the data line DLI, and may provide the received data DTA to the page buffer circuit 110 or output the data DTA received from the page buffer circuit 110 to the outside.

[0051] Figure 2A is a block diagram showing a plane included in a memory cell array according to an exemplary embodiment of the inventive concept.

[0052] Referring to Figure 2A , the memory cell array (e.g., the memory cell array 120) may be a memory cell array of a horizontal NAND flash memory, and may include a plurality of memory blocks. Each memory block BLK may include a plurality of pages PAG, and each page includes a memory cells MC in a direction perpendicular to each of the plurality of bit lines BL0 to BLa-1.

[0053] In a NAND flash memory device having a structure as Figure 2A shown, erasure is performed in units of blocks, and programming is performed in units of pages PAG corresponding to the word lines WL0 to WL7, respectively. Figure 2A shows an example in which one block includes eight pages PAG corresponding to eight word lines WL0 to WL7, respectively. However, the memory blocks of the memory cell array 120 according to an exemplary embodiment of the inventive concept may include different numbers of memory cells and pages. Figure 1 The non-volatile memory device 10 may include a plurality of memory cell arrays, each having the same structure as the memory cell array 120 described above and performing substantially the same operations.

[0054] Figure 2B is a circuit diagram showing a memory block included in a memory cell array according to an exemplary embodiment of the inventive concept.

[0055] Referring to Figure 2B , the memory cell array (e.g., the memory cell array 120) may be a memory cell array of a vertical NAND flash memory and may include a plurality of memory blocks. Each memory block BLK may include a plurality of NAND strings NS11 to NS33, a plurality of word lines WL1 to WL8, a plurality of bit lines BL1 to BL3, a plurality of ground selection lines GSL1 to GSL3, a plurality of string selection lines SSL1 to SSL3, and a common source line CSL. The number of NAND strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may vary according to exemplary embodiments of the inventive concept.

[0056] The NAND strings NS11, NS21, and NS31 are disposed between the bit line BL1 (i.e., the first bit line BL1) and the common source line CSL. The NAND strings NS12, NS22, and NS32 are disposed between the bit line BL2 (i.e., the second bit line BL2) and the common source line CSL. The NAND strings NS13, NS23, and NS33 are disposed between the bit line BL3 (i.e., the third bit line BL3) and the common source line CSL. Each of the NAND strings NS11, NS21, NS31, NS12, NS22, NS32, NS13, NS23, NS33 (e.g., NS11) may include a string selection transistor SST, a plurality of memory cells MC1 to MC8, and a ground selection transistor GST connected in series with each other.

[0057] The NAND strings commonly connected to one bit line configure a column. For example, the NAND strings NS11, NS21, and NS31 commonly connected to the first bit line BL1 may correspond to the first column, the NAND strings NS12, NS22, and NS32 commonly connected to the second bit line BL2 may correspond to the second column, and the NAND strings NS13, NS23, and NS33 commonly connected to the third bit line BL3 may correspond to the third column.

[0058] The NAND strings commonly connected to one string selection line configure a row. For example, the NAND strings NS11, NS12, and NS13 commonly connected to the string selection line SSL1 (i.e., the first string selection line SSL1) may correspond to the first row. The NAND strings NS21, NS22, and NS23 commonly connected to the string selection line SSL2 (i.e., the second string selection line SSL2) may correspond to the second row. The NAND strings NS31, NS32, and NS33 commonly connected to the string selection line SSL3 (i.e., the third string selection line SSL3) may correspond to the third row.

[0059] The string selection transistors SSTs are connected to corresponding first to third string selection lines SSL1 to SSL3. A plurality of memory cells MC1 to MC8 are respectively connected to word lines WL1 to WL8. The ground selection transistors GSTs are connected to corresponding ground selection lines GSL1 to GSL3. The string selection transistors SSTs are connected to corresponding bit lines BL1 to BL3, and the ground selection transistors GSTs are connected to a common source line CSL.

[0060] Word lines (e.g., WL1) having substantially the same height are commonly connected to each other, the string selection lines SSL1 to SSL3 are separated from each other, and the ground selection lines GSL1 to GSL3 are separated from each other. For example, when the memory cells included in the NAND strings NS11, NS12, and NS13 and connected to the word line WL1 (i.e., the first word line WL1) are programmed, the first word line WL1 and the first string selection line SSL1 are selected. According to an exemplary embodiment, the ground selection lines GSL1 to GSL3 may be commonly connected to each other.

[0061] Figure 2C is a perspective view of a memory block according to an exemplary embodiment of the inventive concept Figure 2B of.

[0062] Referring to Figure 2C , each memory block included in a memory cell array (e.g., Figure 1 the memory cell array 120 of) is formed in a vertical direction with respect to a substrate SUB. Although in Figure 2C the memory block includes two selection lines GSL and SSL, eight word lines WL1 to WL8, and three bit lines BL1 to BL3, the number of selection lines, word lines, and bit lines may vary.

[0063] The substrate SUB has a first conductivity type (e.g., p-type), and a common source line CSL that extends in a first direction (e.g., the Y direction) and is doped with impurities of a second conductivity type (e.g., n-type) is disposed on the substrate SUB. On a region of the substrate SUB between two adjacent common source lines CSL, a plurality of insulating layers IL that extend in the first direction are sequentially disposed in a third direction (e.g., the Z direction), and the plurality of insulating layers IL are spaced apart from each other by a specific distance in the third direction. For example, the plurality of insulating layers IL may include an insulating material such as Si oxide.

[0064] On a region of the substrate SUB between two adjacent common source lines CSL, a plurality of pillars P are sequentially arranged in the first direction and penetrate the plurality of insulating layers IL in the third direction. For example, the plurality of pillars P penetrate the plurality of insulating layers IL and contact the substrate SUB. Specifically, a surface layer S of each pillar P may include a Si material of the first conductivity type and may be used as a channel region. An inner layer I of each pillar P may include an insulating material such as Si oxide or an air gap.

[0065] In a region between two adjacent common source lines CSL, a charge storage layer CS is disposed along exposed surfaces of an insulating layer IL, a pillar P, and a substrate SUB. The charge storage layer CS may include a gate insulating layer (or a tunnel insulating layer), a charge trapping layer, and a blocking insulating layer. For example, the charge storage layer CS may have an oxide-nitride-oxide (ONO) structure. In a region between two adjacent common source lines CSL, gate electrodes GE such as selection lines GSL and SSL and word lines WL1 to WL8 are also disposed on an exposed surface of the charge storage layer CS.

[0066] A drain or a drain contact DR is respectively disposed on a plurality of pillars P. For example, the drain or the drain contact DR may include an Si material doped with impurities of a second conductivity type. Bit lines BL1 to BL3 respectively extending in a second direction (e.g., an X direction) and spaced apart from each other by a specific distance in a first direction are disposed on the drain DR.

[0067] Figure 2D is a block diagram of a plane according to an exemplary embodiment of the inventive concept.

[0068] Referring to Figure 1 and Figure 2D , each of a first plane PL1 and a second plane PL2 included in a memory cell array 120 may include a plurality of memory blocks BLK connected to a bit line (e.g., BL1). Each of the plurality of memory blocks BLK may be Figures 2A to 2C one of the memory blocks BLK. The first plane PL1 and the second plane PL2 may include a plurality of pages PAGE included in the plurality of memory blocks BLK.

[0069] The plurality of memory blocks BLK11 to BLK1n and the plurality of memory blocks BLK21 to BLK2n may be respectively connected to a first page buffer circuit 110a and a second page buffer circuit 110b via a first bit line BL1 and a second bit line BL2. For example, the memory blocks BLK11 to BLK1n included in the first plane PL1 may be connected to the first page buffer circuit 110a via the first bit line BL1. The memory blocks BLK21 to BLK2n included in the second plane PL2 may be connected to the second page buffer circuit 110b via the second bit line BL2. In other words, the memory blocks BLK11 to BLK1n included in the first plane PL1 may share the first bit line BL1, and the memory blocks BLK21 to BLK2n included in the second plane PL2 may share the second bit line BL2. Although Figure 2D only two planes, e.g., a first plane PL1 and a second plane PL2, are shown, this is merely an example, and the number of planes PL may vary. The number of page buffer circuits 110 may also vary corresponding to the number of planes.

[0070] Figure 3 It is a block diagram of a page buffer circuit according to an exemplary embodiment of the inventive concept.

[0071] Referring to Figure 1 and Figure 3 , the page buffer circuit 110 may include a plurality of page buffers PB1 to PBm (which may be a first page buffer 111 and a second page buffer 112). The first page buffer 111 may include a first page buffer Pba, and the second page buffer 112 may include a second page buffer PBb.

[0072] For example, the first page buffer 111 may include Figure 1 some of the plurality of page buffers PB1 to PBm, and the second page buffer 112 may include Figure 1 some of the other of the plurality of page buffers PB1 to PBm.

[0073] As another example, the first page buffer 111 may include Figure 1 some of the plurality of page buffers PB1 to PBm, and the second page buffer 112 may include Figure 1 the other or remaining page buffers of the plurality of page buffers PB1 to PBm. The internal structures of the first page buffer PBa and the second page buffer PBb may be substantially the same as each other.

[0074] Figure 4 It is a data flow diagram for explaining a method of sensing and outputting data of a plurality of pages according to an exemplary embodiment of the inventive concept.

[0075] Generally, a sense latch included in the page buffer circuit senses data stored in memory cells of a first page PAG1 and dumps the data of the first page PAG1 to a cache latch included in the page buffer circuit. While the cache latch outputs the dumped data of the first page PAG1, the sense latch may sense data of a second page PAG2 because operations of sensing sense bit lines and outputting data are performed in different latches.

[0076] Referring to Figure 4 , since, for example, a relatively large load occurs due to a physical separation distance between the sense latch and the cache latch, it takes a considerable amount of time to perform the dump. When a time period during which the sense latch dumps data of a page PAG to another latch is reduced, read operation efficiency may be improved.

[0077] Figure 5 It is a block diagram of a page buffer circuit according to an exemplary embodiment of the inventive concept Figure 3 of Figure 6 It is for explaining an exemplary embodiment of the inventive concept Figure 5Data flow diagram of the operation of the page buffer circuit 110.

[0078] Referring to Figure 5 , the page buffer circuit 110 may include a first page buffer PBa and a second page buffer PBb. Each of the first page buffer PBa and the second page buffer PBb may perform a sequential read operation on data stored in the memory cell array 120 in units of pages PAG. For example, the first page buffer PBa and the second page buffer PBb may sense and output data stored in the first page PAG1, and sense and output data stored in the second page PAG2. Referring to Figure 5 , the bit lines BLx and BLy may be bit lines that cross the same word line. The first page buffer PBa and the second page buffer PBb may operate together to read data of the same page (e.g., the first page PAG1).

[0079] The first page buffer PBa may include a first sense latch SL1 and a first cache latch CL1, and the second page buffer PBb may include a second sense latch SL2 and a second cache latch CL2. The first sense latch SL1 may be electrically connected to the bit line BLx, and the second sense latch SL2 may be electrically connected to the bit line BLy. Based on the first sense latch control signal LTCH_S1 and the second sense latch control signal LTCH_S2, the first sense latch SL1 and the second sense latch SL2 may sense data stored in the memory cell MC according to the sense output voltage VSO of the sense output node (e.g., Figure 12A SO), and may store the sensed data. Based on the first sense latch control signal LTCH_S1 and the second sense latch control signal LTCH_S2, the first sense latch SL1 and the second sense latch SL2 may respectively dump (indicated by DPa) the data to the first cache latch CL1 and may dump (indicated by DPb) the data to the second cache latch CL2. For example, the time point at which the first sense latch SL1 dumps the data to the first cache latch CL1 may be different from the time point at which the second sense latch SL2 dumps the data to the second cache latch CL2. As another example, the time period during which the first sense latch SL1 dumps the data to the first cache latch CL1 may at least partially overlap with the time period during which the second sense latch SL2 dumps the data to the second cache latch CL2.

[0080] The first cache latch CL1 can send the dumped data (indicated by DOa) to the data I / O circuit 150 based on the first cache latch control signal LTCH_C1, and the second cache latch CL2 can send the dumped data (indicated by DOb) to the data I / O circuit 150 based on the second cache latch control signal LTCH_C2. The data I / O circuit 150 can output the data received from the first cache latch CL1 and can output the data received from the second cache latch CL2.

[0081] Referring to Figure 5 and Figure 6 in (a) of, the first sense latch SL1 and the second sense latch SL2 can sense the data stored in the same page PAG. The first sense latch SL1 can dump (DPa) a part of the data stored in the same page PAG to the first cache latch CL1, and the second sense latch SL2 can dump (DPb) the remaining part of the data stored in the same page PAG to the second cache latch CL2. In other words, the data can be dumped from the first sense latch SL1 and the second sense latch SL2 to the first cache latch CL1 and the second cache latch CL2 multiple times respectively. For example, after the first sense latch SL1 dumps the data (DPa) to the first cache latch CL1, the second sense latch SL2 can dump the data (DPb) to the second cache latch CL2. As another example, during at least a part of the time period when the first sense latch SL1 dumps the data (DPa) to the first cache latch CL1, the second sense latch SL2 can dump the data (DPb) to the second cache latch CL2. For example, the same page PAG can be the first page PAG1.

[0082] The first sense latch SL1 can dump the sensed data to the first cache latch CL1 during the time period tDPa. Thereafter, while the first cache latch CL1 sends the data to the data I / O circuit 150, the second sense latch SL2 can dump the data (DPb) to the second cache latch CL2. In other words, during the time period tDPb, the first cache latch CL1 can send a part of the data stored in the first page PAG1 to the data I / O circuit 150, and the second sense latch SL2 can dump the remaining part of the data stored in the first page PAG1 to the second cache latch CL2.

[0083] The time period tDOa during which the first cache latch CL1 sends data to the data I / O circuit 150 may be greater than or equal to the time period tDPb during which the second sense latch SL2 dumps data into the second cache latch CL2. The time point at which the operation DOa of the first cache latch CL1 sending data to the data I / O circuit 150 is completed may be later than the time point at which the operation DPb of the second sense latch SL2 dumping data into the second cache latch CL2 is completed.

[0084] The size of the data dumped by the first page buffer 111 may be substantially the same as the size of the data dumped by the second page buffer 112. The dump time period of the first page buffer 111 may be substantially the same as the dump time period of the second page buffer 112. For example, a part of the data stored in the first page PAG1 and dumped by the first sense latch SL1 into the first cache latch CL1 may have a size substantially the same as the data dumped from the second sense latch SL2 into the second cache latch CL2, and the dump duration of that part of the data stored in the first page PAG1 and dumped by the first sense latch SL1 into the first cache latch CL1 may be substantially the same as the dump duration of the data dumped from the second sense latch SL2 into the second cache latch CL2. As another example, the first sense latch SL1 may dump (DPa) half of the data stored in the first page PAG1 into the first cache latch CL1, and the second sense latch SL2 may dump (DPb) the remaining half of the data stored in the first page PAG1 into the second cache latch CL2. In other words, the first sense latch SL1 and the second sense latch SL2 may dump data having a data size corresponding to half of the size of the page PAG. For example, the first sense latch SL1 may be all the sense latches included in the first page buffer 111. The first cache latch CL1 and the second sense latch SL2 may be all the cache latches and all the sense latches included in the first page buffer 111 and the second page buffer 112 respectively, and the sense latches, cache latches, and data latches described later may be similarly interpreted.

[0085] Referring to Figure 5 and Figure 6In (b) thereof, the first sense latch SL1 may dump (DPc) a part of the data stored in the first page PAG1 to the first cache latch CL1, and the second sense latch SL2 may dump (DPd) the remaining part of the data stored in the first page PAG1 to the second cache latch CL2. Optimizations may be performed to reduce the time period for reading data from multiple pages. In some cases, for performing the optimization, the size of the data dumped by the second sense latch SL2 to the second cache latch CL2 may be larger than the size of the data dumped by the first sense latch SL1 to the first cache latch CL1. The time period tDPd taken by the second sense latch SL2 to dump the data to the second cache latch CL2 may be longer than the time period tDPc taken by the first sense latch SL1 to dump the data to the first cache latch CL1.

[0086] The time period tDOc taken by the first cache latch CL1 to send the data to the data I / O circuit 150 may be substantially equal to the time period tDPd taken by the second sense latch SL2 to dump the data to the second cache latch CL2. Thus, the first sense latch SL1 and the second sense latch SL2 may quickly sense the data stored in the next page (e.g., the second page PAG2), and ultimately may quickly read the data stored in the memory cell array 120. In other words, the time point at which the operation of the first cache latch CL1 to send the data to the data I / O circuit 150 is completed may be substantially the same as the time point at which the operation of the second sense latch SL2 to dump the data to the second cache latch CL2 is completed.

[0087] The time period tDOd taken by the second cache latch CL2 to send the data to the data I / O circuit 150 may be substantially equal to the sum of the time period tS' for the first sense latch SL1 to sense the data and the time period tDPc' for the first sense latch SL1 to dump the data to the first cache latch CL1. In other words, the time point at which the second cache latch CL2 completes sending the data stored in the first page PAG1 to the data I / O circuit 150 may be substantially equal to the time point at which the first sense latch SL1 completes sensing the data of the second page PAG2 and dumping the sensed data to the first cache latch CL1. For example, the time period tDOd may be equal to the sum of the time period tS' and the time period tDPc' (i.e., tDOd = tS' + tDPc').

[0088] and Figure 6Compared with (b) thereof, according to an exemplary embodiment of the inventive concept, the time period tDOd during which data is output may be slightly shortened. For example, the time period tDOd taken for the second cache latch CL2 to send data (DOd) to the data I / O circuit 150 may be less than the sum of the time period tS' during which the first sense latch SL1 senses data and the time period tDPc' during which the first sense latch SL1 dumps the data to the first cache latch CL1. For example, the time period tDOd may be less than the sum of the time period tS' and the time period tDPc' (i.e., tDOd < tS' + tDPc'). As another example, the time period tDOd may be greater than the sum of the time period tS' and the time period tDPc' (i.e., tDOd > tS' + tDPc'). In this case, the sensing of the second page PAG2 may be slightly delayed.

[0089] Figure 7 is a block diagram of a page buffer according to an exemplary embodiment of the inventive concept.

[0090] Referring to Figure 7 , the page buffer PB may include a sense latch SL, a data latch DL, and a cache latch CL. The sense latch SL may dump data to the data latch DL. The data latch DL may dump the data to the cache latch CL. The cache latch CL may send the data to the data I / O circuit 150.

[0091] The sense latch SL may be electrically connected to the bit line BLx, and based on the sense latch control signal LTCH_S, it may sense the data stored in the memory cell MC according to the sense output voltage VSO of the sense output node (e.g., Figure 12A SO) and store the sensed data. The sense latch SL may dump the stored data based on the sense latch control signal LTCH_S.

[0092] Based on the data latch control signal LTCH_D, the data latch DL may receive the data dumped by the sense latch SL and may dump the received data to the cache latch CL. In some cases, the data latch DL may selectively dump the data dumped by the sense latch SL. For example, some data latches DL may maintain the data without dumping the data to the cache latch CL.

[0093] Based on the cache latch control signal LTCH_C, the cache latch CL may send the data dumped by the data latch DL to the data I / O circuit 150.

[0094] The latch control signals including the sense latch control signal LTCH_S, the data latch control signal LTCH_D, and the cache latch control signal LTCH_C may be included inFigure 1 in the page buffer control signal CTRL_PB.

[0095] Figure 8 is a data flow diagram for explaining the operation of a page buffer according to an exemplary embodiment of the inventive concept.

[0096] Referring to Figure 7 and Figure 8 , the sense latch SL may sense the data of the first page PAG1 according to the sense output voltage VSO. Thereafter, the sense latch SL may dump (DP1) the data of the first page PAG1 to the data latch DL. The data latch DL may dump (DP2) the dumped data to the cache latch CL.

[0097] While the data latch DL performs the dump (DP2), the sense latch SL may sense the data of the second page PAG2. In other words, the sensing operation and the dump operation involving the different sense latch SL and data latch DL may be performed in parallel. The cache latch CL may dump (DO) the data dumped by the data latch DL.

[0098] Referring to Figure 8 of (a), the time period tDP1 during which the sense latch SL included in the page buffer PB dumps data to the data latch DL may be less than the time period tDP2 during which the data latch DL dumps data to the cache latch CL. For example, the physical distance between the sense latch SL and the data latch DL may be less than the physical distance between the data latch DL and the cache latch CL. As another example, the length of the current path from the sense latch SL to the data latch DL may be less than the length of the current path from the data latch DL to the cache latch CL. As another example, the number of latches included between the data latch DL and the cache latch CL may be less than the number of latches included between the sense latch SL and the data latch DL. In other words, according to an exemplary embodiment of the inventive concept, the load may be adjusted according to, for example, the physical distance between different latches, the current path therebetween, or the number of other latches included therebetween.

[0099] Referring to Figure 8 of (a), the page buffer PB according to an exemplary embodiment of the inventive concept reduces the time period tDP1 during which the sense latch SL dumps the data of the first page PAG1 to the data latch DL, and thus, the time point at which the sense latch SL senses the data of the second page PAG2 may be advanced. In other words, according to an exemplary embodiment of the inventive concept, in a sequential read operation, the page buffer PB may quickly sense the data of the next page PAG.

[0100] Referring to Figure 8In (b), the time period tDP1 during which the sense latch SL included in the page buffer PB dumps data to the data latch DL may be greater than the time period tDP2 during which the data latch DL dumps data to the cache latch CL. For example, the physical distance between the sense latch SL and the data latch DL may be greater than the physical distance between the data latch DL and the cache latch CL. As another example, the current path from the sense latch SL to the data latch DL may be longer than the current path from the data latch DL to the cache latch CL. As another example, the number of latches included between the data latch DL and the cache latch CL may be greater than the number of latches included between the sense latch SL and the data latch DL. According to an exemplary embodiment of the inventive concept, in Figure 8 In the case of (b) (e.g., when the time period tDP1 is greater than the time period tDP2), the time point at which the transfer of data stored in the page after the first page PAG1 to the data I / O circuit 150 starts may be earlier than Figure 8 In the case of (a) (e.g., when the time period tDP1 is less than the time period tDP2).

[0101] Referring to Figure 8 In (c), the time period tDP1 during which the sense latch SL included in the page buffer PB dumps data to the data latch DL may be equal to or substantially equal to the time period tDP2 during which the data latch DL dumps data to the cache latch CL. For example, the physical distance between the sense latch SL and the data latch DL may be equal to the physical distance between the data latch DL and the cache latch CL. As another example, the length of the current path from the sense latch SL to the data latch DL may be equal to the length of the current path from the data latch DL to the cache latch CL. As another example, the number of latches included between the sense latch SL and the data latch DL may be equal to the number of latches included between the data latch DL and the cache latch CL. In other words, according to an exemplary embodiment of the inventive concept, the load may be adjusted according to, for example, the physical distance between different latches, the current path therebetween, or the number of other latches included therebetween.

[0102] Figure 9 is a data flow diagram for explaining the operation of the page buffer according to an exemplary embodiment of the inventive concept.

[0103] Referring to Figure 9In (a), the sum of the time period tS during which the sense latch SL senses data and the time period tDP1 during which the sense latch SL dumps the data into the data latch DL may be equal to the sum of the time period tDP2 during which the data latch DL dumps the data into the cache latch CL and the time period tDO during which the cache latch CL transmits the data (e.g., tS + tDP1 = tDP2 + tDO). The data dumped into the data latch DL may be data included in any page PAG. For example, the sense latch SL may sense and dump (DP1) the data of the first page PAG1 and may sense and dump (DP1) the data of the second page PAG2.

[0104] Referring to Figure 9 In (b), the data latch DL may dump the data dumped by the sense latch SL into the data latch DL after a time period tol1. Thus, while the sense latch SL senses the data of the third page PAG3 during a time period tol2, the cache latch CL may sense the data of the first page PAG1. In other words, the page buffer PB according to an exemplary embodiment of the inventive concept may output the data of the Nth page while sensing the data of the (N + 2)th page.

[0105] Figure 10 is a block diagram of a page buffer including a first page buffer and a second page buffer according to an exemplary embodiment of the inventive concept. Figure 11 is for explaining Figure 10 the operations of the first page buffer and the second page buffer according to an exemplary embodiment of the inventive concept

[0106] Referring to Figure 10 , the first page buffer Pba is one of the page buffers in the first page buffer 111, and the second page buffer PBb is one of the page buffers in the second page buffer 112. Latch control signals (LTCH_S1, LTCH_S2, LTCH_D1, LTCH_D2, LTCH_C1, and LTCH_C2) may be included in Figure 1 the page buffer control signal CTRL_PB of

[0107] Referring to Figure 10 and Figure 11 , the first page buffer PBa and the second page buffer PBb may perform a sequential read operation on the data stored in the memory cell array 120 in units of pages PAG. Thus, referring to Figure 10 , the bit line BLx and the bit line BLy may be bit lines intersecting the same word line. The first page buffer PBa and the second page buffer PBb may operate together to read the data of the same page (e.g., the first page PAG1).

[0108] Referring toFigure 10 The control logic unit 140 can control the page buffer circuit 110 such that the first sense latch SL1 and the second sense latch SL2 included in the first page buffer PBa and the second page buffer PBb respectively sense the voltages of multiple bit lines from the same page PAG, and dump the data to the first data latch DL1 and the second data latch DL2. For example, based on the first sense latch control signal LTCH_S1, the first sense latch SL1 can store the data corresponding to the sensed voltage and dump (DP1a) the stored data to the first data latch DL1. Based on the second sense latch control signal LTCH_S2, the second sense latch SL2 can store the data corresponding to the sensed voltage and dump (DP1b) the stored data to the second data latch DL2. For example, each piece of data dumped (DP1a and DP1b) by the first sense latch SL1 and the second sense latch SL2 respectively can be each piece of data stored in all memory cells included in a single page PAG.

[0109] Refer to Figure 11 Based on the first sense latch control signal LTCH_S1 and the second sense latch control signal LTCH_S2 respectively, the first sense latch SL1 can sense and store a part of the data of the first page PAG1 and dump the stored data (DP1a), and the second sense latch SL2 can sense and store another part of the data of the first page PAG1 and dump the stored data (DP1b).

[0110] Return to refer to Figure 10 The control logic unit 140 can control the page buffer circuit 110 such that the first data latch DL1 stores the data dumped by the first sense latch SL1 and dumps the stored data to the first cache latch CL1. For example, the first data latch DL1 can store data in response to the first data latch control signal LTCH_D1 indicating to store the dumped data. The first data latch DL1 can dump (DP2) data in response to the first data latch control signal LTCH_D1 indicating to dump the stored data.

[0111] The control logic unit 140 can control the page buffer circuit 110 such that while the first data latch DL1 dumps (DP2) data, the second data latch DL2 delays dumping (DP3). For example, after the control logic unit 140 sends the first data latch control signal LTCH_D1 indicating to dump the stored data to the first data latch DL1, the control logic unit 140 can send the second data latch control signal LTCH_D2 indicating to store the data dumped by the second sense latch SL2 to the second data latch DL2.

[0112] According to an exemplary embodiment of the inventive concept, the control logic unit 140 may control the page buffer circuit 110 such that the first cache latch CL1 transmits (DO3) the data dumped by the first data latch DL1 to the data I / O circuit 150. The control logic unit 140 may also control the page buffer circuit 110 such that the second data latch DL2 dumps (DP3) the stored data to the second cache latch CL2.

[0113] Specifically, the control logic unit 140 may control the page buffer circuit 110 such that the second data latch DL2 dumps (DP3) data during at least a portion of a time period in which the first cache latch CL1 transmits (DO3) data to the data I / O circuit 150.

[0114] Referring to Figure 11 , during at least a portion of a time period in which the first cache latch CL1 transmits (DO3) data to the data I / O circuit 150, the second data latch DL2 may dump (DP3) data. For example, the control logic unit 140 may transmit a first cache latch control signal LTCH_C1 indicating transmission of the stored data to the first cache latch CL1, and may transmit a second data latch control signal LTCH_D2 indicating dumping of the stored data to the second data latch DL2.

[0115] In this case, a time period tDP3 during which the second data latch DL2 dumps data may be less than a time period tDO3 during which the first cache latch CL1 transmits data to the data I / O circuit 150. Accordingly, while the data transmission operation (DO3) is being completed, the second data latch DL2 may hide a time period taken for the data dump operation DP3 by performing the data dump operation DP3 within a time period taken for the data transmission operation DO3. Accordingly, it may be considered that there is substantially no additional time period corresponding to the data dump operation DP3 in the page buffer circuit 110. According to experiments, a read time period taken to read one memory block BLK may be reduced by about 40%.

[0116] Returning to referring Figure 10 , the control logic unit 140 may control the page buffer circuit 110 such that the second cache latch CL2 outputs data. For example, the control logic unit 140 may transmit a second cache latch control signal LTCH_C2 indicating output of the stored data to the second cache latch CL2.

[0117] According to an exemplary embodiment of the inventive concept, a total time period taken for the page buffer circuit 110 to sense data and transmit the sensed data to the data I / O circuit 150 may be reduced. Now referring to Figure 4And Figure 11 Describe the time period spent in dumping the data corresponding to the first page PAG1.

[0118] Refer to Figure 4 , it takes a time period tDP to dump from the sense latch to the cache latch. Refer to Figure 11 , it takes a time period tDP1 to dump data from the first sense latch SL1 and the second sense latch SL2 to the first data latch DL1 and the second data latch DL2, a time period tDP2 to dump data from the first data latch DL1 to the first cache latch CL1, and a time period tDP3 to dump data from the second data latch DL2 to the second cache latch CL2.

[0119] Refer to Figure 4 , the cache latch sends the data of the first page PAG1 during the time period tDO. Refer to Figure 11 , the data sent by the first cache latch CL1 and the data sent by the second cache latch CL2 can be the data of the first page PAG1. In this case, the first cache latch CL1 sends data during the time period tDO3, and the second cache latch CL2 sends data during the time period tDO4. Therefore, since Figure 4 all cache latches of Figure 11 the first cache latch CL1 and the second cache latch CL2 send the data of the first page PAG1, the time period tDO can be equal to the sum of the time period tDO3 and the time period tDO4.

[0120] According to an exemplary embodiment of the inventive concept, the first page buffer 111 and the second page buffer 112 may sense each piece of data having substantially the same number of bits from the page PAG and output the sensed data. In other words, the first page buffer 111 and the second page buffer 112 may bisect the depth of the page, and sense and output each piece of data stored in the two halves of the page. In some cases, the number of the first page buffers 111 may be the same as the number of the second page buffers 112.

[0121] For example, the number of bits of the data sensed and stored by the first sense latch SL1 from the first page PAG1 may be substantially the same as the number of bits of the data sensed and stored by the second sense latch SL2 from the second page PAG2. The number of bits of the data sent by the first cache latch CL1 to the data I / O circuit 150 may be substantially the same as the number of bits of the data sent by the second cache latch CL2 to the data I / O circuit 150.

[0122] As another example, the time periods taken for the respective latches of the first page buffer 111 to sense, dump, and / or transmit data may be substantially the same as the time periods taken for the respective latches of the second page buffer 112 corresponding to the respective latches of the first page buffer 111 to sense, dump, and / or transmit data. For example, the time period taken for the first sense latch SL1 to sense data from the first page PAG1 and store the sensed data may be substantially the same as the time period taken for the second sense latch SL2 to sense data from the second page PAG2 and store the sensed data. The time period taken for the first cache latch CL1 to transmit data to the data I / O circuit 150 may be substantially the same as the time period taken for the second cache latch CL2 to transmit data to the data I / O circuit 150.

[0123] According to an exemplary embodiment of the inventive concept, the time period tDP1 taken for dumping data from the first sense latch SL1 and the second sense latch SL2 to the first data latch DL1 and the second data latch DL2 may be less than the time period tDP2 taken for dumping data from the first data latch DL1 to the first cache latch CL1 or the time period tDP3 taken for dumping data from the second data latch DL2 to the second cache latch CL2. This will be described in more detail later with reference to Figure 12A and Figure 12B described in more detail.

[0124] Figure 12A is a block diagram of a page buffer according to an exemplary embodiment of the inventive concept.

[0125] Referring to Figure 12A , in addition to the sense latch SL, the data latch DL, and the cache latch CL, the page buffer PB may further include a bit line connector BLC and a precharge circuit PC. Components included in the page buffer PB may be connected to each other via wires branched from the sense output node SO.

[0126] During a read operation, the control logic unit 140 may precharge the bit line BL. For example, when the load signal LD and the control signal BLSHF are activated, the bit line BL may be precharged to a specific level VPC. In this case, the bit line connector BLC may maintain a conductive state in accordance with the bit line selection signal BLSLT. Thereafter, when the load signal LD is not activated, the charge in the sense output node SO may flow to the bit line BL via the bit line connector BLC that is conductive in accordance with the control signal BLSHF.

[0127] When the selected memory cell is an On cell, the charge in the sense output node SO may flow via the bit line BL and the channel of the string to Figure 2BThe common source line CSL discharges. In this case, since a relatively large current flows from the sense output node SO to the bit line BL, the voltage of the sense output node SO drops at a relatively high speed.

[0128] On the other hand, when the selected memory cell is an Off cell, it may be difficult for the charge in the sense output node SO to discharge to the common source line CSL via the bit line BL. Therefore, since a relatively small current flows from the sense output node SO to the bit line BL, the voltage of the sense output node SO drops at a relatively low speed.

[0129] The sense latch SL can sense the potential change of the sense output node SO and store data corresponding to the potential change. In other words, the sense latch SL can sense and store the data of the selected memory cell via the bit line BL.

[0130] According to an exemplary embodiment of the inventive concept, the control logic unit 140 may send a sense latch control signal LTCH_S such that the data stored in the sense latch SL is dumped to the data latch DL. In this case, the sense latch SL may dump the data to the data latch DL via the first current path C1. The control logic unit 140 may send a data latch control signal LTCH_D such that the data stored in the data latch DL is dumped to the cache latch CL. In this case, the data latch DL may dump the data to the cache latch CL via the second current path C2.

[0131] According to an exemplary embodiment of the inventive concept, the load between the sense latch SL and the data latch DL may be smaller than the load between the data latch DL and the cache latch CL. For example, the distance of the first current path C1 may be smaller than the distance of the second current path C2. For example, the page buffer PB may be designed such that the separation distance between the sense latch SL and the data latch DL may be smaller than the separation distance between the data latch DL and the cache latch CL. Since the load between the sense latch SL and the data latch DL is smaller, the time period (e.g., Figure 11 tDP1) taken for the data to be dumped from the sense latch SL to the data latch DL may be relatively short. Specifically, since the distance of the first current path C1 is smaller than the distance of the second current path C2, the time period (e.g., Figure 11 tDP1) taken for the sense latch SL to dump the data to the data latch DL may be smaller than the time period (e.g., Figure 11 tDP2) taken for the data latch DL to dump the data to the cache latch CL.

[0132] According to an exemplary embodiment of the inventive concept, when the distance of the first current path C1 is smaller than the distance of the second current path C2 , the total time period taken for the page buffer circuit 110 to perform the dump may be reduced.

[0133] Return to reference Figure 10 and Figure 11 , when the load between the first sense latch SL1 and the second sense latch SL2 and the first data latch DL1 and the second data latch DL2 is designed to be small, the time period tDP1 taken to dump data from the first sense latch SL1 and the second sense latch SL2 to the first data latch DL1 and the second data latch DL2 can be reduced by a specific reduction time period △dt. For example, the time period taken for the first sense latch SL1 to perform the dump operation DP1a can be tDP1-△dt. On the other hand, the time period tDP2 taken to dump data from the first data latch DL1 to the first cache latch CL1 can be increased by a first increase time period △it1, and the time period tDP3 taken to dump data from the second data latch DL2 to the second cache latch CL2 can be increased by a second increase time period △it2.

[0134] Figure 12B is a block diagram of a page buffer according to an exemplary embodiment of the inventive concept.

[0135] According to an exemplary embodiment of the present inventive concept, in addition to Figure 12A In addition to the components of the page buffer PB, the page buffer PB may further include a plurality of first latches LT1 and a plurality of second latches LT2. Figure 12B , a sense latch SL, a plurality of first latches LT1, a data latch DL, a plurality of second latches LT2, and a cache latch CL may be sequentially connected in parallel to a sense output node SO, and the number of first latches LT1 may be greater than the number of second latches LT2.

[0136] The page buffer PB may include a plurality of latches as needed. When selecting a latch to be used as the data latch DL from the plurality of latches, the separation distance between the sense latch SL and the data latch DL and the separation distance between the data latch DL and the cache latch CL may be considered. Figure 12A Given the description, the time period tDP1 taken by the sense latch SL to dump data to the data latch DL can be reduced, and thus, the time period tDP2 taken by the data latch DL to dump data to the cache latch CL (i.e., the hidden time period not added to the total dump time period) can be increased. Therefore, the time period taken by the page buffer circuit 110 to dump data can be reduced.

[0137] Figure 13 andFigure 14 This is a data flow diagram for explaining the operations of a first page buffer and a second page buffer according to an exemplary embodiment of the inventive concept.

[0138] Referring to Figure 13 , the time period tDO3 taken by the first cache latch CL1 to send data to the data I / O circuit 150 may be substantially equal to the time period tDP3 taken by the second data latch DL2 to dump data into the second cache latch CL2. In other words, the time period tDO3 taken by the first page buffer Pba to output data to the data I / O circuit 150 may be substantially equal to the time period tDP3 taken by the second data latch DL2 to perform the dump. Thus, compared with the case of Figure 11 , immediately after the operation (DP3) of the second data latch DL2 dumping data into the second cache latch CL2 is completed, the second cache latch CL2 may send (DO4) the data to the data I / O circuit 150.

[0139] According to an exemplary embodiment of the inventive concept, the time period taken by the second cache latch CL2 to output data to the data I / O circuit 150 may be the time period tDO4. The time period tDO4 may be less than the comparison time period.

[0140] The comparison time period may refer to the time period obtained by subtracting the time period tDP2 taken to dump the data of the first page PAG1 from the first data latch DL1 to the first cache latch CL1 and the time period tDP3 taken to dump data from the second data latch DL2 to the second cache latch CL2 from the sum of the time period tS1 taken to sense the second page PAG2, the time period tDP1 taken to dump data, and the time period tDP2 taken to dump the data of the second page PAG2 from the first data latch DL1 to the first cache latch CL1. For example, the time period tDP2 taken to dump the data of the second page PAG2 into the first cache latch CL1 may be equal to the time period tDP2 taken to dump the data of the first page PAG1 into the first cache latch CL1. In this case, the comparison time period may be obtained by summing the time period tS1 and the time period tDP1 and subtracting the time period tDP3 from the sum result. For example, the comparison time period may be expressed as tS1 + tDP1 - tDP3. In this case, the time period tDP1 taken to dump data may be the time period taken to dump data from the first sense latch SL1 to the first data latch DL1 or the time period taken to dump data from the second sense latch SL2 to the second data latch DL2. For example, the time periods taken by the first sense latch SL1 and the second sense latch SL2 to perform the dump respectively may be the same as each other.

[0141] Before all data of the second page PAG2 is sensed by the second page buffer PBb, the second page buffer PBb may complete the operation of sending data from the second cache latch CL2 to the data I / O circuit 150 (DO4).

[0142] According to an exemplary embodiment of the inventive concept, depending on the size of the output data, the time period taken for the second cache latch CL2 to send data to the data I / O circuit 150 may be the sum of the time period tDO4 and the time period tDO4_1. The sum of the time period tDO4 and the time period tDO4_1 may be equal to the comparison time period. When expressed by a formula, the sum of the time period tDO4 and the time period tDO4_1 may be expressed as tDO4 + tDO4_1 = tS1 + tDP1 - tDP3. As described above, the time period tDO3 taken for the first page buffer Pba to output data to the data I / O circuit 150 may be substantially equal to the time period tDP3 taken for the second data latch DL2 to perform a dump. Therefore, the formula may be differently expressed as tDO3 + tDO4 + tDO4_1 = tS1 + tDP1.

[0143] Refer to Figure 14 , the time period taken for the second cache latch CL2 to send data may be the time period tDO4_2. In this case, the time period tDO4_2 may be greater than the comparison time period.

[0144] Return to refer to Figure 13 , at the moment when the operation (DP2) of the first data latch DL1 dumping the data of the second page PAG2 to the first cache latch CL1 is completed, the operation (DO4) of the second cache latch CL2 sending the data of the first page PAG1 may be completed. Alternatively, before the operation (DP2) of the first data latch DL1 dumping the data of the second page PAG2 to the first cache latch CL1 is completed, the operation (DO4) of the second cache latch CL2 sending the data of the first page PAG1 may be completed.

[0145] Refer to Figure 14 , at the moment when the operation (DP3) of the second data latch DL2 dumping data to the second cache latch CL2 is completed or after that moment, the operation DO3 of the first cache latch CL1 sending data to the data I / O circuit 150 may be completed.

[0146] Figure 15A is a block diagram of a page buffer circuit according to an exemplary embodiment of the inventive concept.

[0147] Refer to Figure 15A, the page buffer circuit 110 may include a plurality of first page buffers 111, a plurality of second page buffers 112 to a plurality of nth page buffers 11n. For example, the first page buffer 111 may include Figure 1 some of the plurality of page buffers PB1 to PBm, the second page buffer 112 may include Figure 1 some of the plurality of page buffers PB1 to PBm, and the nth page buffer 11n may include Figure 1 some of the plurality of page buffers PB1 to PBm, where n may be a positive number greater than 2.

[0148] According to an exemplary embodiment of the inventive concept, the first page buffer PBa, the second page buffer PBb, and the nth page buffer PBn included in the page buffer circuit 110 may operate corresponding to one plane PL. For example, each first page buffer Pba, each second page buffer PBb, and each nth page buffer PBn may be operable to read data from the same plane (e.g., Figure 2D the first plane PL1).

[0149] According to an exemplary embodiment of the inventive concept, the first page buffer 111 may be connected to a plurality of bit lines BLx of the first plane PL1, the second page buffer 112 may be connected to a plurality of bit lines B Ly of the first plane PL1, and the nth page buffer 11n may be connected to a plurality of bit lines BLz of the first plane PL1. In other words, the first page buffer PBa may be connected to each bit line BLx, the second page buffer PBb may be connected to each bit line BLy, and the nth page buffer PBn may be connected to each bit line BLz.

[0150] Figure 15B is a block diagram of the page buffers included in the page buffer circuit for illustrating an exemplary embodiment of the inventive concept. The same description as that given above with reference to Figure 15A will not be repeated herein. Figure 15B the same as that Figure 10 given above.

[0151] Referring to Figure 15B , the first page buffer PBa may include a first sense latch SL1, a first data latch DL1, and a first cache latch CL1, the second page buffer PBb may include a second sense latch SL2, a second data latch DL2, and a second cache latch CL2, and the nth page buffer PBn may include an nth sense latch SLn, an nth data latch DLn, and an nth cache latch CLn, where n may be a positive number greater than 2.

[0152] According to an exemplary embodiment of the inventive concept, a first page buffer PBa, a second page buffer PBb, and an n-th page buffer PBn included in a page buffer circuit 110 may read respective data from the same plane. For example, the first page buffer PBa may sense and read data from some bit lines BLx connected to the plane, the second page buffer PBb may sense and read data from some bit lines BLy connected to the plane, and the n-th page buffer PBn may sense and read data from some bit lines BLz connected to the plane.

[0153] According to an exemplary embodiment of the inventive concept, data dumping from a data latch DL to a cache latch CL may be performed three or more times. For example, a first data latch DL1 may perform data dumping DP2 to a first cache latch CL1, a second data latch DL2 may perform data dumping DP3 to a second cache latch CL2, and an n-th data latch DLn may perform data dumping DPn to an n-th cache latch CLn. Since only some of the respective data stored in the plane may be read during a random read, some of the first data latch DL1 to the n-th data latch DLn may perform dumping.

[0154] Figure 15C is a data flow diagram for explaining Figure 15B the operation of a page buffer according to an exemplary embodiment of the inventive concept.

[0155] Referring to Figure 15B and Figure 15C first sense latches SL1 to an n-th sense latch SLn included in the first page buffer Pba to the n-th page buffer PBn may sense data of a first page PAG1 and may dump (DP1) the sensed data to the first data latch DL1 to the n-th data latch DLn.

[0156] According to an exemplary embodiment of the inventive concept, the first data latch DL1 may dump (DP2) data to the first cache latch CL1. Thereafter, while the first cache latch CL1 sends (DO3) the data to a data I / O circuit 150, the second data latch DL2 may dump (DP3) data to the second cache latch CL2. In other words, while the first page buffer PBa outputs (DO3) data, the second page buffer PBb may dump (DP3) data. In other words, while a k-th cache latch included in a k-th page buffer sends data, a (k + 1)-th data latch included in a (k + 1)-th page buffer may dump data, where k may be an integer in a range of 1 to n - 1.

[0157] According to an exemplary embodiment of the inventive concept, when the second cache latch CL2 transmits entire data (DO4), the n-th data latch DLn may dump data of the first page PAG1 to the n-th cache latch CLn (DPn). Thereafter, while the n-th cache latch CLn transmits the data of the first page PAG1 (DOn+1) to the data I / O circuit 150, the n-th sense latch SLn may dump data of the second page PAG2 (DP1n) to the n-th data latch DLn.

[0158] According to an exemplary embodiment of the inventive concept, a time period tDP2 taken by the first data latch DL1 to dump data to the first cache latch CL1, a time period tDP3 taken by the second data latch DL2 to dump data to the second cache latch CL2, a time period tDO3 taken by the first cache latch CL1 to transmit data to the data I / O circuit 150, and a time period tDO4 taken by the second cache latch CL2 to transmit data to the data I / O circuit 150 may be substantially the same as each other.

[0159] Alternatively, a time period taken by the first data latch DL1 to the n-th data latch DLn to dump data to the first cache latch CL1 to the n-th cache latch CLn may be substantially the same as a time period taken by the first cache latch CL1 to the n-th cache latch CLn to transmit data to the data I / O circuit 150. For example, the time period tDP2, the time period tDP3, the time period tDO3, the time period tDO4 to the time periods tDPn and tDOn+1 may be substantially the same as each other.

[0160] Referring to Figure 15C , a time point at which the first page buffer Pba to the n-th page buffer PBn transmit entire data of the first page PAG1 to the data I / O circuit 150 (e.g., a time point at which a transmission operation DOn+1 has been completed) may be later than a time point at which data of the second page PAG2 is transmitted to the data latch DL (e.g., at least one of dump operations DP1a to DP1n).

[0161] However, compared to the above example, a time point at which the first page buffer Pba to the n-th page buffer PBn transmit entire data of the first page PAG1 to the data I / O circuit 150 (e.g., a time point at which a transmission operation DOn+1 has been completed) may be substantially the same as a time point at which data of the second page PAG2 is transmitted to the data latch DL (e.g., at least one of dump operations DP1a to DP1n).

[0162] According to an exemplary embodiment of the inventive concept, a time point at which a first data latch DL1 terminates a dump operation DP2 may be substantially the same as a time point at which a second data latch DL2 starts a dump operation DP3. Alternatively, a time point at which the first data latch DL1 terminates the dump operation DP2 may be a time point before or after the second data latch DL2 starts the dump operation DP3.

[0163] Figure 16 is a block diagram for explaining a non-volatile memory device according to an exemplary embodiment of the inventive concept.

[0164] Referring to Figure 16 , the non-volatile memory device 10 may include: a plurality of planes PLNa and PLNb including a plurality of pages PAG10 to PAG1n and PAG20 to PAG2n; a plurality of page buffer circuits, that is, a first page buffer circuit 110a and a second page buffer circuit 110b; a plurality of row decoders 130a and 130b; and a control logic unit 140, wherein the plurality of pages PAG10 to PAG1n and PAG20 to PAG2n include a plurality of memory cells.

[0165] Each of the planes PLNa and PLNb represents a memory cell array connected to a single page buffer circuit 110 that operates independently. For example, the first plane PLNa may be a memory cell array connected to the first page buffer circuit 110a. The second plane PLNb may be a memory cell array connected to the second page buffer circuit 110b.

[0166] The non-volatile memory device 10 may perform a read operation in units of pages PAG included in the connected planes. For example, in response to a command CMD and an address ADDR indicating a random read operation, the control logic unit 140 may read data from at least one memory cell (e.g., at least one of memory cells MCs1 and MCs2) included in at least one page PAG. Specifically, the control logic unit 140 may control the first page buffer circuit 110a and the second page buffer circuit 110b such that the first page buffer circuit 110a senses data from the first plane PLNa and the second page buffer circuit 110b senses data from the second plane PLNb.

[0167] The random read operation may represent an operation of reading each piece of data occasionally stored in at least one memory cell included in at least one page PAG. Now, an operation of the page buffer circuit 110 when the non-volatile memory device 10 performs a random read operation will be described in detail.

[0168] Figure 17 is a block diagram for explaining a first page buffer and a second page buffer according to an exemplary embodiment of the inventive concept, Figure 18It is a data flow diagram for explaining the operations of a first page buffer and a second page buffer according to an exemplary embodiment of the inventive concept. Figure 17 of the first page buffer and the second page buffer.

[0169] Referring to Figure 17 and Figure 18 , the first page buffer PBa and the second page buffer PBb may perform a random read operation on data stored in a plane in units of a page PAG. Bit lines BLx and BLy may be bit lines that cross the same word line. The first page buffer PBa and the second page buffer PBb may operate together to read data of the same page (e.g., Figure 16 the page PAG10 of

[0170] As described above with reference to Figure 16 , in a random read operation, data stored in some memory cells is read from only one page, and there is no need to read data stored in the remaining memory cells from that page. Referring to Figure 16 , for example, data stored in some memory cells MCs1 among a plurality of memory cells included in the page PAG10 may be read, and data stored in the remaining memory cells may not be read. In this case, Figure 17 the bit line BLx of

[0171] Referring to Figure 10 , the control logic unit 140 may control the page buffer circuit 110 such that a first sense latch SL1 and a second sense latch SL2 included in the first page buffer PBa and the second page buffer PBb respectively sense voltages from multiple bit lines of the same page PAG and dump the data to a first data latch DL1 and a second data latch DL2.

[0172] According to an exemplary embodiment of the inventive concept, the control logic unit 140 may send a first data latch control signal LTCH_D1 for controlling the first data latch DL1 to dump (DP2) data to the first cache latch CL1 based on a command and an address indicating a random read operation. The control logic unit 140 may also send a second data latch control signal LTCH_D2 for controlling the second data latch DL2 not to dump data to the second cache latch CL2.

[0173] For example, the control logic unit 140 may identify memory cells storing data to be read based on an address ADDR (e.g.,Figure 16 The memory cells MCs1) perform a random read operation on the memory cells included in a page (e.g., Figure 16 page PAG10). The control logic unit 140 may identify the data stored in the identified memory cells (e.g., Figure 16 memory cells MCs1) as data corresponding to the data to be dumped from the first data latch DL1 to the first cache latch CL1. The control logic unit 140 may send a first data latch control signal LTCH_D1 such that the data stored in the first data latch DL1 is dumped to the first cache latch CL1 (DP2).

[0174] The control logic unit 140 may also identify, based on the address ADDR, the memory cells storing data not read via the random read operation among the memory cells included in a page (e.g., Figure 16 page PAG10). The control logic unit 140 may also send a second data latch control signal LTCH_D2 so that the data stored in the identified memory cells is not dumped from the second data latch DL2 to the second cache latch CL2. Specifically, the control logic unit 140 may send only the second data latch control signal LTCH_D2 indicating the data dumped by the second sense latch SL2, and then the control logic unit 140 may not send the second data latch control signal LTCH_D2 indicating the data dumped to the second cache latch CL2.

[0175] Referring to Figure 18 , based on the sense latch control signal LTCH_S, the first sense latch SL1 and the second sense latch SL2 may sense and store the data of the x-th page PAGx and may dump the stored data (DP1). Based on the first data latch control signal LTCH_D1, the first data latch DL1 may dump the stored data (DP2). Based on the first cache latch control signal LTCH_C1, the first cache latch CL1 may send the data to the data I / O circuit 150 (DO3).

[0176] According to an exemplary embodiment of the inventive concept, when the non-volatile memory device 10 performs a random read operation, the total time period taken for the page buffer circuit 110 to perform dumping may be reduced. Now, a sequential read operation and a random read operation will be compared and described with reference to Figure 11 and Figure 18 .

[0177] Referring to Figure 11, when the non-volatile memory device 10 performs a sequential read operation, the time period taken for the page buffer circuit 110 to sense data and output the sensed data to the data I / O circuit 150 will be referred to as the first time period. In this case, the first time period is the same as the sum of the time period tS, the time period tDP1, the time period tDP2, the time period tDO3, and the time period tDO4. Refer to Figure 18 , when the non-volatile memory device 10 performs a random read operation, the time period taken for the page buffer circuit 110 to sense data and output the sensed data to the data I / O circuit 150 will be referred to as the second time period. In this case, the second time period is the same as the sum of the time period tS, the time period tDP1, the time period tDP2', and the time period tDO3'.

[0178] Figure 11 and Figure 18 the time periods tS are substantially the same as each other and Figure 11 and Figure 18 the time periods tDP1 are substantially the same as each other because the first sense latch SL1 and the second sense latch SL2 for sensing data of one page PAG in the sequential read operation are the same as those in the random read operation, and the first sense latch SL1 and the second sense latch SL2 for dumping the entire stored data to the first data latch DL1 and the second data latch DL2 in the sequential read operation are the same as those in the random read operation.

[0179] However, in the case of the first time period when the non-volatile memory device 10 performs a sequential read operation, an additional time period tDO4 may be spent. In other words, in the random read operation, compared with the sequential read operation, the time period tDO4 taken for the second cache latch CL2 to output data may be reduced. Figure 18 the time periods tDP2' and tDO3' may be relatively shorter than Figure 11 the time periods tDP2 and tDO3, respectively. Accordingly, the control logic unit 140 may control the second data latch DL2 to selectively dump data to the second cache latch CL2.

[0180] The non-volatile memory device 10 according to an exemplary embodiment of the inventive concept may sense and output data of different pages PAG.

[0181] Refer to Figure 16 and Figure 18, the control logic unit 140 can control the first page buffer circuit 110a to output data stored in some memory cells MCs1 included in page PAG10, and can control the second page buffer circuit 110b to output data stored in some memory cells MCs2 included in page PAG22. Since page PAG10 and page PAG22 are included in different planes PLN, the first page buffer circuit 110a and the second page buffer circuit 110b, which are different page buffer circuits 110, can read data independently. Therefore, when the control logic unit 140 senses pages of different planes PLN (e.g., pages PAG10 and PAG22) in parallel to perform a random read operation, the control logic unit 140 can reduce the time period spent on sensing. Now, the address queuing operation performed by the control logic unit 140 to sense pages in parallel will be described in detail.

[0182] Figure 19 is a diagram for explaining the address queuing operation performed by a control logic unit according to an exemplary embodiment of the inventive concept. Figure 19 (a) of shows a plurality of addresses received by the control logic unit 140 when the non-volatile memory device 10 performs a random read operation, that is, the first address ADD1 to the sixth address ADD6, Figure 19 (b) of shows the queuing of the first address ADD1 to the sixth address ADD6 received by the control logic unit 140. The address ADDR may include the first address ADD1 to the sixth address ADD6.

[0183] Referring to Figure 19 , the first address ADD1 indicates that the data to be read is stored in page PAG10 of the first plane PLN1, the second address ADD2 indicates that the data to be read is stored in page PAG14 of the first plane PLN1, and the third address ADD3 indicates that the data to be read is stored in page PAG22 of the second plane PLN2.

[0184] According to an exemplary embodiment of the inventive concept, when the non-volatile memory device 10 performs a random read operation, the control logic unit 140 can sequentially receive the first address ADD1 to the sixth address ADD6. When two received addresses ADDR indicate the same plane PLN, the control logic unit 140 performs serial queuing, and when two received addresses ADDR indicate different planes PLN, the control logic unit 140 performs parallel queuing. Serial queuing represents an operation of sequentially reading the data indicated by the address ADDR, and parallel queuing represents an operation of substantially simultaneously reading the data indicated by the address ADDR. Since data is read substantially simultaneously in parallel queuing, parallel queuing can be represented as a merging of addresses of different memory planes.

[0185] Referring to Figure 19(a), the control logic unit 140 may sequentially receive a first address ADD1 and a second address ADD2 both indicating the first plane PLN1. In this case, as Figure 19 (b) shows, the control logic unit 140 may serially queue the first address ADD1 and the second address ADD2. After the control logic unit 140 receives the second address ADD2 indicating the first plane PLN1, the control logic unit 140 receives a third address ADD3 indicating the second plane PLN2. In this case, as Figure 19 (b) shows, the control logic unit 140 may parallel queue the second address ADD2 and the third address ADD3 because the second address ADD2 and the third address ADD3 indicate different planes PLN.

[0186] According to an exemplary embodiment of the inventive concept, the control logic unit 140 may control at least one page buffer circuit 110 to sense data stored in the plane PLN based on the queued addresses. For example, when the control logic unit 140 receives the second address ADD2 and the third address ADD3 respectively indicating different planes PLN, the control logic unit 140 may control the first page buffer circuit 110a to sense the data stored in the first plane PLN1 indicated by the second address ADD2, and may control the second page buffer circuit 110b to sense the data stored in the second plane PLN2 indicated by the third address ADD3.

[0187] Specifically, based on the second address ADD2 among the queued addresses, the control logic unit 140 may send a sense latch control signal LTCH_S such that a plurality of sense latches included in the first page buffer circuit 110a may sense each piece of data stored in the page PAG14. Based on the third address ADD3 among the queued addresses, the control logic unit 140 may send a sense latch control signal LTCH_S such that a plurality of sense latches included in the second page buffer circuit 110b may sense each piece of data stored in the page PAG22.

[0188] Therefore, the non-volatile memory device 10 performing a random read operation may reduce the total number of sensing operations. For example, as Figure 19 (a) shows, when the control logic unit 140 controls the page buffer circuit 110 to sequentially perform sensing operations without serially or parallel queuing the received addresses, the page buffer circuit 110 may require a total time period of 6*tSE. In this case, tSE refers to the time period taken for sensing.

[0189] On the other hand, as Figure 19In (b) above, when the control logic unit 140 queues the received address, the control logic unit 140 may control the first page buffer circuit 110a and the second page buffer circuit 110a included in the page buffer circuit 110 to perform sensing operations in parallel. Accordingly, the page buffer circuit 110 may require a total time period of 4*tSE, and the total sensing time may be reduced according to parallel queuing.

[0190] Figure 20 is a flowchart of an operation of a page buffer circuit according to an exemplary embodiment of the inventive concept.

[0191] In operation S210, a plurality of first sense latches SL1 and a plurality of second sense latches SL2 may sense first data and second data from a plurality of bit lines, respectively.

[0192] For example, each of the first data and the second data may include data stored in a first page (e.g., Figure 11 PAG1 of Figure 16 or Figure 16 PAG10 of

[0193] ), the first data may include data stored in some memory cells (e.g., Figure 16 MCs1 of Figure 16 PAG10 of Figure 16 ), and the second data may include the remaining data among the data stored in the first page.

[0194] While sensing the first data and the second data, a plurality of third sense latches and a plurality of fourth sense latches sense third data and fourth data from a plurality of bit lines, respectively. The first data and the second data may include data stored in a first page (e.g., Figure 16 PAG10 of Figure 16 ), the third data and the fourth data may include data stored in a second page (e.g., Figure 16 PAG22 of

[0194] ), and the first page and the second page may be included in different planes (e.g., Figure 16 PLNa and PLNb of

[0194] ).

[0195] In operation S220, the first data may be dumped from the plurality of first sense latches SL1 to the plurality of first data latches DL1, and the second data may be dumped from the plurality of second sense latches SL2 to the plurality of second data latches DL2.

[0196] In operation S230, the plurality of first data latches DL1 may dump the first data to the plurality of first cache latches CL1.

[0197] Figure 21 It is a flowchart of the operation of a page buffer circuit according to an exemplary embodiment of the inventive concept.

[0198] As described above with reference to Figure 20 In operation S240, while the first data is being dumped to the plurality of first cache latches CL1, the plurality of second data latches DL2 may maintain the second data without dumping the second data. As described above with reference to Figure 20 Operation S240 has been described, and thus its description will be omitted here.

[0199] In operation S250, the plurality of first cache latches CL1 may output the first data.

[0200] In operation S260, while the first data is being output by the plurality of first cache latches CL1, the plurality of second data latches DL2 may dump the second data to the plurality of second cache latches CL2.

[0201] In this case, the time period taken for the plurality of first cache latches CL1 to output the first data may be longer than the time period taken for the plurality of second data latches DL2 to dump the second data to the plurality of second cache latches CL2. Since the time period taken to output data is longer than the time period taken to dump data in the same time region or period, as described above with reference to Figure 11 the time period tDP3 taken to perform the dump may be hidden by the time period tDO3 taken to perform the output.

[0202] The second data may be dumped while sensing third data stored in a second page from a plurality of bit lines, and the first page and the second page may be consecutive pages. In other words, the page buffer circuit may perform a sequential read operation. For example, referring to Figure 11 while sensing the data stored in the second page PAG2, the second data latch DL2 may dump (DP3) the sensed data to the second cache latch CL2 during the time period tDP3. Performing sensing and dumping substantially simultaneously may increase the efficiency of the read operation.

[0203] Figure 22 It is a flowchart of the operation of a page buffer circuit according to an exemplary embodiment of the inventive concept.

[0204] As described above with reference to Figure 20 In operation S240, while the first data is being dumped to the plurality of first cache latches CL1, the plurality of second data latches DL2 may maintain the second data without dumping the second data. As described above with reference to Figure 20 Operation S240 has been described, and thus its description will be omitted here.

[0205] In operation S270, memory cells storing data to be read among the memory cells included in the first page (e.g., Figure 16 page PAG10) can be identified based on the received address ADDR. (e.g., Figure 16 memory cells MCs1).

[0206] In operation S280, while maintaining the second data, a plurality of first cache latches CL1 can output the first data to the data I / O circuit 150 and may not output the second data to the data I / O circuit 150.

[0207] For example, referring to Figure 16 and Figure 17 , the first page buffer circuit PBa and the second page buffer circuit PBb can sense data of pages included in different planes. The first page buffer circuit PBa can include a first sense latch SL1 and a second sense latch SL2, and the second page buffer circuit PBb can include a third sense latch and a fourth sense latch. The functions of the first sense latch SL1 and the second sense latch SL2 are respectively similar to the functions of the third sense latch and the fourth sense latch. While the first sense latch SL1 senses the first data and the second sense latch SL2 senses the second data, the third sense latch can sense the third data and the fourth sense latch can sense the fourth data. As described above, the first data and the second data can include data stored in the memory cells of the first page (e.g., Figure 16 PAG10), the third data and the fourth data can include data stored in the memory cells of the second page (e.g., Figure 16 PAG22), and the first page and the second page can be included in different planes (e.g., Figure 16 PLNa and PLNb).

[0208] When the control logic unit 140 performs address queuing, the operations described above with reference to Figure 22 can be performed. Referring to Figure 19 , the control logic unit 140 can perform parallel queuing such that each piece of data stored in different planes (e.g., Figure 19 PLN1 and PLN2) is sensed in the same time region, and can perform serial queuing such that the same plane (e.g., Figure 19 PLN1) is sensed in different time regions. Therefore, the non-volatile memory device 10 basically simultaneously performs sensing operations on different planes PLN, thus improving the performance of the read operation.

[0209] Figure 23 is a block diagram for explaining a solid state drive (SSD) system according to an exemplary embodiment of the inventive concept.

[0210] Referring to Figure 23 , the SSD system 2000 may include a host 2100 and an SSD 2200. The SSD 2200 may send or receive a signal SGL to / from the host 2100 through a signal connector, and may receive power PWR from the host 2100 through a power connector. The SSD 2200 may include an SSD controller 2210, an auxiliary power supply 2220, and a plurality of memory devices 2230, 2240, and 2250. The plurality of memory devices 2230, 2240, and 2250 may be vertical NAND flash memory devices. At least one of the plurality of memory devices 2230, 2240, and 2250 may be implemented to perform a read operation including a sensing operation, a dump operation, etc. described above with reference to Figures 1 to 22 . At least one of the plurality of memory devices 2230, 2240, and 2250 may be implemented using the non-volatile memory device 10 described above with reference to Figures 1 to 22 , and may include a page buffer circuit 110. The functions and operations of the control logic unit 140 described above with reference to Figures 1 to 22 may be similarly executed by at least one of the host 2100 and the SSD controller 2210.

[0211] According to an exemplary embodiment of the inventive concept described above with reference to Figures 1 to 22 , data may be read from a cache latch included in the page buffer circuit 110 via a data I / O circuit 150, but data may also be read from the cache latch included in the page buffer circuit 110 and may be sent to a memory controller without passing through the data I / O circuit 150. In other words, data may be read from the cache latch included in the page buffer circuit 110.

[0212] According to an exemplary embodiment of the inventive concept, a dump operation performed while data sensed from a page buffer is output to a data I / O circuit is split and executed in parallel with a data output operation, and thus, a time period for dumping may be hidden by a data output time period.

[0213] According to an exemplary embodiment of the inventive concept, when a random read operation is performed, a dump time period may be reduced by dumping only a part of data sensed according to an address signal. In addition, a sensing time period may be reduced by merging memory planes to be sensed.

[0214] Therefore, according to an exemplary embodiment of the inventive concept, read performance may be increased by reducing a time period taken for a read operation.

[0215] Although the inventive concept has been shown and described with reference to exemplary embodiments thereof, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the inventive concept as set forth by the appended claims.

Claims

1. A non-volatile memory device, comprising: A memory cell array including a plurality of memory cells; A page buffer circuit including a plurality of first page buffers and a plurality of second page buffers, each of the plurality of first page buffers and the plurality of second page buffers including a sense latch, a data latch, and a cache latch, wherein the sense latch is configured to sense data stored in the memory cell array and dump the sensed data to the data latch, the data latch is configured to dump the data dumped by the sense latch to the cache latch, and the cache latch is configured to send the data dumped by the data latch to a data input / output circuit; and A control logic circuit configured to control the page buffer circuit such that while a cache latch included in at least one of the plurality of first page buffers performs a data sending operation, a data latch included in at least one of the plurality of second page buffers performs a data dumping operation, Wherein the plurality of first page buffers are controlled such that a data latch included in at least one of the plurality of first page buffers dumps the data dumped by a sense latch included in at least one of the plurality of first page buffers to a cache latch included in at least one of the plurality of first page buffers, and Wherein the plurality of second page buffers are controlled such that a data latch included in at least one of the plurality of second page buffers dumps the data dumped by a sense latch included in at least one of the plurality of second page buffers to a cache latch included in at least one of the plurality of second page buffers.

2. The non-volatile memory device according to claim 1, wherein, The control logic circuit is further configured to: Control the plurality of first page buffers such that while a data latch included in at least one of the plurality of second page buffers dumps data, a cache latch included in at least one of the plurality of first page buffers outputs data.

3. The non-volatile memory device according to claim 2, wherein The memory cell array includes pages, each page including the plurality of memory cells connected to the same word line, A cache latch included in at least one of the plurality of first page buffers outputs data based on a part of the data stored in the page, and A cache latch included in at least one of the plurality of second page buffers outputs data based on the remaining part of the data stored in the page.

4. The non-volatile memory device according to claim 3, wherein, The number of data bits output by the plurality of first page buffers is equal to the number of data bits output by the plurality of second page buffers.

5. The non-volatile memory device according to claim 2, wherein, The control logic circuit is further configured to control the page buffer circuit such that while a data latch included in at least one of the plurality of first page buffers dumps data, a data latch included in at least one of the plurality of second page buffers delays dumping.

6. The non-volatile memory device according to claim 1, wherein, The time period it takes for the cache latch included in at least one of the plurality of first page buffers to send data to the data input / output circuit is longer than the time period it takes for the data latch included in at least one of the plurality of second page buffers to dump data.

7. The non-volatile memory device according to claim 1, further comprising: A first current path to which the data latch included in at least one of the plurality of first page buffers and the sense latch included in at least one of the plurality of first page buffers are electrically connected; And A second current path to which the data latch included in at least one of the plurality of first page buffers and the cache latch included in at least one of the plurality of first page buffers are electrically connected, wherein the distance of the first current path is shorter than the distance of the second current path.

8. A non-volatile memory device configured to perform a random read operation, the non-volatile memory device comprising: A memory cell array including pages, the pages including memory cells connected to the same word line; A page buffer circuit including a first page buffer and a second page buffer, the first page buffer and the second page buffer each including a sense latch, a data latch, and a cache latch, wherein the sense latch is configured to sense data from the memory cell array and dump the sensed data, the data latch is configured to selectively dump the data dumped by the sense latch, and the cache latch is configured to send the data dumped by the data latch to a data input / output circuit; And Control logic circuitry configured to: In response to receiving a command and an address indicating the random read operation, control the data latch of the first page buffer to dump first data to the cache latch of the first page buffer and control the data latch of the second page buffer not to dump second data to the cache latch of the second page buffer, Identify, based on the address, a memory cell storing data to be read to perform the random read operation among the memory cells included in the page, and Determine the data stored in the identified memory cell as the first data.

9. The non-volatile memory device according to claim 8, wherein, The first data is based on data stored in some of the memory cells included in the page, and the second data is based on data stored in the remaining memory cells included in the page.

10. The non-volatile memory device according to claim 8, further comprising a plane including a plurality of pages, Among them, The page buffer circuit is configured to sense data from the plane, and The control logic circuitry is further configured to control the first page buffer and the second page buffer such that the first page buffer senses data stored in a first plane and the second page buffer senses data stored in a second plane.

11. The non-volatile memory device according to claim 8, further comprising a plane including a plurality of pages, Among them, The control logic circuitry is further configured to: Receiving a first address and a second address, and controlling the first page buffer and the second page buffer such that if the first address and the second address indicate different planes, while the first page buffer senses data stored in a first plane, the second page buffer senses data stored in a second plane.

12. An operating method of a page buffer circuit for outputting data sensed from a plurality of bit lines to a data input / output circuit, the operating method comprising: sensing first data and second data from the plurality of bit lines using a plurality of first sense latches and a plurality of second sense latches respectively; dumping the first data from the plurality of first sense latches to a plurality of first data latches, and dumping the second data from the plurality of second sense latches to a plurality of second data latches; dumping the first data from the plurality of first data latches to a plurality of first cache latches; maintaining the second data without dumping the second data during at least a part of a time period when the first data is dumped to the plurality of first cache latches, wherein the maintaining of the second data is performed by the plurality of second data latches; outputting the first data from the plurality of first cache latches; and while outputting the first data from the plurality of first cache latches, dumping the second data from the plurality of second data latches to a plurality of second cache latches.

13. The operating method according to claim 12, wherein, A time period taken by the plurality of second data latches to dump the second data to the plurality of second cache latches is shorter than a time period taken by the plurality of first cache latches to output the first data.

14. The operating method according to claim 12, wherein Each of the first data and the second data includes data stored in memory cells of a first page, wherein the first data includes a part of data stored in the first page, and the second data includes a remaining part of the data stored in the first page, the dumping of the second data includes dumping the second data while sensing third data stored in a second page from the plurality of bit lines, and the first page and the second page are consecutive pages.

15. The operating method according to claim 12, further comprising outputting the first data from the plurality of first cache latches to the data input / output circuit while maintaining the second data, and not outputting the second data to the data input / output circuit.

16. The operating method according to claim 15, further comprising identifying data to be read by a random read operation as the first data based on the received address.

17. The operating method according to claim 12, further comprising: outputting the second data from the plurality of second cache latches; and when completely outputting the second data from the plurality of second cache latches, dumping nth data from a plurality of nth data latches to a plurality of nth cache latches, wherein n is an integer greater than 2.

18. The operating method according to claim 17, wherein, The time period taken to transfer data from the multiple first data latches to the multiple first cache latches, the time period taken to transfer data from the multiple second data latches to the multiple second cache latches, the time period taken to output the first data from the multiple first cache latches, and the time period taken to output the second data from the multiple second cache latches are the same as each other.

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