A calibration circuit

Abstract

The present invention discloses a calibration circuit, comprising: a first voltage set generation module, used to generate a first voltage set according to a first reference voltage; the first voltage set includes n voltages; the comparison module, used to compare the n voltages in the first voltage set with the voltage to be calibrated respectively, and output n comparison results to the decoding module; the decoding module, used to decode the n comparison results into corresponding code words; the second voltage set generation module, used to generate a second voltage set according to a second reference voltage; the second voltage set includes m voltages; the switch module, used to output the voltage in the second voltage set corresponding to the code word according to the code word. The calibration circuit disclosed in the present invention can realize calibration of the voltage to be calibrated.

Description

Technical Field

[0001] The invention relates to the field of circuits, and in particular to a calibration circuit in the field of circuits. Background Art

[0002] At present, the signal frequency band in the communication field is relatively wide, the number of spectrums is large, and the interaction of signals of various standards seriously affects the normal use of various communication equipment. The interaction between wireless communication signals usually affects the receiving sensitivity of the chip, which can seriously cause chip blocking, resulting in the chip not being able to work properly, and even seriously burn the chip. In order to reduce this impact, the limiting circuit is widely used in various chip products. As the core component of the limiting circuit, the performance and connection method of the diode have a huge impact on the quality of the limiting circuit. In recent years, the development of chips has been getting better and better, and the requirements for various communication chips to resist interference have become higher and higher. How to implement a good amplitude limiting circuit in the chip has become a new topic.

[0003] The traditional diode limiting circuit structure is as follows Figure 1 As shown, Vb is the DC bias applied to the gate of transistor MN1, Vin is the input AC signal, Vdc is the bias voltage applied to the cathode of the diode, and the number of diodes in series needs to be determined based on the relationship between Vb and Vdc to ensure that the transistor works normally under normal input amplitude of Vin.

[0004] When the input signal amplitude is small, it is required to satisfy equation 1:

[0005] Vg-Vdc<0.7V Formula 1

[0006] At this time, the input signal is normally added to the gate of MN1, and MN1 amplifies the input signal; when Vg-Vdc>0.7V, the peak of the positive end of the input AC signal Vin will be cut off, thereby achieving the effect of limiting.

[0007] In order to ensure chip reliability and yield rate during chip production, in the design of the limiting circuit, the designer needs to ensure that the circuit can work normally under each process corner. However, the Vth voltage of the MOS tube under each process corner varies greatly. Usually, the threshold voltage is larger under the SS process corner, and smaller under the FF process corner. If the limiting circuit is not processed, the amplitude limit of the input signal under each process corner will vary greatly, resulting in a large difference in the energy of the output signal, which cannot meet the consistency requirements.

[0008] Assuming that the gain of the circuit through MN1 is 5dB, when the input signal Vin is 0dbm, that is, the peak-to-peak value of Vin is about 0.6V, the output requirement is met. When the input signal increases further, if there is no limiting circuit, the circuit may be saturated, deteriorating the linearity of the circuit. At this time, take Vb as 1V, Vdc as 0.6V, then Vb-Vdc is 0.4V, such as Figure 1 In the circuit shown, Vg=Vb+Vin. At this time, the amplitude of Vg is 0.7V-1.3V, and Vg-Vdc is just below the critical value of 0.7V. The normal operation of the chip is not affected. If the signal continues to increase, the part of the swing increase satisfies Vg-Vdc greater than 0.7V. At this time, the diode is turned on and will limit the part that exceeds Vg-Vdc greater than 0.7V. The problem faced by this circuit in operation is that when the process angle changes, Vb-Vdc also changes, and it cannot be maintained when the input signal is Vin is 0dbm, the amplitude of Vg is 0.7V-1.3V, and Vg-Vdc is just below the critical value of 0.7V. Then, when the limiter circuit can work normally under different process angles, the corresponding input signal size will be different, thereby affecting the energy size of the output signal.

[0009] The existing technology adopts Figure 2 and Figure 3 To solve the above problems, Figure 2 The figure shows a commonly used Vb voltage generation circuit. This circuit structure has the following characteristics: currents I1 and I2 are mirror current source relationships to ensure that the current flowing through transistor MN1 is constant and the circuit works stably under different process angles; transistors MN1 and MN2 have appropriate reference sizes, usually W, L, and finger are the same, and M can be obtained as needed to ensure that the two transistors have the same threshold voltage (Vth), so that they change with the process angle. Figure 1 The limit requirement, Figure 1 The bias voltage Vb=V1=V2.

[0010] Figure 3 The figure shows a commonly used Vdc voltage generating circuit. This circuit structure has the following characteristics: currents I3 and I2 are of the same source, that is, they are derived from the same current source to ensure that the two currents change the same way under different process angles and the circuit works stably; transistors MN3 and MN2 have appropriate reference sizes, usually W, L, and finger are the same, and M can be obtained as needed to ensure that the two tubes have the same threshold voltage (Vth) and thus change the same way with the process angle. By appropriately selecting the size of MN3 and the size of current I3, a suitable bias voltage Vdc is obtained. Summary of the invention

[0011] The technical problem to be solved by the present invention is to provide a calibration circuit capable of calibrating a voltage to be calibrated.

[0012] In order to solve the above problem, the present invention further provides a calibration circuit, comprising:

[0013] A first voltage set generating module, a comparison module, a decoding module, a second voltage set generating module and a switch module;

[0014] The first voltage set generating module is used to generate a first voltage set according to a first reference voltage; the first voltage set includes n voltages, the n voltages are arranged in ascending order, the n voltages arranged in ascending order are in an arithmetic progression, and the first voltage set in the first voltage set The voltage is the first standard voltage, and n is a natural number;

[0015] The comparison module is used to compare the n voltages in the first voltage set with the voltage to be calibrated respectively, and output n comparison results to the decoding module;

[0016] The decoding module is used to decode the n comparison results into corresponding code words;

[0017] The second voltage set generating module is used to generate a second voltage set according to a second reference voltage; the second voltage set includes m voltages, the m voltages are arranged in ascending order, the m voltages arranged in ascending order are in an arithmetic progression, and the first voltage in the second voltage set The difference between the voltage and the first standard voltage is a preset value, and m is a natural number;

[0018] The switch module is used to output a voltage corresponding to the code word in the second voltage set according to the code word.

[0019] In an exemplary embodiment, the above circuit also has the following characteristics:

[0020] The first voltage set generating module comprises: a first resistor, a second resistor and n-1 third resistors;

[0021] One end of the first resistor serves as an input end of the first voltage set generating module, and is used to input the first reference voltage;

[0022] One end of the second resistor is grounded;

[0023] The n-1 third resistors are connected in series, the other end of the first resistor is connected to one end of the n-1 third resistors connected in series, and the other end of the second resistor is connected to the other end of the n-1 third resistors connected in series;

[0024] The end of the second resistor that is not connected to the ground serves as the first output end of the first voltage set generating module, the end of the third resistor connected to the second resistor that is not connected to the second resistor serves as the second output end of the first voltage set generating module, the common end between the two third resistors connected in series serves as the third to n-1th output ends of the first voltage set generating module, and the end of the first resistor that is not used for inputting the first reference voltage serves as the nth output end of the first voltage set generating module.

[0025] In an exemplary embodiment, the above circuit also has the following characteristics: the comparison circuit includes n comparators; each comparator corresponds one-to-one to the output terminal of the first voltage set generation module;

[0026] Each comparator is used for comparing the voltage outputted from the output terminal of the first voltage set generating module corresponding to the comparator with the voltage to be calibrated, and outputting the comparison result to the decoding module.

[0027] In an exemplary embodiment, the above circuit also has the following characteristics:

[0028] The decoding module includes a decoder;

[0029] The decoder comprises n decoder input terminals and m decoder output terminals, the output terminal of each comparator is connected to each decoder input terminal; each decoder output terminal serves as the output terminal of the decoding module; the decoder is used to decode the outputs of the n comparators into code words.

[0030] In an exemplary embodiment, the above circuit also has the following characteristics:

[0031] The second voltage set generating module comprises: a fourth resistor, a fifth resistor and m-1 sixth resistors;

[0032] One end of the fourth resistor serves as an input end of the second voltage set generating module, and is used to input the second reference voltage;

[0033] One end of the fifth resistor is grounded;

[0034] The m-1 sixth resistors are connected in series in sequence; one end of the m-1 sixth resistors connected in series is connected to the other end of the fourth resistor; the other end of the m-1 sixth resistors connected in series is connected to the other end of the fifth resistor;

[0035] The end of the fifth resistor that is not connected to the ground serves as the first output end of the second voltage set generating module, the end of the sixth resistor connected to the fifth resistor that is not connected to the fifth resistor serves as the second output end of the second voltage set generating module, the common end of the two sixth resistors connected in series serves as the third to m-1th output ends of the second voltage set generating module, and the end of the fourth resistor that is not used for inputting the second reference voltage serves as the mth output end of the second voltage set generating module.

[0036] In an exemplary embodiment, the above circuit also has the following characteristics:

[0037] The switch module comprises m switch devices; the m switch devices correspond one-to-one to the m output terminals of the second voltage set generating module, and each switch device is connected to the output terminal of the corresponding second voltage set generating module; the closing of each switch device is controlled by the codeword.

[0038] In an exemplary embodiment, the above circuit also has the following characteristics:

[0039] The calibration circuit also includes m relays;

[0040] The m switch devices are m nodes of m relays;

[0041] The m relays are connected to the output ends of the decoding modules in a one-to-one correspondence.

[0042] In an exemplary embodiment, the above circuit also has the following characteristics:

[0043] The minimum voltage in the first voltage set is 90% of the first reference voltage, and the maximum voltage in the first voltage set is 110% of the first reference voltage;

[0044] The minimum voltage in the second voltage set is 90% of the second reference voltage, and the maximum voltage in the second voltage set is 110% of the second reference voltage.

[0045] In an exemplary embodiment, the above circuit also has the following characteristics:

[0046] Said n=m.

[0047] In summary, the circuit provided by the embodiment of the present invention can generate a voltage that changes equally with the process angle, ensuring that Vb-Vdc is a basically constant value, solving the problem of the limiting circuit caused by the large change in threshold voltage at different process angles, and maintaining the stability of the input signal at different process angles, thereby ensuring the power stability of the circuit output. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 This is a traditional limiting circuit diagram.

[0049] Figure 2 It is the Vb voltage generating circuit.

[0050] Figure 3 This is a Vdc voltage generating circuit.

[0051] Figure 4 FIG. 1 is a schematic diagram of a calibration circuit according to a first embodiment of the present invention.

[0052] Figure 5 FIG. 4 is a schematic diagram of a calibration circuit according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail with reference to the accompanying drawings. It should be noted that the embodiments and features in the embodiments of the present application can be combined with each other arbitrarily without conflict.

[0054] Embodiment 1

[0055] Figure 4 Schematic diagram of a calibration circuit according to an embodiment of the present invention. Figure 4 As shown, the calibration circuit of this embodiment includes: a first voltage set generation module, a comparison module, a decoding module, a second voltage set generation module and a switch module;

[0056] The first voltage set generating module is used to generate a first voltage set according to a first reference voltage; the first voltage set includes n voltages, the n voltages are arranged in ascending order, the n voltages arranged in ascending order are in an arithmetic progression, and the first voltage set in the first voltage set The voltage is the first standard voltage, and n is a natural number;

[0057] The comparison module is used to compare the n voltages in the first voltage set with the voltage to be calibrated respectively, and output n comparison results;

[0058] The decoding module is used to decode the n comparison results into corresponding code words;

[0059] The second voltage set generating module is used to generate a second voltage set according to a second reference voltage; the second voltage set includes m voltages, the m voltages are arranged in ascending order, the m voltages arranged in ascending order are in an arithmetic progression, and the first voltage in the second voltage set The difference between the voltage and the first standard voltage is a preset value, and m is a natural number;

[0060] The switch module is used to output a voltage corresponding to the code word in the second voltage set according to the code word.

[0061] here, right Round up. Express The first standard voltage may be a Vb value under a typical process angle. The preset value may be 0.4V.

[0062] In an exemplary embodiment, the first voltage set generating module includes: a first resistor, a second resistor and n-1 third resistors;

[0063] One end of the first resistor serves as an input end of the first voltage set generating module, and is used to input the first reference voltage;

[0064] One end of the second resistor is grounded;

[0065] The n-1 third resistors are connected in series, the other end of the first resistor is connected to one end of the n-1 third resistors connected in series, and the other end of the second resistor is connected to the other end of the n-1 third resistors connected in series;

[0066] The end of the second resistor that is not connected to the ground serves as the first output end of the first voltage set generating module, the end of the third resistor connected to the second resistor that is not connected to the second resistor serves as the second output end of the first voltage set generating module, the common end between the two third resistors connected in series serves as the third to n-1th output ends of the first voltage set generating module, and the end of the first resistor that is not used for inputting the first reference voltage serves as the nth output end of the first voltage set generating module.

[0067] In an exemplary embodiment, the comparison circuit includes n comparators; each comparator corresponds one-to-one to an output terminal of the first voltage set generation module;

[0068] Each comparator is used for comparing the voltage outputted from the output terminal of the first voltage set generating module corresponding to the comparator with the voltage to be calibrated, and outputting the comparison result to the decoding module.

[0069] In an exemplary embodiment, the decoding module includes a decoder;

[0070] The decoder comprises n decoder input terminals and m decoder output terminals, the output terminal of each comparator is connected to each decoder input terminal; each decoder output terminal serves as the output terminal of the decoding module; the decoder is used to decode the outputs of the n comparators into code words.

[0071] In an exemplary embodiment, the second voltage set generating module includes: a fourth resistor, a fifth resistor and m-1 sixth resistors;

[0072] One end of the fourth resistor serves as an input end of the second voltage set generating module, and is used to input the second reference voltage;

[0073] One end of the fifth resistor is grounded;

[0074] The m-1 sixth resistors are connected in series in sequence; one end of the m-1 sixth resistors connected in series is connected to the other end of the fourth resistor; the other end of the m-1 sixth resistors connected in series is connected to the other end of the fifth resistor;

[0075] The end of the fifth resistor that is not connected to the ground serves as the first output end of the second voltage set generating module, the end of the sixth resistor connected to the fifth resistor that is not connected to the fifth resistor serves as the second output end of the second voltage set generating module, the common end of the two sixth resistors connected in series serves as the third to m-1th output ends of the second voltage set generating module, and the end of the fourth resistor that is not used for inputting the second reference voltage serves as the mth output end of the second voltage set generating module.

[0076] In an exemplary embodiment, the switch module includes m switch devices; the m switch devices correspond one-to-one to the m output terminals of the second voltage set generating module, and each switch device is connected to the output terminal of the corresponding second voltage set generating module; the closure of each switch device is controlled by the codeword.

[0077] In an exemplary embodiment, the calibration circuit further includes m relays;

[0078] The m switch devices are m nodes of m relays;

[0079] The m relays are connected to the output ends of the decoding modules in a one-to-one correspondence.

[0080] In an exemplary embodiment, the minimum voltage in the first voltage set is 90% of the first reference voltage, and the maximum voltage in the first voltage set is 110% of the first reference voltage;

[0081] The minimum voltage in the second voltage set is 90% of the second reference voltage, and the maximum voltage in the second voltage set is 110% of the second reference voltage.

[0082] In an exemplary embodiment, n=m.

[0083] Embodiment 2

[0084] The design concept of the second embodiment is as follows:

[0085] Multiple comparators are used to compare the Vb voltage with Vref to obtain the output code of the comparator. The code interval will reflect the range of Vb deviating from the typical process angle. By reasonably obtaining the distribution of Vref, high accuracy can be obtained. The process of Vref is as follows: Assuming that the deviation range introduced by the process angle fluctuation is Vb*(1-20%) to Vb*(1+20%), by selecting Vref0 as Vb*(1-20%), Vrefn as Vb*(1+20%), and the middle Vref1 to Vrefn-1 are reasonable voltage values ​​in the interval. The specific working principle is as follows: Assuming that Vb is a typical value of 1V, the process fluctuation is -100mV to +100mV, that is, Vref0 is 0.9V, Vrefn is 1.1V, at this time, if Vdc changes with Vb differently, then Vb-Vdc will be different values ​​under different process angles, and the limiter circuit will limit different amplitudes, seriously affecting the consistency of the output. At this time, assuming that 9 comparators are used for comparison, when the process angle fluctuation range is 200mV, the accuracy of the comparator is 200 / 8=25mV, and the interval is 25mV. The relationship between the comparator output and the input voltage is shown in Table 1. It should be noted that the input voltage range here is 0.9V to 1.1V.

[0086] Table 1

[0087] Input voltage(V) Comparator Output Codeword Closed switch device Output voltage V(Vdc) 0.9≤Vb<0.925 000000001 000000001 S0 0.5 0.925≤Vb<0.95 000000011 000000010 S1 0.525 0.95≤Vb<0.975 000000111 000000100 S2 0.55 0.975≤Vb<1 000001111 000001000 S3 0.575 1≤Vb<1.025 000011111 000010000 S4 0.6 1.025≤Vb<1.05 000111111 000100000 S5 0.625 1.05≤Vb<1.075 001111111 001000000 S6 0.65 1.075≤Vb<1.1 011111111 010000000 S7 0.675 Vb=1.1 111111111 100000000 S8 0.7

[0088] like Figure 5 As shown, the calibration circuit consists of 3 parts:

[0089] Part 1: By choosing a reasonable value for R, the voltage interval between each Vref is 25mV, while satisfying The value of is the Vb0 value under the typical process angle. In this way, a string of digital characters will be obtained through the output of the comparator. The digital characters can know the range of Vb deviating from Vb0 when the process angle deviates. That is, taking the 9-bit comparator output as a column, when the process angle changes, if Vb is 0.925V, the comparator output is 000000011;

[0090] The second part is Figure 5 The Vdc generating circuit on the right side is similar to the first part, except that the middle value The value of is the required Vdc value under the typical process angle, that is, It is 0.4V. At the same time, the interval between each Vdc is also 25mV, and the supply voltage of Vref and Vdc is from the same source, which is generally a stable voltage from the same source;

[0091] The third part is the decoding module and the switch module, which encode according to the various comparator outputs of the first part. When the comparator outputs a certain code, the decoding module can output the corresponding codeword, which will close the corresponding S0-S(n-1) switch device, thereby outputting the required Vdc value. When the output of the comparator is 000000001, the corresponding codeword is 000000001, and Vdc0 is output at this time.

[0092] Taking the 9-bit comparator output as a column, if the comparator outputs 000000001, the corresponding output is bit0 is 1, bit1-bit8 are 0. At this time, if Vb is 0.9V, S0 is closed, S1-S8 are all turned off, Vdc directly outputs 0.5V, and Vb-Vdc is 0.4V.

[0093] If the comparator outputs 000000011, the corresponding output is bit0-bit1 is 1, and the others are 0. At this time, if Vb is 0.925V, S1 is closed, Vdc outputs 0.525V, and Vb-Vdc is 0.4V. It should be noted that switches S0-S8 can be relay nodes, and the codewords control the relays corresponding to switches S0-S8. When the relay is powered, the relay node is closed accordingly, thereby outputting the corresponding voltage. The specific implementation form is not limited here.

[0094] Therefore, when the voltage across the limiting diode fluctuates with the process angle, the voltage difference still remains at 0.4V, thereby achieving a good limiting characteristic that does not change with the process angle.

[0095] Those skilled in the art will appreciate that all or part of the steps in the above method can be completed by instructing related hardware through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a disk or an optical disk. Optionally, all or part of the steps in the above embodiment can also be implemented using one or more integrated circuits. Accordingly, each module / unit in the above embodiment can be implemented in the form of hardware or in the form of a software functional module. The present invention is not limited to any particular form of combination of hardware and software.

[0096] The above are only preferred embodiments of the present invention. Of course, the present invention may also have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A calibration circuit, characterized in that: include: A first voltage set generating module, a comparison module, a decoding module, a second voltage set generating module and a switch module; The first voltage set generating module is used to generate a first voltage set according to a first reference voltage; the first voltage set includes n voltages, the n voltages are arranged in ascending order, the n voltages arranged in ascending order are in an arithmetic progression, and the first voltage set in the first voltage set The voltage is the first standard voltage, and n is a natural number; The comparison module is used to compare the n voltages in the first voltage set with the voltage to be calibrated respectively, and output n comparison results to the decoding module; The decoding module is used to decode the n comparison results into corresponding code words; The second voltage set generating module is used to generate a second voltage set according to a second reference voltage; the second voltage set includes m voltages, the m voltages are arranged in ascending order, the m voltages arranged in ascending order are in an arithmetic progression, and the first voltage in the second voltage set is The difference between the voltage and the first standard voltage is a preset value, and m is a natural number; The switch module is used to output a voltage corresponding to the code word in the second voltage set according to the code word; The minimum voltage in the first voltage set is 90% of the first reference voltage, and the maximum voltage in the first voltage set is 110% of the first reference voltage; The minimum voltage in the second voltage set is 90% of the second reference voltage, and the maximum voltage in the second voltage set is 110% of the second reference voltage; Said n=m.

2. The calibration circuit according to claim 1, characterized in that The first voltage set generating module comprises: a first resistor, a second resistor and n-1 third resistors; One end of the first resistor serves as an input end of the first voltage set generating module, and is used to input the first reference voltage; One end of the second resistor is grounded; The n-1 third resistors are connected in series, the other end of the first resistor is connected to one end of the n-1 third resistors connected in series, and the other end of the second resistor is connected to the other end of the n-1 third resistors connected in series; The end of the second resistor that is not connected to the ground serves as the first output end of the first voltage set generating module, the end of the third resistor connected to the second resistor that is not connected to the second resistor serves as the second output end of the first voltage set generating module, the common end between the two third resistors connected in series serves as the third to n-1th output ends of the first voltage set generating module, and the end of the first resistor that is not used for inputting the first reference voltage serves as the nth output end of the first voltage set generating module.

3. The calibration circuit according to claim 2, characterized in that The comparison module includes n comparators; each comparator corresponds one-to-one to an output terminal of the first voltage set generation module; Each comparator is used for comparing the voltage outputted from the output terminal of the first voltage set generating module corresponding to the comparator with the voltage to be calibrated, and outputting the comparison result to the decoding module.

4. The calibration circuit according to claim 3, wherein: The decoding module includes a decoder; The decoder comprises n decoder input terminals and m decoder output terminals, the output terminal of each comparator is connected to each decoder input terminal; each decoder output terminal serves as the output terminal of the decoding module; The decoder is used for decoding the outputs of the n comparators into code words.

5. The calibration circuit according to claim 1, wherein: The second voltage set generating module comprises: a fourth resistor, a fifth resistor and m-1 sixth resistors; One end of the fourth resistor serves as an input end of the second voltage set generating module, and is used to input the second reference voltage; One end of the fifth resistor is grounded; The m-1 sixth resistors are connected in series in sequence; one end of the m-1 sixth resistors connected in series is connected to the other end of the fourth resistor; the other end of the m-1 sixth resistors connected in series is connected to the other end of the fifth resistor; The end of the fifth resistor that is not connected to the ground serves as the first output end of the second voltage set generating module, the end of the sixth resistor connected to the fifth resistor that is not connected to the fifth resistor serves as the second output end of the second voltage set generating module, the common end of the two sixth resistors connected in series serves as the third to m-1th output ends of the second voltage set generating module, and the end of the fourth resistor that is not used for inputting the second reference voltage serves as the mth output end of the second voltage set generating module.

6. The calibration circuit according to claim 5, characterized in that: The switch module comprises m switch devices; the m switch devices correspond one-to-one to the m output terminals of the second voltage set generating module, and each switch device is connected to the output terminal of the corresponding second voltage set generating module; the closing of each switch device is controlled by the code word.

7. The calibration circuit according to claim 6, wherein: The calibration circuit also includes m relays; The m switch devices are m nodes of m relays; The m relays are connected to the output ends of the decoding modules in a one-to-one correspondence.

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