Apparatus comprising electronic circuitry for amplifying a signal

Abstract

The apparatus relates to providing pre-5G (fifth generation) or 5G communication systems to support higher data rates beyond 4th generation (4G) communication systems such as long term evolution (LTE). The disclosure relates to an apparatus including an electronic circuit for amplifying a signal. The apparatus includes a transceiver including an amplification circuit and at least one processor coupled to the transceiver. The amplification circuit includes a first path generating a first current corresponding to a voltage of an input signal, a second path generating a second current corresponding to the voltage of the input signal, a split unit controlling each of the first current and the second current, a current mirror generating a third current corresponding to the first current, and a folding unit generating an output signal based on the second current and the third current.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to an electronic circuit. More specifically, the present disclosure relates to an apparatus including an electronic circuit for amplifying a signal. BACKGROUND

[0002] To meet the demand for wireless data traffic soaring since the deployment of 4th generation (4G) communication systems, efforts have been made to develop an improved 5th generation (5G) or pre-5G communication system. Therefore, the 5G or pre-5G communication system is also called a 'Beyond 4G Network' or a 'Post long term evolution (LTE) System'.

[0003] The 5G communication system is considered to be implemented in a frequency band of 6 GHz or more, e.g., a 60 GHz band, so as to accomplish a higher data rate. To decrease the propagation loss of radio waves and increase the transmission distance, the beamforming, massive multiple-input multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam forming, and large scale antenna techniques are discussed in the 5G communication system.

[0004] In addition, in the 5G communication system, the development for system network improvement is under way based on advanced small cells, cloud radio access networks (RANs), ultra-dense networks, a device to device (D2D) communication, wireless backhaul, a mobile network, a cooperative communication, coordinated multi-points (CoMP), and reception-end interference cancellation.

[0005] In the 5G system, hybrid frequency shift keying (FSK) and quadrature amplitude modulation (QAM) (FQAM) and sliding window superposition coding (SWSC) as an advanced coding modulation (ACM), and filter bank multi carrier (FBMC), a non-orthogonal multiple access (NOMA), and a sparse code multiple access (SCMA) as an advanced access technology have been developed.

[0006] Generally, an amplifier uses feedback to reduce the gain variation range under process, voltage, and temperature (PVT) conditions. If a feedback coefficient is referred to as 'f' and an open loop gain is referred to as 'A', the overall gain of the amplifier is approximated to A / (1+fxA). Accordingly, as the open loop gain increases, the feedback gain is approximated to 1 / f, and thus accurate feedback can be obtained. However, in a wideband amplifier, increasing the gain generally causes an increase in bandwidth, and accordingly, a decrease in phase margin, thus decreasing stability. Therefore, in the design of a wideband amplifier, it is very difficult to secure stability while increasing the gain.

[0007] The above information is presented as background information only to assist with an understanding of the present disclosure. No determination has been made, and no assertion is made, as to whether any of the above might be applicable as prior art with regard to the present disclosure. SUMMARY

[0008] Aspects of the present disclosure will at least solve the above problems and / or disadvantages and provide at least the advantages described below. Accordingly, an aspect of the present disclosure provides an apparatus including an electronic circuit for efficiently amplifying a signal.

[0009] Another aspect of the present disclosure provides an apparatus including an amplification circuit having high gain and stability using a feed-forward path.

[0010] Another aspect of the present disclosure provides an apparatus including an amplification circuit having low sensitivity and high linearity with respect to process, voltage, and temperature (PVT).

[0011] Additional aspects will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description and / or can be learned by practice of the presented embodiments.

[0012] According to an aspect of the present disclosure, an apparatus including an electronic circuit is provided. The apparatus includes a transceiver including an amplification circuit, and at least one processor coupled to the transceiver. The amplification circuit can include a first path generating a first current corresponding to a voltage of an input signal, a second path generating a second current corresponding to the voltage of the input signal, a split unit controlling each of the first current and the second current, a current mirror generating a third current corresponding to the first current, and a folding unit generating an output signal based on the second current and the third current.

[0013] According to various embodiments, an amount of the second current is greater than an amount of the first current by a first ratio, and an amount of the third current is greater than the amount of the first current by a second ratio. The second path can include a transistor greater than a transistor included in the first path.

[0014] According to various embodiments, the input signal can be input to a gate of a transistor included in the first path and the second path.

[0015] According to various embodiments, the apparatus can further include a transistor connected to a transistor included in the first path in a cascade structure between the first path and the current mirror.

[0016] According to various embodiments, the separation unit can include a first variable transistor connected to the first path, and a second variable transistor connected to the second path. A gate of the first variable transistor and a gate of the second variable transistor can be connected to the same bias voltage. A drain of the first variable transistor can be connected to a source of a transistor included in the first path, a drain of the second variable transistor can be connected to a source of a transistor included in the second path, and a source of the first variable transistor and a source of the second variable transistor can be grounded.

[0017] According to various embodiments, the current mirror can include a first transistor having a gain identical to that of the first path, and a second transistor having a gain higher than that of the first path, the first transistor and the second transistor can share a gate voltage.

[0018] According to various embodiments, the folding unit includes a transistor configured to receive the second current and the third current through a source, and output the output signal through a drain. The folding unit can include a resistor connected to a body terminal of the transistor.

[0019] The apparatus according to various embodiments can secure a wide bandwidth and excellent linearity by separating a path for an amplification operation having a wide bandwidth and a path for an amplification operation having a higher gain.

[0020] Other aspects, advantages, and salient features of the disclosure will become apparent to those skilled in the art from the following detailed description, which, taken in conjunction with the annexed drawings, discloses various embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0021] The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0022] Figure 1 An apparatus including an amplification circuit according to embodiments of the present disclosure is illustrated;

[0023] Figure 2 A conceptual configuration of an amplification circuit according to embodiments of the present disclosure is illustrated;

[0024] Figure 3 A functional configuration of an amplification circuit according to embodiments of the present disclosure is illustrated;

[0025] Figure 4 A configuration of a main amplification unit of an amplification circuit according to embodiments of the present disclosure is illustrated;

[0026] Figure 5 An implementation example of a main amplification unit of an amplification circuit according to an embodiment of the disclosure is shown.

[0027] Figure 6 An implementation example of an output unit of an amplification circuit according to an embodiment of the disclosure is shown.

[0028] Figure 7 An implementation example of a common mode feedback unit of an amplification circuit according to an embodiment of the disclosure is shown.

[0029] Throughout the drawings, it should be noted that like reference numbers are used to depict the same or similar elements, features, and structures. DETAILED DESCRIPTION

[0030] The following description with the accompanying drawings is provided to assist in a comprehensive understanding of various embodiments of the disclosure as defined by the claims and their equivalents. It includes various specific details to assist in that understanding but these are to be regarded as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the various embodiments described herein can be made without departing from the scope and spirit of the disclosure. In addition, descriptions of well-known functions and constructions can be omitted for clarity and conciseness.

[0031] The terms and words used in the following description and claims are not limited to the bibliographical meanings, but are merely used to enable a clear and consistent understanding of the disclosure. Accordingly, it should be apparent to those skilled in the art that the following description of various embodiments of the disclosure is provided for illustration purpose only and not for the purpose of limiting the disclosure as defined by the appended claims and their equivalents.

[0032] It should be understood that the singular forms "a," "an," and "the" include plural referents unless the context clearly dictates otherwise. Thus, for example, reference to "a component surface" includes reference to one or more of such surfaces.

[0033] Hereinafter, the disclosure relates to an apparatus including an electronic circuit for amplifying a signal. Specifically, a circuit structure of an amplifier having higher gain and wide bandwidth characteristics will be described.

[0034] Terms related to signals, terms related to materials, terms related to structures, terms related to elements of a circuit, and the like used in the following description are used for convenience of explanation. Accordingly, the disclosure is not limited to the following terms, and other terms having the same technical meanings can be used.

[0035] Figure 1 An apparatus including an amplification circuit according to an embodiment of the disclosure is shown.

[0036] Referring to Figure 1 , the device includes a communication unit 110 (e.g., a transceiver including a transmission unit) and a controller 120 (e.g., at least one processor).

[0037] The communication unit 110 performs a function for transmitting or receiving a signal. For example, the communication unit 110 can perform conversion between a bit string and a baseband signal, conversion between an analog signal and a digital signal, conversion between a baseband signal and an intermediate frequency (IF) / radio frequency (RF) signal, etc. According to various embodiments, the communication unit 110 includes an amplification circuit 112 configured to amplify a transmission signal or a reception signal. The amplification circuit 112 can amplify at least one of a baseband signal, an intermediate frequency band signal, and an RF signal.

[0038] The controller 120 controls the overall operation of the device. The controller 120 can provide transmission data to the communication unit 110 and process reception data provided from the communication unit 110. In addition, the controller 120 can determine and control the state of elements (e.g., the amplification circuit 112) included in the communication unit 110. The controller 120 can generate and output a control signal for controlling the communication unit 110. To this end, the controller 120 can include at least one of a processor, a microprocessor, a microcontroller, a memory, and a control signal generation circuit.

[0039] Figure 2 A conceptual configuration of an amplification circuit according to an embodiment of the disclosure is illustrated.

[0040] Referring to Figure 2 , the amplification circuit 112 includes a first element 202 configured to provide a gain g mn1 and a second element 204 configured to provide a gain g mn3 In addition, the amplification circuit 112 includes a third element 206 configured to increase the gain by j times. According to an embodiment, the first element 202 can have a relatively high gain characteristic, and the second element 204 can have a characteristic of a relatively wide bandwidth.

[0041] Figure 3 A functional configuration of an amplification circuit according to an embodiment of the disclosure is illustrated. Figure 3 A configuration of the amplification circuit 112 is further illustrated.

[0042] Referring to Figure 3 , the amplification circuit 112 includes a main amplification unit 310, an output unit 320, and a common mode feedback unit 330.

[0043] The main amplification unit 310 amplifies a signal input through an input terminal IN p and IN nAn input input signal is amplified. The amplified signal is provided to an output unit 320. Here, the input signal can be a differential signal. According to various embodiments, the main amplification unit 310 can include a portion for improving a wide bandwidth characteristic and a portion for improving a higher gain characteristic.

[0044] The output unit 320 generates an output signal in response to the input signal amplified by the main amplification unit 310. The output unit 320 has a folded structure with respect to the main amplification unit 310 to secure headroom of the output circuit.

[0045] The common mode feedback unit 330 is a feedback circuit installed in a bias portion of the amplification circuit 112 and generates a signal fed back from the output terminal OUT p and OUT n . The common mode feedback unit 330 can be used to stabilize the common mode of the amplification circuit 112.

[0046] Figure 4 A configuration of a main amplification unit of an amplification circuit according to an embodiment of the disclosure is illustrated. Figure 4 A configuration of the main amplification unit 310 is further illustrated.

[0047] Referring to Figure 4 , the main amplification unit 310 includes a first positive path 412a, a first negative path 412b, a second positive path 414a, a second negative path 414b, a path separation unit 420, and a current mirror 430.

[0048] The first positive path 412a and the first negative path 412b generate a first current using the input signal. The first positive path 412a generates a current corresponding to the voltage of the positive signal of the differential signal, and the first negative path 412b generates a current corresponding to the voltage of the negative signal of the differential signal. The first positive path 412a and the first negative path 412b can be collectively referred to as a first path.

[0049] The second positive path 414a and the second negative path 414b generate a second current using the input signal. The second positive path 414a generates a current corresponding to the voltage of the positive signal of the differential signal, and the second negative path 414b generates a current corresponding to the voltage of the negative signal of the differential signal. Here, the amount of the second current is greater than the amount of the first current. For example, the ratio of the size of the amount of the first current to the size of the amount of the second current can be represented by 1:k. Accordingly, the first positive path 412a and the first negative path 412b can have a relatively high gain characteristic, and the second positive path 414a and the second negative path 414b can have a relatively wide bandwidth characteristic. The second current is provided to the output unit 320 through nodes 442a and 442b. The second positive path 414a and the second negative path 414b can be collectively referred to as a second path.

[0050] The path separation unit 420 controls the first current and the second current. The path separation unit 420 includes a first ground path and a second ground path. The first ground path is used to ground the first positive path 412a and the first negative path 412b, and the second ground path is used to ground the second positive path 414a and the second negative path 414b. The first ground path may include circuitry for controlling the first current, and the second ground path may include circuitry for controlling the second current. Therefore, the first current and the second current can be controlled independently by the path separation unit 420.

[0051] The current mirror 430 generates a third current corresponding to the first current generated via the first positive path 412a and the first negative path 414a. Here, the magnitude of the third current is greater than the magnitude of the first current. For example, the ratio of the magnitude of the first current to the magnitude of the third current can be represented by 1:j. The third current is provided to the output unit 320 via nodes 442a and 442b. Due to the gain of the current mirror 430, the overall gain of the amplifier circuit 112 can be increased. Furthermore, due to the use of the current mirror 430, only one common-mode feedback circuit can be used, and the parasitic pole frequency can be higher.

[0052] Figure 5 An implementation example of the main amplification unit of an amplifier circuit according to an embodiment of the present disclosure is shown. Figure 5 A detailed implementation example of the main amplification unit 310 is further shown.

[0053] Reference Figure 5 The main amplification unit 310 includes transistors 502a, 502b, 504a, 504b, 506a, 506b, a variable transistor 508a, a variable transistor 508b, 510a, 510b, 512a, and 512b. Transistors 502a, 502b, 506a, 506b, 508a, and 508b are n-channel metal-oxide-semiconductor (NMOS) transistors, and transistors 504a, 504b, 510a, 510b, 512a, and 512b are p-channel metal-oxide-semiconductor (PMOS) transistors. According to another embodiment, NMOS transistors can be used instead of p-type metal-oxide-semiconductor (PMOS) transistors, and PMOS transistors can be used instead of NMOS transistors.

[0054] The first positive path 412a includes transistor 502a, and the first negative path 412b includes transistor 502b. An input signal is applied to the gates of transistors 502a and 502b. The drains of transistors 502a and 502b are connected to the drains of transistors 504a and 504b. The gates of transistors 504a and 504b are connected to a bias voltage vbcp.

[0055] The second positive path 414a includes a transistor 506a, and the second negative path 414b includes a transistor 506b. An input signal is applied to the gates of the transistors 506a and 506b. The ratio of the sizes of the transistors 502a and 502b to the sizes of the transistors 506a and 506b can be 1 : k. The drains of the transistors 506a and 506b are connected to the nodes 442a and 442b.

[0056] The path separation unit 420 includes a variable transistor 508a and a variable transistor 508b. A bias voltage vbn is applied to the gates of the variable transistors 508a and 508b, and the sources of the variable transistors 508a and 508b are grounded. The drain of the variable transistor 508a is connected to the sources of the transistors 502a and 502b, and the drain of the variable transistor 508b is connected to the sources of the transistors 506a and 506b. The ratio of the maximum size of the variable transistor 508a to the maximum size of the variable transistor 508b can be 1 : k.

[0057] The current mirror 430 includes a transistor 510a, a transistor 510b, a transistor 512a, and a transistor 512b. V DD is applied to the sources of the transistors 510a, 510b, 512a, and 512b. The gates of the transistors 510a and 510b are connected to the gates of the transistors 512a and 512b. That is, the transistors 510a and 512b share a gate voltage, and the transistors 510b and 512a share a gate voltage. The drains of the transistors 510a and 510b are connected to the sources of the transistors 504a and 504b. The drains of the transistors 512a and 512b are connected to the nodes 422a and 422b.

[0058] The variable transistors 508a and 508b are each variable to adjust the corresponding current amount. For example, the variable transistors 508a and 508b each include a plurality of NMOS transistors, and can have a structure in which some or all of the NMOS transistors are turned on according to a desired current amount. By controlling the variable transistors 508a and 508b, it is possible to adjust the gain g mn1 and g mn3 Furthermore, by controlling the variable transistors 508a and 508b, it is possible to adjust the gain and the bandwidth of the amplification circuit 112.

[0059] The parasitic capacitances 514a and 514b can be configured in the gates of the transistors 510a and 510b.

[0060] The characteristics of the circuit shown in FIG. 13 will be described with reference to the following equations. Figure 5

[0061]

[0062] ​In Equation 1, g mp1 The gain g represents the current mirror corresponding to the first path. mp3 The gain of the current mirror corresponding to the second path is represented by j, and the ratio between the gains of the current mirrors is represented by g. mn1 It is the gain of the first path, g mn3 The gain of the second path is represented by , and k represents the gain ratio between the first and second paths.

[0063] Here, the overall gain of amplifier circuit 112 is defined by Equation 2 below.

[0064]

[0065] In Equation 2, H(s) represents the transfer function of amplifier circuit 112, j represents the gain ratio of the current mirror, k represents the gain ratio between the first path and the second path, and g mn1 r represents the gain of the first path. o2 C represents the parasitic resistance at the output terminal. o1 This indicates a parasitic capacitance of 514b, g mp1 C represents the gain of the current mirror corresponding to the first path. o2 g represents the parasitic capacitance at the output terminal. o2 Indicates r o2 The reciprocal of.

[0066] Each term included in the transfer function of Equation 2 can be defined using Equation 3.

[0067]

[0068] In Equation 3, ω z,LHP The frequency corresponding to zero in the left half-plane (LHP) is represented by j, the gain ratio of the current mirror is represented by k, and the gain ratio between the first and second paths is represented by g. mp1 C represents the gain of the current mirror corresponding to the first path. o1 This indicates a parasitic capacitance of 514 Ω, ω p1 ω represents the frequency at which the first pole occurs. p2 The frequency at which the second pole occurs is represented by r. o2 C represents the parasitic resistance at the output terminal. o2 This indicates the parasitic capacitance at the output terminal.

[0069] Here, if ω z,LHP Eliminate ω p2 The low-frequency gain can then be defined using Equation 4 below.

[0070]

[0071] In Equation 4, G DCrepresents a low frequency gain, j represents a gain ratio of the current mirror, k represents a gain ratio between the first path and the second path, g mn1 represents a gain of the first path, r o2 represents a parasitic resistance at the output terminal, GBW represents a gain bandwidth, g mp1 represents a gain of the current mirror corresponding to the first path, C o1 represents a parasitic capacitance 514b.

[0072] Figure 6 An implementation example of an output unit of an amplification circuit according to an embodiment of the present disclosure is shown. Figure 6 A further implementation example of the output unit 320 is shown.

[0073] Referring to Figure 6 , the output unit 320 includes transistors 602a, 602b, 604a, 604b, 606a, 606b, resistors 608a, and 608b. The transistors 602a and 602b are PMOS transistors, and the transistors 604a, 604b, 606a, and 606b are NMOS transistors. According to another embodiment, NMOS transistors can be used instead of PMOS transistors, and PMOS transistors can be used instead of NMOS transistors.

[0074] A bias voltage vbcp is applied to gates of the transistors 602a and 602b, a bias voltage vbcn is applied to gates of the transistors 604a and 604b, and a bias voltage vcmfb is applied to gates of the transistors 606a and 606b. Sources of the transistors 602a and 602b are connected to nodes 442a and 442b, and drains of the transistors 602a and 602b are connected to output terminals OUT n and OUT p . That is, the transistors 602a and 602b receive an input signal through the sources, and output an output signal through the drains. One node of each of the resistors 608a and 608b is connected to a body terminal of a corresponding one of the transistors 602a and 602b, and V DD is applied to the other node of the resistors 608a and 608b. Drains of the transistors 604a and 604b are connected to the output terminals OUT n and OUT p , respectively, and sources of the transistors 604a and 604b are connected to drains of the transistors 606a and 606b, respectively. Sources of the transistors 606a and 606b are grounded.

[0075] Referring to Figure 5 and Figure 6The transistors 504a, 504b, 602a, and 602b have a cascode structure with the transistors 510a, 510b, 512a, and 512b. In addition, the transistors 504a, 504b, 602a, and 602b hold the voltage of the drain of the transistors 510a, 510b, 512a, and 512b included in the current mirror 430 constant to hold the current division ratio of the current mirror 430. In addition, the transistors 504a, 504b, 602a, 602b improve the gain by increasing the load impedance of the first positive path 412a, the first negative path 412b, the second positive path 414a, and the second negative path 414b.

[0076] The resistors 608a and 608b are arranged between the terminals and the transistors 602a and 602b, thereby serving as a high impedance body biased to the transistors 602a and 602b. Accordingly, it is possible to improve the high frequency characteristics of the amplification circuit 112. The transistors 604a and 604b and the transistors 606a and 606b configure the output impedance. DD The transistors 604a and 604b and the transistors 606a and 606b are arranged between the terminals and the transistors 602a and 602b, thereby serving as a high impedance body biased to the transistors 602a and 602b. Accordingly, it is possible to improve the high frequency characteristics of the amplification circuit 112. The transistors 604a and 604b and the transistors 606a and 606b configure the output impedance.

[0077] The parasitic elements 610a and 610b can be configured at the output terminals OUT n and OUT p The parasitic elements 610a and 610b can be represented by a capacitor and a resistor connected in parallel, respectively.

[0078] Figure 7 An implementation example of the common mode feedback unit of the amplification circuit according to the embodiment of the present disclosure is shown. Figure 7 A further implementation example of the common mode feedback unit 330 is shown.

[0079] Referring to Figure 7 , the common mode feedback unit 330 includes the transistors 702a, 702b, 704a, 704b, 706a, 706b, 708a, 708b, 710a, 710b, 712a, 712b, 714a, and 714b and the resistor 716. The transistors 702a, 702b, 704a, 704a, 704b, 706a, 706b, 708a, 708b, 710a, 710b are PMOS transistors, and the transistors 712a, 712b, 714a, 714b are NMOS transistors. According to another embodiment, the PMOS transistors can be replaced with NMOS transistors, and the NMOS transistors can be replaced with PMOS transistors.

[0080] A bias vbp is applied to the gates of transistors 702a and 702b, a bias vcm is applied to the gates of transistors 704a and 704b, a bias vbcp2 is applied to the gates of transistors 708a and 708b, and a bias vbcp2 is applied to the gates of transistors 710a and 710b. The common mode feedback unit 330 generates a bias vcmfb by means of resistor 716 and applies the bias vcmfb to the main amplifier. DD The sources of transistors 702a and 702b are connected to the drains of transistors 702a and 702b, and the drains of transistors 702a and 702b are connected to the sources of transistors 704a and 704b. The sources of transistors 706a and 706b are connected to the sources of transistors 704a and 704b, and the gates of transistors 706a and 706b are connected to the output terminals OUT n and OUT p .

[0081] The drains of transistors 708a and 708b are interconnected and also connected to another node of resistor 716. The sources of transistors 710a and 710b are connected to the drains of transistors 706a and 706b. The drains of transistors 712a and 712b are connected to the other node of resistor 716, and the sources of transistors 712a and 712b are grounded. The gates of transistors 714a and 714b are connected to the gates of transistors 712a and 712b, the drains of transistors 714a and 714b are connected to the drains of transistors 710a and 710b, and the sources of transistors 714a and 714b are grounded.

[0082] Capacitors 718 can be connected to one node of resistor 716 for stabilization. Furthermore, capacitors 720a and 720b can be connected to the output terminals OUT n and OUT p .

[0083] The methods according to the embodiments of the claims and / or specification of the present disclosure can be implemented in hardware, software, or a combination of hardware and software.

[0084] When the methods are implemented by software, a computer-readable storage medium for storing one or more programs (software modules) can be provided. The one or more programs stored in the computer-readable storage medium can be configured to be executed by one or more processors within an electronic device. At least one program can include instructions that cause the electronic device to perform the methods according to various embodiments as defined by the appended claims and / or disclosed herein.

[0085] The programs (software modules or software) can be stored in non-volatile memories including a random access memory and a flash memory, a read only memory (ROM), an electrically erasable programmable read only memory (EEPROM), a magnetic disc storage device, a compact disc-ROM (CD-ROM), digital versatile discs (DVDs), or other type of optical storage devices, or a magnetic cassette. Alternatively, some or all of them can be configured as a memory embedded in one of application specific integrated circuits (ASICs). Also, the programs can be stored in a memory configured on a server connected to a network on the internet. Further, a plurality of such memories can be included in a storage device.

[0086] Also, the programs can be stored in an attachable storage device which is accessible through a communication network such as the internet, an intranet, a local area network (LAN), a wide area network (WAN), and a storage area network (SAN), or a combination thereof. Such a storage device can be accessed by the electronic device via an external port. Further, a separate storage device on the communication network can access the portable electronic device.

[0087] Also, a plurality of elements expressed in the description can be configured as a single element, or a single element in the description can be configured as a plurality of elements.

[0088] While the disclosure has been shown and described with reference to various embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents.

Claims

1. An apparatus including electronic circuitry, the apparatus comprising: A transceiver, the transceiver including an amplifier circuit; as well as At least one processor, said at least one processor being coupled to the transceiver, The amplifier circuit includes: The main amplifier circuit amplifies the input signal input through the input terminal. Output circuit, which generates an output signal in response to the amplified input signal, and A common-mode feedback circuit generates a feedback signal from the output signal. The main amplifier circuit includes: The first path generates a first current corresponding to the voltage of the input signal. The second path generates a second current corresponding to the voltage of the input signal. A separation unit, which controls each of the first current and the second current, and A current mirror generates a third current corresponding to the first current, and The output circuit includes a folding unit that generates the output signal based on the second current and the third current.

2. The apparatus according to claim 1, in, The amount of the second current is greater than the amount of the first current. The amount of the third current is greater than the amount of the first current.

3. The apparatus according to claim 1, wherein, The second path includes transistors that are larger than those included in the first path.

4. The apparatus according to claim 1, wherein, The input signal is input to the gate of a transistor included in the first path and the second path.

5. The apparatus according to claim 1, further comprising: A first transistor is disposed between the first path and the current mirror, and the first transistor is connected to a second transistor in the first path in a cascaded structure.

6. The apparatus according to claim 1, wherein, The separation unit includes: A first variable transistor, the first variable transistor being connected to the first path; and The second variable transistor is connected to the second path.

7. The apparatus according to claim 6, in, The gates of the first variable transistor and the second variable transistor are connected to the same bias voltage. The drain of the first variable transistor is connected to the source of a transistor included in the first path. The drain of the second variable transistor is connected to the source of the transistor included in the second path. The source of the first variable transistor and the source of the second variable transistor are grounded.

8. The apparatus according to claim 1, in, The current mirror includes: The first transistor, the gain of which is the same as the gain of the first path, and The second transistor has a higher gain than the first path. The first transistor and the second transistor share a gate voltage.

9. The apparatus according to claim 1, wherein, The folding unit includes a transistor, the transistor being configured to: The second current and the third current are received through the source; and The output signal is output through the drain.

10. The apparatus according to claim 9, wherein, The folded unit includes a resistor connected to the body terminal of the transistor.

11. The apparatus according to claim 1, in, The output circuit communicates with the main amplifier circuit and the common-mode feedback circuit.

12. The apparatus according to claim 11, in, The first path has high gain characteristics, and The second path has wide bandwidth characteristics.

13. The apparatus according to claim 11, wherein, The common-mode feedback circuit includes a feedback circuit installed in the bias section of the amplifier circuit.

14. The apparatus according to claim 11, wherein, The output circuit includes a structure folded relative to the main amplifier circuit to ensure reserved space for the output circuit.

15. The apparatus according to claim 11, in, The common-mode feedback circuit includes a feedback circuit installed in the bias section of the amplifier circuit. The common-mode feedback circuit is configured as follows: A feedback signal is generated from the output signal, and Stabilize the common mode of the amplifier circuit.

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