Display device

Abstract

A display device is provided, comprising: a substrate; a first conductive layer including a lower pattern disposed on the substrate; an active layer including a first active pattern disposed on the first conductive layer; and a second conductive layer including a first gate electrode disposed on the active layer, wherein the first gate electrode overlaps with a first channel region included in the first active pattern, the lower pattern overlaps with the first active pattern, and the first active pattern does not intersect with an edge of the lower pattern.

Description

[0001] This application claims priority to and all benefits derived therefrom from Korean Patent Application No. 10-2019-0018526, filed on February 18, 2019, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The disclosure relates to a display device. Background Art

[0003] A display device is a device for displaying an image, and recently, a light emitting diode display has been widely used as a self-luminous display device.

[0004] Unlike liquid crystal displays, light emitting diode display devices have self-emission characteristics and thus may not include a separate light source, so that their thickness and weight may be reduced. In addition, light emitting diode display devices have various desirable characteristics such as low power consumption, high brightness, and fast response speed.

[0005] Generally, a light emitting diode display device generally includes a plurality of transistors and a plurality of light emitting elements. In such a light emitting diode display device, the transistor is connected to a signal line and can transmit a driving current to the light emitting element. The transistor can include an active pattern including a channel region and a conductive region. Summary of the invention

[0006] The present disclosure relates to a display device in which defects in an active pattern are effectively prevented.

[0007] An exemplary embodiment of a display device according to the invention includes: a substrate; a first conductive layer including a lower pattern disposed on the substrate; an active layer including a first active pattern disposed on the first conductive layer; and a second conductive layer including a first gate electrode disposed on the active layer, wherein the first gate electrode overlaps with a first channel region included in the first active pattern, the lower pattern overlaps with the first active pattern, and when viewed from a plan view in a thickness direction of the substrate, the first active pattern does not overlap with an edge of the lower pattern.

[0008] An exemplary embodiment of a display device according to the invention includes: a first conductive layer including a conductive pattern; an active layer including a first active pattern and a second active pattern; a second conductive layer including a first gate electrode; and a third conductive layer including a capacitor electrode, wherein the first active pattern includes a first channel region, a first source region, and a first drain region, wherein the first channel region overlaps with the first gate electrode, the second active pattern includes a second channel region, a second source region, and a second drain region, an edge of the conductive pattern surrounds an edge of the first active pattern, the conductive pattern overlaps with the first active pattern and does not overlap with the second active pattern, and the capacitor electrode is electrically connected to the first drain region and the second source region.

[0009] An exemplary embodiment of a display device according to the invention includes: a first conductive layer including a conductive pattern; and an active layer including a first active pattern and a second active pattern separated from each other, wherein the conductive pattern overlaps the first active pattern and does not overlap the second active pattern, and an edge of the conductive pattern is disposed between the first active pattern and the second active pattern.

[0010] In the disclosed exemplary embodiments, as described herein, defects of active patterns of a display device may be effectively prevented. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] These and / or other features of the invention will become apparent and more readily understood through the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a circuit diagram of one pixel of a display device according to an exemplary embodiment of the invention;

[0013] Figure 2 is a plan view of a plurality of pixels of a display device according to an exemplary embodiment of the invention;

[0014] Figure 3 It is along Figure 2 A cross-sectional view taken along line IIIa-IIIb of the display device shown in FIG.

[0015] Figure 4 It is along Figure 2 A cross-sectional view taken along line IVa-IVb shown in FIG.

[0016] Figure 5 It is along Figure 2 A cross-sectional view taken along line Va-Vb shown in FIG.

[0017] Figure 6 is along with Figure 2 A cross-sectional view taken along line Va-Vb shown in FIG. 1 corresponds to a cross-sectional view of an alternative exemplary embodiment of a display device;

[0018] Figure 7 and Figure 8 is along with Figure 2 A cross-sectional view taken along line IIIa-IIIb shown in FIG. 1 corresponds to a cross-sectional view of another optional exemplary embodiment of a display device;

[0019] Fig. 9 is a plan view of a plurality of pixels of a display device according to an alternative exemplary embodiment of the invention;

[0020] Fig.10 is a plan view of a portion of one pixel of a display device according to an exemplary embodiment of the invention;

[0021] Fig.11 It is along Fig.10 A cross-sectional view taken along line XIa-XIb shown in FIG.

[0022] Fig.12 is a plan view of a plurality of pixels of a display device according to an alternative exemplary embodiment of the invention;

[0023] Fig.13 is a plan view of a pixel electrode layer of a display device according to an exemplary embodiment of the invention; and

[0024] Fig.14 It is along Fig.12 A cross-sectional view taken along line XIVa-XIVb is shown in FIG. DETAILED DESCRIPTION

[0025] Hereinafter, the invention will be described more fully with reference to the accompanying drawings in which various embodiments of the invention are shown. However, the invention can be implemented in many different forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the invention to those skilled in the art.

[0026] The drawings and description are to be regarded as illustrative in nature and not restrictive. Throughout the specification, like reference numerals refer to like elements.

[0027] In addition, in the drawings, for better understanding and ease of description, the size and thickness of each element are arbitrarily indicated, and the invention is not limited thereto. In the drawings, for clarity, the thickness of layers, films, panels, regions, etc. are exaggerated. In the drawings, for better understanding and ease of description, the thickness of some layers and regions are exaggerated.

[0028] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element, or there may be intervening elements. Conversely, when an element is referred to as being "directly on" another element, there are no intervening elements. In addition, in the specification, the words "on..." or "above..." indicate positioning on or below an object part, and do not necessarily mean positioning on the upper side of an object part based on the direction of gravity.

[0029] It will be understood that, although the terms "first", "second", "third", etc., can be used to describe various elements, components, regions, layers and / or parts here, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings here, the first "element", "component", "region", "layer" or "part" being discussed below can be named as the second element, component, region, layer or part.

[0030] The terms used herein are only for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "one (kind / person)" and "the (described)" are also intended to include plural forms, which include "at least one (kind / person)". "Or" means "and / or". "At least A and B" means "A and / or B". As used herein, the term "and / or" includes any combination and all combinations of one or more related listed items. It will also be understood that when the terms "include" or "comprise" are used in this specification, it is explained that there are stated features, regions, wholes, steps, operations, elements and / or components, but it is not excluded that there are or add one or more other features, regions, wholes, steps, operations, elements, components and / or their groups.

[0031] As used herein, "about" or "approximately" are inclusive of the stated value and mean within an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with measurement of the particular quantity (i.e., limitations of the measurement system).

[0032] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those generally understood by those skilled in the art. Terms defined in general dictionaries should be interpreted as having the same meaning as in the relevant technical context, and unless clearly defined in the description, terms should not be ideally or excessively interpreted as having a formal meaning.

[0033] Exemplary embodiments are described herein with reference to cross-sectional views as schematic diagrams of idealized embodiments. As such, variations in the shapes of the diagrams due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the embodiments described herein should not be construed as being limited to the specific shapes of the regions as shown herein, but will include deviations in shapes due to, for example, manufacturing. For example, a region shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the regions, and are not intended to limit the scope of the claims.

[0034] In the present specification and claims, a plan view refers to a view for observing a surface parallel to two directions intersecting each other (e.g., a first direction DR1 and a second direction DR2) (referred to as "in a plan view"), and a cross-sectional view refers to a view for observing a surface cut in a direction perpendicular to the surface parallel to the first and second directions (e.g., a third direction DR3) (referred to as "in a cross-sectional view"). In addition, unless otherwise stated, "two constituent elements overlap each other" means that the two constituent elements overlap each other in a plan view, that is, when viewed from a plan view in the third direction DR3 (e.g., a direction perpendicular to the upper surface of the substrate or a thickness direction of the substrate), the two constituent elements overlap each other.

[0035] Hereinafter, embodiments of the invention will be described in detail with reference to the accompanying drawings.

[0036] First, refer to Figure 1 A structure of a display device according to an exemplary embodiment of the invention is described.

[0037] Figure 1 is a circuit diagram of one pixel of a display device according to an exemplary embodiment of the invention.

[0038] An exemplary embodiment of a display device according to the invention includes a plurality of pixels PX, and one pixel PX may include a plurality of transistors T1, T2, and T3, a capacitor Cst, and at least one light emitting diode ED. In such an embodiment, Figure 1 As shown in FIG. 1 , one pixel PX may include a single light emitting diode ED, but is not limited thereto.

[0039] The plurality of transistors T1, T2 and T3 include first, second and third transistors T1, T2 and T3. The source electrode and the drain electrode described herein correspond to two electrodes disposed on respective or opposite sides of a channel of each transistor T1, T2 and T3, and the terms may be used interchangeably.

[0040] In an exemplary embodiment, if Figure 1As shown in FIG. 1 , a gate electrode G1 of the first transistor T1 is connected to one terminal of the capacitor Cst, a source electrode S1 of the first transistor T1 is connected to a driving voltage line for transmitting a driving voltage ELVDD, and a drain electrode D1 of the first transistor T1 is connected to an anode of the light emitting diode ED and the other terminal of the capacitor Cst. The first transistor T1 receives the data voltage DAT based on a switching operation of the second transistor T2, and can supply a driving current corresponding to a voltage stored in the capacitor Cst to the light emitting diode ED.

[0041] As described in more detail below, the first transistor T1 may overlap the lower pattern 111 , and the lower pattern 111 may be connected to the drain electrode D1 of the first transistor T1 .

[0042] The gate electrode G2 of the second transistor T2 is connected to the first scan line for transmitting the first scan signal SC, the source electrode S2 of the second transistor T2 is connected to the data line that can transmit the data voltage DAT or the reference voltage, and the drain electrode D2 of the second transistor T2 is connected to the one terminal of the capacitor Cst and the gate electrode G1 of the first transistor T1. The second transistor T2 can be turned on in response to the first scan signal SC to transmit the reference voltage or the data voltage DAT to the gate electrode G1 of the first transistor T1 and the one terminal of the capacitor Cst.

[0043] The gate electrode G3 of the third transistor T3 is connected to the second scan line for transmitting the second scan signal SS, the source electrode S3 of the third transistor T3 is connected to the other terminal of the capacitor Cst, the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode ED, and the drain electrode D3 of the third transistor T3 is connected to the initialization voltage line to which the initialization voltage INIT is applied. The third transistor T3 is turned on in response to the second scan signal SS, so that the initialization voltage INIT can be transmitted to the other terminal of the capacitor Cst and the anode of the light emitting diode ED, so that the anode voltage of the light emitting diode ED is initialized.

[0044] The one terminal of the capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and the other terminal of the capacitor Cst is connected to the anode of the light emitting diode ED and the source electrode S3 of the third transistor T3. The cathode of the light emitting diode ED is connected to the common voltage line transmitting the common voltage ELVSS.

[0045] The light emitting diode ED may emit light having brightness corresponding to the driving current generated by the first transistor T1.

[0046] In the following, the Figure 1The operation of the exemplary embodiment of the pixel PX shown in FIG. 1 , and specifically, its operation during one frame will be described. In such an embodiment, the transistors T1 , T2 , and T3 may be N-channel transistors, but are not limited thereto.

[0047] When a frame starts, a high-level first scan signal SC and a high-level second scan signal SS are supplied to the pixel PX in the initialization period, and the second transistor T2 and the third transistor T3 are turned on. The reference voltage from the data line is supplied to the one terminal of the capacitor Cst and the gate electrode G1 of the first transistor T1 through the turned-on second transistor T2, and the initialization voltage INIT is supplied to the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode ED through the turned-on third transistor T3. Therefore, during the initialization period, the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode ED are initialized to the initialization voltage INIT. In this case, a voltage corresponding to the difference between the reference voltage and the initialization voltage INIT is stored in the capacitor Cst.

[0048] Next, in the sensing period, when the second scan signal SS becomes a low level and the high level first scan signal SC is maintained, the second transistor T2 remains in the on state and the third transistor T3 is turned off. The gate electrode G1 of the first transistor T1 and the one terminal of the capacitor Cst are maintained at the reference voltage through the turned-on second transistor T2, and the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode ED are disconnected from the initialization voltage INIT through the turned-off third transistor T3. Therefore, the first transistor T1 allows current to flow from the source electrode S1 to the drain electrode D1, and then when the voltage of the drain electrode D1 becomes a voltage obtained by subtracting the threshold voltage (Vth) from the reference voltage, the first transistor T1 is turned off. Here, Vth represents the threshold voltage of the first transistor T1. At this time, the voltage difference between the gate electrode G1 and the drain electrode D1 of the first transistor T1 is stored in the capacitor Cst, and the threshold voltage Vth of the first transistor T1 can be sensed. By generating a data signal compensated based on the sensed characteristic information (eg, threshold voltage Vth) of the first transistor T1 during the sensing period, characteristic deviation of the first transistor T1 that may be different in each pixel PX may be externally compensated.

[0049] Next, in the data input period, when the first scan signal SC of a high level is supplied and the second scan signal SS of a low level is supplied, the second transistor T2 is turned on and the third transistor T3 is turned off. The data voltage DAT from the data line is supplied to the one terminal of the capacitor Cst and the gate electrode G1 of the first transistor T1 via the turned-on second transistor T2. In this case, the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode ED can be substantially maintained at their potential in the sensing period by the first transistor T1 in the turned-off state.

[0050] Next, in the light emitting period, the first transistor T1 turned on by the data voltage DAT transmitted to the gate electrode G1 generates a driving current corresponding to the data voltage DAT, and the light emitting diode ED may emit light based on the driving current.

[0051] Now refer to Figures 2 to 5 as well as Figure 1 A detailed structure of an exemplary embodiment of a display device according to the invention is described.

[0052] Figure 2 is a plan view of a plurality of pixels of a display device according to an exemplary embodiment of the invention, Figure 3 It is along Figure 2 A cross-sectional view taken along line IIIa-IIIb of the display device shown in FIG. Figure 4 It is along Figure 2 A cross-sectional view taken along line IVa-IVb of the display device shown in FIG. Figure 5 It is along Figure 2 0 is a cross-sectional view taken along line Va-Vb of the display device shown in FIG. Figure 2 A planar structure of three pixels PX1, PX2, and PX3 adjacent to each other is shown, and since each pixel PX1, PX2, or PX3 includes constituent elements corresponding to each other, the figure mark of any one pixel PX1, PX2, or PX3 may be equally applied to the corresponding constituent elements of the other pixels PX1, PX2, and PX3.

[0053] An exemplary embodiment of the display device may include a substrate 110. The substrate 110 may include an insulating material such as glass, plastic, etc., and may have flexibility.

[0054] A lower layer (or first conductive layer) including a plurality of lower patterns 111 may be disposed on the substrate 110. The lower patterns 111 are also referred to as conductive patterns. The lower layer may include at least one selected from various conductive metals and semiconductor materials having conductive properties equivalent thereto.

[0055] In an exemplary embodiment, if Figure 3As shown in , the thickness TK1 of the lower pattern 111 in the third direction DR3 may range from hundreds to thousands of angstroms. In one exemplary embodiment, for example, the thickness TK1 of the lower pattern 111 in the third direction DR3 may range from about 500 angstroms to less than 4000 angstroms.

[0056] The buffer layer 120 as an insulating layer is disposed on the lower layer.

[0057] An active layer including a plurality of active patterns 130a, 130b, and 130c is disposed on the buffer layer 120. In such an embodiment, a lower layer may be disposed between the substrate 110 and the active layer. Each of the active patterns 130a, 130b, and 130c disposed in each pixel PX1, PX2, or PX3 may include a channel region 134a, 134b, and 134c and a conductive region connected thereto, the channel region 134a, 134b, and 134c defining a channel of each of the plurality of transistors T1, T2, and T3 described above. The conductive region of each of the active patterns 130a, 130b, and 130c may include a source region 133a, 133b, or 133c and a drain region 135a, 135b, or 135c of each transistor T1, T2, or T3.

[0058] In each pixel PX1 , PX2 , or PX3 , the active pattern 130 a and the active pattern 130 c may be connected to each other or separated from each other. Figure 2 An exemplary embodiment in which the active pattern 130a and the active pattern 130c are connected to each other is shown. In such an embodiment, the drain region 135a of the active pattern 130a may be the source region 133c of the active pattern 130c.

[0059] The active layer may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

[0060] The thickness of the active layer in the third direction DR3 may be smaller than the thickness TK1 of the lower pattern 111 and may be, for example, several hundred angstroms. In one exemplary embodiment, for example, the thickness of the active layer in the third direction DR3 may range from about 300 angstroms to about 500 angstroms, but is not limited thereto.

[0061] The insulating pattern 144 of the first insulating layer may be disposed on the active layer. The insulating pattern 144 may overlap the channel regions 134a, 134b, and 134c of the active patterns 130a, 130b, and 130c, and may be disposed on the channel regions 134a, 134b, and 134c. The insulating pattern 144 may not substantially overlap the conductive regions of the active patterns 130a, 130b, and 130c.

[0062] The second conductive layer may be disposed on the insulating pattern 144. The second conductive layer may include a first scan line 151 that may transmit the first scan signal SC described above, a second scan line 152 that may transmit the second scan signal SS, a horizontal initialization voltage line 153 that may transmit the initialization voltage INIT, a horizontal driving voltage line 172b that may transmit the driving voltage ELVDD, a driving gate electrode 155, a second gate electrode 154b, and a third gate electrode 154c. The gate electrode G1, the gate electrode G2, and the gate electrode G3 in the circuit diagram described above may correspond to the first gate electrode 154a, the second gate electrode 154b, and the third gate electrode 154c defined by a portion of the driving gate electrode 155, respectively.

[0063] The first and second scan lines 151 and 152 , the transverse initialization voltage line 153 , and the transverse driving voltage line 172 b may extend in the first direction DR1 , respectively.

[0064] In a plan view, the driving gate electrode 155 may be disposed between the first scan line 151 and the second scan line 152 .

[0065] The second gate electrode 154b is spaced apart from the first scan line 151 and may extend approximately in the second direction DR2. Alternatively, the second gate electrode 154b may be directly connected to the first scan line 151.

[0066] The third gate electrode 154c is spaced apart from the second scan line 152 and may extend approximately in the second direction DR2. Alternatively, the third gate electrode 154c may be directly connected to the second scan line 152.

[0067] The driving gate electrode 155 disposed in each pixel PX1 , PX2 , or PX3 may include a protrusion 155 a protruding upward in the second direction DR2 and a first gate electrode 154 a extending approximately downward.

[0068] The first gate electrode 154a intersects the active pattern 130a and overlaps the channel region 134a of the active pattern 130a. The second gate electrode 154b intersects the active pattern 130b and overlaps the channel region 134b of the active pattern 130b. The third gate electrode 154c intersects the active pattern 130c and overlaps the channel region 134c of the active pattern 130c.

[0069] The second insulating layer 160 may be disposed on the second conductive layer. A plurality of contact holes 24 , 26 , 60 , 61 , 62 , 63 , 64 , 65 , 66 , 67 , 68 , and 69 may be defined through the buffer layer 120 and / or the second insulating layer 160 .

[0070] The third conductive layer may be disposed on the second insulating layer 160. The third conductive layer may include a plurality of data lines 171a, 171b, and 171c, a plurality of driving voltage lines 172a, 172c, and 172d, a common voltage line 170, an initialization voltage line 173, a capacitor electrode 175, and a plurality of connection members 174, 176, 177, and 178.

[0071] In a plan view, the data lines 171 a , 171 b , and 171 c , the driving voltage lines 172 a , 172 c , and 172 d , the common voltage line 170 , and the initialization voltage line 173 may respectively extend approximately in the second direction DR2 and intersect the first and second scan lines 151 and 152 .

[0072] Figure 2 The plurality of pixels PX1, PX2, and PX3 of the pixel group (or pixel unit) shown in FIG. 1 may be arranged in a first direction DR1 and adjacent to each other, and may be repeatedly disposed in the first direction DR1 and the second direction DR2. The common voltage line 170 may be disposed on the left and right sides of the plurality of pixels PX1, PX2, and PX3 of one group, respectively. In an exemplary embodiment, the plurality of pixels PX1, PX2, and PX3 in the repeated group include the following: Figure 2 In the case of three pixels PX1 , PX2 , and PX3 shown in FIG, three data lines 171 a , 171 b , and 171 c , three driving voltage lines 172 a , 172 c , and 172 d , and at least one initialization voltage line 173 may be disposed between two adjacent common voltage lines 170 .

[0073] Each data line 171a, 171b or 171c passes through a contact hole 64 (eg, Figure 2 Two contact holes 64) defined in each pixel PX1, PX2 or PX3 shown in FIG. 1 are electrically connected to the source region 133b of the active pattern 130b.

[0074] Each driving voltage line 172 a , 172 c , or 172 d may be provided corresponding to each pixel PX1 , PX2 , or PX3 .

[0075] Each driving voltage line 172a, 172c or 172d passes through a contact hole 61 (eg, Figure 2The two contact holes 61 defined in the pixels PX1 and PX2 and one contact hole 61 defined in the pixel PX3 shown in FIG. 1 are electrically connected to the source region 133a of the active pattern 130a. In such an embodiment, the driving voltage lines 172a, 172c, and 172d are electrically connected to the lateral driving voltage line 172b through the contact hole 60 of the second insulating layer 160. Therefore, the lateral driving voltage line 172b can transmit the driving voltage together with the driving voltage lines 172a, 172c, and 172d, and the driving voltage is transmitted throughout the entire display device in both the first direction DR1 and the second direction DR2, for example, in a grid shape.

[0076] The initialization voltage line 173 is electrically connected to the horizontal initialization voltage line 153 through the contact hole 69 of the second insulating layer 160. Therefore, in an exemplary embodiment, even in the case where a single initialization voltage line 173 is provided for three pixels PX1, PX2, and PX3, the horizontal initialization voltage line 153 may transmit the initialization voltage together with the initialization voltage line 173, and the initialization voltage may be transmitted to all three pixels PX1, PX2, and PX3 through the horizontal initialization voltage line 153. The capacitor electrode 175 (e.g., a single capacitor electrode) may be provided in each pixel PX1, PX2, or PX3. The capacitor electrode 175 may overlap with the corresponding drive gate electrode 155 via the second insulating layer 160 between the capacitor electrode 175 and the drive gate electrode 155, thereby forming a capacitor Cst.

[0077] The capacitor electrode 175 may include a protrusion 175a extending downward therefrom. The protrusion 175a passes through the contact hole 62 (eg, Figure 2 The two contact holes 62 defined at each pixel PX1, PX2 or PX3 as shown in FIG. 1 are electrically connected to the drain region 135a of the active pattern 130a (or the source region 133c of the active pattern 130c). In such an embodiment, as shown in FIG. Figure 3 As shown in FIG. 1 , the capacitor electrode 175 is electrically connected to the lower pattern 111 through a contact hole 68 defined through the second insulating layer 160 and the buffer layer 120 .

[0078] The connection member 174 may be electrically connected to the second scan line 152 and the third gate electrode 154 c through the contact hole 24 of the second insulating layer 160 to electrically connect the second scan line 152 and the third gate electrode 154 c to each other.

[0079] The connection member 176 may be electrically connected to the first scan line 151 and the second gate electrode 154 b through the contact hole 26 of the second insulating layer 160 to electrically connect the first scan line 151 and the second gate electrode 154 b to each other.

[0080] In each pixel PX1, PX2 or PX3, the connection member 177 passes through the contact hole 63 (eg, as shown in FIG. 6A ) of the second insulating layer 160. Figure 2 The two contact holes 63 defined at each pixel PX1, PX2 or PX3 shown in the figure are electrically connected to the drain region 135c of the active pattern 130c, and are electrically connected to the horizontal initialization voltage line 153 through the contact hole 67 of the second insulating layer 160, so that the drain region 135c of the active pattern 130c can be electrically connected to the horizontal initialization voltage line 153.

[0081] The transverse initialization voltage line 153 extends across the three pixels PX1, PX2, and PX3 in the first direction DR1, and may be disposed between two adjacent common voltage lines 170 such that the transverse initialization voltage line 153 does not intersect (or overlap) the two adjacent common voltage lines 170. The transverse initialization voltage line 153 intersects the three adjacent data lines 171a, 171b, and 171c, and may extend only to the initialization voltage line 173.

[0082] The connection member 178 passes through the contact hole 65 (eg, Figure 2 The two contact holes 65 defined in each pixel PX1, PX2 or PX3 as shown in the figure are electrically connected to the drain region 135b of the active pattern 130b in each pixel PX1, PX2 or PX3, and are electrically connected to the protrusion 155a of the driving gate electrode 155 through the contact hole 66 of the second insulating layer 160, so that the drain region 135b of the active pattern 130b and the protrusion 155a of the driving gate electrode 155 can be electrically connected to each other.

[0083] At least one of the first conductive layer, the second conductive layer, and the third conductive layer includes at least one of metals such as copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and combinations thereof (e.g., alloys), or is made of at least one of metals such as copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and combinations thereof (e.g., alloys). Each of the first conductive layer, the second conductive layer, and the third conductive layer may have a single-layer structure or a multi-layer structure. In an exemplary embodiment, for example, the third conductive layer may have a multi-layer structure including a lower layer including titanium and an upper layer including copper.

[0084] The first transistor T1 includes a channel region 134a, a source region 133a, a drain region 135a, and a first gate electrode 154a. The source region 133a of the first transistor T1 is electrically connected to a corresponding driving voltage line 172a, 172c, or 172d to receive a driving voltage.

[0085] The lower pattern 111 corresponding to the first transistor T1 overlaps the channel region 134a of the first transistor T1 between the channel region 134a and the substrate 110 to prevent external light from reaching the channel region 134a, thereby reducing leakage current and characteristic degradation. The lower pattern 111 is electrically connected to the drain region 135a of the first transistor T1 via the capacitor electrode 175.

[0086] The second transistor T2 includes a channel region 134b, a source region 133b, a drain region 135b, and a second gate electrode 154b. The source region 133b of the second transistor T2 is electrically connected to the corresponding data line 171a, 171b, or 171c to receive a data voltage or a reference voltage. The drain region 135b of the second transistor T2 can be electrically connected to the first gate electrode 154a through the driving gate electrode 155.

[0087] The third transistor T3 includes a channel region 134c, a source region 133c, a drain region 135c, and a third gate electrode 154c. The drain region 135c of the third transistor T3 may receive an initialization voltage through the lateral initialization voltage line 153.

[0088] The third insulating layer 181 may be disposed on the second insulating layer 160 and the third conductive layer. Figure 4 As shown in FIG. 1 , a contact hole 83 a may be defined through the third insulating layer 181 to overlap with the capacitor electrode 175, and as shown in FIG. Figure 5 As shown in , a contact hole 81 may be defined through the third insulating layer 181 to overlap the common voltage line 170 .

[0089] A fourth conductive layer including a plurality of ohmic contacts (contact members) 190 a , 190 b , 190 c , and 190 d may be disposed on the third insulating layer 181 .

[0090] Ohmic contacts (contact members) 190 a , 190 b , and 190 c are respectively disposed in the pixels PX1 , PX2 , and PX3 , and may make contact with the capacitor electrode 175 through the contact hole 83 a to be electrically connected to the capacitor electrode 175 .

[0091] The ohmic contact (contact member) 190 d may make contact with the common voltage line 170 through the contact hole 81 to be electrically connected to the common voltage line 170 .

[0092] Ohmic contacts (contact members) 190a, 190b, 190c, and 190d can improve the adhesion of the capacitor electrode 175 and the common voltage line 170 of the third conductive layer, which are respectively in contact with the third conductive layer, to other conductive layers, and can effectively prevent oxidation of the third conductive layer. In an exemplary embodiment, in the case where the upper layer of the third conductive layer includes copper, oxidation of copper can be prevented. In an exemplary embodiment, the fourth conductive layer may include a conductive material that can prevent corrosion of the upper layer of the third conductive layer. Therefore, in such an embodiment where the upper layer of the third conductive layer includes copper, the conductive material prevents copper corrosion by covering the upper layer of the third conductive layer. In an exemplary embodiment, for example, the fourth conductive layer may include a conductive material such as a metal oxide (such as indium tin oxide ("ITO") or indium zinc oxide ("IZO")).

[0093] The fourth insulating layer 182 may be disposed on the third insulating layer 181 and the fourth conductive layer. Figure 4 , the fourth insulating layer 182 is disposed on each of the ohmic contacts (contact members) 190a, 190b, and 190c, and a contact hole 83b may be defined through the fourth insulating layer 182 to overlap the contact hole 83a.

[0094] At least one selected from the buffer layer 120, the second insulating layer 160, the third insulating layer 181, and the fourth insulating layer 182 includes a silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiON) and / or an organic insulating material. In an exemplary embodiment, the fourth insulating layer 182 may include an inorganic insulating material and / or an organic insulating material such as polyimide, an acrylic polymer, a siloxane polymer, etc., and may have a substantially flat upper surface.

[0095] A fifth conductive layer (or pixel electrode layer) including a plurality of pixel electrodes 191a, 191b, and 191c may be disposed on the fourth insulating layer 182. Figure 2 As shown in , each pixel electrode 191a, 191b or 191c can be arranged in a corresponding pixel in the pixels PX1, PX2 and PX3. The plane size and shape of the pixel electrodes 191a, 191b and 191c arranged in the three pixels PX1, PX2 and PX3 can be different from each other, but the invention is not limited thereto. In an exemplary embodiment, the pixel PX2 represents green, the pixel PX1 represents red, and the pixel PX3 represents blue, but it is not limited thereto.

[0096] Each pixel electrode 191a, 191b, or 191c may contact the corresponding ohmic contact (contact member) 190a, 190b, or 190c through the contact hole 83b of the fourth insulating layer 182, and may be electrically connected to the capacitor electrode 175 through the corresponding ohmic contact (contact member) 190a, 190b, or 190c. Therefore, each pixel electrode 191a, 191b, or 191c may be electrically connected to the drain region 135a of the first transistor T1 to receive a voltage from the first transistor T1.

[0097] The pixel electrode layer may include a semi-transmissive or reflective conductive material.

[0098] The fifth insulating layer 350 may be disposed on the fourth insulating layer 182. An opening 355 is defined through the fifth insulating layer 350 to overlap the pixel electrodes 191a, 191b, and 191c. The fifth insulating layer 350 may include an organic insulating material such as polyacrylic resin, polyimide resin, or the like.

[0099] The emission layer 370 is disposed on the fifth insulating layer 350 and the pixel electrode layer. The emission layer 370 may include a portion disposed in the opening 355 of the fifth insulating layer 350. The emission layer 370 may include an organic light emitting material or an inorganic light emitting material. Alternatively, at least a portion of the fifth insulating layer 350 may not be covered by the emission layer 370.

[0100] A contact hole 82 may be defined through the fifth insulating layer 350 and the emission layer 370 to overlap the ohmic contact 190 d .

[0101] The common electrode 270 is disposed over the emission layer 370. The common electrode 270 may be continuously disposed over the plurality of pixels PX1, PX2, and PX3. The common electrode 270 may be electrically connected to the common voltage line 170 through the contact hole 82 by contacting the ohmic contact 190d to receive a common voltage.

[0102] The common electrode 270 may include a conductive transparent material.

[0103] The pixel electrodes 191a, 191b, and 191c of each pixel PX1, PX2, or PX3, the emission layer 370, and the common electrode 270 collectively define a light emitting diode ED, and one of each pixel electrode 191a, 191b, or 191c and the common electrode 270 may be a cathode, and the other of each pixel electrode 191a, 191b, or 191c and the common electrode 270 may be an anode. In an exemplary embodiment, for example, the pixel electrodes 191a, 191b, and 191c are anodes.

[0104] Reference Figure 2, the lower pattern 111 overlaps the entire active pattern 130a of the first transistor T1 in a plan view, thereby overlapping all of the source region 133a, the channel region 134a, and the drain region 135a of the first transistor T1. In such an embodiment, the edge of the lower pattern 111 is disposed outside the edge of the active pattern 130a, and may have a shape surrounding the active pattern 130a. In such an embodiment, the lower pattern 111 may overlap all edges of the active pattern 130a, and the active pattern 130a may not intersect with the edge of the lower pattern 111. In such an embodiment, in a plan view, the active pattern 130a may be disposed inside the lower pattern 111.

[0105] Therefore, in a plan view, since the active pattern 130a does not intersect with the edge of the lower pattern 111, defects such as disconnection of the active pattern 130a near the edge of the lower pattern 111 due to a relatively large step at the edge of the lower pattern 111 having a thickness greater than that of the active pattern 130a can be effectively prevented, and the layout efficiency of the lower pattern 111 and the vicinity of the active pattern 130a can be increased.

[0106] The lower pattern 111 is electrically connected to the pixel electrodes 191a, 191b and 191c through the capacitor electrode 175, and is also overlapped with the channel region 134a of the first transistor T1. Therefore, the current change rate is reduced in the saturation region of the voltage-current characteristic curve of the first transistor T1, so that the range of the region where the output current of the first transistor T1 is constant can be increased. Therefore, even when the source-drain voltage of the first transistor T1 changes, the output current of the first transistor T1 is maintained constant, thereby improving the output saturation characteristic. Therefore, the brightness deviation between pixels caused by the output current of the first transistor T1 is reduced, thereby improving the image quality.

[0107] Next, we will refer to Figure 6 and the above-described drawings illustrate alternative exemplary embodiments of the display device according to the invention.

[0108] Figure 6 is along with Figure 2 A cross-sectional view taken along line Va-Vb of the display device shown in corresponds to a cross-sectional view of an alternative exemplary embodiment of the display device.

[0109] In addition to another contact hole 81a being defined through the fourth insulating layer 182 to overlap the ohmic contact (contact member) 190d and the pixel electrode layer may further include an ohmic contact (contact member) 191d contacting the ohmic contact (contact member) 190d through the contact hole 81a, Figure 6 The exemplary embodiments shown in Figures 2 to 5The exemplary embodiments described above are substantially the same. In such an embodiment, the fifth insulating layer 350 and the emission layer 370 may overlap with the contact hole 82a provided on the ohmic contact (contact member) 191d. The common electrode 270 may be electrically connected to the common voltage line 170 to receive the common voltage by contacting the ohmic contact 191d via the contact hole 82a.

[0110] In the following, reference will be made to Figure 7 and Figure 8 Other optional exemplary embodiments of the display device according to the invention are described with reference to the drawings described above.

[0111] Figure 7 and Figure 8 They are shown along Figure 2 The cross-sectional view taken along line IIIa-IIIb shown in FIG. 1 corresponds to a cross-sectional view of another alternative exemplary embodiment of the display device.

[0112] In addition to further including a sixth insulating layer 122 disposed on the second conductive layer and a sixth conductive layer disposed between the sixth insulating layer 122 and the second conductive layer 160, Figure 7 The exemplary embodiments shown in Figures 2 to 5 The exemplary embodiments described above are basically the same.

[0113] In such an embodiment, the sixth insulating layer 122 may contact the upper surfaces of the conductive regions of the active patterns 130a, 130b, and 130c. Figure 7 As shown in FIG. 1 , a contact hole 61 a is defined through the sixth insulating layer 122 to overlap with the contact hole 61 of the second insulating layer 160 , and contact holes 62 a and 68 a are further defined through the sixth insulating layer 122 .

[0114] Such an embodiment of the display device may include a capacitor electrode 157 as part of the sixth conductive layer instead of the above-described capacitor electrode 175. The capacitor electrode 157 may be electrically connected to the lower pattern 111 through the contact hole 68a and may be electrically connected to the drain region 135a of the active pattern 130a through the contact hole 62a.

[0115] Similar to the capacitor electrode 175 described above, the capacitor electrode 157 may have a planar shape. The capacitor electrode 157 may overlap the corresponding driving gate electrode 155 with the sixth insulating layer 122 therebetween to form a capacitor Cst.

[0116] The sixth conductive layer may include a connection pattern 163. In one exemplary embodiment, for example, the sixth conductive layer includes the connection pattern 163 contacting the source region 133a of the active pattern 130a through the contact hole 61a, and the driving voltage line 172a contacts the connection pattern 163 through the contact hole 61 of the second insulating layer 160 to be electrically connected thereto, so that the driving voltage line 172a can be electrically connected to the source region 133a of the active pattern 130a.

[0117] In addition to further including a seventh insulating layer 180 disposed between the third conductive layer and the third insulating layer 181 and a seventh conductive layer disposed between the seventh insulating layer 180 and the third insulating layer 181, Figure 8 The exemplary embodiment of the display device shown in FIG. Figures 2 to 5 The exemplary embodiments described above are basically the same.

[0118] In a plan view, the seventh conductive layer may include a conductive pattern extending substantially parallel to patterns of data lines 171a, 171b, and 171c, driving voltage lines 172a, 172c, and 172d, a common voltage line 170, and an initialization voltage line 173 disposed in the underlying third conductive layer and electrically connected to the seventh conductive layer. In one exemplary embodiment, for example, referring to Figure 8 , the seventh conductive layer may include a conductive pattern 183 electrically connected to the driving voltage line 172a through the contact hole 80 of the seventh insulating layer 180. In a plan view, the conductive pattern 183 may have a planar shape substantially similar to a planar shape of the third conductive layer to which the conductive pattern 183 is connected. The conductive pattern 183 may reduce resistance by transmitting the same voltage as the voltage of the conductive layer connected thereto.

[0119] Alternatively, a portion of the data lines 171a, 171b and 171c, the driving voltage lines 172a, 172c and 172d, the common voltage line 170, the initialization voltage line 173, the capacitor electrode 175 and the connecting members 174, 176, 177 and 178 set in the third conductive layer may be set in the third conductive layer, and the remaining portions thereof may be set in the seventh conductive layer.

[0120] Next, we will refer to Fig. 9 and the above-described drawings describe another alternative exemplary embodiment of the display device according to the invention.

[0121] Fig. 9 is a plan view of a plurality of pixels of a display device according to an alternative exemplary embodiment of the invention.

[0122] In addition to the active pattern 130a and the active pattern 130c being separated or spaced apart from each other in each pixel PX1, PX2, or PX3, Fig. 9The exemplary embodiment of the display device shown in FIG. 1 may be used in conjunction with the above-described reference Figures 2 to 5 The exemplary embodiments described are essentially the same.

[0123] In such an embodiment, the lower pattern 111 overlaps the entire active pattern 130a in a plan view, thereby overlapping all of the source region 133a, the channel region 134a, and the drain region 135a of the first transistor T1. The edge of the lower pattern 111 may be disposed outside the edge of the active pattern 130a, and may have a shape that surrounds one active pattern 130a. In such an embodiment, the lower pattern 111 may overlap all edges of the active pattern 130a, and the active pattern 130a may not intersect with the edge of the lower pattern 111. In such an embodiment, none of the active patterns 130a, 130b, and 130c may intersect with the edge of the lower pattern 111. In such an embodiment, the edge of the lower pattern 111 may not overlap the active patterns 130a, 130b, and 130c of the active layer in a plan view, and may not intersect with the edges of any of the active patterns 130a, 130b, and 130c.

[0124] Therefore, in a plan view, since no active patterns 130a, 130b, and 130c intersect with the edge of the lower pattern 111, defects such as disconnection of the active pattern 130a, 130b, or 130c near the edge of the lower pattern 111 due to a relatively large step at the edge of the lower pattern 111 having a thickness greater than that of the active patterns 130a, 130b, and 130c can be effectively prevented.

[0125] The active patterns 130 b and 130 c may not overlap the lower pattern 111 .

[0126] The edge of the lower pattern 111 may cross the space between the active patterns 130a and 130b that are spaced apart from each other. In such an embodiment, the edge of the lower pattern 111 may be disposed between the active patterns 130a and 130b that are spaced apart from each other.

[0127] The drain region 135a of the active pattern 130a and the source region 133c of the active pattern 130c, which are separated or isolated from each other, may be electrically connected to each other through a conductive layer other than the first conductive layer and the second conductive layer. In such an embodiment, the drain region 135a of the active pattern 130a and the source region 133c of the active pattern 130c, which are separated or isolated from each other, are electrically connected to each other through the contact holes 62 and 62c and the protrusion 175a of the capacitor electrode 175 disposed in the third conductive layer.

[0128] In such an embodiment, the third gate electrode 154c may protrude above the second scan line 152 to extend in the second direction DR2. In such an embodiment, the third gate electrode 154c may be directly connected to the second scan line 152.

[0129] Next, we will refer to Fig.10 and Fig.11 and the drawings described above describe exemplary embodiments of a display device according to the invention.

[0130] Fig.10 is a plan view of a portion of one pixel of a display device according to an exemplary embodiment of the invention, Fig.11 It is along Fig.10 A cross-sectional view taken along line XIa-XIb shown in FIG.

[0131] exist Fig.10 and Fig.11 The same or identical elements have been used in the above description. Figures 2 to 5 1 and 2 are denoted by the same reference numerals as those of the exemplary embodiments of the display device shown in FIG. In such an embodiment, the functions of the corresponding constituent elements may be the same as each other, but the planar or cross-sectional structures may be different from each other.

[0132] Fig.10 and Fig.11 Such an embodiment of the display device shown in FIG may include a first conductive layer, a buffer layer 120 , an active layer, a first insulating layer 121 , a second conductive layer, a sixth insulating layer 122 , a sixth conductive layer, and a second insulating layer 160 sequentially stacked on one another on a substrate 110 .

[0133] The first conductive layer may include a lower pattern 111 .

[0134] The active layer may include a plurality of active patterns 130d, 130e, and 130f disposed at one pixel. The plurality of active patterns 130d, 130e, and 130f may include channel regions 134a, 134b, and 134c, source regions 133a, 133b, and 133c, and drain regions 135a, 135b, and 135c forming each channel of the transistors T1, T2, and T3. The active patterns 130d, 130e, and 130f may be spaced apart from each other.

[0135] The second conductive layer may include a first scan line 151 and a second scan line 152, a lateral driving voltage line 156 for transmitting a driving voltage, and a driving gate electrode 155. The first scan line 151 may include a second gate electrode 154b intersecting with the active pattern 130e and overlapping with the channel region 134b of the active pattern 130e, the second scan line 152 may include a third gate electrode 154c intersecting with the active pattern 130f and overlapping with the channel region 134c of the active pattern 130f, and the driving gate electrode 155 may include a first gate electrode 154a intersecting with the active pattern 130d and overlapping with the channel region 134a of the active pattern 130d. The driving gate electrode 155 may be disposed between the first scan line 151 and the second scan line 152 in a plan view.

[0136] The source region 133a, the channel region 134a, the drain region 135a and the first gate electrode 154a of the active pattern 130d can jointly define a first transistor T1, the source region 133b, the channel region 134b, the drain region 135b and the second gate electrode 154b of the active pattern 130e can jointly define a second transistor T2, and the source region 133c, the channel region 134c, the drain region 135c and the third gate electrode 154c of the active pattern 130f can jointly define a third transistor T3.

[0137] The sixth conductive layer may include a lateral initialization voltage line 153a, a plurality of connection members 153b, 155b, and 156a, and a capacitor electrode 157a. The capacitor electrode 157a may include a protrusion 152a protruding toward the active pattern 130f.

[0138] The lateral initialization voltage line 153 a may be electrically connected to the drain region 135 c of the active pattern 130 f through the contact hole 53 .

[0139] The connection member 153 b may be electrically connected to the source region 133 b of the active pattern 130 e through the contact hole 55 to transmit a data voltage.

[0140] The connection member 155b may be electrically connected to the driving gate electrode 155 through the contact hole 54a and may be electrically connected to the drain region 135b of the active pattern 130e through the contact hole 54b. Therefore, the driving gate electrode 155 may be electrically connected to the drain region 135b of the active pattern 130e.

[0141] The connection member 156a may be electrically connected to the lateral driving voltage line 156 through the contact hole 51a and to the source region 133a of the active pattern 130d through the contact hole 51b. Therefore, the source region 133a of the active pattern 130d may be electrically connected to the lateral driving voltage line 156 to transmit a driving voltage.

[0142] The capacitor electrode 157a may be electrically connected to the source region 133c of the active pattern 130f through the contact hole 52a, and may be electrically connected to the drain region 135a of the active pattern 130d through the contact hole 52b. Therefore, the source region 133c of the active pattern 130f and the drain region 135a of the active pattern 130d may be electrically connected to each other. The capacitor electrode 157a may be electrically connected to the lower pattern 111 through the contact hole 53b.

[0143] The capacitor electrode 157 a overlaps the driving gate electrode 155 to form a capacitor Cst.

[0144] In such an embodiment, the edge of the lower pattern 111 is disposed outside the edge of the active pattern 130d and may have a shape surrounding the active pattern 130d. In such an embodiment, the lower pattern 111 may overlap all edges of the active pattern 130d, and the active pattern 130d may not intersect with the edge of the lower pattern 111. In such an embodiment, none of the active patterns 130d, 130e, and 130f may intersect with the edge of the lower pattern 111. In such an embodiment, the edge of the lower pattern 111 may not overlap with the active patterns 130d, 130e, and 130f of the active layer in a plan view, and may not overlap with the edges of any of the active patterns 130d, 130e, and 130f.

[0145] In such an embodiment, since no active patterns 130d, 130e, and 130f intersect the edge of the lower pattern 111, defects such as disconnection of the active patterns 130d, 130e, and 130f near the edge of the lower pattern 111 due to a relatively large step at the edge of the lower pattern 111 having a thickness greater than that of the active patterns 130d, 130e, and 130f can be effectively prevented.

[0146] The drain region 135a of the active pattern 130d and the source region 133c of the active pattern 130f, which are separated from each other, may be electrically connected to each other through a conductive layer other than the first conductive layer and the second conductive layer. In such an embodiment, the drain region 135a of the active pattern 130d and the source region 133c of the active pattern 130f, which are separated from each other, may be electrically connected to each other through the capacitor electrode 157a disposed in the sixth conductive layer and through the contact holes 52a and 52b.

[0147] Next, we will refer to Figure 12 to Figure 14 and the above-described drawings to describe alternative exemplary embodiments of the display device according to the invention.

[0148] Fig.12 is a plan view of a plurality of pixels of a display device according to an alternative exemplary embodiment of the invention, Fig.13is a plan view of a pixel electrode layer of a display device according to an exemplary embodiment of the invention, Fig.14 It is along Fig.12 A cross-sectional view taken along line XIVa-XIVb is shown in FIG.

[0149] In addition to the detailed shape and connection method of each of the constituent elements, Figure 12 to Figure 14 The exemplary embodiment of the display device shown in FIG. 1 has substantially the same connection relationship and stacking structure of constituent elements as those of the exemplary embodiment of the display device described above. Figure 12 to Figure 14 The same or identical elements shown in FIG. 1 have been used to describe Figures 2 to 5 The exemplary embodiments of the display device shown in FIG. 1 are denoted by the same reference numerals as the reference numerals, and any repeated detailed description thereof will be omitted or simplified hereinafter.

[0150] Reference Fig.12 In an exemplary embodiment, a plurality of repeated pixels PX4, PX5, and PX6 of one group (or pixel unit) may be arranged along the second direction DR2, and the pixel electrodes 191a, 191b, and 191c respectively corresponding to the pixels PX4, PX5, and PX6 may be arranged as shown in FIG. Fig.13 However, the structures of the pixels PX4, PX5, and PX6 and the corresponding pixel electrodes 191a, 191b, and 191c are not limited thereto.

[0151] Reference Fig.12 , a plurality of data lines 171 a , 171 b , and 171 c , a driving voltage line 172 , and an initialization voltage line 173 may be disposed between two adjacent common voltage lines 170 .

[0152] In a plan view, the first scan line 151 and the second scan line 152 may be disposed above and below a group of the plurality of pixels PX4 , PX5 , and PX6 , respectively.

[0153] The first conductive layer described above may include a plurality of lower patterns 111 a , and the lower patterns 111 a may be disposed in each of the pixels PX4 , PX5 , and PX6 . The first conductive layer may further include a transverse common voltage line 170 a extending in the first direction DR1 .

[0154] A plurality of active patterns 130g, 130h, and 130j disposed in the active layer may include channel regions 134a, 134b, and 134c, source regions 133a, 133b, and 133c, and drain regions 135a, 135b, and 135c that form channels of transistors T1, T2, and T3, respectively. In such an embodiment, the active patterns 130g, 130h, and 130j in each of the pixels PX4, PX5, and PX6 may be separated from each other.

[0155] The second conductive layer may include a first scan line 151, a second scan line 152, a driving gate electrode 155, a second gate electrode 154b, and a third gate electrode 154c. Each of the first scan line 151 and the second scan line 152 may extend in the first direction DR1.

[0156] Each driving gate electrode 155 may be disposed corresponding to each pixel PX4 , PX5 , or PX6 .

[0157] The plurality of second gate electrodes 154 b corresponding to the plurality of pixels PX4 , PX5 , and PX6 may be connected to each other and extend substantially toward the second scan line 152 in a shape extending in the second direction DR2 .

[0158] The plurality of third gate electrodes 154 c corresponding to the plurality of pixels PX4 , PX5 , and PX6 may be connected to each other and extend substantially toward the first scan line 151 in a shape extending in the second direction DR2 .

[0159] The driving gate electrode 155 disposed at each pixel PX4, PX5 or PX6 may include a first gate electrode 154a having a shape protruding upward or downward. The first gate electrode 154a intersects with the active pattern 130g and overlaps with the channel region 134a of the active pattern 130g. The second gate electrode 154b intersects with the active pattern 130h and overlaps with the channel region 134b of the active pattern 130h. The third gate electrode 154c intersects with the active pattern 130j and overlaps with the channel region 134c of the active pattern 130j.

[0160] The third conductive layer may include a plurality of data lines 171 a , 171 b , and 171 c , a driving voltage line 172 , a common voltage line 170 , an initialization voltage line 173 , a capacitor electrode 175 , and a plurality of connection members 178 .

[0161] Each of the data lines 171 a , 171 b , and 171 c , the driving voltage line 172 , the common voltage line 170 , and the initialization voltage line 173 may extend substantially in the second direction DR2 to intersect the first and second scan lines 151 and 152 .

[0162] Each data line 171a, 171b or 171c is electrically connected to the source region 133b of the active pattern 130h via the contact hole 64. The driving voltage line 172 is electrically connected to the source region 133a of the active pattern 130g through the contact hole 61. The initialization voltage line 173 is electrically connected to the drain region 135c of the active pattern 130j via the contact hole 63a. The contact holes 61, 63a and 64 may be defined or formed in the second insulating layer 160.

[0163] The capacitor electrode 175 may be disposed in each pixel PX4, PX5, or PX6 and may be disposed between the driving voltage line 172 and the data line 171c in a plan view. The capacitor electrode 175 may overlap the corresponding driving gate electrode 155, and the second insulating layer 160 is located between the capacitor electrode 175 and the corresponding driving gate electrode 155 to form a capacitor Cst.

[0164] The capacitor electrode 175 is electrically connected to the drain region 135a of the active pattern 130g through the contact hole 62 of the second insulating layer 160, and is electrically connected to the source region 133c of the active pattern 130j through the contact hole 63b of the second insulating layer 160 and the first insulating layer 121. In such an embodiment, the capacitor electrode 175 is electrically connected to the lower pattern 111a through the contact hole 68 of the second insulating layer 160, the first insulating layer 121, and the buffer layer 120. The opening 55a is defined through the driving gate electrode 155 to overlap with the contact hole 62 for contact between the capacitor electrode 175 and the drain region 135a of the active pattern 130g in such a manner that the driving gate electrode 155 surrounds the contact hole 62.

[0165] In each pixel PX4, PX5 or PX6, the connection member 178 is electrically connected to the drain region 135b of the active pattern 130h through the contact hole 65, and is electrically connected to the protrusion 155a of the driving gate electrode 155 through the contact hole 66, so that the drain region 135b of the active pattern 130h and the protrusion 155a of the driving gate electrode 155 can be electrically connected to each other.

[0166] In such an embodiment, the display device may include, for example, Figure 8 2 and 3. The seventh insulating layer 180 and the seventh conductive layer 180 are disposed between the third conductive layer and the third insulating layer 181 in the exemplary embodiment shown in FIG.

[0167] Reference Fig.12 and Fig.14 The seventh conductive layer may include a conductive pattern electrically connected to the third conductive layer and having a planar shape similar to the planar shape of the conductive pattern of the third conductive layer (such as data lines 171a, 171b and 171c, driving voltage lines 172, common voltage lines 170, initialization voltage lines 173 and capacitor electrodes 175 set in the third conductive layer below).

[0168] In an exemplary embodiment, for example, the data lines 171a, 171b and 171c are electrically connected to the corresponding conductive patterns set in the seventh conductive layer through the contact holes 74a, 75a and 76a, respectively, the driving voltage line 172 is electrically connected to the corresponding conductive pattern 183a set in the seventh conductive layer through the contact hole 71a, the common voltage line 170 is electrically connected to the corresponding conductive pattern set in the seventh conductive layer through the contact hole 72a, the initialization voltage line 173 is electrically connected to the corresponding conductive pattern set in the seventh conductive layer through the contact hole 73a, and the capacitor electrode 175 is electrically connected to the corresponding conductive pattern 183b set in the seventh conductive layer through the contact hole 77a.

[0169] The conductive pattern of the seventh conductive layer transmits the same voltage as that of the connected third conductive layer, thereby reducing resistance.

[0170] A contact hole 83d is defined through the third insulating layer 181 to overlap with the conductive pattern 183b of the seventh conductive layer connected to the capacitor electrode 175 , and a contact hole 81d is defined through the third insulating layer 181 to overlap with the conductive pattern of the seventh conductive layer connected to the common voltage line 170 .

[0171] In such an embodiment, the display device may further include the fourth conductive layer described above.

[0172] A plurality of pixel electrodes 191a, 191b, and 191c disposed in the pixel electrode layer of the fifth conductive layer and corresponding to each of the pixels PX4, PX5, and PX6 may be electrically connected to a conductive pattern 183b of the seventh conductive layer connected to the capacitor electrode 175 through a contact hole 83d defined in the fourth insulating layer 182. Each pixel electrode 191a, 191b, or 191c is electrically connected to the drain region 135a of the first transistor T1 via the capacitor electrode 175, thereby receiving a voltage from the first transistor T1.

[0173] The pixel electrode layer may further include an ohmic contact (contact member) 191d connected to the common voltage line 170 similar to the exemplary embodiment described above. The common electrode 270 is electrically connected to the ohmic contact (contact member) 191d through a contact hole 82d defined in the fifth insulating layer 350 and the emission layer 370, thereby receiving a common voltage from the common voltage line 170.

[0174] The common voltage line 170 may be electrically connected to the lateral common voltage line 170 a through the contact hole 70 .

[0175] The second conductive layer may further include a conductive pattern 150a overlapping the common voltage line 170 and conductive patterns 150b and 150c overlapping the driving voltage line 172. In such an embodiment, the conductive pattern 150a is electrically connected to the common voltage line 170 through a plurality of contact holes 60a of the second insulating layer 160, thereby reducing resistance. The conductive patterns 150b and 150c are electrically connected to the driving voltage line 172 through a plurality of contact holes 60b and 60c of the second insulating layer 160. Alternatively, the conductive patterns 150a, 150b, and 150c may be omitted.

[0176] In an exemplary embodiment, the edge of the lower pattern 111a may be disposed outside the edge of the active pattern 130g and may have a shape surrounding the active pattern 130g. In such an embodiment, no active pattern 130g, 130h, or 130j may intersect with the edge of the lower pattern 111a. Therefore, the edge of the lower pattern 111a may not intersect with the edge of any active pattern 130g, 130h, and 130j without overlapping the active patterns 130g, 130h, and 130j of the active layer in a plan view.

[0177] Therefore, in a plan view, since no active pattern 130g, 130h, or 130j intersects with the edge of the lower pattern 111a, defects such as disconnection of the active patterns 130g, 130h, and 130j near the edge of the lower pattern 111a due to a relatively large step at the edge of the lower pattern 111 having a thickness greater than that of the active patterns 130g, 130h, and 130j can be effectively prevented.

[0178] The drain region 135a of the active pattern 130g and the source region 133c of the active pattern 130j, which are separated from each other, may be electrically connected to each other through a conductive layer other than the first conductive layer and the second conductive layer. In one exemplary embodiment, for example, the drain region 135a of the active pattern 130g and the source region 133c of the active pattern 130j, which are separated from each other, may be electrically connected to each other through the contact holes 62 and 63b and the capacitor electrode 175 disposed in the third conductive layer.

[0179] While the invention has been described in connection with what are presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, comprising: substrate; A first conductive layer including a lower pattern disposed on the substrate; an active layer, comprising a first active pattern disposed on the first conductive layer, the first active pattern comprising a first channel region, a first source region and a first drain region; as well as a second conductive layer including a first gate electrode disposed on the active layer, wherein the first gate electrode overlaps the first channel region included in the first active pattern, When viewed in a plan view in a thickness direction of the substrate, the lower pattern overlaps the first active pattern such that the entire first active pattern is disposed inside an outer edge of the lower pattern.

2. The display device according to claim 1, wherein: The active layer further includes a second active pattern spaced apart from the first active pattern, and The second active pattern does not overlap the lower pattern.

3. The display device according to claim 2, further comprising: a third conductive layer disposed in a layer different from the first conductive layer and the second conductive layer, Wherein, the second active pattern includes a second channel region, a second source region and a second drain region, and The first drain region and the second source region are electrically connected to each other through the third conductive layer.

4. The display device according to claim 3, further comprising: a first insulating layer, disposed on the second conductive layer, wherein the third conductive layer comprises a capacitor electrode disposed on the first insulating layer, and The capacitor electrode is electrically connected to the first drain region and the second source region.

5. The display device according to claim 4, wherein: The capacitor electrode overlaps the first gate electrode to form a capacitor.

6. The display device according to claim 5, wherein: The capacitor electrode is electrically connected to the lower pattern.

7. The display device according to claim 6, further comprising: A second insulating layer, disposed on the third conductive layer; a pixel electrode layer, comprising a pixel electrode disposed on the second insulating layer; as well as an emission layer, disposed on the pixel electrode, Wherein, the pixel electrode is electrically connected to the capacitor electrode.

8. The display device according to claim 7, wherein: The active layer further includes a third active pattern spaced apart from the first active pattern and the second active pattern, The third conductive layer also includes a driving voltage line and a data line. The first source region of the first active pattern is electrically connected to the driving voltage line, and The third active pattern includes a third source region electrically connected to the data line.

9. The display device according to claim 7, further comprising: a fourth conductive layer, disposed between the second insulating layer and the pixel electrode layer, and The fourth conductive layer further includes a driving voltage line and a data line.

10. The display device according to claim 7, wherein: The third conductive layer also includes a driving voltage line and a data line.

11. The display device according to claim 1, wherein: The active layer further includes a second active pattern connected to the first active pattern.

12. A display device, comprising: A first conductive layer including a conductive pattern; an active layer, comprising a first active pattern and a second active pattern; a second conductive layer including a first gate electrode; as well as a third conductive layer including capacitor electrodes, wherein the first active pattern comprises a first channel region, a first source region and a first drain region, wherein the first channel region overlaps the first gate electrode, The second active pattern includes a second channel region, a second source region, and a second drain region, When viewed from a plan view in the thickness direction of the conductive pattern, the edge of the conductive pattern surrounds the edge of the entire first active pattern, The conductive pattern overlaps the entire first active pattern and does not overlap the second active pattern, and The capacitor electrode is electrically connected to the first drain region and the second source region.

13. The display device according to claim 12, wherein: The capacitor electrode is electrically connected to the conductive pattern.

14. The display device according to claim 13, wherein: The capacitor electrode overlaps the first gate electrode to form a capacitor.

15. The display device according to claim 14, further comprising: a pixel electrode electrically connected to the capacitor electrode; Common electrode, transmitting common voltage; as well as The emission layer is arranged between the pixel electrode and the common electrode.

16. The display device according to claim 15, further comprising: driving voltage lines, data lines, first scanning lines and second scanning lines, The active layer further includes a third active pattern spaced apart from the first active pattern and the second active pattern, The first source region of the first active pattern is electrically connected to the driving voltage line, The third active pattern includes a third source region electrically connected to the data line, The first scan line includes a second gate electrode overlapping the second channel region of the second active pattern, and The second scan line includes a third gate electrode overlapping a third channel region of the third active pattern.

17. The display device according to claim 16, wherein: The third conductive layer is provided in a different layer from the first conductive layer and the second conductive layer.

18. A display device, comprising: A first conductive layer including a conductive pattern; and an active layer including a first active pattern and a second active pattern separated from each other, wherein the first active pattern includes a first channel region, a first source region, and a first drain region, Wherein, when viewed from a plan view in a thickness direction of the conductive pattern, the conductive pattern overlaps with the first active pattern and does not overlap with the second active pattern so that the entire first active pattern is disposed inside an outer edge of the conductive pattern.

19. The display device according to claim 18, further comprising: a second conductive layer including a first gate electrode; as well as a third conductive layer including capacitor electrodes, Wherein, the capacitor electrode is electrically connected to the first active pattern and the second active pattern.

20. The display device according to claim 19, wherein: The capacitor electrode is electrically connected to the conductive pattern.

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