Surge current limiter

Abstract

This invention provides circuitry (e.g., boost DC-DC converter circuitry) and methods for limiting excessive current in circuits using very low-ohm FETs (VLOFETs) in circuit paths subjected to startup inrush currents. Embodiments include a current mirror driver circuit that can be coupled to the gate of the VLOFET to form a current mirror that limits the current flowing through the VLOFET. The current mirror driver circuit provides pulsed operation, such that the coupled VLOFET continues to switch between a cutoff state and a current-limiting mode, particularly during the startup period. By combining the current mirror driver circuit and the VLOFET in circuit paths subjected to startup inrush currents, the inrush current can be regulated to an acceptable level. In particular, no additional impedance is required to limit the inrush current in circuit paths subjected to startup inrush currents, thus avoiding efficiency losses.

Description

Technical Field

[0001] This invention relates to electronic circuits, and more particularly to surge current limiter circuits and DC-DC converters. Background Technology

[0002] Many electronic products, especially battery-powered mobile computing and / or communication products (e.g., notebook computers, ultrabook computers, and tablet devices), require multiple voltage levels. For example, radio transmitter power amplifiers may require relatively high voltages (e.g., 12V or higher), while logic circuits may require relatively low voltage levels (e.g., 1V–2V). Other circuits may require medium voltage levels (e.g., 2.5V, 3.3V, or 5V).

[0003] DC-to-DC converters are typically used to generate lower or higher DC voltages from a DC power supply. DC-to-DC converters that generate lower voltage levels from higher DC power supplies are often called buck converters or step-down converters, named so because V... OUT Less than V IN Therefore, this converter "steps down" the input voltage. A DC-to-DC converter that produces a voltage level higher than the DC supply is often called a boost converter or step-up converter because V... OUT Greater than V IN .

[0004] There are many options for creating buck and / or boost converters, including inductive, capacitive, and / or linear regulator circuits (including low dropout (LDO) regulators), where size and efficiency are key differences between these options. For example, various configurations of DC-DC converters (including ladder, Dickson, series-parallel, Fibonacci, and Doubler configurations) rely on the alternating arrangement of switching elements to propagate charge and transfer energy between the converter terminals. The energy losses associated with charge propagation determine the converter's efficiency.

[0005] Some buck DC-DC converters have become extremely efficient, achieving efficiencies of 95%–98% through optimization of various circuit elements and configurations. One circuit element contributing to such high efficiency is the extremely low ohmic (VLO) switch, which typically has a total on-resistance R of less than 10 milliohms, as low as 1 milliohm (and in some cases even lower). ON A field-effect transistor (FET) switching composite. To achieve such a low R... ONA VLO FET switching complex (or "VLOFET") typically comprises hundreds to thousands of FETs coupled in parallel but switched as a single unit. This large number of devices results in a fairly large effective total gate width, and the on-resistance is inversely proportional to the gate width.

[0006] Due to its low R ON A VLOFET offers virtually no impedance to high currents. In many buck DC-DC converters, this characteristic is generally not a significant problem for high startup inrush currents because the converter configuration and other circuitry are designed to limit them. However, in many boost DC-DC converter circuits, using a VLOFET will be problematic because the converter configuration and other components do not limit the startup inrush current. Therefore, the startup inrush current can reach levels capable of damaging or destroying the VLOFET and / or other circuitry components, including those connected to the power supply (e.g., the battery and its associated circuitry).

[0007] For example, Figure 1 This is a schematic diagram of a prior art boost DC-DC converter circuit 100. The circuit shown includes a portion or unit of a Dickson 3x boost DC-DC converter; typically, a second similar portion or unit (not shown) having complementary clock phases for corresponding switches S1-S7 is coupled to a shared output storage capacitor C. S Node 102.

[0008] In the example shown, circuit 100 includes three switches S1, S2, and S3 connected in series. These three switches are series-coupled to a first parallel branch including two switches S4 and S6 connected in series, and a second parallel branch including two switches S5 and S7 connected in series. Each switch may include, for example, one or more FETs, and the one or more FETs include one or more MOSFETs; Figure 1 In this design, both NFETs (switches S3-S7) and PFETs (switches S1) are used. Each switch is coupled to one of two complementary clock phases P1 or P2, as shown in parentheses for each switch S1-S7. Each FET switch S1-S7 is schematically shown to include corresponding parasitic diodes D1-D7 between the body and drain of the FET (in this application, "clock phase" refers to a clock signal such as phase P1 or P2, rather than a high-low offset of a single clock signal).

[0009] A first capacitor C1 is coupled between the first upper pair, i.e., alternating phase switches S1(P1) and S2(P2), and the first branch pair, i.e., alternating phase switches S4(P1) and S6(P2). A second capacitor C2 is coupled between the second upper pair, i.e., alternating phase switches S2(P2) and S3(P1), and the second branch pair, i.e., alternating phase switches S5(P2) and S7(P1). In one embodiment, the capacitors have the same value, approximately 10 microfarads. The input voltage V to be amplified by three times at node 102 is coupled through a relatively small inductor L (e.g., approximately 10 nH). IN Its output is a voltage Vx, which, as shown, is coupled between three series-connected switches S1-S3 and the first parallel branch (two series-connected switches S4 and S6) and the second parallel branch (two series-connected switches S5 and S7). During the startup period, after capacitors C1 and C2 are charged, inductor L limits the current flowing into the DC-DC converter circuit 100.

[0010] In the illustrated configuration, after the startup period, the boost DC-to-DC converter circuit 100 operates in an adiabatic mode by limiting current variations caused by charge transfer between capacitors C1 and C2 during alternating operation phases, using non-capacitive elements such as one or more inductors and / or magnetic elements. The switches S1-S7 and supporting circuitry (e.g., a clock phase generation circuit, not shown) shown by the dashed box 104 can be fabricated as "on-chip" components of an integrated circuit (IC). Capacitors C1 and C2 can also be fabricated on-chip, but off-chip capacitors (such as...) are typically used. Figure 1 (As shown). For example, further details regarding the configuration and operation of the Dickson converter can be found, in particular, in U.S. Patent Application No. 15 / 920,327, filed March 13, 2018, entitled "Selectable Conversion Ratio DC-DC Converter". Further information regarding adiabatic DC-DC conversion circuits can be found, for example, in U.S. Patent No. 9,041,459, published May 25, 2015, entitled "Partial Adiabatic Conversion", and in U.S. Patent No. 9,882,471, published January 30, 2018, entitled "DC-DC Converter with Modular Stages".

[0011] If a VLOFET is not used in the circuit path subjected to startup inrush current, then Figure 1The illustrated boost DC-DC converter circuit 100 works well because there is sufficient circuit path resistance (including that of a conventional FET) to limit the current. However, due to this circuit path resistance, such a circuit will have lower efficiency. Attempting to improve efficiency by replacing a conventional FET with a low-resistance VLOFET will cause the following problem: if a VLOFET is used in a circuit path subjected to startup inrush current, the VLOFET will essentially present no resistance to the current.

[0012] For example, in Figure 1 In the boost DC-DC converter circuit 100 shown, a startup inrush current occurs during a relatively short period of time when capacitors C1 and C2 are charging during circuit startup. Once the circuit is running, capacitors C1 and C2 are pre-charged in each clock cycle, and the inrush current stops, thus achieving an operating state or balance. When V IN When a voltage is applied and timing begins for the first time, switch S7 is turned on during clock phase P1, allowing current to flow from V... IN The current path to ground flows through the body-drain diodes D3 and D7 of the FET switches S3 and S7 (switch S3 will not conduct because there is not a sufficiently high voltage to turn it on, but diode D3 conducts current). The body-drain diodes D1-D7 switch the charge in circuit 100 until there is sufficient voltage to initiate normal controlled switching through the FET. Therefore, diodes D1-D7 initiate charge pumping operation, but as the voltage increases, switches S1-S7 begin to take over. The diodes have a voltage drop of approximately 0.7V, so they will decrease in efficiency until the switches are fully activated, which occurs when circuit 100 has stabilized and reached the desired output voltage.

[0013] Using a VLOFET for switches S1-S7 will cause a very significant change from V IN The inrush current to ground. More specifically, during clock phase P1, with switch S7 on and diode D3 conducting current, the base plate of capacitor C2 is effectively grounded through VLOFET switch S7, and VLOFET switch S3 allows a substantially unrestricted and unregulated current to flow through diode D3 to the top plate of capacitor C2. Switches S1 and S6 exhibit similar issues, but the startup inrush current is slightly lower. For example, during startup, switch S6 will be on and diodes D3 and D2 will allow charge to flow onto capacitor C1.

[0014] Figure 2 This demonstrates the use of VLOFETs for all switches. Figure 1The graph 200 shows the startup inrush current through inductor L over time in a modeled circuit of the type shown. When the output stabilizes before the load appears, the inrush current reaches 160 amps within microseconds, then drops to tens of milliamps at approximately 80 μs. In this example, the load appears at approximately 100 μs, at which point the operating current increases to approximately 9 amps. As an illustration of the consequences of such a high inrush current, in battery-powered circuits, a pull-up current of 160 amps, even for microseconds, can damage the battery and other circuitry in the current path (including the boost DC-DC converter circuit 100). This high startup inrush current problem when using VLOFETs is not limited to... Figure 1 The VLOFET is present in the boost DC-DC converter circuit shown, and also in other types of boost DC-DC converter circuits that use VLOFETs in circuit paths subjected to startup inrush current. More generally, high startup inrush currents may occur in many types of circuits that use VLOFETs in startup current paths.

[0015] Such startup inrush current can be limited by increasing the size of the inductor L (thus limiting the rate of change of current through the inductor), by using a relatively high-resistance FET (e.g., 1 to 2 ohms) somewhere in the current path (e.g., the current path of switch S7), or by including a resistor somewhere in the current path (e.g., between switch S7 and ground). However, such methods reduce the efficiency of the circuit, essentially offsetting the efficiency benefits initially sought by using a VLOFET. For example, a sufficiently large inductor negatively impacts circuit area, height, cost, and performance. Furthermore, process-voltage-temperature (PVT) variations in such components reduce the average efficiency of mass-producing such circuits and cause other known problems.

[0016] Therefore, there is a need for circuits and methods for limiting the startup inrush current in circuits (e.g., boost DC-DC converter circuits) that use VLOFETs in circuit paths subjected to startup inrush current. This invention addresses this need and provides additional benefits. Summary of the Invention

[0017] This invention includes circuitry and methods for limiting startup inrush current in circuits (e.g., boost DC-DC converter circuits) that use extremely low-ohm FETs (VLOFETs) in circuit paths subjected to startup inrush current. Embodiments of the invention include a current mirror driver circuit that can be coupled to the gate of the VLOFET to form a current mirror that limits the current flowing through the VLOFET. The current mirror driver circuit provides pulsed operation such that the coupled VLOFET continues to switch between a cutoff state and a current-limiting mode during the startup period.

[0018] By combining a current mirror driver circuit and a VLOFET in the circuit path subjected to startup inrush current, the inrush current can be regulated to an acceptable level. In particular, no additional impedance is required in the circuit path subjected to startup inrush current to limit the inrush current, thus avoiding efficiency losses. This implementation can be achieved using N-type FETs, P-type FETs, or a combination of both (especially CMOS FETs).

[0019] Although various embodiments have been described in the context of boost DC-DC converter circuits, embodiments of the present invention can be used more generally in circuits using VLOFETs that are subjected to startup inrush current.

[0020] Details of one or more embodiments of the invention are set forth in the accompanying drawings and the following description. Other features, objects, and advantages of the invention will become apparent from the specification, the drawings, and the claims. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a boost DC-DC converter circuit in the prior art.

[0022] Figure 2 This shows the use of VLOFETs for all switches. Figure 1 The graph 200 shows the startup surge current through inductor L over time in a modeled circuit of the type shown.

[0023] Figure 3 This is a schematic diagram of a surge current limiting circuit for a boost DC-DC converter circuit (not shown in its entirety) that uses a VLOFET as a switch.

[0024] Figure 4A This is a schematic diagram of a current mirror including a VLOFET and a current mirror driver circuit of the first embodiment.

[0025] Figure 4B This is a schematic diagram of a current mirror driver circuit including VLOFET and PFET implementations.

[0026] Figure 5 This is a schematic diagram of a current mirror including a VLOFET and a current mirror driver circuit according to the second embodiment.

[0027] Figure 6 This is a schematic diagram of a current mirror including a VLOFET and a current mirror driver circuit according to the third embodiment.

[0028] Figure 7 This is a schematic diagram of a current mirror including a VLOFET and a current mirror driver circuit according to the fourth embodiment.

[0029] Figure 8 This is a flowchart of the first method for limiting inrush current through a VLOFET.

[0030] Figure 9 This is a flowchart of a first method for limiting inrush current through a boost DC-DC converter circuit with at least one VLOFET.

[0031] In the various figures, similar reference numerals and designations indicate similar elements. Detailed Implementation

[0032] This invention includes circuitry and methods for limiting startup inrush current in circuits (e.g., boost DC-DC converter circuits) using very low-ohm FETs (VLOFETs) in circuit paths subjected to startup inrush current. Embodiments of the invention include a current mirror driver circuit that can be coupled to the gate of the VLOFET to form a current mirror that limits the current flowing through the VLOFET. By combining the current mirror driver circuit and the VLOFET in circuit paths subjected to startup inrush current, the inrush current can be regulated to an acceptable level.

[0033] In particular, no additional impedance is required in the circuit path subjected to startup inrush current to limit the inrush current, thus avoiding efficiency losses. This can be implemented using N-type FETs, P-type FETs, or a combination of both (including CMOS FETs).

[0034] Although various embodiments have been described in the context of boost DC-DC converter circuits, embodiments of the present invention can be used more generally in circuits using VLOFETs that are subjected to startup inrush current.

[0035] General purpose surge current limiter circuit

[0036] Figure 3 This is a schematic diagram of a surge current limiting circuit 300 for a boost DC-DC converter circuit (not shown in its entirety) that uses a VLOFET as a switch. The boost DC-DC converter circuit can be... Figure 1 The capacitor-based charge pump shown is a type of Dickson boost DC-DC converter circuit (i.e., a Dickson boost DC-DC converter circuit with a multiplication factor of 3), but it can also be any boost DC-DC converter circuit using a VLOFET that withstands startup inrush current.

[0037] exist Figure 3In the diagram, a single VLOFET 302 is shown as comprising multiple FETs M1-Mn connected in parallel, all of whose gates are interconnected; correspondingly, FETs M1-Mn serve as cell switching states. Thus, VLOFET 302 behaves like a single FET with a single control gate. Each individual FET M1-Mn includes a corresponding body-drain diode D1-Dn. The number n of individual FETs M1-Mn can reach hundreds or thousands or more, and is application-specific. Although an N-type FET is schematically shown, a VLOFET 302 including P-type FETs can also be used, where the polarity of some circuitry is appropriately altered (see also below). Figure 4B VLOFET 302 can be used, for example, for... Figure 1 The boost DC-DC converter circuit 100 uses switches S1-S7 to provide high efficiency.

[0038] In this example, the gates of FETs M1-Mn are typically connected to one of two complementary clock phases, P1 or P2, for normal post-startup operation. However, during the overall startup of the converter circuit, the gates of FETs M1-Mn are connected to the current mirror driver circuit 304. The current mirror driver circuit 304 is coupled to the general-purpose circuit supply voltage V. IN The source has one of two complementary clock phases, P1 or P2, which correspond to the clock phase (not shown) coupled to the connected VLOFET 302. The current mirror driver circuit can also be connected to multiple different FETs used in different locations, as long as the multiple different FETs have the same source voltage and share the same clock phase.

[0039] The combination of current mirror driver circuit 304 and VLOFET 302 includes a current mirror. As is known in the art, a current mirror is a circuit designed to control the current in another active device (VLOFET 302) by replicating a reference current (or by replicating a fraction or multiple of the reference current proportional to the size of the constituent devices) through an active device (within current mirror driver circuit 304). The reference current can be amplified proportionally to the number of devices, provided the gate-source voltages of the active devices are the same. An important characteristic of a current mirror is that the output current through the current-controlled active device remains substantially constant and independent of the load. Therefore, by configuring at least some of the VLOFETs 302 in the circuit path subjected to startup inrush current as current mirrors, such inrush currents can be regulated to acceptable levels.

[0040] In some implementations, Figure 1Each VLOFET 302 in the boost DC-DC converter circuit 100 of the type shown can be paired with a current mirror driver circuit 304. Alternatively, the current mirror driver circuit 304 can be paired only with those VLOFETs 302 located at the "edge" of the converter circuit, between the rest of the converter circuit and circuit ground. For example, see reference... Figure 1 Only switches S1, S6, and S7 need to be paired with the current mirror driver circuit 304 to limit the startup inrush current in the entire converter circuit.

[0041] The current mirror driver circuit 304 provides pulsed operation, causing the VLOFET 302 to switch between off and current-limiting modes during the startup period. Once operational equilibrium is achieved for the entire boost DC-DC converter circuit, the current mirror driver circuit 304 can be switched off, and an appropriate clock phase (P1 or P2) can be switched into the circuit via the gates of FETs M1-Mn. Alternatively, the current mirror driver circuit 304 can be reconfigured to provide a normal clock phase voltage value to the VLOFET 302 after operational equilibrium has been achieved.

[0042] The current mirror driver circuit 304 can be implemented in various ways. The following are several implementations of the current mirror driver circuit 304 that are well suited for use in boost DC-DC converter circuits with VLOFET 302.

[0043] First implementation of the current mirror driver circuit

[0044] Figure 4A This is a schematic diagram of a current mirror 400 including a VLOFET 302 and a current mirror driver circuit 304 according to the first embodiment. The current mirror driver circuit 304 shown includes an N-type FET MOSFET MO whose drain is coupled to a diode connected to a current source 402, which in turn is coupled to a source voltage VLOFET 302. IN In many implementations, FET M0 and FETs M1-Mn in VLOFET 302 are typically of the same type and ideally have the same physical parameters (e.g., gate width, gate length, type, etc. for each finger) to optimize current matching between devices. Reference current I REF The voltage is supplied by current source 402, which is preferably designed to remain constant during PVT changes (this is conventional). In the illustrated embodiment, the gate of FET M0 is coupled as a voltage supply to differential amplifier 404. Amplifier 404 may be, for example, an operational amplifier with low output impedance.

[0045] The output of amplifier 404 is coupled to its inverting ("-") input. The non-inverting ("+") input of amplifier 404 is coupled to a clock (P1 or P2) that matches the clock phase typically supplied to VLOFET 302. In the example shown, a single-pole double-throw (SPDT) switch Sw couples the gates of FETs M1-Mn of VLOFET 302 to the output of amplifier 404 or to the clock phase typically supplied to VLOFET 302. Since FET M0 typically cannot directly drive all n gates of the VLOFET 302 device, the output of amplifier 404 should have a high drive strength capable of driving the gates of the numerous individual FETs M1-Mn in VLOFET 302.

[0046] The SPDT switch Sw can be implemented using FETs in a known manner. Although the SPDT switch Sw is shown as external to the current mirror driver circuit 304, it can also be included as part of the current mirror driver circuit 304. For example, switch S W It can be located at the voltage supply input of amplifier 404 to V IN Switching between diode voltages is possible. An alternative would be to have the output of amplifier 404 in a tri-state (i.e., set to high impedance) and to use a tri-state buffer (not shown) to drive FETs M1-Mn when amplifier 404 is used during the inrush current period. More generally, it is typically desirable to place switch Sw where current is limited. Since FETs M1-Mn are relatively large, they require a significant amount of charge to turn off and on. Directly coupling switch Sw to the gate of FETs M1-Mn means that switch Sw is in a high-current path, so switch Sw itself will need to be low-resistance. Therefore, it is preferable to place switch Sw at a low-current point (e.g., at the voltage supply input of amplifier 404), or two components (e.g., amplifier 404 and buffer) can be used to drive the gate of FETs M1-Mn, one of which is always in a high output impedance off state.

[0047] In the example shown, assume V IN The voltage ranges from approximately 2.5V to approximately 5V, and clock signals P1 and P2 have voltages consistent with V. IN The voltages are essentially the same, and the voltage generated by the FET M0 connected across the diode (“diode voltage”) is approximately 1.2V to approximately 1.5V; therefore, V IN The voltage is greater than the diode voltage. As shown, amplifier 404 is configured as a voltage follower, therefore the output of amplifier 404 is the same as the non-inverting ("+") input. When the clock is at 0V, the output voltage of amplifier 404 will drive to ground. When the clock is at P1 or P2 (and therefore at approximately V...), the output voltage will... INWhen (at the point), amplifier 404 attempts to drive its output to V. IN However, since its voltage supply is the diode voltage across FET M0, amplifier 404 cannot drive its output above the diode voltage input supply. Therefore, amplifier 404 (and thus current mirror driver circuit 304) outputs a pulsed voltage in the range from 0V to the diode voltage of FET M0.

[0048] As a result, when the current mirror driver circuit 304 is operably (e.g., via...) Figure 4A In the configuration shown, when the SPDT switch Sw is coupled to FETs M1-Mn, the current of VLOFET 302 is limited, thus mirroring the reference current I through FET M0. REF In the illustrated embodiment, if FET M0 and FETs M1-Mn have the same size, and I REF =1mA and n=10,000, then the current of VLOFET 302 will be limited to approximately 10,000 × 1mA, or approximately 10 amps. After reaching operational equilibrium, in the example shown, the SPDT switch Sw switches to the full-voltage clock input (e.g., P1 or P2) to normally control FETs M1-Mn. Therefore, functionally, in the illustrated embodiment, switch Sw is configured to receive a clock signal (P1 or P2) limited to a reduced range of a first voltage range (e.g., from 0V to the diode voltage of M0 FET) or a second, wider voltage range (e.g., from 0V to approximately V). IN A full-range clock signal (P1 or P2) is applied to the gates of FETs M1-Mn. However, for specific applications, a reduced-range clock signal and / or other voltage ranges of the full-range clock signal may be used appropriately.

[0049] Figure 4A The current mirror driver circuit 304 is implemented using an N-type FET circuit. The current mirror driver circuit 304 can also be implemented using a P-type FET circuit. For example, Figure 4B This is a schematic diagram of a PFET implementation including a PFET VLOFET 302 and a PFET current mirror 420 with a PFET current mirror driver circuit 304. The diagram takes into account the necessary reversal of the polarity of certain connections and components—including coupling the source of FETM0 to VLOFET 302. IN And coupling the drain and gate of FET M0 to the reference current I. REF The circuit shown is basically the same as the current source 422 flowing through it. Figure 4A The N-type FET circuit shown is paired with a P-type FET. A diode voltage is applied to the nominal circuit ground of amplifier 404, and V... IN The voltage applied to amplifier 404 is the supply input.

[0050] like Figure 4A As shown in the example, although the SPDT switch Sw is shown as external to the current mirror driver circuit 304, it can also be included as part of the current mirror driver circuit 304. For example, switch S W It can be located at the nominal circuit ground of amplifier 404 to switch between a diode voltage or a switching voltage that fully turns on the PMOS device in VLOFET 302. An alternative would be to have the output of amplifier 404 in a tri-state (i.e., set to high impedance) and to use a tri-state buffer (not shown) to drive FETs M1-Mn when using amplifier 404 during the startup inrush current period.

[0051] Second embodiment of the current mirror driver circuit

[0052] Figure 5 This is a schematic diagram of a current mirror 500 including a VLOFET 302 and a current mirror driver circuit 304 in the second embodiment. In this NMOS embodiment, the gate of the FET MO is coupled to the non-inverting input of a differential amplifier 404 configured as a voltage follower, and the voltage supply to the amplifier 404 is VLOFET 302. IN Amplifier 404 is used to buffer the diode voltage across FET M0 because the output voltage of amplifier 404 will track the diode voltage applied to the non-inverting ("+") input. The output of amplifier 404 is also coupled to the voltage supply input of a first gate drive inverter 502 and a second gate drive inverter 504 connected in series (circuit ground connections of inverters 502 and 504 are not shown). The first gate drive inverter 502 has an input coupled to a clock (P1 or P2) that matches the clock phase normally supplied to VLOFET 302. As those skilled in the art will understand, the PMOS implementation can be similarly configured to accommodate the necessary reversal of the polarity of certain connections and components.

[0053] In the example shown, the SPDT switch Sw couples the gates of FETs M1-Mn of VLOFET 302 to the output of the second gate drive inverter 504 or to the clock phase normally supplied to VLOFET 302. Figure 4A and Figure 4B As in the illustrated implementation, the current mirror driver circuit 304 outputs a pulsed voltage ranging from 0V to the diode voltage of the MOSFET. As a result, the current of the VLOFET 302 is limited, thereby mirroring the reference current I through the MOSFET. REF After operational balance is achieved, the SPDT switch Sw switches to the clock input (e.g., P1 or P2) to properly control FETs M1-Mn. Figure 4A and Figure 4B As in the example, although the SPDT switch Sw is shown as external to the current mirror driver circuit 304, it can also be included as part of the current mirror driver circuit 304. For example, switch S W It can be located at the non-inverting ("+") input of amplifier 404 to V IN Switching can be performed between diode voltage and voltage. Alternatively, switch Sw can be connected to the inverter's power supply, thereby switching between diode voltage and voltage. IN Switch between inverters.

[0054] Third implementation of the current mirror driver circuit

[0055] Figure 6 This is a schematic diagram of a current mirror 600 including a VLOFET 302 and a current mirror driver circuit 304 according to a third embodiment. In this embodiment, the gate of FET M0 is coupled to the voltage supply input of a buffer 602 (e.g., a small logic buffer), the input to which is a clock (P1 or P2) that is phase-matched to the clock normally supplied to the VLOFET 302. The output of the buffer 602 is coupled to a voltage follower configured to have a voltage supply V IN The non-inverting ("+") input of the differential amplifier 404. Buffer 602 is used to convert the clock voltage (which is approximately V) to the non-inverting ("+") input. IN The voltage level is shifted from the diode voltage to 0V. Amplifier 404 is used to further buffer the output of buffer 602, so that the output voltage of amplifier 404 will track the voltage applied to the non-inverting ("+") input in the range from the diode voltage to 0V. As will be understood by those skilled in the art, the PMOS implementation can be similarly configured to account for the necessary reversal of the polarity of certain connections and components.

[0056] In the example shown, the SPDT switch Sw couples the gates of FETs M1-Mn of VLOFET 302 to the output of amplifier 404 or to the clock phase typically supplied to VLOFET 302. As in the embodiment above, the current mirror driver circuit 304 outputs a pulsed voltage in the range from 0V to the diode voltage of MOSFET 0, thus limiting the current of VLOFET 302 and mirroring the reference current I through MOSFET 0. REF Again, after operational balance is achieved, the SPDT switch Sw switches to the clock input (e.g., P1 or P2) to properly control FETs M1-Mn. Figure 4A , Figure 4B and Figure 5As in the example, although the SPDT switch Sw is shown as external to the current mirror driver circuit 304, it can also be included as part of the current mirror driver circuit 304. For example, switch S W It can be located at diode voltage or V IN The voltage supply input is provided to the buffer 602 between them.

[0057] Fourth implementation of the current mirror driver circuit

[0058] exist Figure 4A , Figure 4B , Figure 5 and Figure 6 The SPDT switch Sw of the embodiment shown enables the current mirror driver circuit 304 to be switched off after operational equilibrium is reached, thus essentially eliminating any influence that the current mirror driver circuit 304 might have on the normal operation of a converter using one or more VLOFETs 302. However, as mentioned above, in an alternative embodiment, the current mirror driver circuit 304 itself can be reconfigured to apply an appropriate clock phase (e.g., P1 or P2) to the FETs M1-Mn of the VLOFETs 302 for normal control after operational equilibrium is reached.

[0059] For example, Figure 7 This is a schematic diagram of a current mirror 700 including a VLOFET 302 and a current mirror driver circuit 304 according to the fourth embodiment. The current mirror driver circuit 304 shown is essentially... Figure 4A The circuit shown, except that the SPDT reconfiguration switch Sw' causes the voltage input of amplifier 404 to be coupled to the gate of FET M0 (i.e., the diode voltage) or coupled to V IN During the startup period, the gate of FET M0 is coupled to the voltage supply input of amplifier 404 via a reconfigured switch Sw', and as described above... Figure 4A As described in the current mirror driver circuit 304 shown, the current of VLOFET 302 is limited. After reaching operational equilibrium, VLOFET 302... IN The voltage supply input to amplifier 404 is coupled to switch Sw' by reconfiguring it. Since the voltage of the clock input (e.g., P1 or P2) is essentially V... IN Furthermore, amplifier 404 is configured as a voltage follower, so the clock input is essentially routed through current mirror driver circuit 304 to the control gate of VLOFET 302. Therefore, the output of amplifier 404 will alternate between 0V and clock input voltage pulses, providing normal control of FETs M1-Mn of VLOFET 302.

[0060] Therefore, reconfiguring the switch Sw' essentially enables two operating modes of the current mirror driver circuit 304: a current-limiting mode, in which the current mirror driver circuit 304 limits the current in the VLOFET 302; and a shoot-through mode, in which the current mirror driver circuit 304 transmits a clock (e.g., P1 or P2) to the control gate of the VLOFET 302. For example, for operation in current-limiting mode, a time period can be set individually based on time, or the time period can be set until the converter circuit operation reaches equilibrium or until the inrush current is measured to be below a specified level by the detection circuit, or by any other suitable criterion. Furthermore, the current-limiting mode can be enabled for non-startup purposes, for example, when the current through the VLOFET 302 measured by the detection circuit exceeds a specified level.

[0061] As should be understood, Figure 4B , Figure 5 and Figure 6 The current mirror driver circuit 304 can also be modified to include a similar reconfigured switch Sw' to allow current-limiting mode and shoot-through mode. In current-limiting mode, the current mirror driver circuit 304 limits the current in VLOFET 302. In shoot-through mode, the current mirror driver circuit 304 passes a clock (e.g., P1 or P2) to the control gate of VLOFET 302.

[0062] method

[0063] Another aspect of the invention includes methods for limiting current through a VLOFET, and methods for limiting current through a boost DC-DC converter circuit having at least one VLOFET. For example, Figure 8 This is a process flowchart 800 for a first method of limiting current through a VLOFET. The VLOFET includes a control gate configured to be coupled to or coupled to a source of clock phase. The method includes: coupling a current mirror driver circuit to the control gate of the VLOFET and to a source of clock phase (block 802); and selectively applying a clock phase limited by the current mirror driver circuit to a first voltage range or a second wider voltage range to the control gate of the VLOFET, wherein, when the current mirror driver circuit and the VLOFET are coupled, a current mirror (block 804) is included to limit the current flowing through the VLOFET when the clock phase is limited to the first voltage range.

[0064] As another example, Figure 9This is a process flowchart 900 for a first method of limiting inrush current through a boost DC-DC converter circuit having at least one VLOFET. The VLOFET includes a control gate configured to be coupled to or potentially coupled to a source of an associated clock phase and connected in a circuit path subjected to an initiation inrush current. The method includes: coupling the control gate of at least one VLOFET to a corresponding current mirror driver circuit configured to be coupled to a source of a general circuit supply voltage and an associated clock phase (block 902); and coupling the current mirror driver circuit to a switch configured to selectively apply to the control gate of at least one VLOFET a clock phase limited by the current mirror driver circuit to a first voltage range or a second, wider voltage range, wherein, when coupled, the at least one VLOFET and the corresponding current mirror driver circuit include a current mirror that limits the inrush current flowing through the at least one VLOFET when the clock phase is limited to the first voltage range (block 904).

[0065] The above method may further include one or more of the following: wherein the corresponding current mirror driver circuit outputs a pulse voltage to the control gate of at least one VLOFET; further comprising applying a clock phase limited to a first voltage range during a time period, and applying a clock phase limited to a second wider voltage range after the time period; wherein the corresponding current mirror driver circuit can be reconfigured to enable a current-limiting operation mode and a shoot-through mode, wherein in the current-limiting operation mode, the corresponding current mirror driver circuit limits the current flowing in at least one VLOFET, and in the shoot-through mode, the associated clock phase is passed to the control gate of at least one VLOFET; wherein the current mirror driver circuit corresponding to at least one VLOFET... The circuit includes a differential amplifier and a diode-connected field-effect transistor (FET) coupled to a reference current and having a gate. The differential amplifier has an output coupled to or potentially coupled to the control gate of at least one VLOFET, a non-inverting input coupled to a source of an associated clock phase, an inverting input coupled to the output, and a voltage supply input coupled to the gate of the diode-connected FET or ground. The current mirror driver circuit corresponding to at least one VLOFET includes a diode-connected FET coupled to a reference current and having a gate, a differential amplifier, a first gate drive inverter, and a second gate drive inverter. The differential amplifier has an output coupled to the diode-connected... The first gate drive inverter has an inverting input to the gate of the FET, an inverting input coupled to the output, and a voltage supply input coupled to a general-purpose circuit power supply voltage. The second gate drive inverter has an input coupled to the output of the first gate drive inverter, a voltage supply input coupled to the output of the amplifier, and an output coupled to or potentially coupled to the control gate of at least one VLOFET. The current mirror driver circuit corresponding to at least one VLOFET includes a field-effect transistor (FET) with a diode-connected gate coupled to a reference current, a buffer, and a differential amplifier. The buffer has an input coupled to a source of associated clock phase, a voltage supply input coupled to the gate of a diode-connected FET, and an output; the differential amplifier has an output coupled to or potentially coupled to the control gate of at least one VLOFET, a non-inverting input coupled to the output of the buffer, an inverting input coupled to the output, and a voltage supply input coupled to a general-purpose circuit power supply voltage; wherein the boost DC-DC converter circuit is a capacitor-based charge pump; wherein the boost DC-DC converter circuit is a Dickson boost DC-DC converter circuit; wherein the boost DC-DC converter circuit is a Dickson boost DC-DC converter circuit with a multiplication factor of 3;The current mirror driver circuit is implemented using either an N-type FET circuit or a P-type FET circuit; wherein the current mirror driver circuit is implemented using FET circuits, and these FETs operate in the saturation region when in current-limiting mode, and in the transistor region when not in current-limiting mode; and / or wherein the current mirror limits the inrush current flowing through the corresponding body diode of at least one VLOFET.

[0066] Benefits, manufacturing technology and choices

[0067] By combining a current mirror driver circuit and a VLOFET in the circuit path subjected to startup inrush current, the inrush current can be regulated to an acceptable level with minimal additional circuitry, thus enabling a boost DC-DC converter circuit with high efficiency (e.g., 95%-98%) that cannot be achieved using conventional inrush current limiting techniques.

[0068] Another advantage of the current mirror circuit in certain embodiments of the present invention is that, since the current limiting characteristics of the current mirror are based on the ratio of the size of the reference FET M0 of the current mirror driver circuit 304 to the size of the FETs M1-Mn of the VLOFET 302, and this ratio remains constant during PVT variations, such a circuit is substantially unaffected by process voltage-temperature (PVT) variations.

[0069] Another benefit of combining the current mirror driver circuit 304 with the VLOFET 302 in a current mirror configuration is that it gives circuit designers complete control over the inrush current timing by selecting the circuit parameters of the current mirror driver circuit 304. A certain amount of charge is required for the boost DC-DC converter circuit 100 to reach its operational state (i.e., equilibrium). Current is simply the rate of charge flow. A conventional boost DC-DC converter circuit 100 design using a VLOFET will uncontrollably dump the required charge in a short amount of time, leading to the aforementioned problem. The boost DC-DC converter circuit 100 including the combination of the current mirror driver circuit 304 and the VLOFET 302 controls the charge flow over a longer period of time. The latter provides a known charging time and a limited, controlled current; the former provides neither. Such control can be useful, for example, as a safety check, and safety is paramount in all power supply circuit designs. For example, a typical DC-to-DC converter circuit will include a timer and a monitor circuit that checks whether the output voltage is at its expected position (e.g., above 95% of the target value within X microseconds) at the end of a certain time period; if not, remedial actions can be taken (e.g., powering off the circuit). In the design of a conventional boost DC-to-DC converter circuit 100, PVT variations must be considered, and accordingly, the time period will need to be long enough to cover cell-to-cell variations, resulting in a long startup time. This can be dangerous if the circuit shows a fast power-up time but requires a long time period, because an error cannot be detected until the end of that time period. Embodiments of the present invention are less susceptible to PVT variations and allow for accurate startup time determination, thereby reducing potential hazards by shortening the measurement time periods of the timer and monitoring circuits.

[0070] As used herein, the term "MOSFET" means any field-effect transistor (FET) having an insulated gate and comprising a metal or metal-like, insulator, and semiconductor structure. The terms "metal" or "metal-like" include at least one conductive material (e.g., aluminum, copper, or other metals, or highly doped polycrystalline silicon, graphene, or other conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0071] As will be apparent to those skilled in the art, various embodiments of the invention can be implemented to meet a wide range of specifications. Unless otherwise stated above, the selection of appropriate component values ​​is a matter of design choice, and various embodiments of the invention can be implemented using any suitable integrated circuit (IC) technology (including, but not limited to, MOSFET structures) or in hybrid or discrete circuit form. Integrated circuit embodiments can be fabricated using any suitable substrate and process, including but not limited to standard bulk silicon, silicon-on-insulator (SOI), and silicon-on-sapphire (SOS). Unless otherwise stated above, the invention can be implemented using other transistor technologies such as bipolar, GaAs HBT, GaN HEMT, GaAs pHEMT, and MESFET technologies. However, the above-described inventive concepts are particularly useful for SOI-based fabrication processes (including SOS) and fabrication processes with similar characteristics. Fabrication using CMOS processes on SOI or SOS results in circuits with low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high-frequency operation (i.e., radio frequency up to and exceeding 50 GHz). The implementation of monolithic ICs is particularly useful because, with careful design, parasitic capacitance can usually be kept low (or kept to a minimum, uniform across all cells, allowing for compensation).

[0072] Depending on specific specifications and / or implementation technologies (e.g., NMOS, PMOS, or CMOS, and enhancement-mode or depletion-mode transistor devices), voltage levels and / or the polarity of voltage and / or logic signals can be adjusted. In embodiments of the invention, with various FETs enabled, in current-limiting mode, the various FETs can operate in their saturation region (where the FET behaves like a voltage-controlled current source), and when not in current-limiting mode (i.e., when switching between on and off in response to an applied clock phase), the various FETs can operate in their transistor region (where the FET behaves like a voltage-controlled resistor). The voltage, current, and power handling capabilities of components can be adjusted as needed, for example, by adjusting device size, sequentially “stacking” components (especially FETs) to withstand greater voltages, and / or using multiple components in parallel to handle greater currents or reduce resistance. Additional circuit components can be added to enhance the performance of the disclosed circuit and / or provide additional functionality without significantly altering the function of the disclosed circuit.

[0073] in conclusion

[0074] Several embodiments of the present invention have been described. It should be understood that various modifications can be made without departing from the spirit and scope of the invention. For example, some of the steps described above may be independent of order, and thus these steps may be performed in an order different from that described. Furthermore, some of the steps described above may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial, or parallel manner.

[0075] It should be understood that the above description is intended to illustrate, not limit, the scope of the invention, which is defined by the scope of the appended claims, and other embodiments are also within the scope of the claims. In particular, the scope of the invention includes any and all possible combinations of one or more processes, machines, manufactures, or compositions of matter set forth in the claims. (Note that the bracket labels of the claim elements are for convenience of reference and do not in themselves indicate a specific required order or enumeration of elements; furthermore, such labels may be reused in dependent claims as references to other elements and are not considered as conflicting label sequences.)

Claims

1. A circuit for limiting the current through an extremely low-ohm FET (VLOFET) having a control gate, the circuit comprising: A current mirror driver circuit, which is coupled to or can be coupled to the control gate of the VLOFET, and is configured to be coupled to a source of general circuit power supply voltage and clock phase; as well as A switch, coupled to the current mirror driver circuit, is configured to be selectively applied to the control gate of the coupled VLOFET by either a clock phase limited to a first voltage range or a clock phase limited to a second wider voltage range by the current mirror driver circuit. The current mirror driver circuit and the VLOFET, when coupled, include a current mirror that limits the current flowing through the VLOFET when the clock phase is limited to the first voltage range.

2. The circuit according to claim 1, wherein, The current mirror driver circuit outputs a pulse voltage to the control gate of the VLOFET.

3. The circuit according to claim 1, wherein, The switch is configured to apply a clock phase limited to a first voltage range during a time period, and to apply a clock phase limited to a second, wider voltage range after the time period.

4. The circuit according to claim 1, wherein, The circuit can be reconfigured to enable a current-limiting operation mode or a pass-through mode. In the current-limiting operation mode, the current mirror driver circuit limits the current flowing in the coupled VLOFET. In the pass-through mode, the clock phase is passed to the control gate of the coupled VLOFET.

5. The circuit according to claim 1, wherein, The current mirror driver circuit includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; and A differential amplifier having an output coupled to or capable of being coupled to the control gate of the VLOFET, a non-inverting input coupled to the source of the clock phase, an inverting input coupled to the output, and one of a voltage supply input or ground coupled to the gate of the diode-connected FET.

6. The circuit according to claim 1, wherein, The current mirror driver circuit includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; A differential amplifier having an output, a non-inverting input coupled to the gate of the diode-connected FET, an inverting input coupled to the output, and a voltage supply input coupled to the general circuit power supply voltage; A first gate-driven inverter has an input coupled to the source of the clock phase, a voltage supply input coupled to the output of the amplifier, and an output; and The second gate drive inverter has an input coupled to the output of the first gate drive inverter, a voltage supply input coupled to the output of the amplifier, and an output coupled to or capable of being coupled to the control gate of the VLOFET.

7. The circuit according to claim 1, wherein, The current mirror driver circuit includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; A buffer having an input coupled to the source of the clock phase, a voltage supply input coupled to the gate of the diode-connected FET, and an output; and A differential amplifier having an output coupled to or capable of being coupled to the control gate of the VLOFET, a non-inverting input coupled to the output of the buffer, an inverting input coupled to the output, and a voltage supply input coupled to the general circuit power supply voltage.

8. A boost DC-DC converter circuit, comprising: At least one very low ohm FET (VLOFET) has a control gate configured to be coupled to or capable of being coupled to a source of an associated clock phase and connected in a circuit path subjected to startup inrush current; A current mirror driver circuit is configured to be coupled to the source of a general circuit power supply voltage and the associated clock phase, and coupled to or capable of being coupled to the control gate of at least one VLOFET; as well as A switch, coupled to the current mirror driver circuit, is configured to be selectively applied to the control gate of the at least one VLOFET by a clock phase limited by the current mirror driver circuit to a first voltage range or by a clock phase limited to a second wider voltage range. Wherein, the at least one VLOFET and the corresponding current mirror driver circuit, when coupled, include a current mirror that limits the inrush current flowing through the at least one VLOFET when the clock phase is limited to the first voltage range.

9. The boost DC-DC converter circuit according to claim 8, wherein, The corresponding current mirror driver circuit outputs a pulse voltage to the control gate of the at least one VLOFET.

10. The boost DC-DC converter circuit according to claim 8, wherein, The switch is configured to apply a clock phase limited to a first voltage range during a time period, and to apply a clock phase limited to a second, wider voltage range after the time period.

11. The boost DC-DC converter circuit according to claim 8, wherein, The corresponding current mirror driver circuit can be reconfigured to enable a current-limiting operation mode and a shoot-through mode. In the current-limiting operation mode, the corresponding current mirror driver circuit limits the current flowing in the at least one VLOFET. In the shoot-through mode, the associated clock phase is passed to the control gate of the at least one VLOFET.

12. The boost DC-DC converter circuit according to claim 8, wherein, The current mirror driver circuit corresponding to the at least one VLOFET includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; and A differential amplifier having an output coupled to or capable of being coupled to the control gate of the at least one VLOFET, a non-inverting input coupled to the source of the associated clock phase, an inverting input coupled to the output, and one of a voltage supply input or ground coupled to the gate of the diode-connected FET.

13. The boost DC-DC converter circuit according to claim 8, wherein, The current mirror driver circuit corresponding to the at least one VLOFET includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; A differential amplifier having an output, a non-inverting input coupled to the gate of the diode-connected FET, an inverting input coupled to the output, and a voltage supply input coupled to the general circuit power supply voltage; A first gate-driven inverter has an input to the source coupled to the associated clock phase, a voltage supply input coupled to the output of the amplifier, and an output; and The second gate drive inverter has an input coupled to the output of the first gate drive inverter, a voltage supply input coupled to the output of the amplifier, and an output coupled to or capable of being coupled to the control gate of the at least one VLOFET.

14. The boost DC-DC converter circuit according to claim 8, wherein, The current mirror driver circuit corresponding to the at least one VLOFET includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; A buffer having an input coupled to the source of the associated clock phase, a voltage supply input coupled to the gate of the diode-connected FET, and an output; and A differential amplifier having an output coupled to or capable of being coupled to the control gate of the at least one VLOFET, a non-inverting input coupled to the output of the buffer, an inverting input coupled to the output, and a voltage supply input coupled to the general circuit power supply voltage.

15. The boost DC-DC converter circuit according to claim 8, wherein, The boost DC-DC converter circuit is based on a capacitor-based charge pump.

16. The boost DC-DC converter circuit according to claim 8, wherein, The boost DC-DC converter circuit is a Dickson boost DC-DC converter circuit.

17. The boost DC-DC converter circuit according to claim 8, wherein, The boost DC-DC converter circuit is a Dickson boost DC-DC converter circuit with a multiplication factor of 3.

18. The boost DC-DC converter circuit according to claim 8, wherein, The current mirror driver circuit is implemented using either an N-type FET circuit or a P-type FET circuit.

19. The boost DC-DC converter circuit according to claim 8, wherein, The current mirror driver circuit is implemented as a FET circuit, and when in current-limiting mode, the FET operates in the saturation region, and when not in the current-limiting mode, the FET operates in the transistor region.

20. The boost DC-DC converter circuit according to claim 8, wherein, The current mirror limits the surge current flowing through the corresponding body diode of the at least one VLOFET.

21. A method for limiting current through an extremely low-ohm FET (VLOFET) having a control gate configured to be coupled to or capable of being coupled to a source of clock phase, the method comprising: The current mirror driver circuit is coupled to the control gate of the VLOFET and the source of the clock phase; as well as The following can be selectively applied to the control gate of the VLOFET: The clock phase is limited to a first voltage range by the current mirror driver circuit, or Clock phase limited to the second wider voltage range; The current mirror driver circuit and the VLOFET, when coupled, include a current mirror that limits the current flowing through the VLOFET when the clock phase is limited to the first voltage range.

22. The method of claim 21, further comprising outputting a pulse voltage from the current mirror driver circuit to the control gate of the VLOFET.

23. The method of claim 21, further comprising applying a clock phase limited to a first voltage range during the time period, and applying a clock phase limited to a second wider voltage range after the time period.

24. The method according to claim 21, wherein, The current mirror driver circuit can be reconfigured to enable a current-limiting operation mode or a shoot-through mode. In the current-limiting operation mode, the current mirror driver circuit limits the current flowing in the VLOFET. In the shoot-through mode, the clock phase is passed to the control gate of the VLOFET.

25. The method according to claim 21, wherein, The current mirror driver circuit includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; and A differential amplifier having an output coupled to or capable of being coupled to the control gate of the VLOFET, a non-inverting input coupled to the source of the clock phase, an inverting input coupled to the output, and one of a voltage supply input or ground coupled to the gate of the diode-connected FET.

26. The method according to claim 21, wherein, The current mirror driver circuit includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; A differential amplifier having an output, a non-inverting input coupled to the gate of the diode-connected FET, an inverting input coupled to the output, and a voltage supply input coupled to a general circuit power supply voltage; A first gate-driven inverter has an input coupled to the source of the clock phase, a voltage supply input coupled to the output of the amplifier, and an output; and The second gate drive inverter has an input coupled to the output of the first gate drive inverter, a voltage supply input coupled to the output of the amplifier, and an output coupled to or capable of being coupled to the control gate of the VLOFET.

27. The method according to claim 21, wherein, The current mirror driver circuit includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; A buffer having an input coupled to the source of the clock phase, a voltage supply input coupled to the gate of the diode-connected FET, and an output; and A differential amplifier having an output coupled to or capable of being coupled to the control gate of the VLOFET, a non-inverting input coupled to the output of the buffer, an inverting input coupled to the output, and a voltage supply input coupled to a general circuit power supply voltage.

28. A method for limiting inrush current through a boost DC-DC converter circuit having at least one ultra-low ohmic FET (VLOFET), the at least one VLOFET having a control gate configured to be coupled to or capable of being coupled to a source of an associated clock phase and connected in a circuit path subjected to startup inrush current, the method comprising: The control gate of the at least one VLOFET is coupled to a corresponding current mirror driver circuit, which is configured to be coupled to the source of the general circuit power supply voltage and the associated clock phase. as well as A current mirror driver circuit is coupled to a switch configured to be selectively applied to the control gate of the at least one VLOFET by either a clock phase limited to a first voltage range or a clock phase limited to a second wider voltage range by the current mirror driver circuit. Wherein, the at least one VLOFET and the corresponding current mirror driver circuit, when coupled, include a current mirror that limits the inrush current flowing through the at least one VLOFET when the clock phase is limited to the first voltage range.

29. The method according to claim 28, wherein, The corresponding current mirror driver circuit outputs a pulse voltage to the control gate of the at least one VLOFET.

30. The method of claim 28, further comprising applying a clock phase limited to a first voltage range during the time period, and applying a clock phase limited to a second wider voltage range after the time period.

31. The method according to claim 28, wherein, The corresponding current mirror driver circuit can be reconfigured to enable a current-limiting operation mode and a shoot-through mode. In the current-limiting operation mode, the corresponding current mirror driver circuit limits the current flowing in the at least one VLOFET. In the shoot-through mode, the associated clock phase is passed to the control gate of the at least one VLOFET.

32. The method according to claim 28, wherein, The current mirror driver circuit corresponding to the at least one VLOFET includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; and A differential amplifier having an output coupled to or capable of being coupled to the control gate of the at least one VLOFET, a non-inverting input coupled to the source of the associated clock phase, an inverting input coupled to the output, and one of a voltage supply input or ground coupled to the gate of the diode-connected FET.

33. The method according to claim 28, wherein, The current mirror driver circuit corresponding to the at least one VLOFET includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; A differential amplifier having an output, a non-inverting input coupled to the gate of the diode-connected FET, an inverting input coupled to the output, and a voltage supply input coupled to the general circuit power supply voltage; A first gate-driven inverter has an input to the source coupled to the associated clock phase, a voltage supply input coupled to the output of the amplifier, and an output; and The second gate drive inverter has an input coupled to the output of the first gate drive inverter, a voltage supply input coupled to the output of the amplifier, and an output coupled to or capable of being coupled to the control gate of the at least one VLOFET.

34. The method according to claim 28, wherein, The current mirror driver circuit corresponding to the at least one VLOFET includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; A buffer having an input coupled to the source of the associated clock phase, a voltage supply input coupled to the gate of the diode-connected FET, and an output; and A differential amplifier having an output coupled to or capable of being coupled to the control gate of the at least one VLOFET, a non-inverting input coupled to the output of the buffer, an inverting input coupled to the output, and a voltage supply input coupled to the general circuit power supply voltage.

35. The method according to claim 28, wherein, The boost DC-DC converter circuit is based on a capacitor-based charge pump.

36. The method according to claim 28, wherein, The boost DC-DC converter circuit is a Dickson boost DC-DC converter circuit.

37. The method according to claim 28, wherein, The boost DC-DC converter circuit is a Dickson boost DC-DC converter circuit with a multiplication factor of 3.

38. The method according to claim 28, wherein, The current mirror driver circuit is implemented using either an N-type FET circuit or a P-type FET circuit.

39. The method according to claim 28, wherein, The current mirror driver circuit is implemented as a FET circuit, and when in current-limiting mode, the FET operates in the saturation region, and when not in the current-limiting mode, the FET operates in the transistor region.

40. The method according to claim 28, wherein, The current mirror limits the surge current flowing through the corresponding body diode of the at least one VLOFET.

41. A current mirror circuit comprising an extremely low-ohm FET (VLOFET) having a control gate, and a current mirror driver circuit coupled to the control gate of the VLOFET, wherein, The current mirror circuit is configured to have a current mirror mode in which the current through the VLOFET is limited by the current mirror driver circuit during the startup period, and wherein the current mirror circuit is also configured to have a shoot-through operation mode in which the clock phase at the control gate has a second wider voltage range after the startup period.

42. The current mirror circuit according to claim 41, wherein, During the pass-through operation mode, the current through the VLOFET after the start-up period is not limited by the current mirror driver circuit.

43. The current mirror circuit according to claim 41, wherein, In the current mirror mode, the current mirror driver circuit and the VLOFET include a current mirror.

44. The current mirror circuit according to claim 43, wherein, As a result of the current mirror driver circuit limiting the clock phase applied to the control gate of the VLOFET to a first voltage range during the startup period, the current mirror is configured to limit the current flowing through the VLOFET.

45. A current mirror circuit comprising an extremely low-ohm FET (VLOFET) having a control gate, and a current mirror driver circuit coupled to the control gate of the VLOFET and configured to be coupled to a clock phase, wherein, The current mirror circuit is configured to have a current mirror mode in which the clock phase is limited to a first voltage range within a selected time period by the current mirror driver circuit when coupled, and wherein the current mirror circuit is further configured to have a pass-through operation mode in which the clock phase has a second wider voltage range after the selected time period.

46. ​​The current mirror circuit according to claim 45, wherein, During the pass-through operation mode, the clock phase is not limited by the current mirror driver circuit when coupled.

47. The current mirror circuit according to claim 45, wherein, In the current mirror mode, the current mirror driver circuit and the VLOFET include a current mirror.

48. The current mirror circuit according to claim 47, wherein, As a result of the current mirror driver circuit limiting the clock phase in a coupled state, the current mirror is configured to limit the current flowing through the VLOFET.

49. A circuit for limiting current through an extremely low-ohm FET (VLOFET) having a control gate, the circuit comprising a current mirror driver circuit configured to be coupled to the control gate and a clock phase of the VLOFET, wherein, The current mirror driver circuit and the VLOFET, when coupled, include a current mirror that limits the current flowing through the VLOFET by limiting the clock phase to a first voltage range for a selected time period.

50. The circuit according to claim 49, wherein, The current mirror driver circuit outputs a pulse voltage to the control gate of the VLOFET.

51. The circuit according to claim 49, wherein, The current mirror limits the surge current flowing through the corresponding body diode of the VLOFET.

52. The circuit according to claim 49, wherein, The circuit can be reconfigured to enable a current-limiting operation mode or a pass-through mode. In the current-limiting operation mode, the current mirror driver circuit limits the current flowing in the VLOFET. In the pass-through mode, the clock phase is passed to the control gate of the VLOFET.

53. The circuit of claim 49 further includes a source of the clock phase.

54. The circuit of claim 49 further includes a switch coupled to the current mirror driver circuit and configured to, when coupled, selectively apply to the control gate of the VLOFET by the current mirror driver circuit at a clock phase limited to the first voltage range or at a clock phase limited to a second wider voltage range.

55. The circuit according to claim 54, wherein, The switch is configured to apply a clock phase limited to the first voltage range during a time period, and to apply a clock phase limited to the second wider voltage range after the time period.

56. The circuit according to claim 54, wherein, The circuit can be reconfigured to enable a current-limiting operation mode or a pass-through mode. In the current-limiting operation mode, the current mirror driver circuit limits the current flowing in the VLOFET. In the pass-through mode, the clock phase is passed to the control gate of the VLOFET.

57. The circuit according to claim 54, wherein, The current mirror driver circuit outputs a pulse voltage to the control gate of the VLOFET.

58. The circuit according to claim 54, wherein, The current mirror limits the surge current flowing through the corresponding body diode of the VLOFET.

59. A DC-to-DC converter circuit, comprising: At least one very low ohmic FET (VLOFET) has a control gate and is connected in a circuit path that is subjected to surge current during the startup period; A current mirror driver circuit, which is coupled to the control gate of the at least one VLOFET and configured to be coupled to the clock phase; The DC-to-DC converter circuit is configured to have a current mirror mode, in which the current through the at least one VLOFET is limited by the current mirror driver circuit during at least some portions of the startup time period; and The current mirror driver circuit is reconfigurable between the current mirror mode and the pass-through operation mode, in which the clock phase is passed from the current mirror driver circuit to the control gate of one or more of the at least one VLOFET.

60. The DC-to-DC converter circuit according to claim 59, wherein, In the pass-through operation mode, the current through one or more of the at least one VLOFETs after the start-up period is not limited by the current mirror driver circuit.

61. The DC-to-DC converter circuit according to claim 59, wherein, In the current mirror mode, the current mirror driver circuit and the at least one VLOFET include a current mirror.

62. The DC-to-DC converter circuit according to claim 59, wherein, The current mirror driver circuit outputs a pulse voltage to the control gate of one or more of the at least one VLOFET.

63. The DC-to-DC converter circuit according to claim 59, wherein, The clock phase is limited to a first voltage range during the time period and to a second, wider voltage range after the time period.

64. The DC-to-DC converter circuit according to claim 59, wherein, The current mirror driver circuit limits the inrush current flowing through the corresponding body diode of one or more of the at least one VLOFET.

65. The DC-to-DC converter circuit according to claim 59, wherein, The DC-DC converter circuit is a capacitor-based charge pump.

66. A DC-to-DC converter circuit, comprising: At least one very low ohmic FET (VLOFET) has a control gate and is connected in a circuit path subjected to startup inrush current; A current mirror driver circuit is configured to be coupled to the clock phase; as well as A switch, coupled between the current mirror driver circuit and the control gate of one or more of the at least one VLOFETs, and configured to be coupled to the clock phase, is configured to be selectively applied to the control gate of one or more of the at least one VLOFETs by the current mirror driver circuit within a first voltage range or by a second wider voltage range of the clock phase. Wherein, one or more of the at least one VLOFETs and the current mirror driver circuit, when coupled, include a current mirror that limits the inrush current flowing through one or more of the at least one VLOFETs when the clock phase is limited to the first voltage range.

67. The DC-to-DC converter circuit according to claim 66, wherein, The current mirror driver circuit outputs a pulse voltage to the control gate of one or more of the at least one VLOFET.

68. The DC-to-DC converter circuit according to claim 66, wherein, The switch is configured to apply a clock phase limited to the first voltage range during a time period, and to apply a clock phase limited to the second wider voltage range after the time period.

69. The DC-to-DC converter circuit according to claim 66, wherein, The current mirror driver circuit can be reconfigured to enable a current-limiting operating mode and a shoot-through mode. In the current-limiting operating mode, the current mirror driver circuit limits the current flowing in one or more of the at least one VLOFET. In the shoot-through mode, the associated clock phase is passed to the control gate of one or more of the at least one VLOFET.

70. The DC-to-DC converter circuit according to claim 66, wherein, The current mirror limits the surge current flowing through the corresponding body diode of one or more of the at least one VLOFET.

71. The DC-to-DC converter circuit according to claim 66, wherein, The DC-DC converter circuit is a capacitor-based charge pump.

72. A method for limiting current through an extremely low-ohm FET (VLOFET) having a control gate, comprising: The current mirror driver circuit is coupled to the control gate and clock phase source of the VLOFET; During the first time period, the current mirror driver circuit is coupled to the control gate of the VLOFET; as well as During the second time period, the source of the clock phase is coupled to the control gate of the VLOFET; The current mirror driver circuit and the VLOFET, when coupled, include a current mirror that limits the current flowing through the VLOFET during the first time period.

73. The method of claim 72, further comprising outputting a pulse voltage from the current mirror driver circuit to the control gate of the VLOFET.

74. The method according to claim 72, wherein, The clock phase is limited to a first voltage range during the first time period and to a second wider voltage range during the second time period.

75. The method according to claim 72, wherein, The current mirror driver circuit can be reconfigured to enable a current-limiting operation mode or a shoot-through mode. In the current-limiting operation mode, the current mirror driver circuit limits the current flowing in the VLOFET. In the shoot-through mode, the clock phase is passed to the control gate of the VLOFET.

76. The method according to claim 72, wherein, The current mirror driver circuit includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; and A differential amplifier having an output coupled to or capable of being coupled to the control gate of the VLOFET, a non-inverting input coupled to the source of the clock phase, an inverting input coupled to the output, and one of a voltage supply input or ground coupled to the gate of the diode-connected FET.

77. The method according to claim 72, wherein, The current mirror driver circuit includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; A differential amplifier having an output, a non-inverting input coupled to the gate of the diode-connected FET, an inverting input coupled to the output, and a voltage supply input coupled to a general circuit power supply voltage; A first gate-driven inverter has an input coupled to the source of the clock phase, a voltage supply input coupled to the output of the differential amplifier, and an output; and The second gate drive inverter has an input coupled to the output of the first gate drive inverter, a voltage supply input coupled to the output of the differential amplifier, and an output coupled to or capable of being coupled to the control gate of the VLOFET.

78. The method according to claim 72, wherein, The current mirror driver circuit includes: A diode-connected field-effect transistor (FET) coupled to a reference current and having a gate; A buffer having an input coupled to the source of the clock phase, a voltage supply input coupled to the gate of the diode-connected FET, and an output; and A differential amplifier having an output coupled to or capable of being coupled to the control gate of the VLOFET, a non-inverting input coupled to the output of the buffer, an inverting input coupled to the output, and a voltage supply input coupled to a general circuit power supply voltage.

79. A method for limiting current through an extremely low-ohm FET (VLOFET) having a control gate configured to be coupled to or capable of being coupled to a source of clock phase, the method comprising: The current mirror driver circuit is coupled to the control gate of the VLOFET and the source of the clock phase; as well as Selectively apply any of the following to the control gate of the VLOFET: The clock phase is limited to a first voltage range by the current mirror driver circuit, or Clock phase limited to the second wider voltage range; Wherein, the current mirror driver circuit and the VLOFET, when coupled, include a current mirror that limits the current flowing through the VLOFET when the clock phase is limited to the first voltage range; and The current mirror driver circuit can be reconfigured to enable a current-limiting operation mode or a pass-through mode. In the current-limiting operation mode, the current mirror driver circuit limits the current flowing through the VLOFET. In the pass-through mode, the clock phase is passed to the control gate of the VLOFET.

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