Noise detection equipment

Abstract

A squelch detection device is provided. The squelch detection device receives first and second input signals and first and second threshold voltages. The squelch detection device determines a first common mode of the first and second input signals and a second common mode of the first and second threshold voltages. The squelch detection device averages the first common mode with the second common mode to generate an average common mode, and sets the first common mode of the first and second input signals as the average common mode. The squelch detection device sets the second common mode of the first and second threshold voltages as the average common mode, and determines a state of a squelch signal based on the first and second input signals and the first and second threshold voltages, the squelch signal indicating whether the first and second input signals are attributable to noise.

Description

Technical Field

[0001] The present application relates to a mute detection device, and more particularly to a mute detection device that tolerates process variations, low supply power, and high input common mode variations. Background Art

[0002] A squelch detector suppresses the output of a device (such as a receiver) in the absence of a sufficiently strong desired input signal. The squelch detector can be implemented as an amplitude envelope detector that distinguishes between a valid signal and noise. In low-power systems (e.g., with a supply voltage of approximately 0.9 volts to 1.1 volts (V)), process variations and large input common-mode ranges become increasingly significant. Consequently, conventional squelch detectors have difficulty distinguishing between valid signals and noise. Furthermore, implementing the squelch function becomes challenging when local and global processes do not match. Summary of the Invention

[0003] This article describes a noise detector that is tolerant to process variations and low-power environments. The noise detector receives a reference threshold voltage generated by a circuit. The noise detector compares an input signal to the reference threshold voltage to distinguish between a valid signal and noise. The noise detector outputs a noise signal. The noise signal is asserted or deasserted (set to logic one or logic zero) to indicate whether the input signal is valid or attributable to noise.

[0004] The squelch detector receives a reference threshold voltage and an input signal. The squelch detector averages the common mode of the static reference threshold voltage and the common mode of the input signal. The squelch detector then shifts (or forces) the common mode of the threshold voltage and the input signal to the average. By shifting the threshold voltage and the common mode of the input signal, the squelch detector is adaptive and responsive to the operating conditions of the environment in which the present disclosure is employed. The squelch detector gradually shifts the threshold voltage and tracks the input signal behavior to dynamically adjust the reference threshold voltage based on environmental conditions affected by the input signal behavior. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 A diagram showing a squelch detection device.

[0006] Figure 2 Circuit diagram of a dividing operational amplifier showing the input signal and threshold voltage registers of a squelch detection device.

[0007] Figure 3 and Figure 4 The conventional squelch detection device and the reference Figure 1 Signal diagram of the described squelch detection device.

[0008] Figure 5 A block diagram of a system including a squelch detection device and a receiver is shown. DETAILED DESCRIPTION

[0009] In the absence of a sufficiently strong input signal, a squelch detector can be used to suppress the output of a device. The squelch detector can be an amplitude envelope detector that distinguishes between a valid signal and noise. In squelch detection, the input common mode signal is compared with a reference voltage (e.g., a threshold voltage) to determine whether the voltage level of the input common mode signal exceeds the reference voltage. If the input signal is lower than the reference voltage, the signal can be attributed to noise or static electricity. The signal level can be determined to be a logical zero. Conversely, if the voltage level is greater than the reference voltage, the input signal can be considered to have a sufficient level, or can be considered to be a logical one.

[0010] The reference voltage can be generated internally and can have a static or constant level. In signaling environments with high noise, process variations, or low supply voltages, the static reference threshold voltage is process independent and intolerant to variations in the common mode of the input signal.

[0011] To make the reference threshold voltage tolerant to variations in the common mode of the input signal, the reference threshold voltage and the common mode of the input signal are averaged (or shorted). The threshold voltage then changes with respect to the average of the reference threshold voltage and the common mode of the input signal.

[0012] Figure 1 A diagram of a squelch detection device 100 is shown. The squelch detection device 100 includes an input signal register-divide operational amplifier 102, a threshold voltage register-divide operational amplifier 104, a plurality of amplifiers (including a first amplifier 106, a second amplifier 108, and a third amplifier 110), and a filter 111. Both the input signal register-divide operational amplifier 102 and the threshold voltage register-divide operational amplifier 104 can be common-mode feedback amplifiers and can have current mirror loads. Operational amplifiers 102 and 104 also perform register-based division as described herein.

[0013] The input signal register divide operational amplifier 102 has a first input for receiving a first input signal (Inp) and a second input for receiving a second input signal (Inn). The first and second input signals can be common-mode signals. The input signal register divide operational amplifier 102 has a first output for outputting a first compensation signal (Vp) and a second compensation signal (Vn). The input signal register divide operational amplifier 102 has a control input for short-circuiting or averaging the midpoints of the first and second compensation signals (Vp and Vn) with the midpoints of the compensation thresholds of the threshold voltage register divide operational amplifier 104 described herein. The input signal register divide operational amplifier 102 and the threshold voltage register divide operational amplifier 104 are coupled to an average common-mode voltage node 109. The average common-mode voltage node 109 has a voltage level that is the average of the common mode of the first and second input signals (Inp and Inn) and the first and second threshold voltages (Vth1 and Vth2).

[0014] The threshold voltage register divide operational amplifier 104 has a first input for receiving a first threshold voltage (Vth1) and a second input for receiving a second threshold voltage (Vth2). The first and second threshold voltages can be common-mode voltages. The threshold voltage register divide operational amplifier 104 has a first output for outputting a first compensated threshold voltage (Vcth1) and a second compensated threshold voltage (Vcth2). The threshold voltage register divide operational amplifier 104 has a control input for short-circuiting or averaging the midpoint of the first and second compensated threshold voltages (Vcth1 and Vcth2) with the midpoint of the first and second compensation signals (Vp and Vn) of the input signal register divide operational amplifier 102 described herein.

[0015] The first amplifier 106 has a first input coupled to the first output of the input signal register divide operational amplifier 102, which may be a non-inverting input. The first amplifier 106 has a second input coupled to the first output of the threshold voltage register divide operational amplifier 104, which may be an inverting input. The first amplifier 106 receives a first compensation signal (Vp) and a first compensation threshold voltage (Vcth1). The first amplifier 106 compares the first compensation signal (Vp) with the first compensation threshold voltage (Vcth1) and outputs a signal based on the comparison. The voltage level of the output signal may be a function of the difference between the first compensation signal (Vp) and the first compensation threshold voltage (Vcth1).

[0016] The second amplifier 108 has a first input coupled to the second output of the input signal register divide operational amplifier 102, and the first input may be a non-inverting input. The second amplifier 108 has a second input coupled to the second output of the threshold voltage register divide operational amplifier 104, and the second input may be an inverting input. The second amplifier 108 receives the second compensation signal (Vn) and the second compensation threshold voltage (Vcth2). The second amplifier 108 compares the second compensation signal (Vn) with the second compensation threshold voltage (Vcth2) and outputs a signal based on the comparison. The voltage level of the output signal may be a function of the difference between the second compensation signal (Vn) and the second compensation threshold voltage (Vcth2).

[0017] The first amplifier 106 and the second amplifier 108 each have a respective output coupled to an input of a third amplifier 110. The third amplifier 110 has an output for providing a muting signal. The third amplifier 110 has a first input coupled to the output of the first amplifier 106, which may be a non-inverting input. The third amplifier 110 has a second input coupled to the output of the second amplifier 108, which may be an inverting input. The third amplifier 110 compares the output of the first amplifier 106 with the output of the second amplifier 108. The third amplifier 110 compares its differential inputs. When the differential amplitude (vp, vn) envelope is greater than the reference threshold (vcth1, vcth2) envelope, the output of the third amplifier 110 toggles. The filter 111 converts the toggled output into a static flag (logic one or "high") signal.

[0018] During operation, the input signal register divide operational amplifier 102 receives first and second input signals (Inp and Inn). The input signal register divide operational amplifier 102 adjusts the common mode of the first and second input signals (Inp and Inn). Specifically, the input signal register divide operational amplifier 102 sets the common mode of the first and second input signals (Inp and Inn) to the average common mode of the input signals (Inp and Inn) and the threshold voltages (Vth1 and Vth2). The input signal register divide operational amplifier 102 outputs the first and second compensation signals (Vp and Vn) having the average common mode as the common mode.

[0019] Similarly, the threshold voltage register divider op amp 104 receives the first and second threshold voltages (Vth1 and Vth2). The threshold voltage register divider op amp 104 adjusts the common mode of the first and second threshold voltages (Vth1 and Vth2). Specifically, the threshold voltage register divider op amp 104 sets the common mode of the first and second threshold voltages (Vth1 and Vth2) to the average common mode of the input signals (Inp and Inn) and the threshold voltages (Vth1 and Vth2). The threshold voltage register divider op amp 104 outputs the first and second compensated threshold voltages (Vcth1 and Vcth2) with the average common mode as the common mode.

[0020] The first amplifier 106 receives a first compensation signal (Vp) and a first compensation threshold voltage (Vcth1), and compares the first compensation signal (Vp) with the first compensation threshold voltage (Vcth1). The first amplifier 106 outputs a first signal having a voltage level that is a function of the difference between the first compensation signal (Vp) and the first compensation threshold voltage (Vcth1). When the first compensation signal (Vp) is greater than the first compensation threshold voltage (Vcth1), the first signal has a positive voltage. When the first compensation signal (Vp) reaches the first compensation threshold voltage (Vcth1), the first signal has a zero voltage.

[0021] The second amplifier 108 receives the second compensation signal (Vn) and the second compensation threshold voltage (Vcth2), and compares the second compensation signal (Vn) with the second compensation threshold voltage (Vcth2). The second amplifier 108 outputs a second signal having a voltage level that is a function of the difference between the second compensation signal (Vn) and the second compensation threshold voltage (Vcth2). When the second compensation signal (Vn) is less than the second compensation threshold voltage (Vcth2), the second signal has a negative voltage. When the second compensation signal (Vn) reaches the second compensation threshold voltage (Vcth2), the second signal has a zero voltage.

[0022] Third amplifier 110 receives the first and second signals output by first amplifier 106 and second amplifier 108, respectively. Third amplifier 110 compares the first and second signals. Third amplifier 110 outputs a switched mute signal that is a function of the difference between the first and second signals. When the voltage level of the first signal is greater than the voltage level of the second signal, the mute signal is asserted. When both the first and second signals have a zero voltage level, or when conditions are reversed such that the second signal has a positive voltage and the first signal has a negative voltage, the mute signal is deasserted.

[0023] During operation, when the first compensation signal (Vp) is greater than the first compensation threshold voltage (Vcth1) and the second compensation signal (Vn) is less than the second compensation threshold voltage (Vcth2), the input signals (Inp and Inn) have voltage levels that meet the established thresholds and are said to be detectable. In this case, the first signal has a positive voltage and the second signal has a negative voltage. Therefore, the mute signal is asserted.

[0024] Conversely, when the first compensation signal (Vp) is less than the first compensation threshold voltage (Vcth1) and the second compensation signal (Vn) is greater than the second compensation threshold voltage (Vcth2), the input signals (Inp and Inn) have voltage levels that do not meet the established thresholds and can be said to be undetectable or can be set to have undesirable voltage levels. In this case, the first signal has a negative voltage and the second signal has a positive voltage. Therefore, the mute signal is deasserted.

[0025] Figure 2 A circuit diagram of input signal and threshold voltage register divide op amps 102 and 104 is shown. Input signal register divide op amp 102 includes a bias transistor 112, first and second input transistors 114 and 116, first and second registers 118 and 120, and first and second load transistors 122 and 124. Threshold voltage register divide op amp 104 includes a bias transistor 132, first and second input transistors 134 and 136, first and second registers 138 and 140, and first and second load transistors 142 and 144.

[0026] In input signal register divide operational amplifier 102, bias transistor 112 has a source coupled to voltage source node 150, a gate for receiving a bias voltage, and a drain coupled to both the source of first input transistor 114 and the source of second input transistor 116. First input transistor 114 has a gate coupled to a first input of operational amplifier 102. The gate receives a first input signal (Inp) via the first input. First input transistor 114 has a drain coupled to a first output of operational amplifier 102. Second input transistor 116 has a gate coupled to a second input of operational amplifier 102. The gate receives a second input signal (Inn) via the second input. Second input transistor 116 has a drain coupled to a second output of operational amplifier 102.

[0027] First load transistor 122 has a drain coupled to the first output of operational amplifier 102, a source coupled to reference voltage node 152, and a gate coupled to average common-mode voltage node 109. Second load transistor 124 has a gate coupled to average common-mode voltage node 109, a drain coupled to the second output of operational amplifier 102, and a source coupled to reference voltage node 152. First register 118 is coupled between the first output of operational amplifier 102 and average common-mode voltage node 109. Second register 120 is coupled between the second output of operational amplifier 102 and average common-mode voltage node 109.

[0028] In the threshold voltage register divide operational amplifier 104, the bias transistor 132 has a source coupled to the voltage source node 150 and is configured to receive a bias voltage (V B ) and a drain coupled to both the source of first input transistor 134 and the source of second input transistor 136. First input transistor 134 has a gate coupled to the first input of operational amplifier 104. The gate receives a first threshold voltage (Vth1) via the first input. First input transistor 124 has a drain coupled to the first output of operational amplifier 104. Second input transistor 136 has a gate coupled to the second input of operational amplifier 104. The gate receives a second threshold voltage (Vth2) via the second input. Second input transistor 136 has a drain coupled to the second output of operational amplifier 104.

[0029] First load transistor 142 has a drain coupled to the first input of operational amplifier 104, a source coupled to reference voltage node 152, and a gate coupled to average common-mode voltage node 109. Second load transistor 144 has a gate coupled to average common-mode voltage node 109, a drain coupled to the second output of operational amplifier 104, and a source coupled to reference voltage node 152. First register 138 is coupled between the first output of operational amplifier 104 and average common-mode voltage node 109. Second register 140 is coupled between the second output of operational amplifier 104 and average common-mode voltage node 109. Input signal register divide operational amplifier 102 and threshold voltage register divide operational amplifier 104 can advantageously be the same device or be constructed identically.

[0030] When the first and second input signals (Inp and Inn) are applied to the gates of the first input transistor 114 and the second input transistor 116, respectively, the voltage levels of the first and second input signals (Inp and Inn) are reflected as the first and second outputs of the operational amplifier 102. The registers 118, 120 average the voltage levels of the first and second input signals (Inp and Inn) and generate a common mode of the first and second input signals (Inp and Inn) at the average common mode voltage node 109. The common mode of the first and second input signals (Inp and Inn) is the average of the first and second input signals (Inp and Inn).

[0031] Similarly, application of the first and second threshold voltages (Vth1 and Vth2) results in a common mode of the first and second threshold voltages (Vth1 and Vth2) being generated at the average common mode voltage node 109. Having received the common mode of the first and second input signals (Inp and Inn) and the common mode of the first and second threshold voltages (Vth1 and Vth2), the average common mode voltage node 109 averages the two common modes.

[0032] Averaging the common mode of the input signals (Inp and Inn) and the common mode of the threshold voltages (Vth1 and Vth2) and using the average common mode to drive the load transistors 122, 124, 142, 144 results in the compensation signals (Vp and Vn) and the second compensation threshold voltages (Vcth1 and Vcth2) having the same common mode voltage.

[0033] In input signal register-dividing operational amplifier 102, an average common-mode voltage is used to drive first load transistor 122 and second load transistor 124. Because load transistors 122 and 124 are driven by the average common-mode voltage, the first and second compensation signals (Vp and Vn) taken from the respective drains of load transistors 122 and 124 have the average common-mode voltage as a common mode. Similarly, in threshold voltage register-dividing operational amplifier 104, the first and second compensation threshold voltages (Vcth1 and Vcth2) taken from the respective drains of load transistors 142 and 144 have the average common-mode voltage as a common mode.

[0034] After forcing the common mode of the compensation signals (Vp and Vn) and the common mode of the compensation threshold voltages (Vcth1 and Vcth2) to be the same, the compensation signals (Vp and Vn) and the compensation threshold voltages (Vcth1 and Vcth2) are compared to determine whether the conditions described herein are met. Figure 1 Described squelch condition.

[0035] Figure 3 and Figure 4 The conventional squelch detection device and the reference Figure 1Signal diagram of the described squelch detection device 100. Figure 3 The signal diagram of includes a first input signal (Inp) 302, a second input signal (Inn) 304, a first threshold voltage (Vth1) 306, a second threshold voltage (Vth2) 308 and a mute signal 310. Figure 3 , the envelope of the first input signal (Inp) 302 is lower than the first threshold voltage (Vth1) 306, which has a voltage level of 220 millivolts (mV). Since the first input signal (Inp) 302 (or its envelope) never exceeds the first threshold voltage (Vth1) 306, the mute signal 310 is continuously de-asserted.

[0036] Figure 4 The signal diagram of FIG3 includes a first compensation input signal (Vp) 312, a second compensation input signal (Vn) 314, a first compensation threshold voltage (Vcth1) 316, a second compensation threshold voltage (Vcth2) 318, and a squelch signal 310. The common mode of the first and second compensation input signals (Vp and Vn) 312, 314 is set or forced to be the average of the common mode of the first and second compensation threshold voltages (Vcth1 and Vcth2) 316, 318 and the common mode of the first and second compensation input signals (Vp and Vn) 312, 314. Therefore, for a duration of operation between approximately 1 microsecond (μs) and 6 μs, the envelope of the first and second compensation input signals (Vp and Vn) 312, 314 surrounds the first and second compensation threshold voltages (Vcth1 and Vcth2) 316, 318. The squelch signal 310 is asserted, which indicates a sufficient voltage level of the input signal compared to the threshold voltage. The squelch signal is de-asserted again after approximately 6 μs, indicating that the voltage level of the input signal is below the required threshold voltage.

[0037] Setting the common mode of the first and second compensating input signals (Vp and Vn) to the average of the common modes may include increasing or decreasing the voltage levels of the first and second input signals (Inp and Inn) by the difference between the average common mode and the common mode of the first and second input signals (Inp and Inn). For example, if the difference between the average common mode and the common mode of the first and second input signals (Inp and Inn) is positive (i.e., the average common mode is greater than the common mode of the first and second input signals (Inp and Inn)), the voltage levels of both the first and second input signals (Inp and Inn) are increased by the difference to generate the first and second compensating input signals (Vp and Vn). Conversely, if the difference between the average common mode and the common mode of the first and second input signals (Inp and Inn) is negative (i.e., the common mode of the first and second input signals (Inp and Inn) is greater than the average common mode), the voltage levels of both the first and second input signals are decreased by the difference to generate the first and second compensating input signals (Vp and Vn). The first and second compensating input signals (Vp and Vn) are copies or replicas of the first and second input signals (Inp and Inn) with their voltage levels or amplitudes adjusted to force their common modes to the average common mode. Similarly, the first and second compensating threshold voltages (Vcth1 and Vcth2) can be generated from the first and second threshold voltages (Vth1 and Vth2).

[0038] In one embodiment, a device including a receiver (such as a universal serial bus (USB) receiver) can receive a squelch signal. The device can use the squelch signal to determine whether to process the first and second input signals (Inp and Inn). The squelch signal, when de-asserted or set to a first state, can cause the device operation to be inhibited. When the squelch signal is de-asserted or set to the first state, the device can stop processing the first and second input signals (Inp and Inn) due to the fact that the first and second input signals (Inp and Inn) are determined to be due to noise, or are determined to be not strong enough to include data or can be reliably processed. When the squelch signal is asserted or set to a second state different from the first state, the device can process the first and second input signals (Inp and Inn).

[0039] Figure 5 A block diagram of a system 500 including a squelch detection device 100 and a receiver 502 is shown. The squelch detection device 100 receives first and second input signals (Inp and Inn) and first and second threshold voltages (Vth1 and Vth2) and outputs a squelch signal as described herein. The receiver 502, which can be a USB receiver in particular, receives the first and second input signals (Inp and Inn) and the squelch signal generated by the squelch detection device 100.

[0040] The state of the squelch signal indicates to the receiver whether the levels (e.g., voltage levels) of the first and second input signals (Inp and Inn) meet a criterion. The state of the squelch signal can indicate to the receiver 502 whether the first and second input signals (Inp and Inn) are attributable to noise or whether they can be reliably received. For example, if the squelch signal has a first state, the receiver 502 can stop processing the first and second input signals (Inp and Inn) due to the fact that the first and second input signals (Inp and Inn) are determined to be attributable to noise, or are determined to be not strong enough to include data or can be reliably processed. When the squelch signal is asserted or set to a second state different from the first state, the receiver 502 can process the first and second input signals (Inp and Inn).

[0041] The various embodiments described above can be combined to provide further embodiments. These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be interpreted to include all possible embodiments and the full range of equivalents to which such claims are entitled. Therefore, the claims are not limited by the disclosure.

Claims

1. A device comprising: a first register-divide operational amplifier configured to: receive a first input signal and a second input signal, determine a first common mode of the first input signal and the second input signal, average the first common mode with a second common mode of a first threshold voltage and a second threshold voltage to produce an average common mode, and generate a first compensation signal and a second compensation signal from the first input signal and the second input signal, respectively, by setting the first common mode of the first input signal and the second input signal to the average common mode; a second register-dividing operational amplifier configured to receive the first threshold voltage and the second threshold voltage and generate a first compensated threshold voltage and a second compensated threshold voltage, respectively, from the first threshold voltage and the second threshold voltage by setting the second common mode of the first threshold voltage and the second threshold voltage to the average common mode; as well as A plurality of amplifiers are configured to receive the first and second compensation signals and the first and second compensation threshold voltages, and output a squelch signal indicating whether the first and second input signals are attributable to noise.

2. The apparatus of claim 1 , wherein the plurality of amplifiers are configured to: comparing the first compensation signal with the first compensation threshold voltage; comparing the second compensation signal with the second compensation threshold voltage; and The squelch signal is set to a first state when the first compensation signal exceeds the first compensation threshold voltage and the second compensation signal is lower than the second compensation threshold voltage.

3. The apparatus of claim 2 , wherein the plurality of amplifiers are configured to: The squelch signal is set to a second state when the first compensation signal does not exceed the first compensation threshold voltage and the second compensation signal exceeds the second compensation threshold voltage.

4. The apparatus of claim 1 , wherein the first register divide operational amplifier is configured to set the first common mode of the first and second input signals to the average common mode by increasing or decreasing a voltage level of the first input signal by a difference between the average common mode and the first common mode, and by increasing or decreasing a voltage level of the second input signal by the difference between the average common mode and the first common mode.

5. The apparatus of claim 1 , wherein the second register divide operational amplifier is configured to set the second common mode of the first and second threshold voltages to the average common mode by increasing or decreasing a voltage level of the first threshold voltage by a difference between the average common mode and the second common mode, and increasing or decreasing a voltage level of the second threshold voltage by the difference between the average common mode and the second common mode.

6. The apparatus of claim 1 , wherein the first register divide-by-operational amplifier comprises: a bias transistor having a source coupled to the voltage source node, a gate for receiving a bias voltage, and a drain; a first input transistor having a gate for receiving the first input signal, a source coupled to the drain of the bias transistor, and a drain for outputting the first compensation signal, the first compensation signal having the first common mode set to the average common mode; a second input transistor having a gate for receiving the second input signal, a source coupled to the drain of the bias transistor, and a drain for outputting the second compensation signal, the second compensation signal having the first common mode set to the average common mode; a first register coupled between the drain of the first input transistor and an average common-mode voltage node; a second register coupled between the drain of the second input transistor and the average common-mode voltage node; a first load transistor having a drain coupled to the drain of the first input transistor, a source coupled to a reference voltage node, and a gate coupled to the average common-mode voltage node; as well as A second load transistor has a drain coupled to the drain of the second input transistor, a source coupled to the reference voltage node, and a gate coupled to the average common-mode voltage node.

7. The apparatus of claim 1 , wherein the second register divide-by-operational amplifier comprises: a bias transistor having a source coupled to the voltage source node, a gate for receiving a bias voltage, and a drain; a first input transistor having a gate for receiving the first threshold voltage, a source coupled to the drain of the bias transistor, and a drain for outputting the first compensated threshold voltage, the first compensated threshold voltage having the second common mode set to the average common mode; a second input transistor having a gate for receiving the second threshold voltage, a source coupled to the drain of the bias transistor, and a drain for outputting the second compensated threshold voltage, the second compensated threshold voltage having the second common mode set to the average common mode; a first register coupled between the drain of the first input transistor and an average common-mode voltage node; a second register coupled between the drain of the second input transistor and the average common-mode voltage node; a first load transistor having a drain coupled to the drain of the first input transistor, a source coupled to a reference voltage node, and a gate coupled to the average common-mode voltage node; as well as A second load transistor has a drain coupled to the drain of the second input transistor, a source coupled to the reference voltage node, and a gate coupled to the average common-mode voltage node.

8. A method comprising: receiving a first input signal and a second input signal; receiving a first threshold voltage and a second threshold voltage; determining a first common mode of the first input signal and the second input signal; determining a second common mode of the first threshold voltage and the second threshold voltage; averaging the first common mode and the second common mode to produce an average common mode; generating first and second compensation signals from the first and second input signals, respectively, by setting the first common mode of the first and second input signals to the average common mode; generating a first compensated threshold voltage and a second compensated threshold voltage, respectively, from the first threshold voltage and the second threshold voltage by setting the second common mode of the first threshold voltage and the second threshold voltage to the average common mode; as well as A state of a squelch signal is determined based on the first and second compensation signals and the first and second compensation threshold voltages, the squelch signal indicating whether the first and second input signals are attributable to noise.

9. The method according to claim 8, comprising: comparing the first compensation signal with the first compensation threshold voltage; comparing the second compensation signal with the second compensation threshold voltage; as well as The squelch signal is set to a first state when the first compensation signal exceeds the first compensation threshold voltage and the second compensation signal is lower than the second compensation threshold voltage.

10. The method according to claim 9, comprising: The squelch signal is set to a second state when the first compensation signal does not exceed the first compensation threshold voltage and the second compensation signal exceeds the second compensation threshold voltage.

11. The method of claim 8, wherein setting the first common mode of the first input signal and the second input signal to the average common mode comprises: increasing or decreasing the voltage level of the first input signal by the difference between the average common mode and the first common mode, and The voltage level of the second input signal is increased or decreased by the difference between the average common mode and the first common mode.

12. The method of claim 8, wherein setting the second common mode of the first threshold voltage and the second threshold voltage to the average common mode comprises: increasing or decreasing the voltage level of the first threshold voltage by a difference between the average common mode and the second common mode, and The voltage level of the second threshold voltage is increased or decreased by the difference between the average common mode and the second common mode.

13. The method of claim 8, wherein determining the first common mode and averaging the first common mode with the second common mode is performed by a first register-divide operational amplifier, the first register-divide operational amplifier comprising: a bias transistor having a source coupled to the voltage source node, a gate for receiving a bias voltage, and a drain; a first input transistor having a gate for receiving the first input signal, a source coupled to the drain of the bias transistor, and a drain for outputting the first compensation signal, the first compensation signal having the first common mode set to the average common mode; a second input transistor having a gate for receiving the second input signal, a source coupled to the drain of the bias transistor, and a drain for outputting the second compensation signal, the second compensation signal having the first common mode set to the average common mode; a first register coupled between the drain of the first input transistor and an average common-mode voltage node; a second register coupled between the drain of the second input transistor and the average common-mode voltage node; a first load transistor having a drain coupled to the drain of the first input transistor, a source coupled to a reference voltage node, and a gate coupled to the average common-mode voltage node; as well as A second load transistor has a drain coupled to the drain of the second input transistor, a source coupled to the reference voltage node, and a gate coupled to the average common-mode voltage node.

14. The method of claim 8, wherein determining the second common mode and averaging the first common mode with the second common mode is performed by a second register-divide operational amplifier, the second register-divide operational amplifier comprising: a bias transistor having a source coupled to the voltage source node, a gate for receiving a bias voltage, and a drain; a first input transistor having a gate for receiving the first threshold voltage, a source coupled to the drain of the bias transistor, and a drain for outputting the first compensated threshold voltage, the first compensated threshold voltage having the second common mode set to the average common mode; a second input transistor having a gate for receiving the second threshold voltage, a source coupled to the drain of the bias transistor, and a drain for outputting the second compensated threshold voltage, the second compensated threshold voltage having the second common mode set to the average common mode; a first register coupled between the drain of the first input transistor and an average common-mode voltage node; a second register coupled between the drain of the second input transistor and the average common-mode voltage node; a first load transistor having a drain coupled to the drain of the first input transistor, a source coupled to a reference voltage node, and a gate coupled to the average common-mode voltage node; as well as A second load transistor has a drain coupled to the drain of the second input transistor, a source coupled to the reference voltage node, and a gate coupled to the average common-mode voltage node.

15. A system comprising: Noise detection equipment, including: a first register-divide operational amplifier configured to: receive a first input signal and a second input signal, determine a first common mode of the first input signal and the second input signal, average the first common mode with a second common mode of a first threshold voltage and a second threshold voltage to produce an average common mode, and generate a first compensation signal and a second compensation signal from the first input signal and the second input signal, respectively, by setting the first common mode of the first input signal and the second input signal to the average common mode; a second register-dividing operational amplifier configured to receive the first threshold voltage and the second threshold voltage and generate a first compensated threshold voltage and a second compensated threshold voltage, respectively, from the first threshold voltage and the second threshold voltage by setting the second common mode of the first threshold voltage and the second threshold voltage to the average common mode; and a plurality of amplifiers configured to: receive the first and second compensation signals and the first and second compensation threshold voltages, and output a squelch signal indicating whether the first and second input signals are attributable to noise; and A receiver is configured to receive the squelch signal and the first and second input signals, and suppress processing of the first and second input signals based on the squelch signal.

16. The system of claim 15, wherein the plurality of amplifiers are configured to: comparing the first compensation signal with the first compensation threshold voltage; comparing the second compensation signal with the second compensation threshold voltage; and The squelch signal is set to a first state when the first compensation signal exceeds the first compensation threshold voltage and the second compensation signal is lower than the second compensation threshold voltage.

17. The system of claim 16, wherein the plurality of amplifiers are configured to: The squelch signal is set to a second state when the first compensation signal does not exceed the first compensation threshold voltage and the second compensation signal exceeds the second compensation threshold voltage.

18. The system of claim 15 , wherein the first register divide operational amplifier is configured to set the first common mode of the first and second input signals to the average common mode by increasing or decreasing the voltage level of the first input signal by the difference between the average common mode and the first common mode, and increasing or decreasing the voltage level of the second input signal by the difference between the average common mode and the first common mode.

19. The system of claim 15 , wherein the second register divide operational amplifier is configured to set the second common mode of the first and second threshold voltages to the average common mode by increasing or decreasing a voltage level of the first threshold voltage by a difference between the average common mode and the second common mode, and increasing or decreasing a voltage level of the second threshold voltage by the difference between the average common mode and the second common mode.

20. The system of claim 15, wherein the first register divide-by-operational amplifier comprises: a bias transistor having a source coupled to the voltage source node, a gate for receiving a bias voltage, and a drain; a first input transistor having a gate for receiving the first input signal, a source coupled to the drain of the bias transistor, and a drain for outputting the first compensation signal, the first compensation signal having the first common mode set to the average common mode; a second input transistor having a gate for receiving the second input signal, a source coupled to the drain of the bias transistor, and a drain for outputting the second compensation signal, the second compensation signal having the first common mode set to the average common mode; a first register coupled between the drain of the first input transistor and an average common-mode voltage node; a second register coupled between the drain of the second input transistor and the average common-mode voltage node; a first load transistor having a drain coupled to the drain of the first input transistor, a source coupled to a reference voltage node, and a gate coupled to the average common-mode voltage node; as well as A second load transistor has a drain coupled to the drain of the second input transistor, a source coupled to the reference voltage node, and a gate coupled to the average common-mode voltage node.

21. The system of claim 15, wherein the second register divide-by-operational amplifier comprises: a bias transistor having a source coupled to the voltage source node, a gate for receiving a bias voltage, and a drain; a first input transistor having a gate for receiving the first threshold voltage, a source coupled to the drain of the bias transistor, and a drain for outputting the first compensated threshold voltage, the first compensated threshold voltage having the second common mode set to the average common mode; a second input transistor having a gate for receiving the second threshold voltage, a source coupled to the drain of the bias transistor, and a drain for outputting the second compensated threshold voltage, the second compensated threshold voltage having the second common mode set to the average common mode; a first register coupled between the drain of the first input transistor and an average common-mode voltage node; a second register coupled between the drain of the second input transistor and the average common-mode voltage node; a first load transistor having a drain coupled to the drain of the first input transistor, a source coupled to a reference voltage node, and a gate coupled to the average common-mode voltage node; as well as A second load transistor has a drain coupled to the drain of the second input transistor, a source coupled to the reference voltage node, and a gate coupled to the average common-mode voltage node.

Images