Switch layout

Abstract

A switching arrangement includes a transceiver node coupled to a first circuit branch and a second circuit branch, the first circuit branch including a transmit node and the second circuit branch including a receive node; wherein the first circuit branch includes an inductor coupled in series and a first semiconductor switch coupled in parallel, the first semiconductor switch being configured to provide switch coupling to a reference voltage; and wherein the second circuit branch includes one of the following: 1) a second semiconductor switch and a third semiconductor switch; and 2) the second semiconductor switch and the third semiconductor switch, the third semiconductor switch being configured to control application of a supply voltage to an amplifier; and 3) another semiconductor switch, the other semiconductor switch being configured to control application of a bias current to the amplifier; wherein in a first switching mode, impedance matching is provided between the transceiver node and the transmit node; and in a second switching mode, impedance matching is provided between the transceiver node and the receive node.

Description

Technical Field

[0001] The present disclosure relates to a switch arrangement. Specifically, the present disclosure relates to a switch arrangement for switching between a receive path and a transmit path of a transceiver. The present disclosure also relates to a corresponding method and a communication device. Background Art

[0002] A communication device, such as a half-duplex communication device, may include a switch arrangement to provide selection of a receive path or a transmit path. The switch arrangement may be part of an RF front-end circuitry of the communication device. Summary of the Invention

[0003] According to a first aspect of the present disclosure, there is provided a switch arrangement comprising:

[0004] a transceiver node for coupling to a transceiver, the transceiver node for receiving signaling to be transmitted and for providing the received signaling based on whether the switch arrangement is in a first switching mode or a second switching mode, the transceiver node being coupled to a first circuit branch and a second circuit branch, the first circuit branch including one of a transmitting node for connecting to a transmitting path and a receiving node for connecting to a receiving path, the second circuit branch including the other of the transmitting node and the receiving node;

[0005] wherein the first circuit branch includes an inductor coupled in series between the transceiver node and the one of the transmit node and the receive node, and a first semiconductor switch coupled to and in parallel with the one of the transmit node and the receive node, and the first semiconductor switch is configured to provide a switched coupling to a reference voltage; and

[0006] The second circuit branch includes one of the following:

[0007] i) a second semiconductor switch coupled in series between the transceiver node and the other of the transmitting node and the receiving node; and a third semiconductor switch coupled to and in parallel with the other of the transmitting node and the receiving node; and

[0008] ii) a second semiconductor switch coupled in series between the transceiver node and the other of the transmitting node and the receiving node; an amplifier coupled to the other of the transmitting node and the receiving node; and a third semiconductor switch configured to control application of a supply voltage to the amplifier to control coupling of the other of the transmitting node and the receiving node to the reference voltage through the amplifier; and

[0009] iii) an amplifier coupled to the other of the transmitting node and the receiving node; and a further semiconductor switch configured to control application of a bias current to the amplifier to control coupling of the other of the transmitting node and the receiving node to the reference voltage through the amplifier;

[0010] wherein in the first switching mode, the first semiconductor switch is open and thereby configured to provide a capacitance in parallel with the inductor, and one of the second semiconductor switch and the third semiconductor switch or the further semiconductor switch is configured to provide a capacitance coupled in parallel between the inductor and the reference voltage to substantially provide impedance matching between the transceiver node and the one of the transmit node and the receive node; and

[0011] wherein in the second switching mode, the first semiconductor switch is closed and thereby couples the inductor and the one of the transmit node and the receive node to the reference voltage, and the one of the second semiconductor switch and the third semiconductor switch or the further semiconductor switch is configured to couple the inductor in parallel to the reference voltage via a capacitance to substantially provide impedance matching between the transceiver node and the other of the transmit node and the receive node.

[0012] In one or more examples, in the first switching mode, the third semiconductor switch can provide coupling of the second branch to a reference voltage, which provides an impedance mismatch between the transceiver node and the other of the transmitting node and the receiving node, thereby allowing impedance matching on the first branch. In one or more examples, in the second switching mode, the first semiconductor switch can provide coupling of the first branch to a reference voltage, which provides an impedance mismatch between the transceiver node and the one of the transmitting node and the receiving node, thereby allowing impedance matching on the second branch.

[0013] In one or more examples, the amplifier includes a first terminal, a second terminal, and a third terminal, wherein the first terminal is coupled to the third semiconductor switch and the other of the transmit node and the receive node (e.g., via a DC blocking capacitor), and wherein the second terminal is configured to be coupled to the reference voltage, and the third terminal is configured to be coupled to a remaining portion of the other of the transmit path or the receive path.

[0014] In one or more examples, the amplifier includes a first terminal, a second terminal, and a third terminal, wherein the first terminal is coupled to a voltage supply node and to the other of the transmit node and the receive node via an inductor (e.g., via a DC blocking capacitor), and wherein the second terminal is configured to be coupled to the reference voltage, and the third terminal is configured to be coupled to a remaining portion of the other of the transmit path or the receive path, wherein the bias current is applied at the third terminal.

[0015] In one or more embodiments, the second circuit branch is free of an inductor.

[0016] In one or more examples, the second circuit branch lacks an inductor between the transceiver node and the other of the transmit node and the receive node. In one or more examples, the second circuit branch lacks an inductor connected in series between the transceiver node and the other of the transmit node and the receive node. In one or more examples, the switch arrangement is formed on an integrated circuit, and the second circuit branch lacks an inductor formed as part of the integrated circuit.

[0017] In one or more embodiments,

[0018] In the first switching mode, the semiconductor switches provide for forming a CLC circuit in the first branch and the second branch, the CLC circuit being configured to substantially provide impedance matching between the transceiver node and the one of the transmitting node and the receiving node; and

[0019] In the second switching mode, the semiconductor switches provide for forming parallel LC tank circuits in the first branch and the second branch, the parallel LC tank circuits being configured to substantially provide impedance matching between the transceiver node and the other of the transmitting node and the receiving node.

[0020] In one or more examples, the first semiconductor switch includes a node for providing a switch connection to the reference voltage. In one or more examples, the reference voltage is ground.

[0021] In one or more embodiments, the third semiconductor switch is configured to provide a switch connection to a reference voltage, and wherein in the first mode, the third semiconductor switch is configured to be closed, and in the second mode, the third switch is configured to be open. In one or more examples, the third semiconductor switch includes a node for providing a switch connection to the reference voltage. In one or more examples, the reference voltage is ground.

[0022] In one or more embodiments, the third semiconductor switch comprises part of an amplifier arrangement and is configured to control application of a supply voltage to the amplifier, wherein in the first mode, the third switch is open and the amplifier of the amplifier arrangement is configured to provide coupling to a reference voltage through the amplifier, and wherein in the second mode, the third switch is closed and the amplifier is provided with the supply voltage.

[0023] In one or more embodiments, the amplifier arrangement includes a series arrangement of a supply node, an npn transistor and a further inductor, the supply node being used to receive the supply voltage, the third semiconductor switch being configured to control application of the supply voltage to the amplifier, the npn transistor including a collector terminal coupled to the further inductor and an emitter terminal for connection to the reference voltage, the other of the transmitting node and the receiving node being coupled between the further inductor and the collector terminal of the npn transistor, the amplifier arrangement further including a decoupling capacitor having a first plate coupled to a node between the third semiconductor switch and the inductor and a second plate for connection to the reference voltage.

[0024] In one or more embodiments, the switch arrangement includes an amplifier arrangement coupled to the other of the transmit node and the receive node, the amplifier arrangement comprising a series arrangement of a supply node, a further inductor, and an npn transistor, the supply node being for receiving a supply voltage, the npn transistor comprising a collector terminal coupled to the inductor and an emitter terminal for connecting to the reference voltage, the other of the transmit node and the receive node being coupled to a node between the inductor and the collector terminal via a DC blocking capacitor, the amplifier arrangement further comprising a bias circuit coupled to a base terminal of the transistor and configured to apply a bias current to the base terminal, the application of the bias current being controlled by the further semiconductor switch;

[0025] wherein in the first switching mode, the further semiconductor switch is off and the bias voltage is not applied to the base terminal; and

[0026] In the second switching mode, the further semiconductor switch is closed and the bias voltage is applied to the base terminal.

[0027] In one or more embodiments,

[0028] The first circuit branch includes a transmit branch and is coupled to the transmit node;

[0029] The second circuit branch includes a receive branch and is coupled to the receive node;

[0030] The first switching mode comprises a transmit mode that provides impedance matching between a transceiver node and the transmit node, thereby enabling signaling to pass from the transceiver node to the transmit node; and

[0031] The second switching mode includes a receive mode that provides impedance matching between a transceiver node and the receive node, thereby enabling signaling to pass from the receive node to the transceiver node.

[0032] In one or more examples, the switch arrangement includes a quarter-wave single-pole double-throw switch arrangement.

[0033] In one or more embodiments, the switch arrangement comprises a differential switch arrangement, the transceiver node comprises a positive transceiver node and a negative transceiver node, the transmitting node comprises a positive transmitting node and a negative transmitting node, and the receiving node comprises a positive receiving node and a negative receiving node;

[0034] wherein the first circuit branch includes a first positive circuit branch and a first negative circuit branch coupled to respective positive and negative transmit nodes, and wherein the inductor includes a first inductor in the first positive circuit branch and a second inductor in the first negative circuit branch, the first inductor being coupled in series between the positive transceiver node and the positive transmit node, and the second inductor being coupled in series between the negative transceiver node and the negative transmit node, and the first semiconductor switch being coupled in parallel with both the positive and negative transmit nodes; and

[0035] wherein the second circuit branch comprises a second positive circuit branch and a second negative circuit branch coupled to respective positive and negative receive nodes, and wherein the second semiconductor switch comprises a pair of switches including a second positive semiconductor switch and a second negative semiconductor switch, the second positive circuit branch comprises the second positive semiconductor switch coupled in series between the positive transceiver node and the positive receive node, and the second negative circuit branch comprises the second negative semiconductor switch coupled in series between the negative transceiver node and the negative receive node, and the third semiconductor switch is connected in parallel with both the positive and negative receive nodes.

[0036] In one or more embodiments, one of the following:

[0037] the first semiconductor switch comprises a pair of first semiconductor switches, and a first of the pair is configured to provide a switched connection to a reference voltage for the first positive circuit branch, and a second of the pair is configured to provide a switched connection to the reference voltage for the first negative circuit branch; and

[0038] The first semiconductor switch is configured to provide a switch connection configured to couple the first positive circuit branch and the first negative circuit branch.

[0039] In one or more embodiments, one of the following:

[0040] the third semiconductor switch comprises a pair of third semiconductor switches, each of the pair being configured to provide a switch connection to a reference voltage for each of the second positive circuit branch and the second negative circuit branch; and

[0041] The third semiconductor switch is configured to provide a switching connection between the second positive circuit branch and the second negative circuit branch.

[0042] In one or more embodiments, the first semiconductor switch and the third semiconductor switch include one of the following:

[0043] a MOS transistor having a drain terminal coupled to the respective transmit node and the receive node and a source terminal for connecting to a reference voltage;

[0044] a reverse saturation mode npn transistor having a collector terminal coupled to respective transmit nodes and the receive node and an emitter terminal for connection to a reference voltage;

[0045] a forward saturation mode npn transistor having an emitter terminal coupled to respective transmit nodes and the receive node and a collector terminal for connection to a reference voltage; and

[0046] A pin diode has a cathode coupled to the corresponding transmit node and the receive node and an anode coupled to a reference voltage through a capacitor.

[0047] In one or more embodiments, the second series semiconductor switch includes one of the following:

[0048] a MOS transistor having a drain terminal coupled to the second branch via a capacitor, a source terminal coupled to the second branch via a capacitor, and a gate terminal, the source terminal, the drain terminal, and the gate terminal being configured to receive respective control signals for controlling the switch;

[0049] an npn transistor having a collector terminal coupled to the second branch via a capacitor, an emitter terminal coupled to the second branch via a capacitor, and a base terminal, the collector terminal, the emitter terminal, and the base terminal configured to receive respective control signals for controlling the switch; and

[0050] A diode has a cathode coupled to the second branch via a capacitor, an anode coupled to the second branch via a capacitor, and the anode and the cathode are configured to receive respective control signals for controlling the switch.

[0051] In one or more embodiments, the switch arrangement is formed as an integrated circuit on a semiconductor die, wherein the transceiver node, the transmit node, and the receive node provide connections to and from the semiconductor die.

[0052] According to a second aspect of the present disclosure, there is provided a method of operating a switch arrangement, the switch arrangement comprising:

[0053] a transceiver node for coupling to a transceiver, the transceiver node for receiving signaling to be transmitted and for providing the received signaling based on whether the switch arrangement is in a first switching mode or a second switching mode, the transceiver node being coupled to a first circuit branch and a second circuit branch, the first circuit branch including one of a transmitting node for connecting to a transmitting path and a receiving node for connecting to a receiving path, the second circuit branch including the other of the transmitting node and the receiving node;

[0054] wherein the first circuit branch includes an inductor coupled in series between the transceiver node and the one of the transmit node and the receive node, and a first semiconductor switch coupled to and in parallel with the one of the transmit node and the receive node, and the first semiconductor switch is configured to provide a switched coupling to a reference voltage; and

[0055] The second circuit branch includes one of the following:

[0056] i) a second semiconductor switch coupled in series between the transceiver node and the other of the transmitting node and the receiving node; and a third semiconductor switch coupled to and in parallel with the other of the transmitting node and the receiving node; and

[0057] ii) a second semiconductor switch coupled in series between the transceiver node and the other of the transmitting node and the receiving node; an amplifier coupled to the other of the transmitting node and the receiving node; and a third semiconductor switch configured to control application of a supply voltage to the amplifier to control coupling of the other of the transmitting node and the receiving node to the reference voltage via a capacitor through the amplifier; and

[0058] iii) an amplifier coupled to the other of the transmitting node and the receiving node; and a further semiconductor switch configured to control application of a bias current to the amplifier to control coupling of the other of the transmitting node and the receiving node to the reference voltage through the amplifier;

[0059] wherein the method comprises employing a first switching mode in which the first semiconductor switch is open and thereby configured to provide a capacitance in parallel with the inductor, and one of the second semiconductor switch and the third semiconductor switch or the further semiconductor switch is configured to provide a capacitance coupled in parallel between the inductor and the reference voltage to substantially provide impedance matching between the transceiver node and the one of the transmit node and the receive node; and

[0060] The method includes employing a second switching mode in which the first semiconductor switch is closed and thereby couples the inductor and the one of the transmit node and the receive node to the reference voltage, and the one of the second and third semiconductor switches or the further semiconductor switch is configured to capacitively couple the inductor in parallel to the reference voltage to substantially provide impedance matching between the transceiver node and the other of the transmit node and the receive node.

[0061] According to a third aspect of the present disclosure, there is provided a communication device comprising a switch arrangement according to the first aspect, the communication device comprising one or more antennas coupled to the transmitting node and the receiving node via one or more amplifiers, and a signal processing element coupled to the transceiver node for providing communication functionality, the switch mode being operable to provide half-duplex signaling transmission and reception performed by the communication device.

[0062] According to a fourth aspect of the present disclosure, there is provided a switch arrangement, comprising:

[0063] a transceiver node for coupling to a transceiver, the transceiver node for receiving signaling to be transmitted and for providing the received signaling based on whether the switch arrangement is in a first switching mode or a second switching mode, the transceiver node being coupled to a first circuit branch and a second circuit branch, the first circuit branch including one of a transmitting node for connecting to a transmitting path and a receiving node for connecting to a receiving path, the second circuit branch including the other of the transmitting node and the receiving node;

[0064] wherein the first circuit branch includes an inductor coupled in series between the transceiver node and the one of the transmit node and the receive node, and a first semiconductor switch coupled to and in parallel with the one of the transmit node and the receive node, and the first semiconductor switch is configured to provide a switched coupling to a reference voltage; and

[0065] The second circuit branch includes one of the following:

[0066] i) a second semiconductor switch coupled in series between the transceiver node and the other of the transmitting node and the receiving node; and a third semiconductor switch coupled to and in parallel with the other of the transmitting node and the receiving node; and

[0067] ii) a second semiconductor switch coupled in series between the transceiver node and the other of the transmitting node and the receiving node; an amplifier coupled to the other of the transmitting node and the receiving node; and a third semiconductor switch configured to control application of a supply voltage to the amplifier to control coupling of the other of the transmitting node and the receiving node to the reference voltage through the amplifier; and

[0068] iii) an amplifier coupled to the other of the transmitting node and the receiving node; and a further semiconductor switch configured to control application of a bias current to the amplifier to control coupling of the other of the transmitting node and the receiving node to the reference voltage through the amplifier;

[0069] wherein in the first switching mode, the switch is configured to provide a CLC network to provide impedance matching between the transceiver node and the one of the transmitting node and the receiving node; and

[0070] Wherein in the second switching mode, the switch is configured to provide a parallel LC energy tank network to provide impedance matching between the transceiver node and the other of the transmitting node and the receiving node.

[0071] Although the present disclosure is susceptible to various modifications and alternative forms, details of the disclosure have been shown by way of example in the accompanying drawings and will be described in detail. However, it should be understood that other embodiments are possible in addition to the specific embodiments described. All modifications, equivalents, and alternative embodiments that fall within the spirit and scope of the appended claims are also encompassed.

[0072] The above discussion is not intended to represent every example embodiment or every implementation within the scope of the current or future claim groups. The following figures and detailed description also illustrate various example embodiments. When the following detailed description is considered in conjunction with the drawings, the various example embodiments can be more thoroughly understood. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

[0074] Figure 1 A first example known switch arrangement is shown;

[0075] Figure 2 A second example known switch arrangement is shown;

[0076] Figure 3 An example embodiment of a switch arrangement is shown;

[0077] Figure 4 Shown in the first switching mode Figure 3 Switch arrangement;

[0078] Figure 5 Shown in the first switching mode Figure 3 Equivalent circuit of the switch arrangement;

[0079] Figure 6 Shown in the second switching mode Figure 3 Switch arrangement;

[0080] Figure 7 Shown in the second switching mode Figure 3 Equivalent circuit of the switch arrangement;

[0081] Figure 8 A first example embodiment of a semiconductor switch is shown;

[0082] Figure 9 A second example embodiment of a semiconductor switch is shown;

[0083] Figure 10 A third example embodiment of a semiconductor switch is shown;

[0084] Figure 11 A fourth example embodiment of a semiconductor switch is shown;

[0085] Figure 12 Shown Figure 3 an example embodiment of , wherein a receiving amplifier is shown in more detail;

[0086] Figure 13 A second example embodiment of a switch arrangement is shown;

[0087] Figure 14 Shown in the first switching mode Figure 13 Switch arrangement;

[0088] Figure 15 Shown in the second switching mode Figure 13 Switch arrangement;

[0089] Figure 16 A third example embodiment of a switch arrangement is shown;

[0090] Figure 17 A third example is shown in the first switching mode;

[0091] Figure 18 A third example is shown in the second switching mode;

[0092] Figure 19 A third example embodiment of a switch arrangement is shown;

[0093] Figure 20 A fourth example embodiment of a switch arrangement is shown;

[0094] Figure 21 A first example embodiment of a second semiconductor switch is shown;

[0095] Figure 22 A second example embodiment of a second semiconductor switch is shown;

[0096] Figure 23 A third example embodiment of a second semiconductor switch is shown;

[0097] Figure 24 A fourth example embodiment of a second semiconductor switch is shown;

[0098] Figure 25 An example method of operating the switch arrangement is shown; and

[0099] Figure 26 An example communication device is shown. DETAILED DESCRIPTION

[0100] The switch arrangement can be used in various electronic devices such as half-duplex communication devices. The switch arrangement can be used within the field of communication devices or outside the field of communication devices to provide a substantially impedance matched path to a first node but not a second node in a first switching mode, and to provide a substantially impedance matched path to the second node but not the first node in a second switching mode. Thus, the switch arrangement can provide selectable coupling based on a preferred impedance match between a receive path, in which signaling is received and provided to a transceiver node, and a transmit path, in which signaling from the transceiver node is provided to a transmit path. However, more generally, the switch arrangement can provide selection of a receive path or a transmit path (i.e., coupling to a receive path or a transmit path) relative to a transceiver node. The switch arrangement can be part of the RF front-end circuitry of a communication device. The present disclosure describes various embodiments of a single-pole double-throw (SPDT) switch arrangement. The present disclosure describes various embodiments of a quarter-wavelength switch arrangement.

[0101] Figure 1 and Figure 2 A known quarter wavelength SPDT switch arrangement is shown. Figure 1A known switching arrangement 100 includes a transceiver node 101 through which signaling to be transmitted and received signaling are passed. Arrangement 100 includes a transmit branch 102, which couples transceiver node 101 to a transmit node 103. Transmitting node 103 is typically coupled to an amplifier 104 for onward transmission of signaling passed through transmit branch 102. Arrangement 100 further includes a receive branch 105, which couples transceiver node 101 to a receive node 106. Receive node 106 is typically coupled to an amplifier 107 for amplifying received signaling received by amplifier 107 for passing through the receive branch to transceiver node 101. Both transmit branch 102 and receive branch 105 include at least one inductor 108, 109. Thus, arrangement 100 includes at least two inductors. The transmit branch 102 and the receive branch 105 include switches 110, 111. Operation of the switches 110, 111 provides for selection of one of the receive path 102 and the transmit path 105 according to a preferred impedance match between the transceiver node 101 and the corresponding transmit node 103 or receive node 106.

[0102] Figure 2 The known switch arrangement 200 and Figure 1 The known switch arrangement is basically similar to Figure 2 2 . A known differential quarter-wavelength SPDT switch arrangement 200 is shown. Thus, the transceiver nodes include a positive transceiver node 201 and a negative transceiver node 202, the transmit nodes include a positive transmit node 203 and a negative transmit node 204, and the receive nodes include a positive receive node 205 and a negative receive node 206. Transmit path 207 further includes a pair of transmit paths, and receive path 208 includes a pair of receive paths. The pair of transmit paths each include inductors 209 and 210. The pair of receive paths each include inductors 211 and 212. Thus, the known differential quarter-wavelength SPDT switch arrangement 200 includes at least four inductors.

[0103] Such a switch arrangement may be embodied as an integrated circuit.The inductors 108, 109, 209, 210, 211, 212 may be area dense on the die of the integrated circuit.

[0104] Figure 3An example embodiment is shown that includes a switching arrangement 300. The switching arrangement 300 may include a quarter-wavelength SPDT-type switching arrangement. The switching arrangement 300 includes a transceiver node 301, through which transmitted and received signaling is communicated. The arrangement 300 includes a first branch, in this example, a transmit branch 302 that couples the transceiver node 301 to a transmit node 303. The transmit node 303 is typically coupled to an amplifier 304, such as directly or through other components, to forward the signaling communicated through the transmit branch 302. The arrangement 300 further includes a second branch, in this example, a receive branch 305 that is separate from and connected in parallel with the transmit branch. The receive branch 305 couples the transceiver node 301 to a receive node 306. The receiving node 306 is typically coupled to an amplifier 307 to amplify received signaling received by the amplifier 307 to be passed through the receiving node 306 and the receiving branch 305, such as directly or through other components, to the transceiver node 301. In this example and one or more examples, the transmit branch 302 and the receive branch 305 extend from the transceiver node 301, such as directly from the transceiver node 301.

[0105] It should be understood that in other examples, the first branch may include a receive branch and the second branch may include a transmit branch, and thus, these branches may be coupled to the other of the transmit node and the receive node.

[0106] The switch arrangement 300 (or any of the example switch arrangements described herein) can be integrated into an integrated circuit. The transceiver node 301, as well as the transmit node 303 and the receive node 306, can represent connections to / from the integrated circuit. Thus, in one or more examples, the amplifiers 304, 307 can be located outside the integrated circuit and, therefore, outside the switch arrangement 300. In other examples, the amplifiers 304, 307 or an amplifier arrangement (described later) can be part of the switch arrangement 300 and may or may not be part of the integrated circuit.

[0107] The switch arrangement 300 provides a selection of a transmit branch 302 or a receive branch, so that the transceiver node 301 can receive signaling to be transmitted through the transmit branch 302 and the transmit node 303 from outside the switch arrangement 300, and at different times, the transceiver node 301 can receive received signaling from the receive node 306 through the receive branch 305. The switch arrangement 300 can provide the selection based on whether the switch arrangement 100 is in the first switching mode or the second switching mode.

[0108] In one or more examples, first or transmit circuit branch 302 includes an inductor 310 coupled in series between transceiver node 301 and transmit node 303. In one or more examples, inductor 310 can be directly coupled to the transceiver node in the transmit branch, i.e., with no intervening electrical components or with one or more electrical components therebetween. First or transmit branch 302 includes a first semiconductor switch 311 coupled to and in parallel with transmit node 303. Thus, a first end 312 of first semiconductor switch 311 can be coupled to node 313 between inductor 310 and transmit node 303, and a second end 314 of first semiconductor switch 311 can be uncoupled from any other components or can be coupled to one or more other components. Although node 313 and node 303 are shown separately, it should be understood that node 313 and node 303 can actually be the same node. In one or more examples, second end 314 is configured to couple to or be coupled to a reference voltage, such as ground 315. Thus, when the switch arrangement is in use, the second terminal 314 can be coupled to a node for coupling to a reference voltage. In this example and one or more examples, the first semiconductor switch 311 can be directly coupled to the inductor 310, e.g., without a capacitor and / or additional inductor therebetween. Independently, in this example and one or more examples, the first semiconductor switch 311 can be directly coupled to the transmit node 303, e.g., without a capacitor and / or additional inductor and / or other components therebetween. Thus, the first semiconductor switch 311 can provide a switched connection to the reference voltage 315. The first semiconductor switch 311 can be considered a first parallel switch. The state of the first semiconductor switch 311 (i.e., open or closed) can be controlled by a control signal applied to the control terminal of the first semiconductor switch 311.

[0109] In one or more examples, the second or receiving circuit branch 305 includes a second semiconductor switch 316 coupled in series between the transceiver node 301 and the receiving node 306. In one or more examples, the second semiconductor switch 316 can be coupled directly to the transceiver node 301, i.e., without intervening electrical components in the receiving branch, or with one or more electrical components therebetween. The second or receiving branch 305 includes a third semiconductor switch 317 (e.g., a second parallel switch) coupled to the receiving node 306 and connected in parallel with the receiving node. Thus, a first end 318 of the third semiconductor switch 317 can be coupled to a node 319 between the second semiconductor switch 316 and the receiving node 306, and a second end 320 of the third semiconductor switch 317 can be uncoupled from any additional components or can be coupled to one or more additional components. In one or more examples, the second end 320 is configured to couple to or be coupled to a reference voltage, such as ground 315. Thus, when the switch arrangement is in use, the second end 320 can be coupled to a node configured to couple to a reference voltage. In this example and one or more examples, the third semiconductor switch 317 can be directly coupled to the inductor 310, e.g., without a capacitor and / or another inductor therebetween. Separately, in this example and one or more examples, the third semiconductor switch 317 can be directly coupled to the transmit node 303, e.g., without a capacitor and / or another inductor therebetween and / or other components therebetween. The state (i.e., open or closed) of the second semiconductor switch 316 or the third semiconductor switch can be controlled by a control signal applied to a control terminal of the second semiconductor switch 316 or the third semiconductor switch 317.

[0110] Operations of the first semiconductor switch 311 , the second semiconductor switch 316 , and the third semiconductor switch 317 may provide selection of one of the receive path 302 and the transmit path 305 according to a preferred impedance match between the transceiver node 301 and the corresponding transmit node 303 or receive node 306 .

[0111] Thus, in the first switching mode, the switch arrangement 300 may substantially provide an impedance matching path between the transceiver node 301 and the transmit node 303, rather than between the transceiver node 301 and the receive node 306, such that the switch arrangement provides a signal path between the transceiver node 301 and the transmit node 303. Thus, in the second switching mode, the switch arrangement 300 may substantially provide an impedance matching path between the transceiver node 301 and the receive node 306, rather than between the transceiver node 301 and the transmit node 303, such that the switch arrangement provides a signal path between the transceiver node 301 and the receive node 306.

[0112] In this example and one or more other examples, in the first switching mode, the first semiconductor switch 311 and the second semiconductor switch 316 are off. Because the semiconductor switches are semiconductor-based and can include either a transistor arrangement or a biased diode arrangement, they have intrinsic capacitance (sometimes referred to as parasitic capacitance) in the off state. Thus, in the first switching mode, the first semiconductor switch 311 and the second semiconductor switch 316 provide capacitance in the switch arrangement 300.

[0113] In this example and one or more other examples, in the first switching mode, the third semiconductor switch 317 is closed and is therefore configured to provide a connection of the receiving branch 305 to the reference voltage 315 (eg, ground).

[0114] Example Figure 4 The states of the first semiconductor switch 311, the second semiconductor switch 316, and the third semiconductor switch 317 in a first switching mode are shown. In the open state, the semiconductor switches can be considered to provide capacitance to the switch arrangement. In the closed state, the semiconductor switches can be considered to provide resistance to the switch arrangement. Thus, in this example and one or more examples, in the first switching mode, the states of the semiconductor switches are configured to provide a CLC network between the transceiver node 301 and the transmitting node 303.

[0115] The CLC network provides impedance matching between the transceiver node 301 and one of the transmitting node 303 and the receiving node 306 (the transmitting node in this embodiment). The other of the transmitting node 303 and the receiving node 306 (the receiving node in this embodiment) is shorted to a reference voltage by the closed third semiconductor switch 317. Therefore, the impedance at the transceiver node 301 does not match (i.e., is mismatched) the impedance at the receiving node 306.

[0116] Example Figure 5 A first semiconductor switch 311, a second semiconductor switch 316, and a third semiconductor switch 317 are shown in a first switching mode, the semiconductor switches being replaced with capacitor and resistor symbols to illustrate an equivalent model of the switches in the first switching mode of the switch arrangement 300. A CLC network is provided by a capacitor 311 coupled to a reference voltage, an inductor 310, and a capacitor 317 connected to the reference voltage.

[0117] Reference example Figure 6In the second switching mode, first semiconductor switch 311 and second semiconductor switch 316 are closed. Since first semiconductor switch 311 is closed, first semiconductor switch 311 is configured to provide a connection between transmit branch 302 and reference voltage 315. In the closed state, first semiconductor switch 311 can be considered to provide a resistance in the switch arrangement. In one or more examples, in the second switching mode, second semiconductor switch 316 is closed. Therefore, second semiconductor switch 316 provides direct coupling between transceiver node 301 and receive node 306.

[0118] In this example and one or more other examples, in the second switching mode, the third semiconductor switch is configured to be open, thereby providing a capacitance in parallel with the receive node 306. Thus, in this example and one or more other examples, in the second switching mode, the states of switches 311, 316, and 317 provide a parallel LC tank circuit that provides impedance matching between transceiver node 301 and the other of transmit node 303 and receive node 306 (in this embodiment, the receive node). In this example and other examples, the arrangement is configured such that inductor 310 tunes out the capacitance of the open first switch 317 to provide the impedance matching. One of transmit node 303 and receive node 306 (in this embodiment, the transmit node) is shorted to a reference voltage by the closed first semiconductor switch 311. Consequently, the impedance at transceiver node 301 does not match (i.e., is mismatched) the impedance at transmit node 303.

[0119] Example Figure 7 The first semiconductor switch 311, the second semiconductor switch 316, and the third semiconductor switch 317 are shown in a second switching mode, with the semiconductor switches replaced with capacitor and resistor symbols to illustrate an equivalent model of the switches in the switch arrangement 300. Thus, in this example and one or more examples, in the second switching mode, the states of the semiconductor switches are configured to provide a parallel LC energy tank network between the transceiver node 301 and the receiving node 306.

[0120] In this example and one or more examples, the second or receiving circuit branch has no inductor. Specifically, the second circuit branch 305 has no inductor between the transceiver node 301 and the receiving node 306. Figure 1 Compared to the known arrangement of Figures 3 to 7 The switch arrangement can be considered to be area efficient and the size of the switch arrangement can be smaller than Figure 1 Dimensions of the switch arrangement.

[0121] Reference Figure 5In an equivalent model, the inductor 310 may have an inductance L, and in the first switching mode, the first semiconductor switch 311 may have a capacitance C off1 , the second semiconductor switch 316 may have a capacitance C off2 , and the third semiconductor switch may have a resistance R on3 It is also assumed that the interface impedance of the transceiver node is Z0 (Z0 is typically 50Ω). Therefore, the first semiconductor switch, the second semiconductor switch, and the third semiconductor switch provide a CLC network, each comprising a parallel capacitor Coff1, a series inductor L, and a parallel capacitor Coff2. In the first switching mode, the CLC network should transform the impedance from Z0 to Z0. The resistance R of the third semiconductor switch in the on state is on3 Can be considered as C off2 The Q factor of is degenerate. Then we can say:

[0122]

[0123] And, therefore,

[0124] C off1 =C off2

[0125] and

[0126]

[0127] where ω=2πf, and f is the intended operating frequency of the switching arrangement 300 .

[0128] Reference Figure 7 In the equivalent model of FIG, the inductor 310 still has an inductance L, and in the second switching mode, the first semiconductor switch 311 may have a resistance R on1 , the second semiconductor switch 316 may have a resistance R on2 , and the third semiconductor switch may have a capacitance C off3 Again, it is assumed that the interface impedance of the transceiver node is Z0 (Z0 is typically 50Ω). Therefore, the first semiconductor switch, the second semiconductor switch, and the third semiconductor switch provide a parallel LC energy storage network with the inductor 310, the parallel LC energy storage network including a parallel inductor L and a parallel capacitor C off3 The LC network formed in the second switching mode should transform the impedance from Z0 to Z0. L and C off3 Can be configured to resonate at the operating frequency. on1 and R on2 can be considered as Q factor degradation. Then we can say:

[0129] ω 2 C off3 L=1

[0130] In one or more examples, the first semiconductor switch and the second semiconductor switch can be configured to provide the same capacitance in the off state, and thus,

[0131] C off2 =C off1

[0132] As determined above:

[0133]

[0134] And it can be shown that:

[0135]

[0136] In one or more examples, the first semiconductor switch and the second semiconductor switch can be configured to provide the same capacitance in the off state as the capacitance provided by the third semiconductor switch in the off state, and thus,

[0137] C off1 =C off2 =C off3

[0138] From the preceding equations, the LC values can be simplified to more practical specifications for circuit tuning and implementation, such that:

[0139]

[0140] and

[0141]

[0142] Thus, the value of inductor 310 may be determined using the aforementioned Equation 2, and then the value of capacitance may be determined using Equation 1. It should be understood that these equations represent simplifications, and thus inductance and capacitance may be determined differently.

[0143] It should be understood that in one or more examples, the semiconductor switches 311, 316, 317 are configured to provide resistance in the on / closed state and capacitance in the off / open state. It should also be understood that there are many possible arrangements of semiconductor switches that exhibit these properties. Figures 8 to 11 Four of many possible configurations of such semiconductor switches are shown.

[0144] It should be understood that in one or more other examples, the first switching mode may include a receiving mode or a transmitting mode, and the second switching mode may include the other of the receiving mode or the transmitting mode, depending on whether the first branch and the second branch are configured as transmitting branches or receiving branches.

[0145] Example Figure 8 Semiconductor switches 311 and 317 are shown, each comprising a MOS transistor, such as an n-channel MOSFET 800. MOSFET 800 includes a drain terminal 801 coupled to a first capacitor 802 and a source terminal 803 coupled to a second capacitor 804. For the first and third semiconductor switches, the drain terminal 801 is coupled to the respective transmit node 303 and receive node 306 via the first capacitor 802. For the first and third semiconductor switches, the source terminal 803 is coupled to, or configured to be coupled to, a reference voltage, such as ground 315, via the second capacitor 804. In this example, the state of the semiconductor switch (i.e., open or closed) is controlled by control signals, including a first control signal, a second control signal, and a third control signal applied to each of the drain terminal 801, the gate terminal 805, and the source terminal 803 of the MOSFET, respectively (in this example, each via a resistor). Specifically, when the first and third control signals are low and the second control signal is high, the semiconductor switch is open / off. When the first control signal and the third control signal are high and the second control signal is low, the semiconductor switch is closed / conducting.

[0146] Example Figure 9 An npn bipolar junction transistor (BJT) 900 is shown. For the first and third semiconductor switches, the collector terminal 901 is coupled to the respective emitter node 303 and receive node 306. The emitter terminal 902 is coupled to a reference voltage, such as ground. In this example, the state of the semiconductor switch (i.e., open or closed) is controlled by a control signal applied to the base terminal 903 via a resistor. Applying a voltage to the base terminal provides a closed or conductive state for the switch.

[0147] Example Figure 10 A forward saturation mode npn BJT transistor 1000 is shown. For the first and third semiconductor switches, the emitter terminal 1001 is coupled to the respective transmit and receive nodes, and the collector terminal 1002 is coupled to the reference voltage 315. In this example, the state of the semiconductor switch (i.e., open or closed) is controlled by a control signal applied at the base terminal 1003 through a resistor. Applying a voltage at the base terminal provides a closed or conductive state for the switch.

[0148] Example Figure 11A pin diode 1100 is shown. For the first and third semiconductor switches, their cathodes 1101 are coupled to the respective transmit and receive nodes, and their anodes 1102 are coupled to a reference voltage 315 via capacitors 1103. In this example, the state of the semiconductor switch (i.e., open or closed) is controlled by a control signal applied at the anode 1102 via a resistor 1104. Applying a voltage at the anode 1102 biases the diode and provides a closed or conducting state for the switch.

[0149] Example Figures 21 to 24 An embodiment of a parallel arrangement of second semiconductor switches 316 is shown. Figures 21 to 23 The examples have a similar configuration. Figure 21 An example includes a MOS transistor 2100, such as an n-channel MOSFET. MOSFET 2100 includes a drain terminal 2101 coupled to a first capacitor 2102 and a source terminal 2103 coupled to a second capacitor 2104. Drain terminal 2101 is coupled to transceiver node 301 via first capacitor 2102. Source terminal 2103 is coupled to the other of a transmit node and a receive node (in this example, the receive node) via second capacitor 2104. In this example, the state of the semiconductor switch (i.e., open or closed) is controlled by control signals including a first control signal, a second control signal, and a third control signal applied to each of drain terminal 2101, gate terminal 2105, and source terminal 2103 of the MOSFET, respectively (in this example, each via a resistor). Specifically, when the first and third control signals are low and the second control signal is high, the semiconductor switch is open / off. When the first and third control signals are high and the second control signal is low, the semiconductor switch is closed / on.

[0150] Example Figure 22 and 23 A similar arrangement is shown using BJTs 2200, 2300 instead of MOSFET 2100. Example Figure 22 and 23NPN bipolar junction transistors (BJTs) 2200 and 2300 are shown. Collector terminals 2201 and 2303 are coupled to transceiver node 301 or one of a transmit node and a receive node via capacitors 2304 and 2202. Emitter terminals 2203 and 2301 are coupled to the other of transceiver node 301 and one of the transmit node and the receive node via capacitors 2302 and 2204. In this example, the state (i.e., open or closed) of semiconductor switches 2200 and 2300 is controlled by a first control signal applied to base terminals 2205 and 2305 via resistors, and separate second and third control signals applied to the collector and emitter terminals via resistors. When the second and third control signals are low, applying a high voltage to the base terminal provides a closed or conducting state for the switch. A low first control signal, together with high second and third control signals, provides an open or off state.

[0151] Example Figure 24 A diode 2400 is shown. For the first and third semiconductor switches, their cathodes 2401 are coupled to the respective transmit and receive nodes, and their anodes 2402 are coupled to the transceiver node 301, both couplings being achieved via capacitors 2403 and 2404. In this example, the state of the semiconductor switches (i.e., open or closed) is controlled by a first control signal applied at the anode via a resistor and a second control signal applied at the cathode via a resistor. The high voltage at the anode and the low voltage at the cathode bias the diodes and provide a closed or conducting state for the switches. The low voltage at the anode and the high voltage at the cathode provide an open or off state for the switches.

[0152] Example Figure 12 Shown with example Figure 3 The same switching arrangement is shown, except that amplifier 307 is shown in greater detail. In one or more examples, amplifier 307 comprises a receive path buffer amplifier. Specifically, amplifier 307 includes a transistor, such as an npn bipolar junction transistor (BJT) 1200. The amplifier / transistor is coupled to additional auxiliary components. Specifically, collector terminal 1201 is coupled to receive node 306, such as via DC blocking capacitor 1202. Capacitor 1202 can be ignored when considering the coupling of RF signals between the transceiver node and transistor 1200. Collector terminal 1201 is also coupled in parallel to power supply node 1203 via inductor 1204. Power supply node 1203 is configured to be connected to a power supply. Emitter terminal 1205 is configured to be coupled to a reference voltage, such as ground 315. The remainder of the receive path can be connected to a base terminal.

[0153] Example Figure 13Another example of a switch arrangement 1300 is shown. The same reference numerals are used for similar components. In this example, third semiconductor switch 317 is provided by semiconductor switch 1317, which is configured to provide a switched connection between power supply node 1203 and transistor 1200. Thus, a first end of switch 1317 is coupled to power supply node 1203, and a second end of switch 1317 is coupled to transistor 1200 via inductor 1204. In one or more examples, a first plate of decoupling capacitor 1301 can be coupled in parallel to a node between the second end of switch 1317 and inductor 1204. A second plate of decoupling capacitor 1301 can be coupled to a reference voltage, such as ground 315.

[0154] In one or more examples, insertion loss can be reduced by providing a third semiconductor switch in the form of power switch 1317. Additionally, in one or more examples, third switch 317 can limit the output voltage swing margin of the receive path. Therefore, providing a third switch in the form of power switch 1317 can increase the output power limit from the receive path.

[0155] In the above examples, transistor 1200 may include any of the following types of transistors: npn common emitter; common base or cascode stage; nmos common source; common gate or cascode stage; pnp emitter follower; and pmos source follower.

[0156] Example Figure 14 and 15 The states of the first semiconductor switch 311 , the second semiconductor switch 316 and the third semiconductor switch 1317 in the first switching mode and the second switching mode are shown respectively.

[0157] In the example Figure 14 In the first switching mode depicted in FIG, the first semiconductor switch 311 and the second semiconductor switch 316 are disconnected. In this example and one or more other examples, the third semiconductor switch 1317 is disconnected and, therefore, the power supply node 1203 is disconnected or decoupled from the amplifier or transistor 1200. As a result, the transistor 1200 is pushed into a forward saturation mode to achieve a short termination to the reference voltage (ground 315). The impedance at the node 1400 (and therefore the receiving node 306) is approximately 0 ohms. Therefore, the receiving node is shorted to ground and there is no impedance matching between the transceiver node 301 and the receiving node 306 / node 1400. The principle is then combined with Figure 4 and Figure 5 The CLC network consists of the capacitance of the open first semiconductor switch 311 plus the inductor 310 plus the capacitance (C) of the open second semiconductor switch 316 also coupled to the reference voltage via the transistor 1200.off1 + Series L+C off2 ) is formed. The CLC network (or more generally, the switch arrangement 1300) transforms the impedance Z0 at the transceiver node to Z0 at the transmit node 303. As a result, signaling will flow from the transceiver node 301 to the transmit node 303 (impedance-matched path) rather than from the receive node 306 to the transceiver node 301 (non-impedance-matched path).

[0158] In the example Figure 15 In the second switching mode depicted in FIG, first semiconductor switch 311 and second semiconductor switch 316 are closed. In this example and one or more other examples, third semiconductor switch 1317 is closed, and thus, the power supply node is coupled to amplifier or transistor 1200. Thus, transistor 1200 is active. In this example, transmit node 303 is shorted to a reference voltage via closed first semiconductor switch 311, and thus its impedance does not match the impedance of transceiver node 301. In this example and one or more other examples, inductor 310 and inductor 1204 form part of the receive path output matching network. Specifically, in this example and other examples, a parallel LC tank network is formed by two inductors 310 and 1204, rather than the single inductor of the previous example. In this example and other examples, the parallel LC tank network is used to tune out the output capacitance inherent in buffer transistor 1200 to provide impedance matching between transceiver node 301 and receive node 306 (and therefore amplifier 1200).

[0159] Thus, signaling will flow from the receiving node 306 to the transceiver node 301 (impedance matched path) rather than from the transceiver node 301 to the transmitting node 303 (non-impedance matched path).

[0160] Therefore, to summarize Figures 12 to 15 In the example of FIG. 1 , the switch arrangement 1300 includes a third semiconductor switch 1317, which comprises a portion of an amplifier arrangement coupled to the receive node 306 of the receive path 305. The third semiconductor switch 1317 is configured to control the application of a supply voltage to the amplifier 1200, wherein in a first switching mode, the third switch is open, and the connection between the receive path 305 and a reference voltage (e.g., ground 315) is provided through the amplifier 1200. In a second switching mode, the third semiconductor switch 1317 is closed, and the amplifier is provided with the supply voltage. Thus, the inductor 1204 and the inductor 310 are used to provide impedance matching between the transceiver node 301 and the amplifier 1200 of the receive path 305.

[0161] Example Figure 16 Another example of a switch arrangement 1600 is shown, which is similar to Figure 13 The switch arrangement 1300. Figure 16 In the example switch arrangement 1600 of , the second switch 316 is absent, and the further semiconductor switch 1617 provides the functionality of the second semiconductor switch 316 and the third semiconductor switch 1317 in the previous example. The differences from the switch arrangement 1300 will now be described.

[0162] Example switch arrangement 1600 includes an amplifier arrangement comprising a series arrangement of a supply node 1203 for receiving a supply voltage, an additional inductor 1604, and an npn transistor 1200 (which includes a collector terminal 1201 coupled to inductor 1604 and an emitter terminal 1205 for connection to reference voltage 315). In this example, a receiving node 306 is coupled to node 1601 between inductor 1604 and collector terminal 1201 via a DC blocking capacitor 1202. Therefore, when considering the flow of RF signaling, DC blocking capacitor 1202 can be ignored. In this example, amplifier arrangement 1600 further includes a bias circuit 1602 coupled to a base terminal 1603 of transistor 1200 and configured to apply a bias voltage to base terminal 1603. Application of the bias voltage is controlled by an additional semiconductor switch 1617. The amplifier comprises npn transistors, but may be embodied as any of the following types of transistors: npn common emitter; common base or cascode stage; nmos common source; common gate or cascode stage; pnp emitter follower; and pmos source follower.

[0163] In this example and one or more examples, refer to the example Figure 17 In the first switching mode, the further semiconductor switch 1617 is disconnected and the bias voltage is not applied to the base terminal 1603. The first semiconductor switch 311 is also disconnected and thus provides a capacitance. Figure 17 , box 1722 is shown to indicate that transistor 1200 has intrinsic capacitance 1721 and intrinsic resistance 1720. Therefore, components 1720, 1721 are not different components, but rather represent the electrical characteristics of transistor 1200. Example Figure 18 The same box 1722 is shown in FIG.

[0164] In this example and one or more examples, refer to the example Figure 18 In the second switching mode, the further semiconductor switch 1617 is closed and the bias voltage is applied to the base terminal 1603. The first semiconductor switch 311 is closed and thus connects the emission node 303 of the first branch 302 to the reference voltage 315.

[0165] As mentioned, the example Figure 17 and 18With a given resistance value R out The intrinsic resistance of transistor 1200 is shown in the form of resistor 1720. Figure 17 and 18 Also with a given capacitance C out The intrinsic capacitance of transistor 1200 is shown in the form of capacitor 1721.

[0166] exist Figure 16-18 In the example, the inductor 310 has an inductance

[0167]

[0168] In addition, when in the off state, the capacitance of the first switch is

[0169]

[0170] The inductance of the inductor 1204 is L2.

[0171] In the first switching mode, bias current is not applied to the amplifier transistor 1200, and therefore, the collector current (bias current) Ic of the transistor 1200 is 0. In addition, the transconductance gm of the transistor 1200 is also substantially zero, because for an npn transistor, gm=Ic / V T , where V T =25mV thermal voltage at 25°C. Therefore, R out Became very large (almost disconnected).

[0172] Therefore, the input impedance of the second branch 305 is:

[0173]

[0174] Thus, the switch arrangement 1600 can be simplified to a CLC network 1750, where capacitance is provided by the open first semiconductor switch 311, inductance is provided by the inductor 310, and further capacitance is provided by the intrinsic capacitance 1721 of the transistor 1200. Thus, impedance matching is provided between the transceiver node 301 and the transmit node 303 (or more generally, one of the transmit and receive nodes in the first branch).

[0175] In the second switching mode, a bias current is applied to the amplifier transistor 1200, and thus:

[0176] Where V early is the Early voltage of the transistor, C fb is the feedback capacitance from the transistor output to the input, C inis the input capacitance of the transistor, gm is the transconductance of transistor 1200, and Ic is the collector (bias) current of the transistor.

[0177] Therefore, R out Depending on the current through transistor 1200, and in the second switching mode, resistor 1720 or R out Low, such as about 100 ohms.

[0178] Assume Cout is constant.

[0179] In the second switching mode, L1 (the inductance of inductor 310) in parallel with L2 (the inductance of inductor 1204) should be configured to tune out the C of the transistor. out :

[0180]

[0181] Thus, in the second switching mode, the switch arrangement provides for shorting the transmit node 303 (i.e., one of the transmit and receive nodes) to the reference voltage via the first semiconductor switch 311. Furthermore, in the second switching mode, the switch arrangement 1600 provides a parallel LC tank circuit, which in this example is formed by both the inductors 310 and 1604 connected in parallel and the intrinsic junction capacitance of the transistor 1200 (shown as 1721).

[0182] Cout mainly comes from the junction capacitance of the npn transistor, so specifically it is not tunable. Inductors 310, 1604 (ie, L1 and L2) are configured to tune out Cout in the second switching mode to provide impedance matching between the transceiver node 301 and the receiving node 306 / transistor 1200.

[0183] The value of L1 is determined by the requirements of the CLC network formed in the first switching mode, where:

[0184]

[0185] Since L1 is determined and Cout is known, L2 can be calculated accordingly.

[0186] As reference Figure 2 As explained in the known arrangements of , known switch arrangements of the differential type are known. Example Figure 19 and 20 Included with examples Figure 3 The example of the differential type switch arrangement 1900, 2000 with the reduced number of inductors consistent with the switch arrangement 300. Therefore, the layout of the arrangement 1900, 2000 is the same as Figure 3 The example arrangement 300 is generally consistent with FIG.

[0187] Reference example Figure 19 , shows an example differential switch arrangement 1900. Arrangement 1900 includes transceiver nodes, which in this differential example include a positive transceiver node 1901 and a negative transceiver node 1902. Similarly, the transmit nodes include a positive transmit node 1903 and a negative transmit node 2003. Similarly, the receive nodes include a positive receive node 1906 and a negative receive node 2006.

[0188] In this example and one or more other examples, the first circuit leg includes a first positive circuit leg 1902 and a first negative circuit leg 2002 coupled to respective positive transmit node 1903 and negative transmit node 2003. In this example and one or more other examples, the inductors include a first inductor 1910 in first positive circuit leg 1902 and a second inductor 2010 in first negative circuit leg 2002, with first inductor 1910 coupled in series between positive transceiver node 1901 and positive transmit node 1903, and second inductor 2010 coupled in series between negative transceiver node 2001 and negative transmit node 2003. In this example and one or more other examples, a first semiconductor switch 1911 is coupled in parallel with both positive transmit node 1903 and negative transmit node 2003. Additionally, in one or more examples, the first semiconductor switch 1911 includes a pair of first semiconductor switches, each configured to selectively couple one of the first positive circuit branch 1902 and the first negative circuit branch 2002 to a reference voltage, such as ground 315 .

[0189] In this example and one or more other examples, the second circuit leg includes a second positive circuit leg 1905 and a second negative circuit leg 2005 coupled to respective positive receive node 1906 and negative receive node 2006. In this example and one or more other examples, the second semiconductor switch 1916 includes a pair of switches including a second positive semiconductor switch 1916 and a second negative semiconductor switch 2016, the second positive circuit leg 1905 including the second positive semiconductor switch 1916 coupled in series between the positive transceiver node 1901 and the positive receive node 1906, and the second negative circuit leg 2005 including the second negative semiconductor switch 2016 coupled in series between the negative transceiver node 2001 and the negative receive node 2006.

[0190] In this example and one or more other examples, the third semiconductor switch 1917 is connected in parallel with both the positive receiving node 1906 and the negative receiving node 2006. Furthermore, in this example and one or more other examples, the third semiconductor switch 1917 includes a pair of third semiconductor switches each configured to selectively couple one of the second positive circuit leg 1905 and the second negative circuit leg 2005 to a reference voltage, such as ground 315.

[0191] It should be understood that in this example and one or more other examples, first positive circuit leg 1902 and first negative circuit leg 2002 comprise transmit legs, and second positive circuit leg 1905 and second negative circuit leg 2005 comprise receive legs. In other examples of any of the examples herein, the leg designated as "first" may comprise a receive leg, and the leg designated as "second" may comprise a transmit leg.

[0192] exist Figure 19 In the example switch arrangement 1900, the first semiconductor switch 1911 includes a pair of first semiconductor switches, wherein the first of the pair is configured to provide a switch connection to a reference voltage for the first positive circuit branch 1902, and the second of the pair is configured to provide a switch connection to the reference voltage for the first negative circuit branch 2002.

[0193] Figure 20 An example switch arrangement 2000 is shown. Figure 20 An example switch arrangement 2000 with Figure 19 The example switch arrangements of FIG. 1 are substantially the same, and like reference numerals are used for similar parts. However, in this example, first semiconductor switch 2011 is configured to provide a switching connection between first positive circuit leg 1902 and first negative circuit leg 2002. Additionally, in this example and one or more other examples, third semiconductor switch 2017 is configured to provide a switching connection between second positive circuit leg 1905 and second negative circuit leg 2005.

[0194] The operation of the switch arrangements 1900, 2000 in the first switching mode and in the second switching mode is combined with Figures 4 to 7 Specifically, the example Figure 5 Similarly, in the first switching mode, the first semiconductor switch 1911, 2011 or a pair of first semiconductor switches 1911 are disconnected and thus provide capacitance. Figure 5Similarly, in the first switching mode, the second semiconductor switches 1916, 2016 are open and thus provide capacitance. In addition, in the first switching mode, the third semiconductor switches 1917, 2017 or a pair of third semiconductor switches 1917 are closed and thus provide coupling to ground 315 or short-circuit the second positive branch 1902 and the second negative branch 2002.

[0195] In the second switching mode, the first semiconductor switch 1911, 2011, or a pair of first semiconductor switches 1911, is closed and thus provides a coupling to ground 315 or shorts the first positive branch 1902 and the first negative branch 2002. In the second switching mode, the second semiconductor switches 1916, 2016 are closed. In addition, in the second switching mode, the third semiconductor switch 1917, 2017, or a pair of third semiconductor switches 1917, is open and thus provides a capacitance between the corresponding branch and ground 315 or between the second positive branch 1905 and the second negative branch 2005.

[0196] In each of the first switching mode and the second switching mode, the effect of the switch arrangement is the same as previously described in connection with the other examples.

[0197] In the first switching mode, the switch arrangements 1900, 2000 provide substantial impedance matching between the positive transceiver node 1901 and the positive transmit node 1903, and substantially provide substantial impedance matching between the negative transceiver node 2001 and the negative transmit node 2003. In the first switching mode, the impedance between the positive transceiver node 1901 and the positive receive node 1906, and the impedance between the negative transceiver node 2001 and the negative receive node 2006, are substantially unmatched.

[0198] In the second switching mode, the switch arrangements 1900, 2000 provide substantial impedance matching between the positive transceiver node 1901 and the positive receive node 1906, and substantial impedance matching between the negative transceiver node 2001 and the negative receive node 2006. In the second switching mode, the impedance between the positive transceiver node 1901 and the positive transmit node 1903, and the impedance between the negative transceiver node 2001 and the negative transmit node 2003, are substantially unmatched.

[0199] Example Figure 25 A method of operating a switch arrangement 300, 1300, 1600, 1900, 2000 is shown, wherein the method comprises switching between:

[0200] a first switching mode 2501 in which the first semiconductor switch is open and thereby configured to provide a capacitance in parallel with the inductor, and one or more of the second and third semiconductor switches is configured to provide a capacitance coupled in parallel between the inductor and a reference voltage to substantially provide impedance matching between the transceiver node and one of the transmit and receive nodes; and

[0201] A second switching mode 2502, in which the first semiconductor switch is closed and thereby couples the inductor and one of the transmit node and the receive node to a reference voltage, and one of the second semiconductor switch and the third semiconductor switch or another semiconductor switch is configured to couple the inductor to the reference voltage in parallel via a capacitor to substantially provide impedance matching between the transceiver node and the other of the transmit node and the receive node.

[0202] Optionally, the example method includes, at 2503 , switching back to the first switching mode.

[0203] Figure 26 A communication device 2600 is shown, comprising an RF front-end integrated circuit 2601, a transceiver 2602, and an antenna. It should be understood that the communication device may include additional components connected to the transceiver 2602. The front-end integrated circuit includes two instances of a switch arrangement 300, 1300, 1600, 1700 to control the flow of signaling between the transceiver 2602 and the antenna 2603 on a transmit path 2604 including one or more amplifiers 2605 and a receive path 2606 including one or more amplifiers 2607. It should be understood that, in general, the device 2600 includes one or more antennas 2603 coupled to a transmitting node and a receiving node via one or more amplifiers, and one or more signal processing elements (such as the transceiver 2602) coupled to the transceiver node to provide communication functionality. The switching mode is operable to provide half-duplex signaling transmission and reception by the telecommunications device 2600. The signal processing element 2202 may provide processing for transmitted and received signals.

[0204] exist Figure 26 In the example of , two switch arrangements are shown, but in other examples, there is only one (or another number of) switch arrangements.

[0205] Unless a specific order is explicitly stated, the instructions and / or flowchart steps in the above figures can be executed in any order. Moreover, those skilled in the art will recognize that although an example set of instructions / methods has been discussed, the materials in this specification can also be combined in various ways to produce other examples and should be understood in the context provided by this detailed description.

[0206] In some example embodiments, the set of instructions / method steps described above are implemented as functions and software instructions embodied as a set of executable instructions, which are implemented on a computer or machine programmed and controlled using the executable instructions. Such instructions are loaded for execution on a processor (such as one or more CPUs). The term processor includes a microprocessor, a microcontroller, a processor module or subsystem (including one or more microprocessors or microcontrollers), or other control or computing devices. A processor can refer to a single component or multiple components.

[0207] In other examples, a set of instructions / methods described herein and the data and instructions associated therewith are stored in corresponding storage devices, which are implemented as one or more non-transitory machine or computer readable or computer usable storage media. Such one or more computer readable or computer usable storage media are considered to be part of an article (or product). An article or product may refer to a single component or multiple components of any manufacture. One or more non-transitory machine or computer usable media as defined herein do not include signals, but one or more such media may be capable of receiving and processing information from signals and / or other transient media.

[0208] Example embodiments of the materials discussed in this specification may be implemented in whole or in part via network, computer, or data-based devices and / or services. These may include the cloud, the Internet, an intranet, a mobile device, a desktop computer, a processor, a lookup table, a microcontroller, a consumer device, infrastructure, or other enabling devices and services. As used herein and in the claims, the following non-exclusive definitions are provided.

[0209] In one example, one or more instructions or steps discussed herein are automated. The terms automated or automatically (and similar variations thereof) refer to the controlled operation of equipment, systems, and / or processes using computers and / or mechanical / electrical devices without the need for human intervention, observation, effort, and / or decision-making.

[0210] It should be understood that any components referred to as being coupled can be coupled or connected directly or indirectly. In the case of indirect coupling, additional components can be located between the two components referred to as being coupled.

[0211] In this specification, example embodiments have been presented with respect to a selected set of details. However, one skilled in the art will appreciate that many other example embodiments can be practiced that include a different selected set of these details. The following claims are intended to cover all possible example embodiments.

Claims

1. A switch arrangement, characterized in that include: a transceiver node for coupling to a transceiver, the transceiver node for receiving signaling to be transmitted and for providing the received signaling based on whether the switch arrangement is in a first switching mode or a second switching mode, the transceiver node being coupled to a first circuit branch and a second circuit branch, the first circuit branch including one of a transmitting node for connecting to a transmitting path and a receiving node for connecting to a receiving path, the second circuit branch including the other of the transmitting node and the receiving node; wherein the first circuit branch includes an inductor coupled in series between the transceiver node and the one of the transmit node and the receive node, and a first semiconductor switch coupled to and in parallel with the one of the transmit node and the receive node, and the first semiconductor switch is configured to provide a switched coupling to a reference voltage; and The second circuit branch includes one of the following: i) a second semiconductor switch coupled in series between the transceiver node and the other of the transmitting node and the receiving node; and a third semiconductor switch coupled to and connected in parallel with the other of the transmitting node and the receiving node; as well as ii) a second semiconductor switch coupled in series between the transceiver node and the other of the transmitting node and the receiving node; and an amplifier coupled to the other of the transmitting node and the receiving node; and a third semiconductor switch configured to control application of a supply voltage to the amplifier to control coupling of the other of the transmitting node and the receiving node to the reference voltage through the amplifier; as well as iii) an amplifier coupled to the other of the transmitting node and the receiving node; and a further semiconductor switch configured to control application of a bias current to the amplifier to control coupling of the other of the transmitting node and the receiving node to the reference voltage through the amplifier; wherein in the first switching mode, the first semiconductor switch is open and thereby configured to provide a capacitance in parallel with the inductor, and one of the second semiconductor switch and the third semiconductor switch or the further semiconductor switch is configured to provide a capacitance coupled in parallel between the inductor and the reference voltage to substantially provide impedance matching between the transceiver node and the one of the transmit node and the receive node; and wherein in the second switching mode, the first semiconductor switch is closed and thereby couples the inductor and the one of the transmit node and the receive node to the reference voltage, and the one of the second semiconductor switch and the third semiconductor switch or the further semiconductor switch is configured to couple the inductor in parallel to the reference voltage via a capacitance to substantially provide impedance matching between the transceiver node and the other of the transmit node and the receive node; The third semiconductor switch comprises part of an amplifier arrangement and is configured to control application of a supply voltage to the amplifier, wherein in the first switching mode the third semiconductor switch is open and an amplifier of the amplifier arrangement is configured to provide coupling to a reference voltage through the amplifier, and wherein in the second switching mode the third semiconductor switch is closed and the amplifier is provided with the supply voltage.

2. The switch arrangement according to claim 1, characterized in that The second circuit branch has no inductor.

3. A switch arrangement according to claim 1 or claim 2, characterised in that In the first switching mode, the first semiconductor switch, the second semiconductor switch, and the third semiconductor switch form a CLC circuit in the first circuit branch and the second circuit branch, the CLC circuit being configured to substantially provide impedance matching between the transceiver node and the one of the transmitting node and the receiving node; and In the second switching mode, the first semiconductor switch, the second semiconductor switch, and the third semiconductor switch provide parallel LC tank circuits formed in the first circuit branch and the second circuit branch, the parallel LC tank circuits being configured to substantially provide impedance matching between the transceiver node and the other of the transmitting node and the receiving node.

4. The switch arrangement according to claim 1 or 2, characterized in that The third semiconductor switch is configured to provide a switched connection to a reference voltage, and wherein in the first switching mode the third semiconductor switch is configured to be closed, and in the second switching mode the third semiconductor switch is configured to be open.

5. The switch arrangement according to claim 1 or 2, characterized in that The amplifier arrangement comprises a series arrangement of a supply node for receiving the supply voltage, an npn transistor and a further inductor, the supply node being for controlling application of the supply voltage to the amplifier, the npn transistor comprising a collector terminal coupled to the further inductor and an emitter terminal for connection to the reference voltage, the other of the transmit node and the receive node being coupled between the further inductor and the collector terminal of the npn transistor, the amplifier arrangement further comprising a decoupling capacitor having a first plate coupled to a node between the third semiconductor switch and the further inductor and a second plate for connection to the reference voltage.

6. The switch arrangement according to claim 1 or 2, characterized in that the switch arrangement comprising an amplifier arrangement coupled to the other of the transmit and receive nodes, the amplifier arrangement comprising a series arrangement of a supply node for receiving a supply voltage, a further inductor, and an npn transistor comprising a collector terminal coupled to the further inductor and an emitter terminal for connection to the reference voltage, the other of the transmit and receive nodes being coupled to a node between the further inductor and the collector terminal via a DC blocking capacitor, the amplifier arrangement further comprising a bias circuit coupled to a base terminal of the transistor and configured to apply a bias current to the base terminal, the application of the bias current being controlled by the further semiconductor switch; wherein in the first switching mode, the further semiconductor switch is off and a bias voltage is not applied to the base terminal; and In the second switching mode, the further semiconductor switch is closed and the bias voltage is applied to the base terminal.

7. The switch arrangement according to claim 1 or 2, characterized in that The first circuit branch includes a transmit branch and is coupled to the transmit node; The second circuit branch includes a receive branch and is coupled to the receive node; The first switching mode includes a transmit mode that provides impedance matching between a transceiver node and the transmit node, thereby enabling signaling to be passed from the transceiver node to the transmit node; and The second switching mode includes a receive mode that provides impedance matching between a transceiver node and the receive node, thereby enabling signaling to pass from the receive node to the transceiver node.

8. A method of operating a switch arrangement, characterized in that The switch arrangement comprises: a transceiver node for coupling to a transceiver, the transceiver node for receiving signaling to be transmitted and for providing the received signaling based on whether the switch arrangement is in a first switching mode or a second switching mode, the transceiver node being coupled to a first circuit branch and a second circuit branch, the first circuit branch including one of a transmitting node for connecting to a transmitting path and a receiving node for connecting to a receiving path, the second circuit branch including the other of the transmitting node and the receiving node; wherein the first circuit branch includes an inductor coupled in series between the transceiver node and the one of the transmit node and the receive node, and a first semiconductor switch coupled to and in parallel with the one of the transmit node and the receive node, and the first semiconductor switch is configured to provide a switched coupling to a reference voltage; and The second circuit branch includes one of the following: i) a second semiconductor switch coupled in series between the transceiver node and the other of the transmitting node and the receiving node; and a third semiconductor switch coupled to and in parallel with the other of the transmitting node and the receiving node; and ii) a second semiconductor switch coupled in series between the transceiver node and the other of the transmitting node and the receiving node; an amplifier coupled to the other of the transmitting node and the receiving node; and a third semiconductor switch configured to control application of a supply voltage to the amplifier to control coupling of the other of the transmitting node and the receiving node to the reference voltage via a capacitor through the amplifier; and iii) an amplifier coupled to the other of the transmitting node and the receiving node; and a further semiconductor switch configured to control application of a bias current to the amplifier to control coupling of the other of the transmitting node and the receiving node to the reference voltage through the amplifier; wherein the method comprises employing a first switching mode in which the first semiconductor switch is open and thereby configured to provide a capacitance in parallel with the inductor, and one of the second semiconductor switch and the third semiconductor switch or the further semiconductor switch is configured to provide a capacitance coupled in parallel between the inductor and the reference voltage to substantially provide impedance matching between the transceiver node and the one of the transmit node and the receive node; and wherein the method comprises employing a second switching mode in which the first semiconductor switch is closed and thereby couples the inductor and the one of the transmit node and the receive node to the reference voltage, and the one of the second and third semiconductor switches or the further semiconductor switch is configured to capacitively couple the inductor in parallel to the reference voltage to substantially provide impedance matching between the transceiver node and the other of the transmit node and the receive node; The supply voltage is applied to the amplifier by controlling the third semiconductor switch. In the first switching mode, the third semiconductor switch is opened and the amplifier provides coupling to the reference voltage through the amplifier. In the second switching mode, the third semiconductor switch is closed and the amplifier provides the supply voltage.

9. A communication device comprising a switch arrangement according to any one of claims 1 to 7, characterized in that The communication device includes one or more antennas coupled to the transmitting node and the receiving node through one or more amplifiers, and a signal processing element coupled to the transceiver node for providing communication functions, and the switching mode is capable of operating to provide half-duplex signaling transmission and reception by the communication device.

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