Semiconductor Structure and Method of Forming the Same

Abstract

The present invention provides a semiconductor structure and a method for forming the same. By disposing an electrically conductive structure on a trench isolation structure to utilize the space above the trench isolation structure, the space occupied by the electrically conductive structure in the entire semiconductor integrated circuit can be reduced, which is conducive to realizing the size reduction of the formed semiconductor integrated circuit.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Shallow trench isolation (STI) is currently the main method used to achieve device isolation in large-scale integrated circuits. For example, trench isolation structures can be used to isolate adjacent active areas (AA) from each other, thereby preventing components formed on different active areas from interfering with each other. In addition, a large number of electrically conductive structures are usually provided in semiconductor integrated circuits. These electrically conductive structures can be used, for example, to achieve electrical transmission or serve only as redundant components (i.e., they do not achieve electrical functions). Generally speaking, the electrically conductive structures in integrated circuits will deviate from the trench isolation structure setting. Based on this, it is necessary to reserve a certain amount of accommodation space for the electrically conductive structures.

[0003] With the continuous development of semiconductor technology, the size of integrated circuits tends to decrease. Even though the size of integrated circuits can be reduced by reducing the size of electrical conductive structures, it is still necessary to reserve a large space for the electrical conductive structures, making it difficult to further reduce the overall size of semiconductor integrated circuits. Summary of the Invention

[0004] An object of the present invention is to provide a semiconductor structure to facilitate reducing the overall size of a semiconductor integrated circuit.

[0005] To solve the above technical problems, the present invention provides a semiconductor structure, comprising:

[0006] A trench isolation structure formed in an isolation trench of a substrate, wherein the trench isolation structure includes multiple insulating layers, the multiple insulating layers sequentially covering inner walls of the isolation trench, and a top surface of an innermost insulating layer of the multiple insulating layers is sunken relative to a top surface of the substrate to form a first recess in the isolation trench; and

[0007] An electrically conductive structure is formed on the substrate and is at least partially located on the trench isolation structure, and the electrically conductive structure completely fills the first groove; wherein the electrically conductive structure includes a first conductive layer and a second conductive layer, the first conductive layer fills the first groove and extends out of the isolation trench, and the second conductive layer is formed on the first conductive layer.

[0008] Based on the semiconductor structure described above, the present invention further provides a method for forming a semiconductor structure, comprising:

[0009] Provide a substrate and form isolation trenches in the substrate;

[0010] Form a multi-layer insulating layer in the isolation trenches in sequence to form a trench isolation structure, and the top surface of the innermost insulating layer in the multi-layer insulating layer sinks more relative to the top surface of the substrate to form a first groove in the isolation trenches; and,

[0011] Form a first conductive layer and a second conductive layer on the substrate, and the first conductive layer completely fills the first groove and extends out of the isolation trenches, and the second conductive layer is formed on the first conductive layer.

[0012] In the semiconductor structure provided by the present invention, based on the formation of a trench isolation structure in the substrate, at least part of the electrical conduction structure is further formed on the trench isolation structure, so that the space above the trench isolation structure can be effectively utilized, and correspondingly, the space reserved additionally for the electrical conduction structure can be reduced, and even there is no need to reserve space for the electrical conduction structure. Thus, it is beneficial to realize the size reduction of the formed semiconductor integrated circuit. Description of the Drawings

[0013] Figure 1 It is a schematic diagram of a semiconductor structure in an embodiment of the present invention;

[0014] Figure 2 It is a schematic flow chart of a method for forming a semiconductor structure in an embodiment of the present invention;

[0015] Figures 3a to 3d It is a schematic diagram of a semiconductor structure during its preparation process in an embodiment of the present invention.

[0016] Among them, the reference numerals are as follows:

[0017] 100 - Substrate;

[0018] 200a - Isolation trench;

[0019] 200b - First groove;

[0020] 200c - Second groove;

[0021] 200 - Trench isolation structure;

[0022] 210 - First insulating layer;

[0023] 220 - Second insulating layer;

[0024] 230 - Third insulating layer;

[0025] 300 - Electrical conduction structure;

[0026] 300a - Pseudo-gate structure;

[0027] 300b - Gate structure;

[0028] 310a / 310b - First conductive layer;

[0029] 320a / 320b - Second conductive layer;

[0030] 330a / 330b - Third conductive layer;

[0031] 340a / 340b - Masking layer;

[0032] 341 - Gap;

[0033] 400 - Sidewall structure;

[0034] 410 - First isolation layer;

[0035] 420 - Second isolation layer. Detailed implementation mode

[0036] The semiconductor structure and its forming method proposed by the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0037] Figure 1 It is a schematic diagram of the semiconductor structure in an embodiment of the present invention. As Figure 1 shown, the semiconductor structure in this embodiment includes:

[0038] A trench isolation structure 200, formed in an isolation trench 200a of a substrate 100, and at least a part of the top surface of the trench isolation structure 200 is more sunken relative to the top surface of the substrate 100; and,

[0039] An electrically conductive structure 300, formed on the substrate 100, and at least a part of the electrically conductive structure 300 is located above the trench isolation structure 200 and fills the isolation trench 200a.

[0040] Wherein, the electrically conductive structure 300 includes a first conductive layer 310a and a second conductive layer 320a. The first conductive layer 310a fills the isolation trench 200a and extends out of the isolation trench 200a, and the second conductive layer 320a is formed on the first conductive layer 310a. In this embodiment, the first conductive layer 310a extends out of the isolation trench 200a, so that the entire top surface of the first conductive layer 310a is higher than the top surface of the substrate 100.

[0041] It should be noted that by forming the electrical conduction structure 300 on the trench isolation structure 200, the space above the trench isolation structure 200 can be effectively utilized, thereby reducing the accommodation space reserved for the electrical conduction structure, or it may not be necessary to reserve additional accommodation space for the electrical conduction structure 300. In this way, it is beneficial to reduce the size of the entire integrated circuit.

[0042] In addition, it should also be noted that although part of the electrical conduction structure 300 formed on the trench isolation structure 200 is embedded in the isolation trench 200a, this will not have a great impact on the performance of the electrical conduction structure 300. For example, when the electrical conduction structure 300 is used to achieve electrical transmission, although part of the electrical conduction structure 300 is filled in the isolation trench 200a, the electrical transmission performance of the first conductive layer 310a and the second conductive layer 320a can still meet the requirements; or, when the electrical conduction structure 300 is used to form a redundant component, such as forming a Dummy Gate, since the redundant component does not need to achieve electrical functions at this time, there is no problem of function being affected.

[0043] In this embodiment, the projected area of the second conductive layer 320a in the height direction is not less than the top surface area of the first conductive layer 310a. That is to say, the top surface of the first conductive layer 310a is not exposed under the direct or indirect coverage of the second conductive layer 320a, so that only the side walls of the first conductive layer 310a are laterally exposed relative to the second conductive layer 320a. Among them, the material of the first conductive layer 310a includes, for example, doped polysilicon (poly), and the second conductive layer 320a can be a metal layer, for example, the material of the second conductive layer 320a includes tungsten (W).

[0044] Furthermore, the trench isolation structure 200 has multiple insulating layers, and the multiple insulating layers sequentially cover the inner wall of the isolation trench 200a, and the top surface of the innermost insulating layer in the multiple insulating layers sinks more relative to the top surface of the substrate to form a first groove in the isolation trench 200a.

[0045] In this embodiment, the side wall boundary of the electrical conduction structure 300 is between the boundary of the first groove and the boundary of the isolation trench 200a, so that the electrical conduction structure 300 completely fills the first groove, that is, at least part of the first conductive layer 310a in the electrical conduction structure 300 is formed on the innermost insulating layer to completely fill the first groove and further extend upward out of the isolation trench 200a. It should be noted that the "side wall boundary of the electrical conduction structure" mentioned here is, for example, the side wall of the electrical conduction structure extending along the length direction.

[0046] Continue to refer to Figure 1 As shown, in this embodiment, the multi-layer insulating layer in the trench isolation structure 200 includes a first insulating layer 210, a second insulating layer 220, and a third insulating layer 230. The first insulating layer 210 and the second insulating layer 220 conformally cover the inner wall of the isolation trench 200a in sequence, and the third insulating layer 230 is located at the innermost layer of the multi-layer insulating layer to fill the isolation trench 200a. That is, the second insulating layer 220 is located between the first insulating layer 210 and the third insulating layer 230, and the third insulating layer 230 constitutes the innermost layer of the trench isolation structure 200, and the top surface of the third insulating layer 230 is lower than the top of the isolation trench 200a, so that the third insulating layer 230 sinks more relative to the top surface of the substrate 100.

[0047] Furthermore, the top surface of the third insulating layer 230 is also lower than the top surface of the second insulating layer 220, so as to utilize the second insulating layer 220 to surround a first groove above the third insulating layer 230.

[0048] Continue to refer to Figure 1 As shown, the sidewall boundary of the electrical conduction structure 300 extends beyond the sidewall boundary of the third insulating layer 230 and overlaps on the second insulating layer 220. It can be understood that the width dimension of the electrical conduction structure 300 in a predetermined direction is greater than the opening dimension of the first groove surrounded by the second insulating layer and less than the width dimension of the trench isolation structure 200.

[0049] In this embodiment, the first conductive layer 310a in the electrical conduction structure 300 fills the first groove surrounded by the second insulating layer 220 to cover the third insulating layer 230 and the sidewall of the second insulating layer 220 close to the third insulating layer, and further extends out of the first groove, so that the sidewall boundary of the first conductive layer 310a overlaps on the top of the second insulating layer 220, and correspondingly, the first conductive layer 310a has a sidewall extending out of the first groove.

[0050] In an alternative solution, the top surface of the first insulating layer 210 can also sink more relative to both the second insulating layer 220 and the substrate 100, so that a micro second groove can be surrounded by the sidewall of the second insulating layer 220, the sidewall of the isolation trench 200a, and the top surface of the first insulating layer 210. The second groove is correspondingly located between the sidewall of the second insulating layer 220 and the sidewall of the isolation trench.

[0051] Based on this, for example, the first insulating layer 210 and the third insulating layer 230 can include the same material, and the second insulating layer 220 can have a material different from that of the third insulating layer 230. In this way, when forming the trench isolation structure 200 using the etch-back process, the top surfaces of the first insulating layer 210 and the third insulating layer 230 can both sink relative to the top surface of the substrate 100. Moreover, since the second insulating layer 220 can have a material different from that of the third insulating layer 230, through the etch-back process, the first insulating layer 210 and the third insulating layer 230 can also be lower than the top surface of the second insulating layer 220.

[0052] Specifically, the materials of the first insulating layer 210 and the third insulating layer 230 both include silicon oxide (SiO), for example, and the material of the second insulating layer 220 includes silicon nitride (SiN), for example, so that the trench isolation structure 200 presents an ONO structure to improve the isolation performance of the trench isolation structure 200.

[0053] Next, referring to Figure 1 as shown, the semiconductor structure further includes a sidewall structure 400, and the sidewall structure 400 covers at least the sidewalls of the electrical conduction structure 300, so that the sidewall structure 400 covers at least the sidewalls of the first conductive layer 310a extending out of the isolation trench 200a and the sidewalls of the second conductive layer 320a.

[0054] In this embodiment, the width dimension of the electrical conduction structure 300 in a predetermined direction is greater than the width dimension of the third insulating layer 230 and less than the width dimension of the trench isolation structure 200, so that the electrical conduction structure 300 does not cover the second groove located between the second insulating layer and the sidewall of the isolation trench. Based on this, the sidewall structure 400 can be further extended to cover the second insulating layer 220 and the first insulating layer 210, so that the sidewall structure 400 also embeds into the second groove. That is, the second groove is also filled with the sidewall structure 400, so that the voids at the edge portion of the isolation trench 200a can be compensated.

[0055] Among them, the sidewall structure 400 can be a single-layer structure or a stacked structure. In this embodiment, the sidewall structure 400 includes a first isolation layer 410 and a second isolation layer 420. The first isolation layer 410 and the second isolation layer 420 sequentially cover the sidewalls of the electrical conduction structure 300 and further fill the second groove in compliance with the second insulating layer 220. Specifically, the first isolation layer 410 and the second isolation layer 420 can have different materials respectively. For example, the material of the first isolation layer 410 includes silicon oxide, and the material of the second isolation layer 420 includes silicon nitride.

[0056] Of course, in other embodiments, the sidewall structure may further include three isolation layers, and the three isolation layers sequentially cover the sidewalls of the electrical conduction structure. Moreover, the materials of the three isolation layers in the sidewall structure are, for example, silicon oxide, silicon nitride, and silicon oxide, respectively, so as to form an isolation structure of an ONO structure.

[0057] It can be understood that the trench isolation structure 200 further defines a first groove in the isolation trench 200a, the first conductive layer 310a fills the first groove in the isolation trench 200a, and the sidewall boundary of the first conductive layer 310a also overlaps on the top of the sidewall of the first groove. Moreover, the trench isolation structure 200 also defines a second groove in the isolation trench 200a, the second groove is located on the side of the first groove, and the sidewall structure 400 can fill the second groove to compensate for the voids in the edge region of the isolation trench 200a.

[0058] Specifically referring to Figure 1 As shown, in combination with the above, the sidewall boundary of the first conductive layer 310a also overlaps on the top of the sidewall of the first groove, so a first depression can be formed on the top surface of the first conductive layer 310a corresponding to the isolation trench 200a (more specifically, a first depression is formed on the top surface of the first conductive layer 310a corresponding to the first groove), and the bottom of the first depression is higher than the top of the isolation trench 200a. Moreover, the second conductive layer 320a is located above the first conductive layer 310a, and correspondingly, the bottom surface of the second conductive layer 320a corresponding to the isolation trench 200a bulges in the direction towards the first conductive layer 310a, and the top surface of the second conductive layer 320a corresponding to the isolation trench 200a concaves in the direction towards the first conductive layer 310a to form a second depression.

[0059] That is, in this embodiment, the first depression on the first conductive layer 310a and the second depression on the second conductive layer 320a are in corresponding positions. More specifically, the bottom of the first depression on the first conductive layer 310a and the bottom of the second depression on the second conductive layer 320a are aligned on the same vertical line.

[0060] Continuing to refer to Figure 1 As shown, the electrical conduction structure 300 further includes a third conductive layer 330a, and the third conductive layer 330a is formed between the first conductive layer 310a and the second conductive layer 320a. Among them, the material of the third conductive layer 330a includes, for example, titanium nitride.

[0061] In this embodiment, the third conductive layer 330a conformally covers the top surface of the first conductive layer 310a, so that the third conductive layer 330a presents a bent structure corresponding to the first recess of the first conductive layer 310a. That is, the bottom of the third conductive layer 330a corresponding to the first recess protrudes into the first recess, and further, the top surface of the third conductive layer 330a corresponding to the first recess is concave downward in the direction of the first conductive layer 310a to form a third recess. And, the part of the second conductive layer 320a close to the third conductive layer protrudes into the third recess.

[0062] Continuing to refer to Figure 1 As shown, the electrical conduction structure 300 further includes a shielding layer 340a. The shielding layer 340a is formed on the second conductive layer 320a, and the top surface of the shielding layer 340a is flatter than the top surface of the second conductive layer 320a. Specifically, for example, a planarization process can be used to make the shielding layer 340a have a flat top surface.

[0063] In addition, in this embodiment, the bottom surface of the shielding layer 340a corresponding to the second recess and the second recess also surround a gap 341. Specifically, the top surface of the second conductive layer 320a has a second recess, so that the gap 341 can be formed above the second recess.

[0064] Next, referring to Figure 1 As shown, the semiconductor structure of this embodiment includes at least two trench isolation structures 200, and adjacent trench isolation structures 200 can be used to define an active area (Active Area, AA), and semiconductor devices can also be provided in the active area. In this embodiment, an electrical conduction structure is also formed on the active area, and the electrical conduction structure located in the active area can also include a first conductive layer, a third conductive layer, a second conductive layer, and a shielding layer stacked in sequence.

[0065] Specifically, the electrical conduction structure in the semiconductor device is used to form a gate structure 300b, for example. That is, the gate structure 300b can include a first conductive layer 310b and a second conductive layer 320b, and can further include a third conductive layer 330b and a shielding layer 340b.

[0066] Further, the semiconductor integrated circuit formed by the gate structure 300b located in the active region and the electrically conductive structure 300 located in the isolation region (the region corresponding to the trench isolation structure) is, for example, the peripheral circuit of a memory. Among them, the gate structure 300b located in the active region can, for example, further form the switching transistor in the peripheral circuit. And, the electrically conductive structure 300 located in the isolation region is used, for example, for electrical transmission or for forming a dummy gate structure.

[0067] As described above, when the electrically conductive structure 300 in the isolation region is used for electrical transmission, even if the bottom of the electrically conductive structure 300 extends into the isolation trench 200a, the electrical transmission performance of the first conductive layer 310a and the second conductive layer 320a in the electrically conductive structure 300 can still be ensured. In addition, in this embodiment, the width dimension of the electrically conductive structure 300 in the isolation region is also made smaller than the width dimension of the isolation trench 200a, so as to avoid the electrically conductive structure 300 in the isolation region extending into the active region and preventing interference with the semiconductor devices in the active region.

[0068] Next, taking the electrically conductive structure 300 in the isolation region being used to form the dummy gate structure 300a as an example, a further explanation will be given.

[0069] As Figure 1 shown, the gate structure 300b is formed on the top surface of the substrate 100, and the top surface of the first conductive layer 310b in the gate structure 300b is flatter than the top surface of the first conductive layer 310a in the dummy gate structure 300a. Correspondingly, the top surfaces of the third conductive layer 330b and the second conductive layer 320b in the gate structure 300b are both flatter than the top surfaces of the third conductive layer 330a and the second conductive layer 320a in the dummy gate structure 300a.

[0070] And, in the gate structure 300b, the bottom surface of its shielding layer 340b is in closed contact with the top surface of the second conductive layer 320b, so there is no gap formed in the shielding layer 340b of the gate structure 300b.

[0071] In addition, the top surface of the first conductive layer 310b in the gate structure 300b is also higher than the top surface of the first conductive layer 310a in the dummy gate structure 300a. Correspondingly, the third conductive layer 330b in the gate structure 300b is also higher than the third conductive layer 330a in the dummy gate structure 300a; and, the second conductive layer 320b in the gate structure 300b is also higher than the second conductive layer 320a in the dummy gate structure 300a. However, it should be noted that in this embodiment, the top surface of the masking layer 340b in the gate structure 300b may be flush with the top surface of the masking layer 340a in the dummy gate structure 300a, that is, the top surfaces of the masking layer located on the trench isolation structure and the masking layer located on the active region are coplanar.

[0072] Based on the semiconductor structure described above, in this embodiment, a method for forming a semiconductor structure is also provided. Figure 2 It is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present invention. As Figure 2 shown, the method for forming a semiconductor structure in this embodiment includes:

[0073] Step S100: Provide a substrate and form isolation trenches in the substrate.

[0074] Step S200: Form a trench isolation structure in the isolation trenches, and at least a part of the top surface of the trench isolation structure sinks more relative to the top surface of the substrate.

[0075] Step S300: Form a first conductive layer and a second conductive layer on the substrate. The first conductive layer fills the isolation trenches and extends out of the isolation trenches, and the second conductive layer is formed on the first conductive layer.

[0076] Figures 3a to 3d It is a schematic structural diagram of a semiconductor structure in the preparation process according to an embodiment of the present invention. Hereinafter, with reference to the drawings, each step of forming the semiconductor structure in this embodiment will be described in detail.

[0077] In step S100, specifically referring to Figure 3a shown, provide a substrate 100 and form isolation trenches 200a in the substrate 100.

[0078] Among them, the method for forming the isolation trenches 200a includes, for example: First, form a mask layer (not shown in the figure) on the substrate 100 to define the pattern of the isolation trenches by using the mask layer; then, etch the substrate 100 with the mask layer as a mask to form the isolation trenches 200a.

[0079] Figure 3a ​As shown, in this embodiment, the opening size of the isolation trench 200a can gradually decrease from the top to the bottom of the trench, so that the isolation trench 200a has inclined sidewalls. By forming the isolation trench 200a with inclined sidewalls, when filling the insulating material into the isolation trench 200a subsequently, the filling performance of the insulating material can be effectively improved, and the problem of voids in the insulating material layer filled in the isolation trench 200a can be avoided.

[0080] In step S200, specifically referring to Figure 3b As shown, a trench isolation structure 200 is formed in the isolation trench 200a, and at least a part of the top surface of the trench isolation structure 200 sinks more relative to the top surface of the substrate 100.

[0081] It should be noted that in the traditional process, the trench isolation structure is often prepared by a planarization process, so that the top surface of the formed trench isolation structure is flush with the top surface of the substrate, or even the trench isolation structure protrudes from the top surface of the substrate (that is, the top surface of the trench isolation structure is higher than the top surface of the substrate).

[0082] In this embodiment, based on an etching process, a multi-layer insulating layer is formed in the isolation trench 200a to form a trench isolation structure 200, so as to at least reduce the height of the innermost insulating layer in the trench isolation structure 200, thereby realizing that the formed trench isolation structure 200 can be recessed relative to the top surface of the substrate 100.

[0083] Specifically, the formation method of the trench isolation structure 200 includes the following steps, for example.

[0084] Step 1, a first insulating material layer and a second insulating material layer are sequentially formed on the substrate 100. The first insulating material layer and the second insulating material layer conformally cover the inner walls (including the bottom wall and the side walls) of the isolation trench 200a, and also cover the top surface of the substrate 100.

[0085] In this embodiment, the first insulating material layer includes a silicon oxide layer, for example, and the second insulating material layer includes a silicon nitride layer, for example. Among them, the silicon oxide layer can be formed by an oxidation process, and the silicon nitride layer can be formed by a chemical vapor deposition process.

[0086] Step 2, a third insulating material layer is deposited on the substrate 100. The third insulating material layer covers the second insulating material layer and fills the isolation trench 200a. Among them, the material of the third insulating material layer includes silicon oxide, for example.

[0087] Step 3, perform an etching process to etch the third insulating material layer, the second insulating material layer, and the first insulating material layer, so as to remove the portions of the third insulating material layer, the second insulating material layer, and the first insulating material layer located on the top surface of the substrate, and fill the remaining third insulating material layer, second insulating material layer, and first insulating material layer in the isolation trenches, respectively, to form a third insulating layer 230, a second insulating layer 220, and a first insulating layer 210, wherein the top surface of the third insulating layer 230 is lower than the top surface of the substrate 100.

[0088] Specifically, the third insulating material layer covers the top layer. Therefore, in the etching process, the etchant preferentially etches the third insulating material layer to remove the portion of the third insulating material layer located on the top surface of the substrate, thereby exposing the second insulating material layer; then, continue to remove the second insulating material layer on the top surface of the substrate to make the second insulating material layer remaining in the isolation trench 200a form the second insulating layer 220; then, the exposed first insulating material layer can be continuously etched to form the first insulating layer 210.

[0089] Furthermore, when etching the first insulating material layer and / or the second insulating material layer, the etchant also etches the third insulating material layer located in the isolation trench, so that the third insulating material layer remaining in the isolation trench 200a can sink more relative to the top surface of the substrate 100.

[0090] In this embodiment, when etching the first insulating material layer, the etchant can also etch the third insulating material layer located in the isolation trench, so that both the third insulating material layer and the first insulating material layer remaining in the isolation trench 200a sink more relative to the top surface of the substrate 100, and form the third insulating layer 230 and the first insulating layer 210, respectively.

[0091] That is, in this embodiment, the top surfaces of the first insulating layer 210 and the third insulating layer 230 are both lower than the top surface of the second insulating layer 220. In this way, a first groove 200b can be surrounded by the second insulating layer 220 in the isolation trench 200a; and, a second groove 200c can also be surrounded by the sidewalls of the second insulating layer 220 and the isolation trench 200a.

[0092] In addition, it should be noted that at least two trench isolation structures 200 are formed on the substrate 100, and the adjacent trench isolation structures 200 can be used to further define the active area (Active Area, AA) of the semiconductor device. In subsequent processes, corresponding semiconductor devices can be fabricated in the active area.

[0093] In step S300, specifically refer toFigure 3c As shown, a first conductive layer 310a and a second conductive layer 320a are formed on the substrate 100, wherein the sidewall boundary of the first conductive layer 310a is between the boundary of the first groove 200b and the boundary of the isolation trench 200a to fill the first groove 200b, and the top of the first conductive layer 310a also extends upward out of the isolation trench 200a, and the second conductive layer 320a is formed on the first conductive layer 310a. Among them, the first conductive layer 310a and the second conductive layer 320a can be used to form an electrical conduction structure 300.

[0094] Furthermore, the projected area of the second conductive layer 320a in the height direction can be made not less than the top surface area of the first conductive layer 310a. In this embodiment, the sidewall boundaries of the second conductive layer 320a and the first conductive layer 310a coincide.

[0095] In this embodiment, the electrical conduction structure has a portion formed on the trench isolation structure 200 and can further form a pseudo-gate structure 300a.

[0096] In an alternative solution, when fabricating an electrical conduction structure (pseudo-gate structure 300a) on the trench isolation structure 200, an electrical conduction structure can also be fabricated on the active region at the same time to form a gate structure 300b in the active region. Specifically, the method for simultaneously forming the pseudo-gate structure 300a and the gate structure 300b includes the following steps, for example.

[0097] The first step is to deposit a first conductive material layer on the substrate 100. In this embodiment, the first conductive material layer covers the substrate of the active region and covers the trench isolation structure 200 and fills the first groove 200b.

[0098] Among them, a first depression is formed on the top surface of the first conductive material layer corresponding to the first groove 200b, and the bottom of the first depression is higher than the top of the isolation trench 200a. That is, the top surface of the first conductive material layer corresponding to the active region is flatter than the top surface of the first conductive material layer corresponding to the isolation region.

[0099] The second step is to deposit a second conductive material layer on the first conductive material layer.

[0100] Similarly, the second conductive material layer covers the active region and the isolation region (i.e., the trench isolation structure), and the bottom surface of the second conductive material layer corresponding to the first depression protrudes in the direction towards the first conductive material layer, and the top surface of the second conductive material layer corresponding to the first depression is concave in the direction towards the first conductive material layer to form a second depression.

[0101] Further, before depositing the second conductive material layer, it further includes: depositing a third conductive material layer on the first conductive material layer. And the second conductive material layer is formed on the third conductive material layer.

[0102] Furthermore, after depositing the second conductive material layer, it further includes: forming a masking material layer on the second conductive material layer. Specifically, the masking material layer can be formed by a planarization process so that the top surface of the masking material layer is flatter than the top surface of the second conductive material layer, that is, the top surfaces of the masking material layer located in the isolation region and the active region are flush.

[0103] In addition, in this embodiment, there is a second depression on the second conductive material layer located in the isolation region. Based on this, when depositing the masking material layer, a gap can be formed in the part of the masking material layer corresponding to the second depression.

[0104] The third step is to pattern the second conductive material layer and the first conductive material layer to form the second conductive layer and the first conductive layer stacked. Specifically, the patterning method for the second conductive material layer and the first conductive material layer includes, for example:

[0105] First, form a patterned mask layer on the second conductive material layer; in this embodiment, the mask layer is formed on the masking material layer, and the pattern of the mask layer includes a dummy gate pattern corresponding to the isolation region and a gate pattern corresponding to the active region;

[0106] Then, using the mask layer as a mask, etch the second conductive material layer and the first conductive material layer in sequence to form the second conductive layer and the first conductive layer respectively. In this embodiment, the masking material layer and the third conductive material layer are also etched using the mask layer as a mask to form a masking layer and a third conductive layer respectively. As described above, the top surfaces of the masking material layer located in the isolation region and the active region are flush. Based on this, after forming the masking layers on the isolation region and the active region respectively, the top surfaces of the masking layer located in the isolation region and the masking layer located in the active region are coplanar.

[0107] Focus on Figure 3cAs shown, the first conductive layer, the third conductive layer, the second conductive layer, and the shielding layer are formed in the isolation region (corresponding to the trench isolation structure) and the active region. The first conductive layer 310a, the third conductive layer 330a, the second conductive layer 320a, and the shielding layer 340a in the isolation region are used to form a dummy gate structure 300a; and the first conductive layer 310b, the third conductive layer 330b, the second conductive layer 320b, and the shielding layer 340b in the active region are used to form a gate structure 300b.

[0108] In this embodiment, the dummy gate structure 300a fills the first groove 200b of the isolation trench 200a, and the sidewall boundary of the dummy gate structure 300a overlaps the second insulating layer 220, that is, the dummy gate structure 300a does not fill the second groove 200c in the isolation trench 200a.

[0109] In a further solution, the method for forming a semiconductor structure further includes: step S400, forming a sidewall structure.

[0110] Specific reference Figure 3d As shown, the spacer structure 400 at least covers the sidewalls of the first conductive layer 310a extending out of the isolation trench and the sidewalls of the second conductive layer 320a, and further extends into the second groove to fill the second groove.

[0111] like Figure 3d As shown, in this embodiment, a sidewall structure 400 is formed on the sidewall of the dummy gate structure 300a, and a sidewall structure is also formed on the sidewall of the gate structure 300b to cover the sidewalls of the first conductive layer 310b, the third conductive layer 330b and the second conductive layer 320b in the gate structure 300b.

[0112] At this point, it is achieved that the gate structure 300b can be formed in the active area and the dummy gate structure 300a can be formed in the isolation area at the same time using the same process steps, and the sidewall structure 400 can be formed on the side walls of the gate structure 300b and the dummy gate structure 300a at the same time, which is conducive to simplifying the process.

[0113] In summary, in the semiconductor structure of this embodiment, by arranging at least a portion of the electrically conductive structure above the trench isolation structure, the space above the trench isolation structure can be fully utilized, which is equivalent to reducing the space occupied by the electrically conductive structure in the entire semiconductor integrated circuit, thereby facilitating the size reduction of the constructed semiconductor integrated circuit.

[0114] In an alternative solution, the width dimension of the electrically conductive structure forming the pseudo-gate structure is smaller than the opening dimension of the isolation trench, so as to prevent the pseudo-gate structure from interfering with the semiconductor devices in the active region (for example, affecting the gate structure in the active region).

[0115] In a further solution, even if the trench isolation structure is composed of multiple insulating material layers, the same etching process is still used to etch the multiple insulating material layers in sequence. At this time, due to the difference in the etching rates of different insulating materials, there is a height difference between the obtained multiple insulating layers (for example, there is a height difference between the first insulating layer and the second insulating layer in this embodiment). And, since the electrically conductive structure in the isolation region does not extend to the edge of the isolation trench in a predetermined direction (for example, the width direction of the electrically conductive structure), the second groove surrounded by the second insulating layer and the side wall of the isolation trench in the isolation trench is not filled by the electrically conductive structure. Based on this, the sidewall structure can further fill the second groove on the basis of covering the sidewall of the electrically conductive structure, so as to compensate for the gap at the edge of the isolation trench and ensure the isolation performance of the trench isolation structure.

[0116] It should be noted that when forming a trench isolation structure by a planarization process in the prior art, when the trench isolation structure includes multiple insulating material layers, the planarization process needs to be performed separately for the specific materials of different insulating material layers, and its operation steps are relatively cumbersome. It can be seen that compared with the traditional process, in this embodiment, when preparing the trench isolation structure, the process can be simplified on the basis of ensuring the isolation performance of the trench isolation structure.

[0117] It should be noted that the above description is only a description of the preferred embodiments of the present invention, and does not limit the scope of the present invention in any way. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or it can be modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of the protection of the technical solution of the present invention.

[0118] It should also be noted that unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish each component, element, step, etc. in the specification, rather than to represent the logical relationship or sequential relationship between each component, element, step, etc. And, the word "or" should be understood as having the definition of logical "or", rather than the definition of logical "exclusive or", unless the context clearly indicates the opposite meaning.

Claims

1. A semiconductor structure, characterized in that, Comprising: A trench isolation structure formed in an isolation trench of a substrate, wherein the trench isolation structure includes multiple insulating layers which sequentially cover the inner wall of the isolation trench, and the top surface of the innermost insulating layer in the multiple insulating layers sinks more relative to the top surface of the substrate to form a first groove in the isolation trench; the multiple insulating layers include a first insulating layer, a second insulating layer, and a third insulating layer. The first insulating layer and the second insulating layer sequentially cover the inner wall of the isolation trench, and the third insulating layer is located at the innermost layer of the multiple insulating layers to fill the isolation trench. The top surface of the first insulating layer sinks more relative to the second insulating layer; The top surface of the third insulating layer is lower than the top surface of the second insulating layer to define the first groove above the third insulating layer by means of the second insulating layer; And, An electrically conductive structure formed on the substrate and at least partially located on the trench isolation structure, and the electrically conductive structure completely fills the first groove; wherein, the electrically conductive structure includes a first conductive layer and a second conductive layer. The first conductive layer fills the first groove and extends out of the isolation trench, and the second conductive layer is formed on the first conductive layer.

2. The semiconductor structure according to claim 1, wherein The sidewall boundary of the electrically conductive structure is between the boundary of the first groove and the boundary of the isolation trench.

3. The semiconductor structure according to claim 1, wherein The sidewall boundary of the electrically conductive structure extends beyond the sidewall boundary of the third insulating layer and overlaps on the second insulating layer.

4. The semiconductor structure according to claim 1, wherein, The projected area of the second conductive layer in the height direction is not less than the top surface area of the first conductive layer.

5. The semiconductor structure according to claim 1, wherein A first depression is formed on the top surface of the first conductive layer corresponding to the first groove, and the bottom of the first depression is higher than the top of the first groove.

6. The semiconductor structure according to claim 5, characterized in that, The electrically conductive structure further includes a third conductive layer formed between the first conductive layer and the second conductive layer; and, the bottom of the third conductive layer corresponding to the first depression protrudes into the first depression, and the top surface of the third conductive layer corresponding to the first depression is concave in the direction towards the first conductive layer.

7. The semiconductor structure according to claim 1, wherein The bottom surface of the second conductive layer corresponding to the first groove protrudes in the direction towards the first conductive layer, and the top surface of the second conductive layer corresponding to the first groove is concave in the direction towards the first conductive layer to form a second depression.

8. The semiconductor structure according to claim 7, wherein The electrically conductive structure further includes a shielding layer formed on the second conductive layer, and a gap is defined between the bottom surface of the shielding layer corresponding to the second depression and the second depression.

9. The semiconductor structure as described in claim 1, wherein, In the semiconductor structure, an active region is defined by the trench isolation structure, and an electrically conductive structure is also formed on the active region; Wherein, the electrically conductive structures located on the trench isolation structure and the electrically conductive structures located on the active region both include a shielding layer. The shielding layer is formed on the conductive layer of the electrically conductive structure, and the top surfaces of the shielding layer located on the trench isolation structure and the shielding layer located on the active region are coplanar.

10. A semiconductor structure, characterized in that, Comprising: A trench isolation structure is formed in an isolation trench of a substrate, and at least a part of the top surface of the trench isolation structure is sunken more relative to the top surface of the substrate; wherein the trench isolation structure includes a multi-layer insulating layer, the multi-layer insulating layer includes a first insulating layer, a second insulating layer and a third insulating layer, the first insulating layer and the second insulating layer sequentially cover the inner wall of the isolation trench, and the third insulating layer is located in the innermost layer of the multi-layer insulating layer to fill the isolation trench; The top surface of the third insulating layer is lower than the top surface of the second insulating layer to define a first groove above the third insulating layer by using the second insulating layer; An electrically conductive structure is formed on the trench isolation structure of the substrate and fills the isolation trench, wherein the electrically conductive structure includes a first conductive layer and a second conductive layer, the first conductive layer fills the isolation trench and extends out of the isolation trench, the second conductive layer is formed on the first conductive layer, and depressions are formed on the top surfaces of the first conductive layer and the second conductive layer corresponding to the top surface of the isolation trench; And, A masking layer is formed on the second conductive layer of the electrically conductive structure, and a gap is defined by the depression in the masking layer corresponding to the depression in the second conductive layer and the depression in the second conductive layer.

11. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a substrate and forming an isolation trench in the substrate; Forming a multi-layer insulating layer in the isolation trench to constitute a trench isolation structure, and the top surface of the insulating layer located in the innermost layer of the multi-layer insulating layer is sunken more relative to the top surface of the substrate to constitute a first groove in the isolation trench; And, Forming a first conductive layer and a second conductive layer on the substrate to constitute an electrically conductive structure, wherein the first conductive layer completely fills the first groove and extends out of the isolation trench, and the second conductive layer is formed on the first conductive layer; Wherein, the method for forming the trench isolation structure includes: Sequentially forming a first insulating material layer and a second insulating material layer on the substrate, the first insulating material layer and the second insulating material layer sequentially cover the inner wall of the isolation trench and also cover the top surface of the substrate; Depositing a third insulating material layer on the substrate, the third insulating material layer covers the second insulating material layer and fills the isolation trench; and, Performing an etching process to etch the third insulating material layer, the second insulating material layer and the first insulating material layer to remove the portions of the third insulating material layer, the second insulating material layer and the first insulating material layer located on the top surface of the substrate, and filling the remaining third insulating material layer, second insulating material layer and first insulating material layer in the isolation trench to respectively constitute a third insulating layer, a second insulating layer and a first insulating layer; In the etching process, when etching the second insulating material layer and / or the first insulating material layer, the etchant also etches the third insulating material layer located in the isolation trench, so that the top surface of the formed third insulating layer is lower than the top surface of the second insulating layer, and the second insulating layer is used to surround the first groove above the third insulating layer.

12. The method for forming a semiconductor structure according to claim 11, wherein The sidewall boundary of the first conductive layer is between the boundary of the first groove and the boundary of the isolation trench.

13. The method for forming a semiconductor structure according to claim 11, wherein In the etching process, after removing the second insulating material layer on the top surface of the substrate and etching the first insulating material layer, the etchant also etches the third insulating material layer located in the isolation trench, so that both the first insulating layer and the third insulating layer remaining in the isolation trench sink more relative to the top surface of the second insulating layer, and the second insulating layer and the sidewall of the isolation trench are used to surround the second groove.

14. The method for forming a semiconductor structure according to claim 11, wherein The method for forming the first conductive layer and the second conductive layer includes: Depositing a first conductive material layer on the substrate, the first conductive material layer covering the trench isolation structure and filling the first groove, and a first depression being formed in the first conductive material layer corresponding to the top surface of the first groove, the bottom of the first depression being higher than the top of the first groove; Depositing a second conductive material layer on the first conductive material layer, the second conductive material layer protruding into the first depression corresponding to the bottom of the first depression, and the top surface of the second conductive material layer corresponding to the first depression being concave downward in the direction towards the first conductive material layer to form a second depression; and Patterning the second conductive material layer and the first conductive material layer to form the second conductive layer and the first conductive layer stacked.

15. The method for forming a semiconductor structure according to claim 11, wherein In the semiconductor structure, when the trench isolation structure is used to define the active region and an electrically conductive structure is fabricated on the trench isolation structure, an electrically conductive structure is also fabricated on the active region; wherein, after forming the conductive layer of the electrically conductive structure, it further includes: Using a planarization process to form a masking layer on the conductive layer of the electrically conductive structure, and the top surfaces of the masking layer located on the trench isolation structure and the masking layer located on the active region being coplanar.

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