Transistor and method for forming the same

Abstract

The present invention provides a transistor, a method for forming the same, and a semiconductor device. The gate dielectric layer in the transistor has an upper portion and a lower portion, and the upper portion is stacked, so that the thickness of the upper portion can be increased without changing the thickness of the lower portion. Thus, the gate-induced drain leakage (GIDL) phenomenon can be improved while maintaining the performance of the transistor; moreover, in the present invention, the thickness of the upper portion is increased by stacking, which is conducive to realizing flexible adjustment of the parameters of the upper portion.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a transistor and a method for forming the same. Background Art

[0002] With the continuous reduction of the size of semiconductor devices, the feature size of field effect transistors has also been rapidly reduced, and the thickness of the corresponding gate dielectric layer has become thinner and thinner. The problem of device reliability caused by the thin gate dielectric layer has become increasingly prominent.

[0003] Specifically, due to the increasing thinness of transistor devices, the gate-induced drain leakage (GIDL) generated by transistors in the off state or waiting state has become more and more serious, which will have a greater impact on the reliability of transistors, resulting in the instability of transistors and an increase in the static power consumption of transistors. Therefore, with the continuous reduction of the feature size of transistors, how to reduce the leakage current of devices has become a key issue in high-density, low-power semiconductor technology. Summary of the Invention

[0004] The purpose of the present invention is to provide a transistor to improve the phenomenon of gate-induced drain leakage (GIDL) existing in existing transistors.

[0005] To solve the above technical problems, the present invention provides a transistor, including:

[0006] A substrate, in which a gate trench is formed; and,

[0007] A gate dielectric layer covering the inner wall of the gate trench, wherein the gate dielectric layer has an upper portion and a lower portion, the upper portion covering the inner wall of the gate trench at a position higher than a predetermined height, and the lower portion covering the inner wall of the gate trench at a position lower than the predetermined height; wherein, the upper portion includes a lining layer and an outer covering layer, the lining layer covering the inner wall of the gate trench, the outer covering layer covering the outer side wall of the lining layer, and the sum of the thicknesses of the lining layer and the outer covering layer is greater than the thickness value of the lower portion.

[0008] Optionally, in the gate dielectric layer, the thickness difference between the lower portion and the lining layer is less than the thickness value of the outer covering layer; or the thickness difference between the lower portion and the outer covering layer is less than the thickness value of the lining layer.

[0009] Optionally, the gate dielectric layer includes a first dielectric layer and a second dielectric layer;

[0010] Wherein, the first dielectric layer covers the inner wall of the gate trench, and the part of the first dielectric layer below the predetermined height position constitutes the lower layer part, and the part of the first dielectric layer above the predetermined height position constitutes the inner liner layer; and, the second dielectric layer covers the part of the first dielectric layer above the predetermined height position to constitute the outer cover layer of the upper layer part.

[0011] Optionally, the outer cover layer of the upper layer part protrudes away from the inner wall of the trench with respect to the lower layer part.

[0012] Optionally, the transistor further includes:

[0013] A gate conductive layer, the gate conductive layer is formed on the gate dielectric layer and is located in the gate trench, and the gate conductive layer extends from the lower layer part to the upper layer part, and the width dimension of the gate conductive layer above the predetermined height position is smaller than the width dimension of the gate conductive layer below the predetermined height position.

[0014] Optionally, the gate dielectric layer includes a first dielectric layer and a second dielectric layer;

[0015] Wherein, the first dielectric layer covers the inner wall of the gate trench above the predetermined height position to constitute the inner liner layer; and, the second dielectric layer covers the first dielectric layer and the inner wall of the gate trench below the predetermined height position, and the part of the second dielectric layer above the predetermined height position constitutes the outer cover layer, and the part of the second dielectric layer below the predetermined height position constitutes the lower layer part.

[0016] Optionally, the inner liner layer of the upper layer part protrudes towards the inner wall of the trench with respect to the lower layer part.

[0017] Optionally, the transistor further includes:

[0018] A gate conductive layer, the gate conductive layer is formed on the gate dielectric layer and is located in the gate trench, and the sidewall boundary of the gate conductive layer conforms to the sidewall of the second dielectric layer and extends from the lower layer part to the upper layer part.

[0019] Optionally, the transistor further includes:

[0020] Source-drain regions, the bottom boundary of the source-drain regions is lower than the top position of the gate conductive layer and higher than the predetermined height position, so that there is an upper layer part of the gate dielectric layer between the source-drain regions and the gate conductive layer.

[0021] Based on the transistor as described above, the present invention further provides a method for forming a transistor, including:

[0022] Provide a substrate in which gate trenches are formed; and,

[0023] Form a gate dielectric layer on the inner walls of the gate trenches. The gate dielectric layer includes an upper portion and a lower portion. The upper portion covers the inner walls of the gate trenches at positions higher than a predetermined height, and the lower portion covers the inner walls of the gate trenches at positions lower than the predetermined height. Wherein, the upper portion includes a liner layer and an outer cover layer. The liner layer covers the inner walls of the gate trenches, and the outer cover layer covers the outer sidewalls of the liner layer. And the sum of the thicknesses of the liner layer and the outer cover layer is greater than the thickness value of the lower portion.

[0024] Optionally, after forming the gate trenches, form the gate dielectric layer. The method for forming the gate dielectric layer includes:

[0025] Form a first dielectric layer on the inner walls of the gate trenches;

[0026] Fill a sacrificial layer in the gate trenches. The sacrificial layer is filled upward from the bottom of the gate trenches to a predetermined height position, and exposes the outer sidewalls of the first dielectric layer that are higher than the sacrificial layer;

[0027] Form a second dielectric layer on the exposed outer sidewalls of the first dielectric layer. The gate dielectric layer is composed of the first dielectric layer and the second dielectric layer. Wherein, the portion of the first dielectric layer at positions lower than the predetermined height forms the lower portion, the portion of the first dielectric layer at positions higher than the predetermined height forms the liner layer, and the second dielectric layer forms the outer cover layer; and,

[0028] Remove the sacrificial layer.

[0029] Optionally, form the gate trenches when preparing the gate dielectric layer. The method for forming the gate trenches and the gate dielectric layer includes:

[0030] Form a first trench in the substrate. The bottom position of the first trench is at the predetermined height position;

[0031] Form a first dielectric layer on the sidewalls of the first trench;

[0032] Etch the bottom of the first trench using the first dielectric layer as a mask to form a second trench. The second trench and the first trench are vertically connected to form the gate trench;

[0033] Form a second dielectric layer in the gate trench, where the second dielectric layer covers the inner wall of the second trench and the outer sidewall of the first dielectric layer, and the gate dielectric layer is composed of the second dielectric layer and the first dielectric layer. Among them, the first dielectric layer forms the inner lining layer, the part of the second dielectric layer covering the first dielectric layer forms the outer cover layer, and the part of the second dielectric layer covering the inner wall of the second trench forms the lower layer part.

[0034] Optionally, after forming the gate dielectric layer, it further includes:

[0035] Form a gate conductive layer in the gate trench, and the top position of the gate conductive layer is higher than the predetermined height position, so that the gate conductive layer extends from the lower layer part of the gate dielectric layer to the upper layer part.

[0036] Optionally, after forming the gate dielectric layer, it further includes:

[0037] Form source and drain regions in the substrate, and the bottom boundary of the source and drain regions is lower than the top position of the gate conductive layer and higher than the predetermined height position, so that there is an upper layer part of the gate dielectric layer between the source and drain regions and the gate conductive layer.

[0038] In the transistor provided by the present invention, the gate dielectric layer has an upper layer part and a lower layer part with different thicknesses, where the upper layer part is a stacked structure including an inner lining layer and an outer cover layer. That is, in the gate dielectric layer of the present invention, the thickness of the upper layer part can be further increased by stacking film layers while maintaining the thickness of the lower layer part unchanged. In this way, on the basis of maintaining the on-state performance and saturation current of the transistor, the phenomenon of gate-induced drain leakage (GIDL) can be improved, and the problem of mutual limitation between the transistor performance and the phenomenon of gate-induced drain leakage existing in the existing transistors is overcome.

[0039] Moreover, it should be noted that since the upper layer part of the gate dielectric layer realizes the increase in thickness through stacking, it is beneficial to flexibly adjust the parameters of each stack in the upper layer part (for example, the thickness, material, etc. of each stack can be flexibly adjusted), and then the parameters of the upper layer part of the gate dielectric layer can be correspondingly adjusted according to actual needs. Description of the Drawings

[0040] Figure 1a It is a schematic structural diagram of the transistor in the first embodiment of the present invention;

[0041] Figure 1b It is a schematic structural diagram of the gate dielectric layer of the transistor in the first embodiment of the present invention

[0042] Figures 2a - 2fSchematic diagram of the structure in the preparation process of the method for forming a transistor in Embodiment 1 of the present invention;

[0043] Figure 3a Schematic diagram of the structure of the transistor in Embodiment 2 of the present invention;

[0044] Figure 3b Schematic diagram of the structure of the gate dielectric layer of the transistor in Embodiment 2 of the present invention;

[0045] Figures 4a - 4e Schematic diagram of the structure in the preparation process of the method for forming a transistor in Embodiment 2 of the present invention.

[0046] Among them, the reference numerals are as follows:

[0047] 10 - Substrate;

[0048] 100 / 100’ - Gate conductive layer;

[0049] 100a / 100a’ - Gate trench;

[0050] 110a - First trench;

[0051] 200 / 200’ - Gate dielectric layer;

[0052] 210 / 210’ - First dielectric layer;

[0053] 220 / 220’ - Second dielectric layer;

[0054] 200a / 200a’ - Lower layer part;

[0055] 200b / 200b’ - Upper layer part;

[0056] 210b / 210b’ - Inner lining layer;

[0057] 220b / 220b’ - Outer cover layer;

[0058] 310 - First source / drain region;

[0059] 320 - Second source / drain region;

[0060] 400 - Insulating dielectric layer;

[0061] 500 - Sacrificial layer;

[0062] H1 - First height position;

[0063] H2 - Second height position;

[0064] H3 - Third height position. Detailed implementation manners

[0065] As described in the background art, as the size of semiconductor devices continues to shrink, in existing transistors, since the thickness of the gate dielectric layer also decreases accordingly, the phenomenon of gate-induced drain leakage (GIDL) becomes particularly obvious.

[0066] To improve the gate-induced drain leakage (GIDL) of existing transistors, directly increasing the thickness of the gate dielectric layer can indeed improve the drain leakage problem of the transistors. However, it will also have an adverse impact on the conduction performance of the transistors. For example, it will cause problems such as an increase in the turn-on voltage of the transistors and a decrease in the saturation current of the transistors. It can be seen that for the performance of the transistors and the phenomenon of gate-induced drain leakage, the two limit each other, resulting in the inability of existing transistors to meet both simultaneously.

[0067] In view of this, the present invention provides a transistor that can improve the drain leakage phenomenon of the transistor on the basis of ensuring the performance of the transistor.

[0068] The transistor, its forming method, and the semiconductor device proposed by the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0069] Embodiment 1

[0070] Figure 1a is a schematic structural diagram of the transistor in Embodiment 1 of the present invention, Figure 1b is a schematic structural diagram of the gate dielectric layer of the transistor in Embodiment 1 of the present invention. As Figure 1a and Figure 1b shown, the transistor includes: a substrate 10 in which a gate trench 100a is formed; and a gate dielectric layer 200 covering the inner wall of the gate trench 100a.

[0071] With key reference to Figure 1b and in conjunction with Figure 1a shown, the gate dielectric layer 200 has an upper portion 200b and a lower portion 200a. The upper portion 200b covers the inner wall of the gate trench 100a at a position higher than a predetermined height (i.e., the first height position H1), and the lower portion 200a covers the inner wall of the gate trench 100a at a position lower than the predetermined height (i.e., the first height position H1).

[0072] Among them, the upper part 200b has a laminated structure so that the thickness of the upper part 200b is greater than that of the lower part 200a. In this embodiment, the upper part 200b includes a lining layer 210b and an outer cover layer 220b. The lining layer 210b covers the inner wall of the gate trench 100a, and the outer cover layer 220b covers the outer side wall of the lining layer 210b. Moreover, the sum of the thicknesses of the lining layer 210b and the outer cover layer 220b is greater than the thickness value of the lower part 200a.

[0073] Furthermore, in the gate dielectric layer 200 of this embodiment, the thickness difference between the lower part 200a and the lining layer 210b is less than the thickness value of the outer cover layer 220b; or, the thickness difference between the lower part 200a and the outer cover layer 220b is less than the thickness value of the lining layer 210b. In this way, the sum of the thicknesses of the lining layer 210b and the outer cover layer 220b will necessarily be greater than the thickness value of the lower part 200a.

[0074] Illustrated with a specific example, since the thickness difference between the lower part 200a and the lining layer 210b is small (that is, the thickness difference is less than the thickness value of the outer cover layer 220b), for example, the lower part 200a and the lining layer 210b have the same or similar thickness values. At this time, based on the fact that the upper part 200b further includes the outer cover layer 220b, the thickness value of the upper part 200b will necessarily be greater than the thickness value of the lower part 200a.

[0075] Continue to refer to Figure 1a As shown, in a specific transistor, the lower part 200a in the gate dielectric layer 200 is located between the gate conductive layer 100 and the substrate for forming the conductive channel. The lower part 200a can be adjusted according to actual requirements to ensure the conduction performance of the transistor and maintain the saturation current of the transistor. And, the upper part 200b in the gate dielectric layer 200 is at least located between the gate conductive layer 100 and the source-drain region. Since the upper part 200b has a relatively thick thickness, it can effectively alleviate the gate-induced drain leakage current (GIDL) and relieve the drain leakage current phenomenon of the transistor, so as to further improve the overall performance of the transistor. That is, the transistor in this embodiment can reduce the gate-induced drain leakage current (GIDL) of the transistor on the basis of ensuring the conduction performance and saturation current of the transistor, and thus can improve the overall performance of the transistor.

[0076] It can be understood that the predetermined height position described in this embodiment is: not lower than the bottom boundary of the overlapping region where the gate conductive layer and the source-drain region overlap each other.

[0077] Specifically, the source / drain regions of the transistor include a first source / drain region 310 and a second source / drain region 320 respectively located on both sides of the gate trench 100a. The side edge boundaries of the first source / drain region 310 and the second source / drain region 320 both extend to the side walls of the gate trench 100a. Moreover, the bottom boundaries of the first source / drain region 310 and the second source / drain region 320 are not lower than the predetermined height position. In this embodiment, the bottom positions of the first source / drain region 310 and the second source / drain region 320 are the second height position H2, and the second height position H2 is higher than the first height position H1.

[0078] In addition, the gate conductive layer 100 is formed on the gate dielectric layer 200 and is located within the gate trench 100a, and the gate conductive layer 100 extends from the lower portion 200a to the upper portion 200b of the gate dielectric layer 200, so that the top position of the gate conductive layer 100 is higher than the predetermined height position (i.e., the first height position H1).

[0079] Specifically, the top position of the gate conductive layer 100 corresponds to the third height position H3, and the third height position H3 is higher than the first height position H1. Moreover, the third height position H3 is further higher than the second height position H2. It can be considered that the overlapping region between the gate conductive layer 100 and the source / drain regions is between the second height position H2 and the third height position H3.

[0080] As described above, the upper portion 200b of the gate dielectric layer 200 covers the inner wall of the gate trench 100a that is higher than the predetermined height position. Then, the upper portion 200b correspondingly covers the inner wall of the gate trench 100a between the second height position H2 and the third height position H3, so that there is a relatively thick upper portion 200b between the gate conductive layer 100 and the source / drain regions.

[0081] Continue to refer to Figure 1a and Figure 1b As shown, the gate dielectric layer 200 includes a first dielectric layer 210 and a second dielectric layer 220 that sequentially cover the inner wall of the trench. Among them, the first dielectric layer 210 and the second dielectric layer 220 can be formed of the same material. For example, both include silicon oxide. Of course, they can also be formed of different materials, which will be described in detail later.

[0082] In this embodiment, the first dielectric layer 210 covers the inner wall of the gate trench 100a, and the portion of the first dielectric layer 210 below the predetermined height position (i.e., the first height position H1) constitutes the lower portion 200a, and the portion of the first dielectric layer 210 above the predetermined height position (i.e., the first height position H1) constitutes the lining layer 210b of the upper portion 200b; and, the second dielectric layer 220 covers the portion of the first dielectric layer 210 above the predetermined height position, constituting the outer cover layer 220b of the upper portion 200b.

[0083] It can be understood that in this embodiment, the lower portion 200a of the gate dielectric layer 200 is formed by the first dielectric layer 210, and the upper portion 200b of the gate dielectric layer is formed by stacking the second dielectric layer 220 on the basis of the first dielectric layer 210, thereby increasing the thickness of the upper portion 200b. It should be recognized that the thickness of the second dielectric layer 220 can be adjusted according to actual needs without affecting the thickness of the first dielectric layer 210. For example, the thickness dimension of the second dielectric layer 220 in the direction perpendicular to the trench sidewall can be greater than or equal to the thickness dimension of the first dielectric layer 210 in the direction perpendicular to the trench sidewall.

[0084] As described above, the materials of the first dielectric layer 210 and the second dielectric layer 220 can be the same or different. In this embodiment, the material of the first dielectric layer 210 for forming the upper and lower portions includes, for example, silicon oxide (SiO). And, the material of the second dielectric layer 220 for forming the upper portion can be adjusted according to actual needs. Specifically, the second dielectric layer 220 can be formed of the same material as the first dielectric layer 210. At this time, it is equivalent to increasing the thickness of the upper portion 200b; or, a material with better barrier performance can also be used to form the second dielectric layer 220 (for example, the material of the second dielectric layer 220 includes silicon nitride, etc.). In this way, on the basis of increasing the thickness of the upper portion 200b, the gate-induced drain leakage current (GIDL) can be further reduced.

[0085] Further, the sidewall of the gate trench 100a is a smooth sidewall, the first dielectric layer 210 conformally covers the inner wall of the gate trench 100a along the inner wall of the gate trench 100a, and the second dielectric layer 220 covers the outer sidewall of the first dielectric layer 210 to constitute the outer cover layer 220b of the upper portion 200b, so that the outer cover layer 220b protrudes away from the trench inner wall relative to the lower portion 200a.

[0086] It can be considered that the gate dielectric layer 200 covers the inner wall of the gate trench 100a and further defines a receiving space for accommodating the gate conductive layer in the gate trench 100a. Among them, in the gate dielectric layer 200, the upper portion 200b protrudes away from the trench inner wall relative to the lower portion 200a. Based on this, the opening size of the receiving space defined by the gate dielectric layer 200 at a position higher than the predetermined height is smaller than the opening size of the receiving space at a position lower than the predetermined height. In this way, the side wall of the gate conductive layer 100 at a position higher than the predetermined height in the receiving space is recessed relative to the side wall at a position lower than the predetermined height, and correspondingly, the width dimension of the gate conductive layer 100 at a position higher than the predetermined height is smaller than the width dimension of the gate conductive layer 100 at a position lower than the predetermined height.

[0087] Continue to refer to Figure 1a As shown, the top position of the gate conductive layer 100 is lower than the top position of the gate trench 100a, and an insulating dielectric layer 400 is further filled in the space of the gate trench 100a above the gate conductive layer 100 to cover the gate conductive layer 100.

[0088] It can be understood that in the transistor of this embodiment, the gate dielectric layer 200 includes a first dielectric layer 210 and a second dielectric layer 220. Among them, the first dielectric layer 210 covers the bottom wall and side wall of the gate trench 100a, and the second dielectric layer 220 covers the part of the first dielectric layer 210 at a position higher than the predetermined height (the first height position H1), so that the part of the gate dielectric layer 200 at a position higher than the predetermined height protrudes away from the trench side wall relative to the part of the gate dielectric layer 200 at a position lower than the predetermined height.

[0089] And, the gate conductive layer 100 in the transistor is filled in the gate trench 100a, and the side wall of the gate conductive layer 100 at a position lower than the predetermined height is in contact with the first dielectric layer 210, and the side wall of the gate conductive layer 100 at a position higher than the predetermined height is in contact with the second dielectric layer 220, so that the gate conductive layer 100 presents a convex structure.

[0090] Based on the transistor described above, the formation method of the transistor in this embodiment will be described in detail below. Figures 2a - 2f It is a schematic structural diagram in the preparation process of the formation method of the transistor in Embodiment 1 of the present invention.

[0091] First, refer to Figure 2a As shown, a substrate 10 is provided, and a gate trench 100a is formed in the substrate 10.

[0092] In this embodiment, after forming the gate trench 100a, a gate dielectric layer is further prepared in the gate trench 10a. The following will be described in conjunction with reference to Figures 2b - 2d to explain the formation method of the gate dielectric layer in this embodiment.

[0093] Specifically, referring to Figure 2b as shown, a first dielectric layer 210 is formed on the inner wall of the gate trench 100a. Among them, the material of the first dielectric layer 210 includes, for example, silicon oxide.

[0094] Furthermore, the first dielectric layer 210 can be formed, for example, by a thermal oxidation process. And in this embodiment, while forming the first dielectric layer 210 on the inner wall of the gate trench 100a, a dielectric layer is also further formed on the top surface of the substrate 10.

[0095] It should be noted that the part of the first dielectric layer 210 at a position lower than the predetermined height is used to form the gate dielectric layer between the gate conductive layer and the conductive channel of the formed transistor. Therefore, the thickness of the first dielectric layer 210 can be adjusted according to the specific formed transistor to meet the device performance of the formed transistor.

[0096] Next, referring to Figure 2b as shown, a sacrificial layer 500 is filled in the gate trench 100a. The sacrificial layer 500 is filled from the bottom of the gate trench 100a upward to a predetermined height position (the first height position H1). That is, the sacrificial layer 500 is used to cover the part of the first dielectric layer 210 at a position lower than the predetermined height and expose the outer sidewall of the first dielectric layer 210 higher than the sacrificial layer.

[0097] Among them, the material of the sacrificial layer 500 includes, for example, an organic material. And the specific formation method of the sacrificial layer 500 includes, for example: first, an organic material is filled into the gate trench 100a by a spin coating process; then, an etch-back process is performed to reduce the height of the organic material in the gate trench 100a to the predetermined height position to form the sacrificial layer 500.

[0098] Next, referring to Figure 2c as shown, a second dielectric layer 220 is formed on the exposed outer sidewall of the first dielectric layer 210, that is, the second dielectric layer 220 is correspondingly formed on the outer sidewall of the first dielectric layer 210 at a position higher than the predetermined height.

[0099] Wherein, the first dielectric layer 210 and the second dielectric layer 220 form a gate dielectric layer, and a portion of the first dielectric layer 210 at a position lower than a predetermined height constitutes the lower layer portion, a portion of the first dielectric layer 210 at a position higher than the predetermined height constitutes the liner layer, and the second dielectric layer 220 constitutes the outer cover layer.

[0100] Further, the material of the second dielectric layer 220 may be the same as that of the first dielectric layer 210. For example, both may include silicon oxide. Also, the second dielectric layer 220 may be formed by chemical vapor deposition process or atomic layer deposition process, or may also be formed by in-situ steam generation (ISSG) method to obtain a high-quality gate dielectric layer.

[0101] Specifically, the forming method of the second dielectric layer 220 includes: First, deposit a dielectric material layer on the substrate 10, and the dielectric material layer covers the exposed outer sidewall of the first dielectric layer 210, the top surface of the sacrificial layer 500, and the top surface of the substrate 10; Then, perform an etch-back process to remove the portion of the dielectric material layer covering the top surface of the substrate and the portion covering the top surface of the sacrificial layer, and retain the portion of the dielectric material layer covering the outer sidewall of the first dielectric layer to constitute the second dielectric layer 220.

[0102] Then refer to Figure 2d as shown, remove the sacrificial layer 500, so as to expose the portion of the first dielectric layer 210 at a position lower than the predetermined height.

[0103] That is, in the gate dielectric layer of this embodiment, its lower layer portion is constituted by the first dielectric layer 210, and its upper layer portion is constituted by the first dielectric layer 210 and the second dielectric layer 220, so that the upper layer portion protrudes away from the inner wall of the trench relative to the lower layer portion.

[0104] Then refer to Figure 2e as shown, after forming the gate dielectric layer, it further includes: forming a gate conductive layer 100 in the gate trench 100a. The material of the gate conductive layer 100 includes, for example, polysilicon or tungsten, etc.

[0105] Specifically, the top position (the third height position H3) of the gate conductive layer 100 is higher than the predetermined height position (the first height position H1), so that the gate conductive layer 100 extends from the lower layer portion of the gate dielectric layer 200 to the upper layer portion.

[0106] In this embodiment, the top position of the gate conductive layer 100 is also lower than the top surface of the substrate 10, that is, the gate conductive layer 100 does not fill the gate trench 100a. Specifically, for example, the height of the gate conductive layer 100 in the gate trench 100a can be reduced by an etch-back process so that the top surface of the gate conductive layer 100 is lower than the top surface of the substrate 10.

[0107] In a further aspect, specifically referring to Figure 2f as shown, the method for forming the transistor further includes: filling an insulating dielectric layer 400 in the space of the gate trench 100a above the gate conductive layer 100 to cover the gate conductive layer 100. Among them, the material of the insulating dielectric layer 500 includes, for example, silicon nitride.

[0108] Continuing to refer to Figure 2f as shown, the method for forming the transistor further includes: forming source / drain regions in the substrate 100, the side edge boundaries of the source / drain regions extending to the side walls of the gate trench 100a near the top opening, and the bottom boundary of the source / drain regions (corresponding to the second height position H2) being lower than the top position of the gate conductive layer (the third height position H3) and higher than the predetermined height position (the first height position H1).

[0109] Therefore, an overlapping region exists between the gate conductive layer 100 and the source / drain regions between the second height position and the third height position, and the gate conductive layer 100 and the source / drain regions are spaced apart from each other by the upper part of the gate dielectric layer 200 within the overlapping region.

[0110] Specifically, the source / drain regions include a first source / drain region 310 and a second source / drain region 320, and the first source / drain region 310 and the second source / drain region 320 are respectively located on both sides of the gate trench 100a.

[0111] It should be noted that in this embodiment, the source / drain regions are fabricated after forming the gate trench and the gate conductive layer. However, in other embodiments, the source / drain regions can also be formed first, and then the gate trench and the gate conductive layer are fabricated in sequence, which is not limited here.

[0112] Embodiment 2

[0113] The difference from Embodiment 1 is that in the gate dielectric layer of this embodiment, the upper part protrudes towards the inner wall of the trench relative to the lower part. The following combines Figure 3a and Figure 3b to describe the transistor in this embodiment in detail.

[0114] Figure 3a is a schematic structural diagram of the transistor in Embodiment 2 of the present invention, Figure 3bThis is a schematic diagram of the gate dielectric layer of the transistor in the second embodiment of the present invention. As Figure 3a and Figure 3b shown, in this embodiment, the gate dielectric layer 200' includes a first dielectric layer 210' and a second dielectric layer 220'.

[0115] Among them, the first dielectric layer 210' covers the inner wall of the gate trench 100a' at a position higher than a predetermined height (the first height position H1), and is used to form the liner layer 210b' of the upper part 200b'. The second dielectric layer 220' covers the first dielectric layer 210' and the inner wall of the gate trench 100a' at a position lower than the predetermined height, and the part of the second dielectric layer 220' higher than the predetermined height forms the outer cover layer 220b', and the part of the second dielectric layer 220' lower than the predetermined height forms the lower part 200a'.

[0116] It can be understood that in this embodiment, the lower part 200a' of the gate dielectric layer 200' is formed by the second dielectric layer 220', and the upper part 200b' of the gate dielectric layer is formed by superimposing the first dielectric layer 210' on the basis of the second dielectric layer 220', thereby increasing the thickness of the upper part 200b'. It should be recognized that the thickness of the first dielectric layer 210' can be adjusted according to actual needs without affecting the thickness of the second dielectric layer 220'. For example, the thickness dimension of the first dielectric layer 210' in the direction perpendicular to the trench sidewall can be greater than or equal to the thickness dimension of the second dielectric layer 220' in the direction perpendicular to the trench sidewall.

[0117] Similar to Embodiment 1, the first dielectric layer 220' and the second dielectric layer 220' in this embodiment can be made of the same material or different materials. Specifically, the material of the second dielectric layer 220' for forming the upper part and the lower part can include silicon oxide. And, the material of the first dielectric layer 210' for forming the upper part can also include silicon oxide. Or, the first dielectric layer 210' can also be formed of a material with better barrier performance (for example, the material of the first dielectric layer 210' includes silicon nitride, etc.). In this way, on the basis of increasing the thickness of the upper part 200b, the gate-induced drain leakage current (GIDL) can be further reduced.

[0118] Combining Embodiment 1 and Embodiment 2, it can be seen that when selecting the materials of the first dielectric layer and the second dielectric layer, for the dielectric layer that is simultaneously used to form the upper part and the lower part, it can be formed of, for example, silicon oxide, and for the dielectric layer that is only used to form the upper part, it can be adjusted according to actual needs (for example, including silicon nitride and / or silicon oxide).

[0119] Continue to refer toFigure 3a As shown, in this embodiment, the sidewall of the gate trench 100a' at a position higher than the predetermined height (the first height position H1) is recessed with respect to the sidewall of the gate trench 100a' at a position lower than the predetermined height (the first height position H1). It can be understood that, with respect to the sidewall of the gate trench 100a' at a position lower than the predetermined height (the first height position H1), there is a recessed area in the sidewall of the gate trench 100a' at a position higher than the predetermined height (the first height position H1).

[0120] In this embodiment, the first dielectric layer 210' is formed in the recessed area to cover the sidewall of the gate trench 100a' at a position higher than the predetermined height. And, the second dielectric layer 220' conforms to the outer sidewall of the first dielectric layer 210' and the inner wall of the gate trench 100a' at a position lower than the predetermined height, and conformally covers the first dielectric layer 210' and the inner wall of the gate trench. In this way, the liner layer 210b' can protrude towards the inner wall of the trench with respect to the lower part 200a'.

[0121] It can be considered that, in this embodiment, when the accommodation space is defined by the gate dielectric layer 200' in the gate trench 100a', the sidewall of the accommodation space corresponds to the outer sidewall of the second dielectric layer 220', and thus can be presented as a smooth sidewall. In this way, the sidewall boundary of the gate conductive layer 100' filled in the accommodation space can conform to the outer sidewall of the second dielectric layer 220'.

[0122] The formation method of the transistor in this embodiment will be described in detail below. Specifically, in the formation method of the transistor in this embodiment, a gate trench is formed during the preparation of the gate dielectric layer. The following will be combined with Figures 4a - 4e for a detailed description, where Figures 4a - 4e is a schematic structural diagram during the preparation process of the formation method of the transistor in the second embodiment of the present invention.

[0123] First, referring to Figure 4a as shown, a substrate 10 is provided, and a first trench 110a is formed in the substrate 10, and the bottom position of the first trench 110a is at the predetermined height (the first height position H1).

[0124] Then, referring to Figure 4b as shown, a first dielectric layer 210' is formed on the sidewall of the first trench 110a. At this time, the first dielectric layer 210' is correspondingly higher than the predetermined height.

[0125] Then, referring to Figure 4cAs shown, using the first dielectric layer 210' as a mask, etch the bottom of the first trench 110a to form a second trench, which is vertically connected to the first trench 110a. That is, the second trench extends further downward from a predetermined height position, and the gate trench 100a' is formed by the second trench and the first trench 110a.

[0126] It should be noted that although the mask layer on the top surface of the substrate is not shown in the drawings of this embodiment, it should be recognized that during the process of etching the substrate 10 to form the first trench and the second trench, a mask layer is usually formed on the top surface of the substrate 10 to prevent the areas of the substrate other than the corresponding trenches from being etched.

[0127] As Figure 4c shown, in the gate trench 100a' in this embodiment, the side wall of the second trench is smoothly connected to the outer side wall of the first dielectric layer 210', and there is a step between the side walls of the second trench and the first trench 110a, and the opening size of the second trench is smaller than that of the first trench 110a.

[0128] Next, referring to Figure 4d shown, form a second dielectric layer 220' in the gate trench 100a', and the second dielectric layer 220' covers the inner wall of the second trench and the outer side wall of the first dielectric layer 210'.

[0129] Moreover, the gate dielectric layer 200' is formed by the second dielectric layer 220' and the first dielectric layer 210'. Among them, the first dielectric layer 210' forms the inner lining layer, the part of the second dielectric layer 220' covering the first dielectric layer 210' forms the outer cover layer, and the part of the second dielectric layer 220' covering the inner wall of the second trench forms the lower layer part.

[0130] Next, referring to Figure 4e shown, after forming the gate dielectric layer 200', the gate conductive layer 100' can be further filled into the gate trench 100a'. In this embodiment, the side wall boundary of the gate conductive layer 100' extends from the lower layer part to the upper layer part along the side wall of the second dielectric layer 220'.

[0131] Similar to Embodiment 1, the top position of the gate conductive layer 100' is lower than the top position of the gate trench 100a'. Based on this, after forming the gate conductive layer 100', an insulating dielectric layer 400 is further filled in the space above the gate conductive layer in the gate trench.

[0132] For the transistor as described above, its gate dielectric layer has a thicker upper portion and a thinner lower portion, such that the gate conductive layer and the source / drain regions are spaced apart from each other through the thicker upper portion in the overlapping region where they overlap, and a thinner lower portion is provided between the gate conductive layer and the substrate for forming the conductive channel. In this way, on the one hand, since a gate dielectric layer with a relatively thin thickness is still used between the gate conductive layer and the substrate for forming the conductive channel, the performance of the transistor is ensured; on the other hand, a thicker gate dielectric layer is used to space apart the gate conductive layer and the source / drain regions, thereby effectively improving the gate-induced drain leakage (GIDL) phenomenon.

[0133] In addition, in the transistor as described above, the upper portion of its gate dielectric layer is provided in a stacked manner, so that the thickness of the upper portion can be increased without changing the thickness of the lower portion. This can not only improve the gate-induced drain leakage (GIDL) phenomenon while maintaining the performance of the transistor, but also facilitate flexible adjustment of the parameters of the upper portion. For example, the thickness and material of the upper portion can be flexibly adjusted.

[0134] It should be recognized that when the transistor as described above is applied to a semiconductor device, the performance of the semiconductor device can be correspondingly improved. Hereinafter, the semiconductor device is taken as an example of a memory for explanation.

[0135] In the storage region of a memory, there are usually multiple active regions, and transistors can be formed in the active regions to form storage cells. Therefore, when the transistors in the active regions have good performance, the performance of the memory can be correspondingly improved. Specifically, the memory further includes multiple word lines, the word lines can intersect with the corresponding active regions, and the portion of the word line that intersects with the active region can form the gate conductive layer of the transistor.

[0136] It should be noted that the embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. The same or similar parts among the embodiments can be referred to each other. For the system disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the description of the method part.

[0137] It should also be noted that although the present invention has been disclosed above in preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible changes and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or it can be modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present invention without departing from the content of the technical solution of the present invention still belong to the scope protected by the technical solution of the present invention.

[0138] It should also be understood that unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, rather than to represent the logical relationship or sequential relationship, etc. between the various components, elements, steps.

[0139] In addition, it should also be recognized that the terms described herein are only used to describe specific embodiments and are not used to limit the scope of the present invention. It must be noted that the singular forms "a" and "an" used herein and in the appended claims include plural referents unless the context clearly dictates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices and may include sub-steps and sub-devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or", rather than the definition of a logical "exclusive or", unless the context clearly dictates otherwise. In addition, the implementation of the methods and / or devices in the embodiments of the present invention may include performing the selected tasks manually, automatically, or in combination.

Claims

1. A method for forming a transistor, characterized in that, Including: Providing a substrate in which a gate trench is formed; And, Forming a gate dielectric layer on the inner wall of the gate trench, the gate dielectric layer including an upper portion and a lower portion, the upper portion covering the inner wall of the gate trench at a position higher than a predetermined height, and the lower portion covering the inner wall of the gate trench at a position lower than the predetermined height; Forming a gate conductive layer, the gate conductive layer being formed on the gate dielectric layer and located in the gate trench; Forming an insulating dielectric layer on the gate conductive layer; Wherein, the upper portion includes a lining layer and a capping layer, the lining layer covering the inner wall of the gate trench, the capping layer covering the outer sidewall of the lining layer, and the sum of the thicknesses of the lining layer and the capping layer being greater than the thickness value of the lower portion; Wherein, after forming the gate trench, forming the gate dielectric layer, and the forming method of the gate dielectric layer includes: Forming a first dielectric layer on the inner wall of the gate trench; Filling a sacrificial layer in the gate trench, the sacrificial layer being filled upward from the bottom of the gate trench to a predetermined height position and exposing the outer sidewall of the first dielectric layer that is higher than the sacrificial layer; Forming a second dielectric layer on the exposed outer sidewall of the first dielectric layer, and the gate dielectric layer being composed of the first dielectric layer and the second dielectric layer, wherein the portion of the first dielectric layer at a position lower than the predetermined height constitutes the lower portion, the portion of the first dielectric layer at a position higher than the predetermined height constitutes the lining layer, and the second dielectric layer constitutes the capping layer; and, Removing the sacrificial layer; Wherein, the materials of the first dielectric layer and the second dielectric layer are the same or different.

2. The method for forming a transistor according to claim 1, wherein, The top position of the gate conductive layer is higher than the predetermined height position, so that the gate conductive layer extends from the lower portion of the gate dielectric layer to the upper portion.

3. The method for forming a transistor as claimed in claim 1, wherein, After forming the gate dielectric layer, further including: Forming source / drain regions in the substrate, the bottom boundary of the source / drain regions being lower than the top position of the gate conductive layer and higher than the predetermined height position, so that there is an upper portion of the gate dielectric layer between the source / drain regions and the gate conductive layer.

4. A method for forming a transistor, characterized in that, Including: Providing a substrate in which a gate trench is formed; And, Forming a gate dielectric layer on the inner wall of the gate trench, the gate dielectric layer including an upper portion and a lower portion, the upper portion covering the inner wall of the gate trench at a position higher than a predetermined height, and the lower portion covering the inner wall of the gate trench at a position lower than the predetermined height; Forming a gate conductive layer, the gate conductive layer being formed on the gate dielectric layer and located in the gate trench; Forming an insulating dielectric layer on the gate conductive layer; Wherein, the upper portion includes a lining layer and a capping layer, the lining layer covering the inner wall of the gate trench, the capping layer covering the outer sidewall of the lining layer, and the sum of the thicknesses of the lining layer and the capping layer being greater than the thickness value of the lower portion; Wherein, the gate trench is formed when preparing the gate dielectric layer, and the forming methods of the gate trench and the gate dielectric layer include: Form a first trench in the substrate, where the bottom position of the first trench is located at a predetermined height position; Form a first dielectric layer on the sidewalls of the first trench; Etch the bottom of the first trench using the first dielectric layer as a mask to form a second trench, where the second trench communicates with the first trench vertically to form the gate trench; Form a second dielectric layer in the gate trench, where the second dielectric layer covers the inner wall of the second trench and the outer sidewall of the first dielectric layer, and the gate dielectric layer is composed of the second dielectric layer and the first dielectric layer, where the first dielectric layer forms the inner lining layer, the part of the second dielectric layer covering the first dielectric layer forms the outer cover layer, and the part of the second dielectric layer covering the inner wall of the second trench forms the lower layer part; Wherein, the materials of the first dielectric layer and the second dielectric layer are the same or different.

5. The method for forming a transistor according to claim 4, wherein The top position of the gate conductive layer is higher than the predetermined height position, so that the gate conductive layer extends from the lower layer part of the gate dielectric layer to the upper layer part.

6. The method for forming a transistor according to claim 4, wherein After forming the gate dielectric layer, it further includes: Form source and drain regions in the substrate, where the bottom boundary of the source and drain regions is lower than the top position of the gate conductive layer and higher than the predetermined height position, so that there is an upper layer part of the gate dielectric layer between the source and drain regions and the gate conductive layer.

7. A transistor, characterized in that, Prepared by using the method for forming a transistor according to any one of claims 1 to 3, or prepared by using the method for forming a transistor according to any one of claims 4 to 6, and the transistor includes: A substrate, in which a gate trench is formed; and, A gate dielectric layer, covering the inner wall of the gate trench, where the gate dielectric layer has an upper layer part and a lower layer part, the upper layer part covers the inner wall of the gate trench higher than the predetermined height position, and the lower layer part covers the inner wall of the gate trench lower than the predetermined height position; A gate conductive layer, formed on the gate dielectric layer and located in the gate trench; An insulating dielectric layer, located on the gate conductive layer; Wherein, the upper layer part includes an inner lining layer and an outer cover layer, the inner lining layer covers the inner wall of the gate trench, the outer cover layer covers the outer sidewall of the inner lining layer, and the sum of the thicknesses of the inner lining layer and the outer cover layer is greater than the thickness value of the lower layer part.

8. The transistor according to claim 7, wherein In the gate dielectric layer, the thickness difference of the lower layer part relative to the inner lining layer is less than the thickness value of the outer cover layer; or the thickness difference of the lower layer part relative to the outer cover layer is less than the thickness value of the inner lining layer.

9. The transistor according to claim 7, wherein, The gate dielectric layer includes a first dielectric layer and a second dielectric layer; Wherein, the first dielectric layer covers the inner wall of the gate trench, and the part of the first dielectric layer lower than the predetermined height position forms the lower layer part, and the part of the first dielectric layer higher than the predetermined height position forms the inner lining layer; and, the second dielectric layer covers the part of the first dielectric layer higher than the predetermined height position to form the outer cover layer of the upper layer part.

10. The transistor according to claim 7, characterized in that, The thickness dimension of the second dielectric layer in the direction perpendicular to the sidewall of the trench is greater than the thickness dimension of the first dielectric layer in the direction perpendicular to the sidewall of the trench.

11. The transistor according to claim 7, characterized in that, The outer cover layer of the upper part protrudes away from the inner wall of the trench relative to the lower part.

12. The transistor according to claim 11, characterized in that, The gate conductive layer extends from the lower part to the upper part, and the width dimension of the gate conductive layer at a position higher than a predetermined height is smaller than the width dimension of the gate conductive layer at a position lower than the predetermined height.

13. The transistor according to claim 7, characterized in that, The gate dielectric layer includes a first dielectric layer and a second dielectric layer; Wherein, the first dielectric layer covers the inner wall of the gate trench at a position higher than a predetermined height to form the inner liner layer; and, the second dielectric layer covers the first dielectric layer and the inner wall of the gate trench at a position lower than the predetermined height, and the part of the second dielectric layer at a position higher than the predetermined height forms the outer cover layer, and the part of the second dielectric layer at a position lower than the predetermined height forms the lower part.

14. The transistor according to claim 13, wherein The thickness dimension of the first dielectric layer in the direction perpendicular to the sidewall of the trench is greater than the thickness dimension of the second dielectric layer in the direction perpendicular to the sidewall of the trench.

15. The transistor according to claim 13, characterized in that, The inner liner layer of the upper part protrudes towards the inner wall of the trench relative to the lower part.

16. The transistor according to claim 15, characterized in that, The sidewall boundary of the gate conductive layer conforms to the sidewall of the second dielectric layer and extends from the lower part to the upper part.

17. The transistor according to claim 7, characterized in that, The top position of the gate conductive layer is higher than the predetermined height position, so that the gate conductive layer extends from the lower part of the gate dielectric layer to the upper part.

18. The transistor according to claim 17, characterized in that, The transistor further includes: Source-drain regions, the bottom boundary of the source-drain regions is lower than the top position of the gate conductive layer and higher than the predetermined height position, so that there is an upper part of the gate dielectric layer between the source-drain regions and the gate conductive layer.

19. A transistor, characterized in that, Prepared by using the method for forming a transistor according to any one of claims 1 to 3, and the transistor includes: A substrate, in which a gate trench is formed; A first dielectric layer and a second dielectric layer, the first dielectric layer covers the bottom wall and the sidewall of the gate trench, and the second dielectric layer covers the part of the first dielectric layer at a position higher than a predetermined height; and, A gate conductive layer, filled in the gate trench, and the sidewall of the gate conductive layer at a position lower than the predetermined height is in contact with the first dielectric layer, and the sidewall of the gate conductive layer at a position higher than the predetermined height is in contact with the second dielectric layer, so that the gate conductive layer presents a convex structure; An insulating dielectric layer, located on the gate conductive layer.

20. The transistor according to claim 19, wherein, The thickness dimension of the second dielectric layer in the direction perpendicular to the sidewall of the trench is greater than the thickness dimension of the first dielectric layer in the direction perpendicular to the sidewall of the trench.

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