Alignment mark and semiconductor structure

Abstract

The present application relates to the field of semiconductor technology, and more specifically, to an alignment mark and a semiconductor structure. The alignment mark can be set on a semiconductor substrate, and the alignment mark includes a first area and a second area, the first area is provided with an alignment pattern, and the second area is provided with an identification pattern, and the identification pattern is used to indicate the process step corresponding to the alignment mark. In this solution, it is easy to identify which process step this alignment mark corresponds to, thereby improving the alignment efficiency, which is conducive to improving the yield of the product. In addition, it is also convenient to quickly verify whether the process step corresponding to this alignment mark is wrong in the subsequent process step, so as to improve the verification efficiency.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to an alignment mark and a semiconductor structure. Background Art

[0002] In the manufacture of semiconductor chips, it is necessary to perform multiple photolithography processes through photolithography equipment to transfer the patterns on different mask plates to the semiconductor substrate and the film layers of the semiconductor substrate in sequence. Since alignment marks are required for alignment before each photolithography process, and the alignment marks used in each photolithography process may be the same, in order to facilitate the determination of which process an alignment mark belongs to, currently, the coordinates of the alignment marks are usually detected to determine, which is time-consuming, resulting in low alignment efficiency and is not conducive to improving product yield. In addition, when verifying which process is wrong in the subsequent process, the verification efficiency is greatly reduced.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0004] The purpose of the present application is to provide an alignment mark and a semiconductor structure, which can easily identify which process step the alignment mark corresponds to, thereby improving the alignment efficiency and facilitating the subsequent rapid verification of whether the process step corresponding to the alignment mark is wrong, thereby improving the verification efficiency.

[0005] In a first aspect, the present application provides an alignment mark, which can be set on a semiconductor substrate, and the alignment mark includes a first area and a second area, the first area is provided with an alignment pattern, and the second area is provided with an identification pattern, and the identification pattern is used to indicate the process step corresponding to the alignment mark.

[0006] In an exemplary embodiment of the present application, the second area is arranged around the first area.

[0007] In an exemplary embodiment of the present application, the identification pattern includes at least one identification portion, and the orthographic projection of the identification portion on the second area is in a grid shape.

[0008] In an exemplary embodiment of the present application, the identification portion includes a first portion in a concave shape and a second portion in a convex shape, and an orthographic projection of the first portion on the second area and an orthographic projection of the second portion on the second area form the grid shape.

[0009] In an exemplary embodiment of the present application, the orthographic projection of the first portion on the second area and the orthographic projection of the second portion on the second area are both rectangular grids and have the same size.

[0010] In an exemplary embodiment of the present application, the identification pattern includes a plurality of identification portions, and at least two of the plurality of identification portions have different shapes.

[0011] In an exemplary embodiment of the present application, the identification portions are arranged adjacent to each other and at intervals.

[0012] In an exemplary embodiment of the present application, the grid shape is a nine-square grid.

[0013] A second aspect of the present application provides a semiconductor structure, which includes:

[0014] Semiconductor substrate;

[0015] A plurality of alignment marks as described in any one of the above items, wherein the alignment marks are respectively arranged on the semiconductor substrate, wherein identification patterns of at least two of the plurality of alignment marks are different.

[0016] In an exemplary embodiment of the present application, the semiconductor substrate includes a plurality of to-be-processed regions and scribe lines between adjacent to-be-processed regions, and the alignment mark is disposed within the scribe lines.

[0017] In an exemplary embodiment of the present application, alignment patterns of at least two of the plurality of alignment marks are different.

[0018] The technical solution provided by this application can achieve the following beneficial effects:

[0019] The alignment mark and semiconductor structure provided in the present application are provided with an identification pattern on the alignment mark, and the process step corresponding to the alignment mark can be determined by the identification pattern. Compared with the solution of determining which process the alignment mark belongs to by detecting the coordinates of the alignment mark, this reduces the difficulty of identifying the alignment mark, thereby improving the alignment efficiency, which is beneficial to improving the yield of the product. In addition, it is also convenient for subsequent rapid verification whether the process step corresponding to the alignment mark is wrong, so as to improve the verification efficiency.

[0020] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 A schematic diagram of the structure of an alignment mark according to an embodiment of the present application;

[0023] Figure 2 for Figure 1 An enlarged structural diagram of the A portion shown in FIG.

[0024] Figure 3 A schematic diagram of the structure of an alignment mark according to another embodiment of the present application;

[0025] Figure 4 A schematic structural diagram of a semiconductor structure according to an embodiment of the present application;

[0026] Figure 5 This is a diagram showing the correspondence between identification parts of different shapes and different numbers and letters in the embodiments of the present application.

[0027] Description of reference numerals:

[0028] Figure 3 to Figure 4 middle:

[0029] 1. Alignment mark; 10. First area; 101. Alignment pattern; 11. Second area; 111. Identification part; 111a. First part; 111b. Second part; 2. Area to be processed; 3. Cutting path. DETAILED DESCRIPTION

[0030] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted.

[0031] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.

[0032] The terms "a", "an", "the", and "said" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusion and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first" and "second", etc. are used merely as labels and are not intended to limit the quantity of their objects.

[0033] In semiconductor chip manufacturing, multiple photolithography processes are required to be performed using photolithography equipment to sequentially transfer patterns on different mask plates to a semiconductor substrate and various film layers of the semiconductor substrate.

[0034] At present, in order to ensure the performance of the product, the semiconductor substrate needs to be aligned with the alignment mark before each photolithography process. As a result, a large number of alignment marks need to be used in the semiconductor chip manufacturing process to achieve alignment in different photolithography processes. However, since the alignment marks used in different photolithography processes may be the same, when determining which process an alignment mark belongs to, it is necessary to determine by detecting the coordinates of the alignment mark, which is time-consuming and leads to low alignment efficiency, which is not conducive to improving the yield of the product. In addition, when verifying which process has an error in the subsequent verification, the verification efficiency is greatly reduced.

[0035] In order to solve the above technical problems, the embodiment of the present application provides an alignment mark 1, which can be set on a semiconductor substrate. For example, the semiconductor substrate can be a wafer. Figure 1 and Figure 3 As shown, the alignment mark 1 may include a first region 10 and a second region 11. The first region 10 is provided with an alignment pattern 101, and the alignment pattern 101 may be aligned with an alignment system to facilitate alignment of a semiconductor substrate, thereby facilitating the improvement of the accuracy of subsequent process steps (e.g., photolithography process). The second region 11 is provided with an identification pattern, and the identification pattern may be used to indicate the process step corresponding to the alignment mark 1.

[0036] In this embodiment, an identification pattern is provided on the alignment mark 1 so as to facilitate rapid determination of the process step corresponding to the alignment mark 1. This reduces the difficulty of identifying the alignment mark 1, compared with a solution of determining which process the alignment mark 1 belongs to by detecting the coordinates of the alignment mark 1. This can improve the alignment efficiency, which is beneficial to improving the yield of the product. In addition, it is also convenient for subsequent rapid verification of whether there is an error in the process step corresponding to the alignment mark 1, thereby improving the verification efficiency.

[0037] Among them, Figure 1 and Figure 3 As shown, the second area 11 in the alignment mark 1 can be arranged around the first area 10, so as to avoid the alignment pattern 101 on the first area 10 being located at the edge of the entire alignment mark 1, thereby alleviating the wear or etching of the alignment pattern 101, and then alleviating the poor alignment accuracy in the subsequent alignment process.

[0038] It should be noted that the alignment pattern 101 on the first area 10 and the identification pattern on the second area 11 in this alignment mark 1 can be three-dimensional patterns. Compared with flat patterns, this can prevent the identification pattern from being affected by subsequent etching, polishing and other process steps, thereby improving the service life of the identification pattern.

[0039] As mentioned above, multiple photolithography processes are required in the manufacturing process of semiconductor chips. In order to facilitate identification of which photolithography process the alignment mark 1 corresponds to, the identification patterns in the alignment mark 1 corresponding to different photolithography processes need to be designed differently. Figure 2 As shown, the identification pattern in this embodiment may include at least one identification portion 111 , and the identification pattern can be changed by changing the pattern of the identification portion 111 .

[0040] Optionally, the orthographic projection of the identification portion 111 mentioned in this embodiment on the second area 11 is in a grid shape. In other words, the identification portion 111 can be divided into multiple blocks, wherein the orthographic projection of each block on the second area 11 can be a grid in the grid, but the structures of each block are not the same.

[0041] For example, when designing the structural pattern of the logo portion 111, one side of the portion to be processed may be designed as a grid surface first, and then the structure corresponding to some grids in the grid surface may be modified. For example, the structure corresponding to some grids may be etched to form a recessed portion on the cube, thereby processing the logo portion 111. It should be noted that if a logo portion 111 with a different pattern is to be processed, the structure corresponding to different grids in the grid surface may be modified.

[0042] In this embodiment, since different grid combinations can form a variety of patterns, the aforementioned processing method can not only obtain a variety of logo parts 111 with different patterns, but also reduce the design difficulty of the logo part 111, thereby facilitating processing and forming.

[0043] Optionally, the aforementioned grid shape is a nine-square grid, so that while being able to change into a variety of patterns, it can also ensure that the part corresponding to each grid is large enough, so as to facilitate clear distinction of the identification parts 111 with different patterns, and then quickly identify the process step corresponding to this alignment mark 1.

[0044] Based on the above, it can be known that the identification portion 111 may include a first portion 111a in a concave shape and a second portion 111b in a convex shape, and the orthographic projection of the first portion 111a on the second area 11 and the orthographic projection of the second portion 111b on the second area 11 form a grid. For example, the first portion 111a and the second portion 111b may be provided in multiples, but not limited to this, the first portion 111a or the second portion 111b may also be provided with only one. Among them, the multiple first portions 111a in the identification portion 111 may be directly connected into one piece and / or the multiple first portions 111a may also be arranged at intervals through the second portion 111b; similarly, the multiple second portions 111b in the identification portion 111 may be directly connected into one piece and / or the multiple second portions 111b may also be arranged at intervals through the first portion 111a.

[0045] Optionally, the orthographic projection of the first portion 111 a on the second area 11 and the orthographic projection of the second portion 111 b on the second area 11 are both rectangular grids and have the same size, which can reduce the difficulty of processing the identification portion 111 .

[0046] In one embodiment, the aforementioned identification part 111 may be provided in plurality, that is, the identification pattern may include a plurality of identification parts 111, and at least two of the plurality of identification parts 111 have different shapes. This design can generate more different identification patterns, so that the identification patterns in the alignment mark 1 in different process steps are different, so that the process step to which the alignment mark 1 belongs can be determined only by identifying the identification pattern, which greatly reduces the difficulty of identifying the alignment mark 1, thereby improving the alignment efficiency, which is conducive to improving the yield of the product, and also facilitates the subsequent rapid verification of whether the process step corresponding to the alignment mark 1 is wrong, so as to improve the verification efficiency.

[0047] For example, in the manufacturing process of semiconductor chips, each process step is usually named using numbers, letters, or a combination of numbers and letters. In other words, the name of each process step may be composed of at least one of numbers and letters. It should be noted that the number of numbers or letters in the name of each process step may be one or more, and the name of each process step may include the same numbers and letters, or may be composed of different numbers or letters.

[0048] In this embodiment, the identification pattern on the second area 11 can be used to indicate the name of the process step, so as to intuitively and quickly identify the process step corresponding to the alignment mark. Different numbers or letters in the name of each process step can be represented by identification parts 111 of different shapes. Figure 5 As shown, the positive projection of the logo portion 111 on the second area 11 is a nine-square grid, and the gray grids can represent the concave parts of the logo portion 111, and the white grids can represent the convex parts of the logo portion 111, but it is not limited to this. The gray grids can also represent the convex parts of the logo portion 111, and the white grids can represent the concave parts of the logo portion 111.

[0049] In the following, the gray grid represents the concave part of the logo part 111, and the white grid represents the convex part of the logo part 111 as an example. Figure 5 The shape of the identification portion 11 corresponding to the individual numbers or letters is described in detail:

[0050] The part corresponding to the first grid in the first row of the nine-square grid is recessed relative to the parts corresponding to the other eight grids, and the marking portion 111 of this shape can correspond to the number 1; the part corresponding to the second grid in the second row of the nine-square grid is recessed relative to the parts corresponding to the other eight grids, and the marking portion 111 of this shape can correspond to the number 2; the part corresponding to the second grid in the second row of the nine-square grid and the part corresponding to the third grid are both recessed relative to the parts corresponding to the other 7 grids, and the marking portion 111 of this shape can correspond to the letter A.

[0051] It should be noted that Figure 5 The shapes of the identification parts corresponding to other numbers or letters are not described in detail here, and reference may be made to the description of the aforementioned number 1, number 2 and letter A.

[0052] In addition, the arrangement order of the identification parts 111 in the identification pattern must also be based on the arrangement order of the numbers or letters in the name of each process step. Figure 1 , Figure 2 and Figure 5 Take the content shown as an example, Figure 1 The name of the process step corresponding to the alignment mark in may be ABC.

[0053] It should be noted that the corresponding relationship between different numbers or letters and the shape of the identification portion 111 is not limited to Figure 5 As shown in , other corresponding relationships are also possible.

[0054] For example, Figure 2 As shown, each identification portion 111 can be arranged adjacent to each other and at intervals. In this embodiment, by arranging each identification portion 111 at intervals, it is possible to avoid the situation where adjacent identification portions 111 are mixed together and it is difficult to distinguish the meaning represented by each identification portion 111. In addition, by arranging each identification portion 111 adjacent to each other, it is convenient to view the identification pattern as a whole, so that it is possible to quickly determine to which process step the alignment mark 1 having the identification pattern belongs, thereby greatly reducing the difficulty of identifying the alignment mark 1.

[0055] It should be noted that the orthographic projection of each identification portion 111 on the second area 11 may be a rectangle, and the length and width of the rectangle may be 0.9 um, but it is not limited thereto and may be modified according to the size of the second area 11 .

[0056] Furthermore, if Figure 4 As shown, this embodiment further provides a semiconductor structure, which may include a semiconductor substrate and a plurality of alignment marks 1 described in any of the above embodiments. The alignment marks 1 are arranged on the semiconductor substrate, wherein at least two of the plurality of alignment marks 1 have different identification patterns, and different identification patterns indicate that the alignment marks 1 having the identification patterns correspond to different process steps.

[0057] It should be noted that, in one photolithography process, a plurality of alignment marks 1 are usually required, and the alignment patterns 101 of at least two of the plurality of alignment marks 1 are different to improve the alignment accuracy; the alignment pattern 101 may be as follows: Figure 1 and Figure 2 As shown, but not limited thereto, it may also be in the form of. Wherein, the alignment pattern 101 of the alignment mark 1 in different photolithography processes may be the same.

[0058] For example, the semiconductor substrate may be a wafer, wherein the semiconductor substrate may include a plurality of to-be-processed regions 2 and a scribe line 3 between adjacent to-be-processed regions 2, and the alignment mark 1 is disposed in the scribe line 3. It should be noted that the alignment mark 1 may be in the shape of a long strip, but is not limited thereto.

[0059] Those skilled in the art will readily appreciate other embodiments of the present application after considering the specification and practicing the invention disclosed herein. The present application is intended to cover any modification, use or adaptation of the present application, which follows the general principles of the present application and includes common knowledge or customary techniques in the art that are not disclosed in the present application. The specification and examples are intended to be exemplary only, and the true scope and spirit of the present application are indicated by the appended claims.

Claims

1. An alignment mark, characterized in that: The alignment mark can be set on a semiconductor substrate, and the alignment mark includes a first area and a second area, the first area is provided with an alignment pattern, and the second area is provided with an identification pattern, and the identification pattern is used to indicate the process step corresponding to the alignment mark; the identification pattern includes at least one identification part, and the positive projection of the identification part on the second area is a grid shape.

2. The alignment mark according to claim 1, characterized in that The second area is arranged around the first area.

3. The alignment mark according to claim 1, characterized in that The identification portion includes a first portion in a concave shape and a second portion in a convex shape, and an orthographic projection of the first portion on the second area and an orthographic projection of the second portion on the second area form the grid shape.

4. The alignment mark according to claim 3, characterized in that The orthographic projection of the first part on the second area and the orthographic projection of the second part on the second area are both rectangular grids and have the same size.

5. The alignment mark according to claim 1, characterized in that: The identification pattern includes a plurality of identification parts, and at least two of the plurality of identification parts have different shapes.

6. The alignment mark according to claim 5, characterized in that The identification parts are arranged adjacent to each other and at intervals.

7. The alignment mark according to claim 1, characterized in that: The grid shape is a nine-square grid.

8. A semiconductor structure, characterized in that: include: Semiconductor substrate; A plurality of alignment marks according to any one of claims 1 to 7, wherein the alignment marks are respectively arranged on the semiconductor substrate, wherein identification patterns of at least two of the plurality of alignment marks are different.

9. The semiconductor structure according to claim 8, characterized in that: The semiconductor substrate comprises a plurality of to-be-processed regions and scribe lines between adjacent to-be-processed regions, and the alignment mark is arranged in the scribe lines.

10. The semiconductor structure according to claim 8, characterized in that At least two of the plurality of alignment marks have different alignment patterns.

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