Display panel and display device comprising the same

Abstract

The present disclosure relates to a display panel and a display device including the same, the display panel including a substrate including a display area and a sensor area, wherein the display area includes a main pixel and the sensor area includes an auxiliary pixel, wherein the main pixel is electrically connected to a main pixel circuit and the auxiliary pixel is electrically connected to an auxiliary pixel circuit, wherein the auxiliary pixel circuit includes a first auxiliary thin film transistor including a first semiconductor layer including an oxide semiconductor material and a first gate electrode overlapping the first semiconductor layer, and a second auxiliary thin film transistor including a second semiconductor layer including low temperature poly silicon (LTPS) and a second gate electrode overlapping the second semiconductor layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0025860 filed in the Korean Intellectual Property Office on March 6, 2019, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] One or more embodiments relate to a display panel and a display device including the same, and more particularly, to a display panel in which a display area is expanded to allow an image to be displayed in a sensor area, and a display device including the same. Background Art

[0004] Recently, display devices have been used for various purposes. In addition, due to the reduced thickness and light weight of the display devices, the display devices tend to be more widely used.

[0005] According to various uses and increased functionality of a display device, there are many methods of designing the form or appearance of the display device. Summary of the Invention

[0006] As a method of increasing the functionality of a display device, one or more embodiments include a display device including a sensor area in an interior of a display area in which a sensor or the like may be arranged.

[0007] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0008] According to one or more embodiments, a display panel includes: a substrate, the substrate including a display area and a sensor area, wherein the display area includes a main pixel, and the sensor area includes an auxiliary pixel, wherein the main pixel is electrically connected to a main pixel circuit, and the auxiliary pixel is electrically connected to an auxiliary pixel circuit, wherein the auxiliary pixel circuit includes a first auxiliary thin film transistor and a second auxiliary thin film transistor, the first auxiliary thin film transistor includes a first semiconductor layer and a first gate electrode overlapping with the first semiconductor layer, the first semiconductor layer includes an oxide semiconductor material, the second auxiliary thin film transistor includes a second semiconductor layer and a second gate electrode overlapping with the second semiconductor layer, and the second semiconductor layer includes low-temperature polycrystalline silicon (LTPS).

[0009] According to this embodiment, the first auxiliary thin film transistor drives the auxiliary pixel, and the second auxiliary thin film transistor includes a switching thin film transistor that transmits a data signal to the first auxiliary thin film transistor.

[0010] According to this embodiment, the auxiliary pixel circuit also includes a third auxiliary thin film transistor connected to the first auxiliary thin film transistor in the form of a diode, and the third auxiliary thin film transistor also includes a third semiconductor layer and a third gate electrode overlapping with the third semiconductor layer, and the third semiconductor layer includes an oxide semiconductor material.

[0011] According to this embodiment, the auxiliary pixel circuit also includes a fourth auxiliary thin film transistor that initializes the voltage of the first gate electrode of the first auxiliary thin film transistor, and the fourth auxiliary thin film transistor includes a fourth semiconductor layer and a fourth gate electrode overlapping with the fourth semiconductor layer, and the fourth semiconductor layer includes an oxide semiconductor material.

[0012] According to this embodiment, the first semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are integrally formed on the same layer.

[0013] According to this embodiment, the main pixel circuit includes a plurality of thin film transistors, and the plurality of thin film transistors include low temperature polysilicon (LTPS).

[0014] According to this embodiment, the auxiliary pixel circuit further includes a storage capacitor including a lower electrode and an upper electrode both overlapping the first semiconductor layer, and the storage capacitor is located between the first semiconductor layer and the substrate.

[0015] According to the present embodiment, the second gate electrode includes the same material as the lower electrode of the storage capacitor.

[0016] According to this embodiment, the first auxiliary thin film transistor includes a first gate electrode disposed above the first semiconductor layer and at least partially overlapping the first semiconductor layer.

[0017] According to this embodiment, the display panel further includes a component disposed below the substrate and corresponding to the sensor area and including an electronic element that emits or receives light.

[0018] According to this embodiment, the auxiliary pixel circuit further includes an auxiliary connection line electrically connecting the first semiconductor layer to the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are respectively provided on different layers.

[0019] According to this embodiment, the first auxiliary thin film transistor further includes a connection electrode electrically connected to a source region or a drain region of the first semiconductor layer, and the auxiliary connection line includes the same material as the connection electrode.

[0020] According to this embodiment, the auxiliary pixel circuit further includes a data line for transmitting a data signal to the auxiliary pixel, and the connection electrode includes the same material as that of the data line.

[0021] According to this embodiment, the auxiliary pixel circuit includes a first scan line and a second scan line, the first scan line and the second scan line each transmit a scan signal to the auxiliary pixel, and the first scan line extends from the second gate electrode, and the second scan line extends from the third gate electrode.

[0022] According to this embodiment, the auxiliary pixel circuit includes a previous scan line transmitting a previous scan signal to the fourth auxiliary thin film transistor, and the previous scan line extends from the fourth gate electrode.

[0023] According to this embodiment, the second scan line comprises the same material as the previous scan line.

[0024] According to this embodiment, the auxiliary pixel includes a pixel electrode, and the auxiliary pixel circuit includes a next scan line and a seventh auxiliary thin film transistor, the seventh auxiliary thin film transistor is turned on in response to a next scan signal received through the next scan line and initializes the pixel electrode, the seventh auxiliary thin film transistor includes a seventh semiconductor layer and a seventh gate electrode overlapping with the seventh semiconductor layer, and the next scan line extends from the seventh gate electrode.

[0025] According to this embodiment, the first scan line includes the same material as the next scan line.

[0026] According to one or more embodiments, a display device may include: a substrate including a display area and a sensor area, wherein the display area includes a main pixel and the sensor area includes an auxiliary pixel, wherein the main pixel includes a plurality of thin film transistors, and each of the plurality of thin film transistors includes low-temperature polysilicon (LTPS), wherein the auxiliary pixel includes: a pixel electrode; a first auxiliary thin film transistor, the first auxiliary thin film transistor driving the auxiliary pixel; a third auxiliary thin film transistor, the third auxiliary thin film transistor connected to the first auxiliary thin film transistor in the form of a diode; a fourth auxiliary thin film transistor, the fourth auxiliary thin film transistor initializing a voltage of a gate electrode of the first auxiliary thin film transistor; a second auxiliary thin film transistor, the second auxiliary thin film transistor transmitting a data signal to the first auxiliary thin film transistor; and a seventh auxiliary thin film transistor, the seventh auxiliary thin film transistor being turned on and initializing the pixel electrode, wherein the first auxiliary thin film transistor, the third auxiliary thin film transistor, and the fourth auxiliary thin film transistor each include a semiconductor layer and a gate electrode overlapping the semiconductor layer, the semiconductor layer includes low-temperature polysilicon (LTPS), and the second auxiliary thin film transistor and the seventh auxiliary thin film transistor each include an oxide semiconductor layer and a gate electrode overlapping the oxide semiconductor layer.

[0027] According to this embodiment, the display device further includes a component disposed below the sensor area of ​​the substrate and including an electronic element that emits or receives light, and a resolution of an image displayed in the sensor area is lower than a resolution of an image displayed by the display area. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic perspective view of a display device according to an embodiment.

[0029] Figure 2 is a cross-sectional view of a display device according to an embodiment, which corresponds to a cross-sectional view taken along Figure 1 The line A-A' in Figure 1 A cross section of a display device is shown in FIG.

[0030] Figure 3 is a schematic top plan view of a display panel according to an embodiment.

[0031] Figure 4 yes Figure 3 An enlarged top plan view of the sensor area is shown in FIG.

[0032] Figure 5 is an equivalent circuit diagram of a main pixel according to an embodiment.

[0033] Figure 6is a schematic plan view of a pixel circuit in a main pixel according to an embodiment.

[0034] Figure 7 It is along Figure 6 The lines I-I' and II-II' in Figure 6 2 is a cross-sectional view of a pixel circuit in a main pixel shown in FIG.

[0035] Figure 8 is an equivalent circuit diagram of an auxiliary pixel according to an embodiment.

[0036] Figure 9 is a schematic plan view of a pixel circuit in an auxiliary pixel according to an embodiment.

[0037] Figure 10 It is along Figure 9 The lines III-III', IV-IV' and V-V' in Figure 9 sectional view of a pixel circuit in an auxiliary pixel shown in FIG. DETAILED DESCRIPTION

[0038] Because the embodiments contemplate various variations and numerous embodiments, the exemplary embodiments will be illustrated in the accompanying drawings and described in detail in the written description. The features of the exemplary embodiments and methods of implementing the exemplary embodiments will be clearly understood by reference to the exemplary embodiments described in detail in conjunction with the accompanying drawings. However, the exemplary embodiments may be implemented in many different forms and are not limited to the exemplary embodiments set forth herein.

[0039] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. Like reference numerals in the drawings may represent like elements, and their repeated description will be omitted.

[0040] When a part such as a layer, region or component is referred to as being “on” another layer, region or component, it can be directly on the other layer, region or component or intervening parts may be present therebetween.

[0041] The sizes of components in the drawings may be exaggerated for convenience of explanation.

[0042] Figure 1 is a schematic perspective view of a display device 1 according to the embodiment.

[0043] Reference Figure 1 According to an embodiment, the display device 1 includes a display area DA displaying an image and a non-display area NDA not displaying an image. The display device 1 displays an image by using light emitted from a plurality of primary pixels Pm displayed in the display area DA.

[0044] According to an embodiment, the display device 1 includes a sensor area SA located in the display area DA. Figure 2 As described, the sensor area SA is an area below which a component 20, such as a sensor that can detect infrared light, visible light, and / or sound, is disposed. The sensor area SA includes a transmissive portion TA, through which light and / or sound can be transmitted from the component 20 to the external environment, or the component 20 can receive light and / or sound transmitted from the external environment. Depending on the embodiment, when infrared light is received through the sensor area SA, the transmittance can be approximately 10% or greater, approximately 20% or greater, approximately 25% or greater, 50% or greater, 85% or greater, or 90% or greater.

[0045] In this embodiment, a plurality of auxiliary pixels Pa are provided in the sensor area SA, and an image can be displayed using light emitted from the plurality of auxiliary pixels Pa. The image displayed by the sensor area SA is an auxiliary image and has a lower resolution than the image displayed by the display area DA. That is, because the sensor area SA includes a transmissive portion TA through which light and / or sound can be transmitted, the number of auxiliary pixels Pa that can be provided per unit area in the sensor area SA is smaller than the number of primary pixels Pm that can be provided per unit area in the display area DA.

[0046] According to an embodiment, the sensor area SA is at least partially surrounded by the display area DA, and Figure 1 An embodiment is shown in which the sensor area SA is completely surrounded by the display area DA.

[0047] Hereinafter, an organic light emitting display device according to an embodiment will be described as an example of the display device 1, but the embodiment of the display device 1 is not limited thereto. Other embodiments may use various other types of display devices, such as an inorganic light emitting display or a quantum dot light emitting display.

[0048] exist Figure 1 In the embodiment, the sensor area SA is arranged at one side (e.g., the upper right side) of the rectangular display area DA, but the embodiment is not limited thereto. The shape of the display area DA may be circular, elliptical, or polygonal such as a triangle or a pentagon. In other embodiments, the position of the sensor area SA and the number of the sensor areas SA may be variously changed.

[0049] Figure 2 is a cross-sectional view of a display device 1 according to an embodiment. Figure 2 Corresponding to along Figure 1 A cross section of the display device 1 taken along line AA′ in FIG.

[0050] Reference Figure 2According to an embodiment, a display device 1 includes a display panel 10 including a display element and an assembly 20 located below the display panel 10 and corresponding to a sensor area SA.

[0051] According to the embodiment, the display panel 10 includes a substrate 100, a display element layer 200 disposed on the substrate 100, and a thin film encapsulation layer 300 disposed on the display element layer 200 to seal the display element layer 200. In addition, the display panel 10 further includes a bottom protective film 175 disposed under the substrate 100.

[0052] According to an embodiment, the substrate 100 may include glass or a high molecular weight resin. The high molecular weight resin may be polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyacrylate, polyimide (PI), polycarbonate (PC), or cellulose acetate propionate (CAP). The substrate 100 including the high molecular weight resin is flexible, rollable, or bendable. The substrate 100 has a multilayer structure including a high molecular weight resin and an inorganic layer.

[0053] According to an embodiment, the display element layer 200 includes a circuit layer including thin film transistors such as a main thin film transistor TFTm and an auxiliary thin film transistor TFTa, an organic light emitting diode OLED as a display element, and an insulating layer IL between the circuit layer and the organic light emitting diode OLED.

[0054] According to an embodiment, a main pixel Pm including a main thin film transistor TFTm and an organic light emitting diode OLED connected to the main thin film transistor TFTm is provided in the display area DA. An auxiliary pixel Pa including an auxiliary thin film transistor TFTa and an organic light emitting diode OLED connected to the auxiliary thin film transistor TFTa, and wiring (not shown) is provided in the sensor area SA.

[0055] In addition, according to an embodiment, the sensor area SA includes a transmissive portion TA, which lacks the auxiliary thin film transistor TFTa and the display element. The transmissive portion TA is a region through which light and / or sound emitted from the component 20 is transmitted or a region through which light and / or sound incident on the component 20 is received.

[0056] According to an embodiment, component 20 is located in the sensor area SA. Component 20 is an electronic component that uses light or sound. For example, component 20 can be a sensor such as an infrared sensor that detects infrared light, a sensor that outputs and detects light or sound to measure distance or identify fingerprints, a small lamp that outputs light, a speaker that outputs sound, etc. Electronic components that use light can use various wavelengths, such as visible light, infrared light, or ultraviolet light. Multiple components 20 can be arranged in the sensor area SA. For example, a light-emitting device and a light-receiving device can be arranged together as components 20 in a single sensor area SA. Alternatively, the light-emitting portion and the light-receiving portion can be simultaneously arranged in a single component 20.

[0057] In an embodiment, a conductive layer BSM is disposed in the sensor area SA. More specifically, the conductive layer BSM is positioned to correspond to the auxiliary pixel Pa in the sensor area SA and also to the lower portion of the auxiliary thin-film transistor TFTa. The conductive layer BSM can prevent light emitted from the component 20 from reaching the auxiliary thin-film transistor TFTa of the auxiliary pixel Pa.

[0058] According to an embodiment, an insulating layer IL' is disposed on the conductive layer BSM to insulate the auxiliary thin film transistor TFTa from the conductive layer BSM. The insulating layer IL' includes an inorganic insulating material such as one of silicon oxide, silicon nitride, and silicon oxynitride.

[0059] According to an embodiment, a constant voltage or signal is transmitted to the conductive layer BSM to prevent damage to the pixel circuit due to electrostatic discharge. In addition, the conductive layer BSM is electrically connected to the wiring that transmits power or signals to the auxiliary pixel Pa. Therefore, a constant voltage or signal is transmitted to the conductive layer BSM.

[0060] According to an embodiment, the thin film encapsulation layer 300 includes at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, Figure 2 A first inorganic encapsulating layer 310 and a second inorganic encapsulating layer 330 and an organic encapsulating layer 320 interposed between the first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 are shown.

[0061] According to an embodiment, the first inorganic encapsulating layer 310 and the second inorganic encapsulating layer 330 each include at least one inorganic insulating material selected from aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulating layer 320 includes a polymeric material. The polymeric material may include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resins such as polymethyl methacrylate, polyacrylic acid, etc., or combinations thereof.

[0062] According to an embodiment, a bottom protective film 175 is attached below the substrate 100 and supports and protects the substrate 100. The bottom protective film 175 includes an opening 175OP corresponding to the sensor area SA. The presence of the opening 175OP in the bottom protective film 175 improves light transmittance of the sensor area SA. The bottom protective film 175 includes PET or PI.

[0063] According to an embodiment, the area of ​​the sensor region SA is larger than the area of ​​the arrangement component 20 . Figure 2 The area of ​​the sensor region SA is shown to be the same as the area of ​​the opening 175OP, but the embodiment is not limited thereto, and the area of ​​the opening 175OP provided in the bottom protective film 175 does not need to be the same as the area of ​​the sensor region SA. For example, the area of ​​the opening 175OP may be smaller than the area of ​​the sensor region SA.

[0064] In addition, according to an embodiment, an input sensing member that senses a touch input, an anti-reflection member including a polarizer and a retarder or a color filter and a black matrix, or a transparent window may be further provided on the display panel 10 .

[0065] In this embodiment, the thin film encapsulation layer 300 is used to seal the display element layer 200, but the embodiment is not limited thereto. For example, a sealing substrate attached to the substrate 100 by a sealant or glass frit can seal the display element layer 200.

[0066] Figure 3 is a schematic top plan view of a display panel 10 according to an embodiment, and Figure 4 yes Figure 3 An enlarged top plan view of the sensor area SA.

[0067] Reference Figure 3 According to an embodiment, the display panel 10 is provided in a display area DA and includes a plurality of primary pixels Pm. Each of the primary pixels Pm includes a display element, such as an organic light emitting diode OLED. Each primary pixel Pm emits, for example, one of red light, green light, blue light, and white light through the organic light emitting diode OLED. The display area DA is composed of a plurality of primary pixels Pm and a plurality of primary pixels Pm. Figure 2 The depicted thin film encapsulation layer 300 is covered and protected by the thin film encapsulation layer 300 from external air or moisture.

[0068] According to an embodiment, a sensor area SA is provided in the display area DA, and a plurality of auxiliary pixels Pa are provided in the sensor area SA. The auxiliary pixels Pa each include a display element, such as an organic light-emitting diode (OLED). Each auxiliary pixel Pa emits one of red, green, blue, and white light, for example, through the organic light-emitting diode OLED. Furthermore, a transmissive portion TA is provided between the auxiliary pixels Pa in the sensor area SA.

[0069] According to an embodiment, because the sensor area SA includes the transmissive portion TA, the resolution of the sensor area SA is lower than the resolution of the display area DA. For example, the resolution of the sensor area SA is approximately half the resolution of the display area DA. In some embodiments, the resolution of the display area DA is equal to or greater than approximately 400 ppi, and the resolution of the sensor area SA is approximately 200 ppi.

[0070] Reference Figure 4 According to an embodiment, the sensor area SA includes an auxiliary pixel area PaA including at least one auxiliary pixel Pa and a transmission area TAA including a transmission portion TA. The auxiliary pixel area PaA and the transmission area TAA are arranged in a grid.

[0071] In an embodiment, the auxiliary pixel area PaA includes a first auxiliary pixel Par emitting red light, a second auxiliary pixel Pag emitting green light, and a third auxiliary pixel Pab emitting blue light. Figure 4 The auxiliary pixel Pa of the PenTile type is shown, but the auxiliary pixel Pa may also be a stripe type. Figure 4 It is shown that eight auxiliary pixels Pa are provided in the auxiliary pixel area PaA, but the embodiment is not limited thereto, and the number of the auxiliary pixels Pa may be modified according to the resolution of the sensor area SA.

[0072] In an embodiment, one primary pixel Pm and one auxiliary pixel Pa may include the same pixel circuit. However, the embodiment is not limited thereto. The pixel circuit of the primary pixel Pm may be different from the pixel circuit of the auxiliary pixel Pa.

[0073] According to an embodiment, the main pixel Pm and the auxiliary pixel Pa are each connected to an external circuit provided in the non-display area NDA. The first scan driving circuit 110, the second scan driving circuit 120, the terminal 140, the data driving circuit 150, the first power line 160 and the second power line 170 are provided in the non-display area NDA.

[0074] According to an embodiment, the first scan driver circuit 110 transmits a scan signal to each of the primary pixels Pm and the auxiliary pixels Pa via scan lines SL. The first scan driver circuit 110 transmits an emission control signal to each pixel via emission control lines EL. A second scan driver circuit 120 is provided in parallel with the first scan driver circuit 110, with the display area DA provided between the second scan driver circuit 120 and the first scan driver circuit 110. Some of the primary pixels Pm and the auxiliary pixels Pa provided in the display area DA are electrically connected to the first scan driver circuit 110, while the remaining pixels are electrically connected to the second scan driver circuit 120. In another embodiment, the second scan driver circuit 120 is omitted.

[0075] According to an embodiment, the terminal 140 is provided at one side of the substrate 100. The terminal 140 is not covered by the insulating layer IL but is exposed and is electrically connected to the printed circuit board PCB. The first power line 160 is connected to the terminal 140 through the first connection line 161, and the second power line 170 is connected to the terminal 140 through the second connection line 171. The terminal PCB-P of the printed circuit board PCB is electrically connected to the terminal 140 of the display panel 10. The printed circuit board PCB transmits a signal or power from the controller to the display panel 10. The control signal generated by the controller is transmitted to each of the first scan driving circuit 110 and the second scan driving circuit 120 through the printed circuit board PCB. The controller can respectively supply the first power voltage ELVDD and the second power voltage ELVSS (see Figure 5 and Figure 6 ) is transmitted to the first power line 160 and the second power line 170. The first power voltage ELVDD is transmitted to each of the primary pixel Pm and the auxiliary pixel Pa through the driving voltage line PL connected to the first power line 160, and the second power voltage ELVSS is transmitted to the opposite electrodes of the primary pixel Pm and the auxiliary pixel Pa connected to the second power line 170.

[0076] According to an embodiment, the data driving circuit 150 is electrically connected to the data line DL. The data signal of the data driving circuit 150 is transmitted to each of the primary pixel Pm and the auxiliary pixel Pa through the connection wiring 151 connecting the terminal 140 to the data line DL. Figure 3 The case where the data driving circuit 150 is provided in the printed circuit board PCB is shown. However, in another embodiment, the data driving circuit 150 is provided on the substrate 100. For example, the data driving circuit 150 may be provided between the terminal 140 and the first power wiring 160.

[0077] According to an embodiment, the first power wiring 160 includes a first sub-line 162 and a second sub-line 163 extending parallel to each other in the x direction, with the display area DA disposed therebetween. The second power line 170 has a loop form with one side open and partially surrounding the display area DA.

[0078] Figure 5 is an equivalent circuit diagram of a primary pixel Pm according to an embodiment.

[0079] Reference Figure 5According to an embodiment, a primary pixel Pm includes a primary pixel circuit PCm and an organic light emitting diode OLED connected to the primary pixel circuit PCm. The primary pixel circuit PCm includes a plurality of thin film transistors and a storage capacitor Cst. The thin film transistors and the storage capacitor Cst are connected to signal lines such as a scan line SL, a previous scan line SL-1, an emission control line EL, and a data line DL, an initialization voltage line VL, and a drive voltage line PL.

[0080] exist Figure 5 In the embodiment, the main pixel Pm is connected to the signal line, initialization voltage line VL, and driving voltage line PL, such as the scan line SL, the previous scan line SL-1, the emission control line EL, and the data line DL, but the embodiment is not limited thereto. In other embodiments, at least one of the signal line, initialization voltage line VL, and driving voltage line PL is shared with an adjacent pixel.

[0081] According to an embodiment, the plurality of thin film transistors include a first main thin film transistor T1, a second main thin film transistor T2, a third main thin film transistor T3, a fourth main thin film transistor T4, a fifth main thin film transistor T5, a sixth main thin film transistor T6, and a seventh main thin film transistor T7. The plurality of thin film transistors are respectively referred to as a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initial thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, and a second initial thin film transistor T7 according to their functional characteristics.

[0082] According to an embodiment, the signal lines include a scan line SL for transmitting the scan signal Sn to the switching thin film transistor T2 and the compensation thin film transistor T3, a scan line SL for transmitting the previous scan signal S n-1 The previous scan line SL-1 transmitted to the first initial thin film transistor T4 and the second initial thin film transistor T7, the emission control line EL that transmits the emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, and the data line DL that intersects the scan line SL and transmits the data signal Dm. The driving voltage line PL transmits the first power supply voltage ELVDD to the driving thin film transistor T1, and the initialization voltage line VL transmits the initialization voltage Vint that initializes the driving thin film transistor T1 and the pixel electrode.

[0083] According to an embodiment, the driving gate electrode G1 of the driving thin film transistor T1 is connected to the lower electrode CE1 of the storage capacitor Cst; the driving source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line PL via the operation control thin film transistor T5; and the driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm in response to the switching operation of the switching thin film transistor T2 and drives the driving current IOLED Transmitted to the organic light emitting diode OLED.

[0084] According to an embodiment, a switching gate electrode G2 of the switching thin film transistor T2 is connected to the scan line SL; a switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL; a switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1, and is also connected to the driving voltage line PL via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to a scan signal Sn received via the scan line SL and performs a switching operation to transmit a data signal Dm received via the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0085] According to an embodiment, the compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the scan line SL; the compensation source electrode S3 of the compensation thin film transistor T3 is connected to the drive drain electrode D1 of the drive thin film transistor T1 and is also connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6; the compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the lower electrode CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initialization thin film transistor T4, and the drive gate electrode G1 of the drive thin film transistor T1. The compensation thin film transistor T3 is turned on in response to the scan signal Sn received via the scan line SL and electrically connects the drive gate electrode G1 and the drive drain electrode D1 of the drive thin film transistor T1 to each other, thereby connecting the drive thin film transistor T1 in a diode form.

[0086] According to an embodiment, a first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to a previous scan line SL-1; a first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to a second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL; and a first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to a lower electrode CE1 of the storage capacitor Cst, a compensation drain electrode D3 of the compensation thin film transistor T3, and a driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 is responsive to a previous scan signal S received through the previous scan line SL-1. n-1 The transistor 1 is turned on and transmits the initialization voltage Vint to the driving gate electrode G1 of the driving thin film transistor T1 , thereby initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1 .

[0087] According to an embodiment, the operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL; the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the driving voltage line PL; the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0088] According to an embodiment, the emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL; the emission control source electrode S6 of the emission control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3; and the emission control drain electrode D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initial thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0089] According to an embodiment, the operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal En received through the emission control line EL, so that the first power voltage ELVDD is transmitted to the organic light emitting diode OLED and the driving current I OLED Flow to the organic light emitting diode OLED.

[0090] According to an embodiment, the second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to the previous scan line SL-1; the second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED; the second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to the first initialization source electrode S4 of the first initialization thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 responds to the previous scan signal S received through the previous scan line SL-1. n-1 The OLED is turned on and the pixel electrode of the organic light emitting diode OLED is initialized.

[0091] exist Figure 5 In the embodiment, the first initial thin film transistor T4 and the second initial thin film transistor T7 are connected to the previous scan line SL-1, but the embodiment is not limited thereto. In other embodiments, the first initial thin film transistor T4 is connected to the previous scan line SL-1 and responds to the previous scan signal S n-1 The second initial thin film transistor T7 is connected to an additional scan line (such as a next scan line) and is driven in response to a signal received through the scan line.

[0092] According to an embodiment, the upper electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL, and the opposite electrode of the organic light emitting diode OLED is connected to the second power voltage ELVSS, that is, the common voltage. Therefore, the organic light emitting diode OLED can receive the driving current I from the driving thin film transistor T1. OLED and emits light, thereby displaying images.

[0093] exist Figure 5 According to an embodiment, each of the compensation thin film transistor T3 and the first preliminary thin film transistor T4 has a dual gate electrode, but the embodiment is not limited thereto. In other embodiments, each of the compensation thin film transistor T3 and the first preliminary thin film transistor T4 has a single gate electrode.

[0094] Figure 6 is a schematic plan view of a pixel circuit of a main pixel according to an embodiment, and Figure 7 Shown along Figure 6 1 and 2 show cross sections of the pixel circuit of the main pixel taken along lines II′ and II-II′.

[0095] Reference Figure 6 According to an embodiment, a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initial thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6 and a second initial thin film transistor T7 are disposed on the semiconductor layer 1130.

[0096] According to an embodiment, the semiconductor layer 1130 is provided on a substrate on which a buffer layer including an inorganic insulating material is formed. In this embodiment, the semiconductor layer 1130 includes low temperature polysilicon (LTPS). The polysilicon material has a thickness equal to or greater than 100 cm 2 The semiconductor layer 1130 has high electron mobility, low energy consumption, and high reliability at 100 nm / Vs, and is therefore used as a semiconductor layer of a thin film transistor in a display device. However, the embodiment is not limited thereto. In other embodiments, the semiconductor layer 1130 includes amorphous silicon (a-Si) or an oxide semiconductor, and some semiconductor layers in the plurality of thin film transistors include LTPS, while other semiconductor layers include a-Si or an oxide semiconductor.

[0097] According to an embodiment, various portions of the semiconductor layer 1130 correspond to the semiconductor layers in the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first preliminary thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second preliminary thin film transistor T7, respectively. In other words, the semiconductor layers in the driving thin film transistor T1, the switching thin film transistor T2, the compensation thin film transistor T3, the first preliminary thin film transistor T4, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second preliminary thin film transistor T7 are connected to each other and bent in various shapes.

[0098] According to an embodiment, the semiconductor layer 1130 includes a channel region, a source region and a drain region located on each side of the channel region, wherein the source region and the drain region correspond to the source electrode and the drain electrode of the relevant thin film transistor. Hereinafter, for ease of description, the source region and the drain region are referred to as the source electrode and the drain electrode, respectively.

[0099] According to an embodiment, the driving thin-film transistor T1 includes a driving gate electrode G1 that overlaps a driving channel region, and a driving source electrode S1 and a driving drain electrode D1 located on either side of the driving channel region. The driving channel region is curved into an Ω shape, resulting in a long channel length within a relatively narrow area. Increasing the length of the driving channel region increases the gate voltage drive range. Consequently, the grayscale of light emitted from the organic light-emitting diode (OLED) can be more precisely controlled, improving display quality.

[0100] According to an embodiment, the switching thin film transistor T2 includes a switching gate electrode G2 overlapping a switching channel region, and a switching source electrode S2 and a switching drain electrode D2 located at each side of the switching channel region. The switching drain electrode D2 is connected to the driving source electrode S1.

[0101] According to an embodiment, the compensation thin film transistor T3, which is a dual thin film transistor, includes a compensation gate electrode G3 that overlaps with two compensation channel regions, and further includes a compensation source electrode S3 and a compensation drain electrode D3 arranged on either side of the two compensation channel regions. The compensation thin film transistor T3 is connected to the drive gate electrode G1 of the drive thin film transistor T1 via a node connection line 1174, which will be described below.

[0102] According to an embodiment, the first initialization thin film transistor T4 as a double thin film transistor includes a first initialization gate electrode G4 overlapping two first initialization channel regions, and further includes a first initialization source electrode S4 and a first initialization drain electrode D4 respectively disposed at each side of the first initialization channel region.

[0103] According to an embodiment, the operation control thin film transistor T5 includes an operation control gate electrode G5 overlapping the operation control channel region, and an operation control source electrode S5 and an operation control drain electrode D5 arranged at each side of the operation control channel region. The operation control drain electrode D5 is connected to the driving source electrode S1.

[0104] According to an embodiment, the emission control thin film transistor T6 includes an emission control gate electrode G6 overlapping the emission control channel region and an emission control source electrode S6 and an emission control drain electrode D6 arranged at each side of the emission control channel region. The emission control source electrode S6 is connected to the driving drain electrode D1.

[0105] According to an embodiment, the second initialization thin film transistor T7 includes a second initialization gate electrode G7 overlapping the second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 arranged at each side of the second initialization channel region.

[0106] According to an embodiment, the thin film transistor is connected to signal lines such as the scan line SL, the previous scan line SL- 1 , the emission control line EL, and the data line DL, the initialization voltage line VL, and the driving voltage line PL.

[0107] According to an embodiment, a scan line SL, a previous scan line SL-1, an emission control line EL and a driving gate electrode G1 are arranged on the semiconductor layer 1130, and an insulating layer (multiple insulating layers) is interposed between the semiconductor layer 1130 and the scan line SL, the previous scan line SL-1, the emission control line EL and the driving gate electrode G1.

[0108] According to an embodiment, the scan line SL extends in a first direction. Portions of the scan line SL correspond to the switching gate electrode G2 and the compensation gate electrode G3, respectively. For example, the portion of the scan line SL that overlaps with the channel region of the switching thin film transistor T2 and the portion that overlaps with the channel region of the compensation transistor T3 are the switching gate electrode G2 and the compensation gate electrode G3, respectively.

[0109] According to an embodiment, the previous scan line SL-1 extends in the first direction, and portions of the previous scan line SL-1 correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively. For example, a portion of the previous scan line SL-1 that overlaps with the channel region of the first initial thin film transistor T4 and a portion that overlaps with the channel region of the second initial thin film transistor T7 are the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively.

[0110] According to an embodiment, the emission control line EL extends in a first direction. Respective portions of the emission control line EL correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively. For example, the portion of the emission control line EL that overlaps with the channel region of the operation control thin film transistor T5 and the portion that overlaps with the channel region of the emission control thin film transistor T6 are the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0111] According to an embodiment, the driving gate electrode G1 is a floating electrode and is connected to the compensation thin film transistor T3 via a node connection line 1174 .

[0112] According to an embodiment, the electrode voltage line HL is set on the scan line SL, the previous scan line SL-1, the emission control line EL and the driving gate electrode G1, and an insulating layer (multiple insulating layers) is interposed between the electrode voltage line HL and the scan line SL, the previous scan line SL-1, the emission control line EL and the driving gate electrode G1.

[0113] According to an embodiment, the electrode voltage line HL extends in a first direction to intersect with the data line DL and the drive voltage line PL extending in a second direction intersecting the first direction. A portion of the electrode voltage line HL covers at least a portion of the drive gate electrode G1 and forms a storage capacitor Cst together with the drive gate electrode G1. For example, the drive gate electrode G1 is the lower electrode CE1 of the storage capacitor Cst, and a portion of the electrode voltage line HL is the upper electrode CE2 of the storage capacitor Cst.

[0114] According to an embodiment, the upper electrode CE2 of the storage capacitor Cst is electrically connected to the drive voltage line PL. In this regard, the electrode voltage line HL contacts the drive voltage line PL disposed above the electrode voltage line HL via a contact hole CNT. Therefore, the constant voltage level of the electrode voltage line HL is equal to the voltage level of the drive voltage line PL. For example, the electrode voltage line HL has a constant voltage of approximately +5V. The electrode voltage line HL is a transverse drive voltage line.

[0115] According to an embodiment, the driving voltage line PL extends in the second direction, and the electrode voltage line HL electrically connected to the driving voltage line PL extends in the first direction intersecting the second direction. Therefore, the plurality of driving voltage lines PL and the plurality of electrode voltage lines HL form a grid structure in the display area DA.

[0116] According to an embodiment, the data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 are arranged on the electrode voltage line HL, and an insulating layer (multiple insulating layers) is interposed between the electrode voltage line HL and the data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174.

[0117] According to an embodiment, the data line DL extends in the second direction and contacts the switching source electrode S2 of the switching thin film transistor T2 via the contact hole 1154. A portion of the data line DL serves as the switching source electrode.

[0118] According to the embodiment, as described above, the driving voltage line PL contacts the electrode voltage line HL via the contact hole CNT. In addition, the driving voltage line PL is connected to the operation control thin film transistor T5 via the contact hole 1155. The driving voltage line PL contacts the operation control drain electrode D5 via the contact hole 1155.

[0119] According to an embodiment, one end of the initialization connection line 1173 is connected to the first and second initial thin film transistors T4 and T7 via the contact hole 1152 , and the other end of the initialization connection line 1173 is connected to an initialization voltage line VL to be described below via the contact hole 1151 .

[0120] According to an embodiment, one end of the node connection line 1174 is connected to the compensation drain electrode D3 via the contact hole 1156 , and the other end of the node connection line 1174 contacts the driving gate electrode G1 via the contact hole 1157 .

[0121] According to an embodiment, the initialization voltage line VL is disposed on the data line DL, the driving voltage line PL and the initialization connection line 1173 with an insulating layer (or layers) interposed therebetween.

[0122] According to an embodiment, the initialization voltage line VL extends in the first direction and is connected to the first and second initial thin film transistors T4 and T7 through the initialization connection line 1173. The initialization voltage line VL has a constant voltage, such as -2V.

[0123] According to an embodiment, the initialization voltage line VL is connected to Figure 7 The pixel electrode 210 of the organic light emitting diode OLED shown in FIG. 1 is provided on the same layer and includes Figure 7 The pixel electrode 210 of the organic light emitting diode OLED shown in FIG. Pixel electrode 210 is connected to emission control thin film transistor T6. Pixel electrode 210 contacts contact metal 1175 via contact hole 1163, and contact metal 1175 contacts emission control drain electrode D6 via contact hole 1153.

[0124] exist Figure 6 In the embodiment, the initialization voltage line VL is provided on the same layer as the pixel electrode 210. However, the embodiment is not limited thereto, and in other embodiments, the initialization voltage line VL is provided on the same layer as the electrode voltage line HL.

[0125] In the following, reference is made to Figure 7 , describing a stacked structure of elements included in a display panel according to an embodiment.

[0126] According to an embodiment, the substrate 100 includes glass or a high molecular weight resin. The high molecular weight resin may be one of polyethersulfone (PES), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyacrylate, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). The substrate 100 including the high molecular weight resin is flexible, rollable, or bendable. The substrate 100 may have a multilayer structure including a high molecular weight resin and an inorganic layer.

[0127] According to an embodiment, the buffer layer 111 is located on the substrate 100 and reduces or prevents foreign matter, moisture or external air from penetrating from the lower portion of the substrate 100, and provides a flat surface on the substrate 100. The buffer layer 111 includes an inorganic material such as an oxide or a nitride, an organic material, or an organic-inorganic composite material, and may include a single layer or multiple layers of an inorganic material and an organic material. A barrier layer that prevents penetration of external air is further interposed between the substrate 100 and the buffer layer 111. In an embodiment, the buffer layer 111 includes a first buffer layer 111a and a second buffer layer 111b stacked together.

[0128] According to an embodiment, the gate electrodes G1 and G6 (i.e., the drive gate electrode G1 and the emission control gate electrode G6) are respectively disposed on the semiconductor layers A1 and A6, with a first gate insulating layer 112 interposed between the gate electrodes G1 and G6 and the semiconductor layers A1 and A6. The gate electrodes G1 and G6 include one or more of molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and may include a single layer or multiple layers. For example, the gate electrodes G1 and G6 each include a single layer of Mo. The scan line SL, the previous scan line SL-1, and the emission control line EL are formed on the same layer as the gate electrodes G1 and G6. In other words, the gate electrodes G1 and G6, the scan line SL, the previous scan line SL-1, and the emission control line EL are disposed on the first gate insulating layer 112.

[0129] According to an embodiment, the first gate insulating layer 112 includes silicon dioxide (SiO2), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al2O3), titanium dioxide (TiO2), tantalum oxide (Ta2O5), hafnium oxide (HfO2) and zinc oxide (ZnO2).

[0130] According to an embodiment, a second gate insulating layer 113 is provided to cover the gate electrodes G1 and G6. The second gate insulating layer 113 includes SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2 and ZnO2, etc.

[0131] According to an embodiment, the lower electrode CE1 of the storage capacitor Cst is integrally formed with the driving gate electrode G1 of the driving thin film transistor T1 . That is, the driving gate electrode G1 of the driving thin film transistor T1 serves as the lower electrode CE1 of the storage capacitor Cst.

[0132] According to an embodiment, the upper electrode CE2 of the storage capacitor Cst overlaps the lower electrode CE1, and the second gate insulating layer 113 is between the upper electrode CE2 and the lower electrode CE1 of the storage capacitor Cst. In this case, the second gate insulating layer 113 serves as a dielectric layer of the storage capacitor Cst. The upper electrode CE2 includes a conductive material such as Mo, Al, Cu, or Ti, and may include multiple layers or a single layer including the above materials. For example, the upper electrode CE2 may include a single layer of Mo or a multilayer of Mo / Al / Mo.

[0133] exist Figure 7 In the embodiment, the storage capacitor Cst overlaps with the driving thin film transistor T1, but the embodiment is not limited thereto. In other embodiments, the arrangement of the storage capacitor Cst may be variously changed. For example, in an alternative embodiment, the storage capacitor Cst does not overlap with the driving thin film transistor T1.

[0134] According to an embodiment, the upper electrode CE2 serves as the electrode voltage line HL. For example, a portion of the electrode voltage line HL is the upper electrode CE2 of the storage capacitor Cst.

[0135] According to an embodiment, a first interlayer insulating layer 114 is provided to cover the upper electrode CE2, and a second interlayer insulating layer 115 and a third interlayer insulating layer 116 are provided on the first interlayer insulating layer 114. The first to third interlayer insulating layers 114 to 116 include SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2 or ZnO2, etc.

[0136] According to an embodiment, the data line DL, the driving voltage line PL, and the contact metal 1175 are disposed on the third interlayer insulating layer 116. The data line DL, the driving voltage line PL, and the contact metal 1175 include a conductive material such as Mo, Al, Cu, or Ti, and may be a multi-layer or single-layer structure including one or more of the foregoing materials. For example, the data line DL, the driving voltage line PL, and the contact metal 1175 each have a multi-layer structure including Ti / Al / Ti.

[0137] According to an embodiment, the upper electrode CE2 of the storage capacitor Cst contacts the driving voltage line PL via a contact hole CNT that passes through the first interlayer insulating layer 114 to the third interlayer insulating layer 116. The electrode voltage line HL contacts the driving voltage line PL via the contact hole CNT. Therefore, the voltage level of the electrode voltage line HL, which is a constant voltage, is equal to the voltage level of the driving voltage line PL.

[0138] According to an embodiment, contact metal 1175 contacts semiconductor layer A6 of emission control thin film transistor T6 via contact hole 1153 passing through third interlayer insulating layer 116, second interlayer insulating layer 115, first interlayer insulating layer 114, second gate insulating layer 113, and first gate insulating layer 112. Emission control thin film transistor T6 is electrically connected to pixel electrode 210 of organic light emitting diode OLED through contact metal 1175.

[0139] According to an embodiment, a planarization layer 117 is disposed on the data line DL, the driving voltage line PL, and the contact metal 1175 , and an organic light emitting diode OLED is disposed on the planarization layer 117 .

[0140] According to an embodiment, the planarization layer 117 has a planarized upper surface that planarizes the shape of the pixel electrode 210. The planarization layer 117 may include a single layer or a multilayer including a film formed of an organic material. The planarization layer 117 includes a general commercial polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a general commercial polymer having a phenol group, an acrylic polymer, an imide polymer, an aryl ether polymer, an amide polymer, a fluorinated polymer, a p-xylene polymer, a vinyl alcohol polymer, or a mixture thereof. The planarization layer 117 includes an inorganic material. The planarization layer 117 includes SiO2, SiN x , SiON, Al2O3, TiO2, Ta2O5, HfO2, and ZnO2, etc. When the planarization layer 117 includes an inorganic material, a chemical planarization polishing operation can be performed as needed. In addition, the planarization layer 117 can include both organic and inorganic materials.

[0141] According to an embodiment, the pixel electrode 210 may be a (semi) transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode 210 includes a reflective film and may further include a transparent or semi-transparent electrode layer formed on the reflective film, the reflective film including one or more of silver (Ag), magnesium (Mg), Al, platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and combinations thereof. The transparent or semi-transparent electrode layer includes at least one of indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), and aluminum zinc oxide (AZO). In some embodiments, the pixel electrode 210 includes a stacked structure including ITO / Ag / ITO.

[0142] According to an embodiment, a pixel defining layer 119 is provided on the planarization layer 117. The pixel defining layer 119 forms an emission region of the pixel by having an opening 119OP that exposes a central portion of the pixel electrode 210. In addition, the pixel defining layer 119 prevents arcing, etc., from occurring at the edge of the pixel electrode 210 by increasing the distance between the edge of the pixel electrode 210 and the opposing electrode 230 above the pixel electrode 210. The pixel defining layer 119 includes an organic insulating material such as polyimide, polyamide, acrylic resin, BCB, HMDSO, or phenolic resin, and can be formed by a spin coating method, etc.

[0143] According to an embodiment, the intermediate layer 220 of the organic light emitting diode OLED includes an organic emission layer. The organic emission layer includes an organic material, which includes one of a fluorescent material and a phosphorescent material, each of which emits red light, green light, blue light or white light. The organic emission layer may include a low molecular weight material or a high molecular weight material, and functional layers such as a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL) and an electron injection layer (EIL) may be further alternately arranged below or above the organic emission layer. The intermediate layer 220 corresponds to each pixel electrode 210 in the plurality of pixel electrodes 210. However, the embodiment of the intermediate layer 220 is not limited thereto. In other embodiments, for example, the intermediate layer 220 may be modified differently so as to include a layer formed integrally across the plurality of pixel electrodes 210.

[0144] According to the embodiment, the relative electrode 230 can be a light-transmitting electrode or a reflective electrode. In some embodiments, the relative electrode 230 includes a transparent or translucent electrode and includes a metal film including one or more of lithium (Li), calcium (Ca), lithium fluoride (LiF) / Ca, LiF / Al, Al, Ag, Mg and combinations thereof, and has a small work function. A transparent conductive oxide (TCO) layer including ITO, IZO, ZnO or In2O3 is further provided on the metal film. The relative electrode 230 is provided above the display area DA and the peripheral area PA and is provided on the intermediate layer 220 and the pixel defining layer 119. The relative electrode 230 is formed as a single body with a plurality of organic light-emitting diodes OLED corresponding to the plurality of pixel electrodes 210.

[0145] According to some embodiments, when the pixel electrode 210 is a reflective electrode and the opposing electrode 230 is a transmissive electrode, light emitted from the intermediate layer 220 is emitted toward the opposing electrode 230, and thus the display device 1 is a top-emission type. According to other embodiments, when the pixel electrode 210 is a transparent or semi-transparent electrode and the opposing electrode 230 is a reflective electrode, light emitted from the intermediate layer 220 is emitted toward the substrate 100, and thus the display device 1 is a bottom-emission type. However, embodiments are not limited thereto. According to other embodiments, the display device 1 is a dual-emission type, emitting light in both the top and bottom directions.

[0146] Figure 8 is an equivalent circuit diagram of the auxiliary pixel Pa according to an embodiment.

[0147] According to an embodiment, Figure 8 The equivalent circuit diagram of the auxiliary pixel Pa shown in FIG has the same Figure 5 The circuit structure of the main pixel Pm shown in FIG is similar to the circuit structure, but the structure of some thin film transistors is different from Figure 5 Hereinafter, the main pixel Pm will be described. Figure 8 and Figure 5 The difference between.

[0148] Reference Figure 8 According to an embodiment, the auxiliary pixel Pa includes an auxiliary pixel circuit PCa and an organic light emitting diode OLED connected to the auxiliary pixel circuit PCa. The auxiliary pixel circuit PCa includes a plurality of thin film transistors and a storage capacitor Cst. The plurality of thin film transistors and the storage capacitor Cst are connected to scan lines such as a first scan line SL, a second scan line SL', a previous scan line SL-1, a next scan line SL+1, an emission control line EL, and a data line DL, an initialization voltage line VL, and a driving voltage line PL.

[0149] and Figure 5Compared to the main pixel circuit PCm shown in FIG. 2 , the auxiliary pixel circuit PCa according to the embodiment includes additional signal lines such as a second scan line SL′ and a next scan line SL+1.

[0150] According to an embodiment, the plurality of thin film transistors include a first auxiliary thin film transistor T1, a second auxiliary thin film transistor T2, a third auxiliary thin film transistor T3, a fourth auxiliary thin film transistor T4, a fifth auxiliary thin film transistor T5, a sixth auxiliary thin film transistor T6, and a seventh auxiliary thin film transistor T7. The plurality of thin film transistors are respectively referred to as a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initial thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, and a second initial thin film transistor T7 according to their functional characteristics.

[0151] According to an embodiment, the scan lines include a first scan line SL transmitting a first scan signal Sn, a second scan line SL′ transmitting a second scan signal Sn′, and a scan line SL′ transmitting a previous scan signal Sn′. n-1 The previous scan line SL-1 transmitted to the first initial thin film transistor T4, the emission control signal En is transmitted to the emission control line EL of the operation control thin film transistor T5 and the emission control thin film transistor T6, the next scan signal S n+1 The data signal is transmitted to the next scan line SL+1 of the second initial thin film transistor T7 and the data line DL intersecting the first scan line SL and transmitting the data signal Dm thereto.

[0152] According to an embodiment, the driving voltage line PL transmits a first power voltage (driving voltage) ELVDD to the driving thin film transistor T1 , and the initialization voltage line VL transmits an initialization voltage Vint that initializes the driving thin film transistor T1 and the pixel electrode.

[0153] According to an embodiment, the driving gate electrode G1 of the driving thin film transistor T1 is connected to the lower electrode CE1 of the storage capacitor Cst, the driving source electrode S1 of the driving thin film transistor T1 is connected to the driving voltage line PL via the operation control thin film transistor T5, and the driving drain electrode D1 of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm in response to the switching operation of the switching thin film transistor T2 and converts the driving current I OLED Transmitted to the organic light emitting diode OLED.

[0154] According to an embodiment, a switching gate electrode G2 of the switching thin film transistor T2 is connected to the first scan line SL, a switching source electrode S2 of the switching thin film transistor T2 is connected to the data line DL, and a switching drain electrode D2 of the switching thin film transistor T2 is connected to the driving source electrode S1 of the driving thin film transistor T1 and is also connected to the driving voltage line PL via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on in response to a first scan signal Sn received through the first scan line SL and performs a switching operation to transmit a data signal Dm received through the data line DL to the driving source electrode S1 of the driving thin film transistor T1.

[0155] According to an embodiment, a compensation gate electrode G3 of the compensation thin film transistor T3 is connected to the second scan line SL', a compensation source electrode S3 of the compensation thin film transistor T3 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and is also connected to the pixel electrode 210 of the organic light emitting diode OLED, and a compensation drain electrode D3 of the compensation thin film transistor T3 is connected to the lower electrode CE1 of the storage capacitor Cst, the first initialization drain electrode D4 of the first initial thin film transistor T4, and the driving gate electrode G1 of the driving thin film transistor T1. The compensation thin film transistor T3 is turned on in response to a second scan signal Sn' received through the second scan line SL', electrically connecting the driving gate electrode G1 and the driving drain electrode D1 of the driving thin film transistor T1, thereby connecting the driving thin film transistor T1 in a diode form.

[0156] According to an embodiment, a first initialization gate electrode G4 of the first initialization thin film transistor T4 is connected to a previous scan line SL-1, a first initialization source electrode S4 of the first initialization thin film transistor T4 is connected to a second initialization drain electrode D7 of the second initialization thin film transistor T7 and the initialization voltage line VL, and a first initialization drain electrode D4 of the first initialization thin film transistor T4 is connected to a lower electrode CE1 of the storage capacitor Cst, a compensation drain electrode D3 of the compensation thin film transistor T3, and a driving gate electrode G1 of the driving thin film transistor T1. The first initialization thin film transistor T4 is responsive to a previous scan signal S received through the previous scan line SL-1. n-1 The transistor 1 is turned on and transmits the initialization voltage Vint to the driving gate electrode T1 of the driving thin film transistor, thereby initializing the voltage of the driving gate electrode G1 of the driving thin film transistor T1.

[0157] According to an embodiment, the operation control gate electrode G5 of the operation control thin film transistor T5 is connected to the emission control line EL, the operation control source electrode S5 of the operation control thin film transistor T5 is connected to the driving voltage line PL, and the operation control drain electrode D5 of the operation control thin film transistor T5 is connected to the driving source electrode S1 of the driving thin film transistor T1 and the switching drain electrode D2 of the switching thin film transistor T2.

[0158] According to an embodiment, the emission control gate electrode G6 of the emission control thin film transistor T6 is connected to the emission control line EL, the emission control source electrode S6 of the emission control thin film transistor T6 is connected to the driving drain electrode D1 of the driving thin film transistor T1 and the compensation source electrode S3 of the compensation thin film transistor T3, and the emission control drain electrode D6 of the emission control thin film transistor T6 is electrically connected to the second initialization source electrode S7 of the second initial thin film transistor T7 and the pixel electrode of the organic light emitting diode OLED.

[0159] According to an embodiment, the operation control thin film transistor T5 and the emission control thin film transistor T6 are simultaneously turned on in response to the emission control signal En received through the emission control line EL, so that the first power supply voltage (driving voltage) ELVDD is transmitted to the organic light emitting diode OLED, and the driving current I OLED Flow to the organic light emitting diode OLED.

[0160] According to an embodiment, the second initialization gate electrode G7 of the second initialization thin film transistor T7 is connected to the next scan line SL+1, the second initialization source electrode S7 of the second initialization thin film transistor T7 is connected to the emission control drain electrode D6 of the emission control thin film transistor T6 and the pixel electrode of the organic light emitting diode OLED, and the second initialization drain electrode D7 of the second initialization thin film transistor T7 is connected to the first initialization source electrode S4 of the first initial thin film transistor T4 and the initialization voltage line VL. The second initialization thin film transistor T7 is responsive to the next scan signal S received through the next scan line SL+1. n+1 The OLED is turned on and the pixel electrode of the organic light emitting diode OLED is initialized.

[0161] Figure 8 In the embodiment shown, the first initial thin film transistor T4 is connected to the previous scan line SL-1 and the second initial thin film transistor T7 is connected to the next scan line SL+1, but the embodiment is not limited thereto. In other embodiments, the second initial thin film transistor T7 is connected to the emission control line EL and is driven in response to the emission control signal En.

[0162] In addition, according to the embodiment, Figure 5 and Figure 8 The source electrodes S1 to S7 and the drain electrodes D1 to D7 shown in FIG. 5 may be changed depending on whether each transistor is of p-type or n-type.

[0163] The specific operation of the auxiliary pixel Pa according to the embodiment is as follows:

[0164] During the initialization period, according to an embodiment, when the previous scan signal S is transmitted through the previous scan line SL-1, n-1 When the first initial thin film transistor T4 responds to the previous scan signal S n-1The driving thin film transistor T1 is turned on, and is initialized by the initialization voltage Vint received from the initialization voltage line VL.

[0165] During the data programming period, according to an embodiment, when first and second scan signals Sn and Sn' are received through the first and second scan lines SL and SL', respectively, the switching thin film transistor T2 and the compensation thin film transistor T3 are turned on in response to the first and second scan signals Sn and Sn'. Here, the driving thin film transistor T1 is diode-connected and biased in the forward direction by the turned-on compensation thin film transistor T3.

[0166] By doing so, according to an embodiment, a compensation voltage Dm+Vth is transmitted to the driving gate electrode G1 of the driving thin film transistor T1, where Vth is a negative value, and the compensation voltage Dm+Vth is smaller than the data signal Dm received from the data line DL by the threshold voltage Vth of the driving thin film transistor T1.

[0167] According to an embodiment, the first power voltage (driving voltage) ELVDD and the compensation voltage Dm+Vth are transmitted to both ends of the storage capacitor Cst, and charges corresponding to the voltage difference between both ends of the storage capacitor Cst are stored in the storage capacitor Cst.

[0168] During the emission period, according to an embodiment, the operation control thin film transistor T5 and the emission control thin film transistor T6 are turned on in response to the emission control signal En received from the emission control line EL. A driving current I corresponding to the voltage difference between the first power supply voltage (driving voltage) ELVDD and the voltage of the driving gate electrode G1 of the driving thin film transistor T1 is generated. OLED , and the driving current I OLED The light is transmitted to the organic light emitting diode OLED via the emission control thin film transistor T6.

[0169] In this embodiment, at least one of the thin film transistors T1, T2, T3, T4, T5, T6, and T7 in the auxiliary pixel Pa includes a semiconductor layer including an oxide, and the other thin film transistors include a semiconductor layer including silicon. For example, the driving thin film transistor T1, the compensation thin film transistor T3, and the first initial thin film transistor T4 include an oxide semiconductor, and the switching thin film transistor T2, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initial thin film transistor T7 include an LTPS semiconductor. In another embodiment, at least one of the switching thin film transistor T2, the operation control thin film transistor T5, the emission control thin film transistor T6, and the second initial thin film transistor T7 includes an oxide semiconductor.

[0170] The display device 1 according to this embodiment includes a component 20, such as an infrared optical sensor, located below the sensor area SA of the display panel 10. In this case, image quality abnormality occurs in the auxiliary pixels Pa in the sensor area SA due to infrared light emitted from the component 20.

[0171] Therefore, in the display panel 10 according to the present embodiment, some of the multiple thin film transistors T1, T2, T3, T4, T5, T6 and T7 in the auxiliary pixel Pa are oxide semiconductors to solve image quality abnormalities that may occur in the auxiliary pixel Pa in the sensor area SA due to infrared light emitted from the component 20.

[0172] Oxide semiconductors have a wide band gap (about 3.1 eV), high carrier mobility, and low leakage current, so there is almost no voltage drop even during long driving periods. In addition, during low-frequency driving, the change in brightness due to voltage drop is not large. Therefore, because the driving thin film transistor T1, the compensation thin film transistor T3, and the first initial thin film transistor T4, which are most affected by infrared radiation, each include an oxide semiconductor, the brightness change of the auxiliary pixel Pa due to infrared radiation can be reduced.

[0173] Figure 9 is a schematic plan view of a pixel circuit of an auxiliary pixel according to an embodiment, and Figure 10 Shows the images taken along line III-III', line IV-IV' and line V-V'. Figure 9 A cross section of a pixel circuit of an auxiliary pixel is shown in FIG.

[0174] Reference Figure 9 , the auxiliary pixel Pa according to the embodiment includes a first scan line SL, a second scan line SL', a previous scan line SL-1, a next scan line SL+1, an emission control line EL and an initialization voltage line VL extending in a first direction, and a data line DL and a driving voltage line PL extending in a second direction intersecting the first direction.

[0175] According to an embodiment, the auxiliary pixel Pa includes a driving thin film transistor T1, a switching thin film transistor T2, a compensation thin film transistor T3, a first initial thin film transistor T4, an operation control thin film transistor T5, an emission control thin film transistor T6, a second initial thin film transistor T7 and a storage capacitor Cst.

[0176] In the present embodiment, each of the driving thin film transistor T1 , the compensation thin film transistor T3 , and the first preliminary thin film transistor T4 in the auxiliary pixel Pa includes an oxide semiconductor.

[0177] In the auxiliary pixel Pa, according to an embodiment, the switching thin film transistor T2 , the operation control thin film transistor T5 , the emission control thin film transistor T6 , and the second preliminary thin film transistor T7 include a silicon semiconductor.

[0178] According to an embodiment, the oxide semiconductor layer 1130a of the driving thin film transistor T1, the oxide semiconductor layer 1130a of the compensation thin film transistor T3, and the oxide semiconductor layer 1130a of the first preliminary thin film transistor T4 are connected to each other and bent into various shapes. The oxide semiconductor layer 1130a may include various metal oxides such as indium gallium zinc oxide (IGZO).

[0179] According to an embodiment, the silicon semiconductor layer 1130b of the switching thin film transistor T2, the silicon semiconductor layer 1130b of the operation control thin film transistor T5, the silicon semiconductor layer 1130b of the emission control thin film transistor T6, and the silicon semiconductor layer 1130b of the second initial thin film transistor T7 are provided on the same layer and include the same material. For example, the silicon semiconductor layer 1130b includes LTPS.

[0180] According to an embodiment, the driving thin film transistor T1 includes a driving gate electrode G1 that overlaps with a driving channel region, and a driving source electrode S1 and a driving drain electrode D1 located on each side of the driving channel region. The driving channel region overlapping with the driving gate electrode G1 is curved into an Ω shape, thereby having a long channel length in a narrow area. Increasing the length of the driving channel region increases the driving range of the gate voltage. Therefore, the grayscale of light emitted from the organic light emitting diode OLED can be more accurately controlled, and the display quality can be improved. The driving gate electrode G1 is disposed above the island-type driving semiconductor layer A1 and is electrically connected to the compensation drain electrode D3 of the compensation thin film transistor T3 via a node connection line 1174.

[0181] According to an embodiment, the storage capacitor Cst overlaps the driving thin film transistor T1. The storage capacitor Cst includes a lower electrode CE1 and an upper electrode CE2. The storage capacitor Cst is disposed under the driving semiconductor layer A1.

[0182] According to an embodiment, the switching thin film transistor T2 includes a switching gate electrode G2 overlapping a switching channel region, and a switching source electrode S2 and a switching drain electrode D2 located at each side of the switching channel region. The switching drain electrode D2 is connected to the driving source electrode S1.

[0183] According to an embodiment, the compensation thin film transistor T3 includes a compensation gate electrode G3 overlapping the compensation channel region, and includes a compensation source electrode S3 and a compensation drain electrode D3 located on each side of the compensation gate electrode G3. The compensation thin film transistor T3 is connected to the driving gate electrode G1 of the driving thin film transistor T1 through a node connection line 1174 to be described below. In another embodiment, as Figure 6As shown in FIG, the compensation thin film transistor T3 has a dual gate electrode.

[0184] According to an embodiment, the first initialization thin film transistor T4 includes a first initialization gate electrode G4 overlapping the first initialization channel region, and further includes a first initialization source electrode S4 and a first initialization drain electrode D4 located at each side of the first initialization gate electrode G4. Figure 6 As shown in FIG, the first initial thin film transistor T4 has a dual gate electrode.

[0185] According to an embodiment, the operation control thin film transistor T5 includes an operation control gate electrode G5 overlapping the operation control channel region, and further includes an operation control source electrode S5 and an operation control drain electrode D5 located at each side of the operation control channel region. The operation control drain electrode D5 is connected to the driving source electrode S1.

[0186] According to an embodiment, the emission control thin film transistor T6 includes an emission control gate electrode G6 overlapping the emission control channel region, and further includes an emission control source electrode S6 and an emission control drain electrode D6 located at each side of the emission control gate electrode G6. The emission control source electrode S6 is connected to the driving drain electrode D1.

[0187] According to an embodiment, the second initialization thin film transistor T7 includes a second initialization gate electrode G7 overlapping the second initialization channel region, and further includes a second initialization source electrode S7 and a second initialization drain electrode D7 at each side of the second initialization gate electrode G7.

[0188] According to an embodiment, the thin film transistor is connected to signal lines such as the first scan line SL, the second scan line SL', the previous scan line SL-1, the next scan line SL+1, the emission control line EL and the data line DL, the initialization voltage line VL and the driving voltage line PL.

[0189] Reference Figure 9 and Figure 10 According to an embodiment, the silicon semiconductor layer 1130b described above is disposed on the buffer layer 111 located on the substrate 100. In addition, Figure 2 The conductive layer BSM shown in FIG is disposed on the first buffer layer 111 a and the second buffer layer 111 b .

[0190] According to an embodiment, the first scan line SL, the next scan line SL+1, the emission control line EL, and the lower electrode CE1 are disposed above the silicon semiconductor layer 1130 b, and the first gate insulating layer 112 is interposed between the first scan line SL, the next scan line SL+1, the emission control line EL, the lower electrode CE1, and the silicon semiconductor layer 1130 b. The first scan line SL, the next scan line SL+1, the emission control line EL, and the lower electrode CE1 are disposed on the same layer and include the same material.

[0191] According to an embodiment, the first scan line SL extends in the first direction, and a portion of the first scan line SL corresponds to the switching gate electrode G2. For example, a portion of the first scan line SL overlapping the channel region of the switching thin film transistor T2 is the switching gate electrode G2.

[0192] The next scan line SL+1 extends in the first direction, and a portion of the next scan line SL+1 corresponds to the second initialization gate electrode G7. For example, a portion of the next scan line SL+1 overlapping the channel region of the second initial thin film transistor T7 is the second initialization gate electrode G7.

[0193] According to an embodiment, the emission control line EL extends in the first direction, and respective portions of the emission control line EL correspond to the operation control gate electrode G5 and the emission control gate electrode G6, respectively. For example, a portion of the emission control line EL that overlaps with the channel region of the operation control thin film transistor T5 and a portion that overlaps with the channel region of the emission control thin film transistor T6 are the operation control gate electrode G5 and the emission control gate electrode G6, respectively.

[0194] According to an embodiment, the electrode voltage line HL is set on the first scan line SL, the next scan line SL+1, the emission control line EL and the lower electrode CE1, and the second gate insulating layer 113 is interposed between the electrode voltage line HL and the first scan line SL, the next scan line SL+1, the emission control line EL and the lower electrode CE1.

[0195] According to an embodiment, the electrode voltage line HL extends in a first direction and intersects the data line DL and the driving voltage line PL. A portion of the electrode voltage line HL covers at least a portion of the lower electrode CE1 to form a storage capacitor Cst.

[0196] According to an embodiment, the upper electrode CE2 of the storage capacitor Cst is electrically connected to the drive voltage line PL. In this regard, the electrode voltage line HL contacts the drive voltage line PL located above the electrode voltage line HL via a contact hole CNT. Therefore, the voltage level of the electrode voltage line HL, which is a constant voltage, is equal to the voltage level of the drive voltage line PL. For example, the electrode voltage line HL has a constant voltage of approximately +5V. The electrode voltage line HL is a transverse drive voltage line.

[0197] According to an embodiment, the driving voltage lines PL extend in the second direction, and the electrode voltage lines HL extend in the first direction intersecting the second direction. Therefore, in the display area DA, the plurality of driving voltage lines PL and the plurality of electrode voltage lines HL form a grid structure.

[0198] According to an embodiment, the oxide semiconductor layer 1130a is disposed above the electrode voltage line HL, with the first interlayer insulating layer 114 interposed therebetween. As described above, portions of the oxide semiconductor layer 1130a form the driving thin film transistor T1, the compensation thin film transistor T3, and the first initial thin film transistor T4.

[0199] According to an embodiment, the second scan line SL', the previous scan line SL-1 and the driving gate electrode G1 are disposed on the oxide semiconductor layer 1130a, and the second interlayer insulating layer 115 is interposed between the second scan line SL', the previous scan line SL-1 and the driving gate electrode G1 and the oxide semiconductor layer 1130a. Figure 10 The second interlayer insulating layer 115 serves as a gate insulating layer that insulates the driving semiconductor layer A1 from the driving gate electrode G1 and insulates the compensation semiconductor layer A3 from the compensation gate electrode G3.

[0200] According to an embodiment, the second scan line SL' extends in the first direction, and a portion of the second scan line SL' corresponds to the compensation gate electrode G3. For example, a portion of the second scan line SL' overlapping the compensation thin film transistor T3 is the compensation gate electrode G3.

[0201] According to an embodiment, the previous scan line SL-1 extends in the first direction, and a portion of the previous scan line SL-1 corresponds to the first initialization gate electrode G4. For example, a portion of the previous scan line SL-1 overlapping the channel region of the first initial thin film transistor T4 is the first initialization gate electrode G4.

[0202] like Figure 10 As shown in FIG, according to an embodiment, the driving gate electrode G1 is disposed above the driving semiconductor layer A1. The driving gate electrode G1 is a floating electrode and is electrically connected to the compensation drain electrode D3 of the compensation thin film transistor T3 through a node connection line 1174.

[0203] According to an embodiment, the data line DL, the driving voltage line PL, the initialization connection line 1173, the node connection line 1174 and the auxiliary connection lines 1176, 1177 and 1178 are set on the driving gate electrode G1, and the third interlayer insulating layer 116 is between the data line DL, the driving voltage line PL, the initialization connection line 1173, the node connection line 1174 and the auxiliary connection lines 1176, 1177 and 1178 and the driving gate electrode G1.

[0204] According to an embodiment, the data line DL extends in the second direction and contacts the switching source electrode S2 of the switching thin film transistor T2 via the contact hole 1154. A portion of the data line DL serves as the switching source electrode S2.

[0205] According to the embodiment, as described above, the driving voltage line PL extends in the second direction and contacts the electrode voltage line HL via the contact hole CNT. In addition, the driving voltage line PL is connected to the operation control thin film transistor T5 via the contact hole 1155. A portion of the driving voltage line PL serves as the operation control drain electrode D5.

[0206] According to an embodiment, one end of the initialization connection line 1173 is connected to the second initial thin film transistor T7 via the contact hole 1152 , and the other end of the initialization connection line 1173 is connected to an initialization voltage line VL to be described below via the contact hole 1151 .

[0207] According to an embodiment, one end of the node connection line 1174 is connected to the compensation drain electrode D3 via the contact hole 1156 , and the other end of the node connection line 1174 contacts the driving gate electrode G1 via the contact hole 1157 .

[0208] According to an embodiment, auxiliary connection lines 1176, 1177, and 1178 connect the oxide semiconductor layer 1130a and the silicon semiconductor layer 1130b to each other, wherein the oxide semiconductor layer 1130a and the silicon semiconductor layer 1130b are provided on different layers. The auxiliary connection line 1176 connects the driving thin film transistor T1 and the emission control thin film transistor T6, the auxiliary connection line 1177 connects the driving thin film transistor T1, the switching thin film transistor T2, and the operation control thin film transistor T5 to each other, and the auxiliary connection line 1178 connects the first initial thin film transistor T4 and the second initial thin film transistor T7.

[0209] According to an embodiment, the initialization voltage line VL is provided on the data line DL, the driving voltage line PL, the initialization connection line 1173, the node connection line 1174, and the auxiliary connection lines 1176, 1177, and 1178, and an insulating layer (a plurality of insulating layers) is interposed between the initialization voltage line VL and the data line DL, the driving voltage line PL, the initialization connection line 1173, the node connection line 1174, and the auxiliary connection lines 1176, 1177, and 1178. The initialization voltage line VL is provided on the planarization layer 117.

[0210] According to an embodiment, the initialization voltage line VL extends in the first direction and contacts the first and second initial thin film transistors T4 and T7 connected to each other through the auxiliary connection line 1178 through the initialization connection line 1173. The initialization voltage line VL has a constant voltage, such as -2V.

[0211] According to an embodiment, the initialization voltage line VL is connected to Figure 10 The pixel electrode 210 of the organic light emitting diode OLED shown in FIG. 1 is provided on the same layer and includes Figure 10The pixel electrode 210 of the organic light emitting diode OLED shown in FIG. Pixel electrode 210 is connected to emission control thin film transistor T6. Pixel electrode 210 contacts contact metal 1175 via contact hole 1163, and contact metal 1175 contacts emission control drain electrode D6 via contact hole 1153.

[0212] An embodiment in which the initialization voltage line VL and the pixel electrode 210 are disposed on the same layer is described, but in another embodiment, the initialization voltage line VL and the electrode voltage line HL are disposed on the same layer.

[0213] In addition, according to the embodiment, the above reference Figure 10 The stacking structure described is Figure 7 The stacking structure is the same, therefore, for the detailed description of the layers, reference will be made to the reference Figure 7 , and repeated descriptions will be omitted.

[0214] The display device 1 according to this embodiment includes a component 20, such as an infrared optical sensor, located below the sensor area SA of the display panel 10. In this case, image quality abnormalities may occur in the auxiliary pixels Pa in the sensor area SA due to infrared light emitted from the component 20.

[0215] According to an embodiment, according to the functions of the thin film transistors, some of the multiple thin film transistors T1, T2, T3, T4, T5, T6 and T7 in the auxiliary pixel circuit PCa of the auxiliary pixel Pa are oxide semiconductors, while the other transistors are silicon semiconductors, thereby solving image quality abnormalities that may occur in the auxiliary pixel Pa in the sensor area SA due to infrared light emitted from the component 20.

[0216] Therefore, the display device 1 according to this embodiment can minimize the brightness change of the auxiliary pixel Pa due to infrared radiation (the characteristics of brightness change are most affected by infrared radiation) by including an oxide semiconductor in the driving thin film transistor T1, the compensation thin film transistor T3 and the first initial thin film transistor T4.

[0217] According to the above-described embodiments, a display panel having an expanded display area that can display an image in a sensor area and a display device including the display panel can be realized. However, the scope of the embodiments is not limited to these effects.

[0218] It will be understood that the exemplary embodiments described herein are to be considered in a descriptive sense only and not for purposes of limitation, and that persons of ordinary skill in the art will appreciate that various changes in form and detail may be made from the exemplary embodiments. Accordingly, the scope of the exemplary embodiments will be limited in accordance with the technical concepts of the present disclosure.

Claims

1. A display panel, wherein: The display panel includes: a substrate including a display area and a sensor area, wherein the display area includes primary pixels and the sensor area includes auxiliary pixels and a transmissive portion lacking the auxiliary pixels, wherein the primary pixel is electrically connected to a primary pixel circuit, and the auxiliary pixel is electrically connected to an auxiliary pixel circuit, The auxiliary pixel circuit includes a first auxiliary thin film transistor and a second auxiliary thin film transistor, the first auxiliary thin film transistor includes a first semiconductor layer and a first gate electrode overlapping the first semiconductor layer, the first semiconductor layer includes an oxide semiconductor material, the second auxiliary thin film transistor includes a second semiconductor layer and a second gate electrode overlapping the second semiconductor layer, the second semiconductor layer includes low-temperature polysilicon, and The first auxiliary thin film transistor is a driving thin film transistor for driving the auxiliary pixel.

2. The display panel according to claim 1, wherein The second auxiliary thin film transistor includes a switching thin film transistor that transmits a data signal to the first auxiliary thin film transistor.

3. The display panel according to claim 1, wherein: The auxiliary pixel circuit further includes a third auxiliary thin film transistor connected to the first auxiliary thin film transistor in a diode form, and The third auxiliary thin film transistor includes a third semiconductor layer and a third gate electrode overlapping the third semiconductor layer, wherein the third semiconductor layer includes an oxide semiconductor material.

4. The display panel according to claim 3, wherein: The auxiliary pixel circuit includes a fourth auxiliary thin film transistor that initializes a voltage of the first gate electrode of the first auxiliary thin film transistor, and The fourth auxiliary thin film transistor includes a fourth semiconductor layer and a fourth gate electrode overlapping the fourth semiconductor layer, wherein the fourth semiconductor layer includes an oxide semiconductor material.

5. The display panel according to claim 4, wherein: The first semiconductor layer, the third semiconductor layer, and the fourth semiconductor layer are integrally arranged on the same layer. The display panel according to claim 1 , wherein: The main pixel circuit includes a plurality of thin film transistors, and each of the plurality of thin film transistors includes low-temperature polysilicon.

7. The display panel according to claim 1, wherein: The auxiliary pixel circuit further includes a storage capacitor including a lower electrode and an upper electrode both overlapping the first semiconductor layer, and The storage capacitor is located between the first semiconductor layer and the substrate.

8. The display panel according to claim 7, wherein: The second gate electrode includes the same material as the lower electrode of the storage capacitor.

9. The display panel according to claim 1, wherein: The first auxiliary thin film transistor includes a first gate electrode disposed above the first semiconductor layer and at least partially overlapping the first semiconductor layer.

10. The display panel according to claim 1, wherein The display panel further includes a component disposed under the substrate and corresponding to the sensor area and including an electronic element that emits or receives light.

11. The display panel according to claim 1, wherein: The auxiliary pixel circuit further includes an auxiliary connection line electrically connecting the first semiconductor layer to the second semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer are respectively provided on different layers.

12. The display panel according to claim 11, wherein: The first auxiliary thin film transistor further includes a connection electrode electrically connected to a source region or a drain region of the first semiconductor layer, and The auxiliary connection line includes the same material as the connection electrode.

13. The display panel according to claim 12, wherein: The auxiliary pixel circuit further includes a data line that transmits a data signal to the auxiliary pixel, and The connection electrode includes the same material as the data line.

14. The display panel according to claim 4, wherein: The auxiliary pixel circuit includes a first scan line and a second scan line, each of the first scan line and the second scan line transmits a scan signal to the auxiliary pixel, and The first scan line extends from the second gate electrode, and the second scan line extends from the third gate electrode.

15. The display panel according to claim 14, wherein: The auxiliary pixel circuit includes a previous scanning line that transmits a previous scanning signal to the fourth auxiliary thin film transistor, and The previous scan line extends from the fourth gate electrode.

16. The display panel according to claim 15, wherein: The second scan line includes the same material as that of the previous scan line.

17. The display panel according to claim 14, wherein: The auxiliary pixel includes a pixel electrode, and The auxiliary pixel circuit includes a next scan line and a seventh auxiliary thin film transistor, wherein the seventh auxiliary thin film transistor is turned on in response to a next scan signal received through the next scan line and initializes the pixel electrode. The seventh auxiliary thin film transistor includes a seventh semiconductor layer and a seventh gate electrode overlapping the seventh semiconductor layer, and The next scan line extends from the seventh gate electrode.

18. The display panel according to claim 17, wherein: The first scan line includes the same material as the next scan line.

19. A display device, wherein: The display device comprises: a substrate comprising a display area and a sensor area, wherein the display area comprises primary pixels and the sensor area comprises auxiliary pixels, The main pixel includes a plurality of thin film transistors, and each of the plurality of thin film transistors includes low-temperature polysilicon. Wherein, the auxiliary pixels include: pixel electrode; a first auxiliary thin film transistor, wherein the first auxiliary thin film transistor drives the auxiliary pixel; a third auxiliary thin film transistor, the third auxiliary thin film transistor being connected to the first auxiliary thin film transistor in a diode form; a fourth auxiliary thin film transistor, configured to initialize a voltage of a gate electrode of the first auxiliary thin film transistor; a second auxiliary thin film transistor, which transmits a data signal to the first auxiliary thin film transistor; and a seventh auxiliary thin film transistor, the seventh auxiliary thin film transistor being turned on and initializing the pixel electrode, The first auxiliary thin film transistor, the third auxiliary thin film transistor, and the fourth auxiliary thin film transistor each include a semiconductor layer and a gate electrode overlapping the semiconductor layer, the semiconductor layer includes an oxide semiconductor material, and Each of the second auxiliary thin film transistor and the seventh auxiliary thin film transistor includes a semiconductor layer and a gate electrode overlapping the semiconductor layer, the semiconductor layer including low-temperature polysilicon.

20. The display device according to claim 19, wherein The display device further includes a component disposed below the sensor area of ​​the substrate and including electronic elements that emit or receive light, wherein a resolution of an image displayed in the sensor area is lower than a resolution of an image displayed in the display area.

Images