Circuit, method and control system for controlling a switching element

Abstract

Embodiments described herein relate to simulated predicted dead time. A controller circuit for controlling a switch element and controlling the dead time of the switch element is configured to generate a phase difference voltage using a voltage at a control node of a first switch element and a voltage at a control node of a second switch element. The first switch element is configured to couple a first node and a switch node of a power supply, and the second switch element is configured to couple the switch node and a second node of the power supply. The controller circuit is also configured to generate a first drive signal based on a first pulse width modulation (PWM) signal for the first switch element and the phase difference voltage. The first drive signal includes a voltage controlled delay module. The controller circuit is also configured to generate a second drive signal for driving the second switch element based on a second PWM signal for the second switch element.

Description

Technical Field

[0001] The present disclosure relates to simulation-based techniques for predicting the dead time between switching two switches, such as a half-bridge used as a power stage of a switched mode power supply (SMPS). Background Art

[0002] The duty cycle of a switching power supply (SMPS) can be controlled to adjust the voltage, current or power supplied to a load. A controller for the SMPS generates a pulse width modulation (PWM) signal including a first portion for driving a high-side switch to be turned on and a low-side switch to be turned off, and a second portion for driving the high-side switch to be turned off and the low-side switch to be turned on. The PWM signal can include a dead time portion selected to avoid switching in both the high-side switch and the low-side switch at the same time. Summary of the invention

[0003] In general, the present invention is directed to techniques for minimizing dead time when alternately switching a first switching element and a second switching element. For example, a circuit for controlling a switching element and a circuit for controlling the dead time of a switching element may generate a phase difference voltage using a voltage at a control node of the first switching element and a voltage at a control node of the second switching element, and may generate a first drive signal based on a first pulse width modulation (PWM) signal for the first switching element and the phase difference voltage. In this way, the circuit can help minimize the dead time for alternately switching the first switching element and the second switching element while helping to ensure that only one of the first switching element and the second switching element is turned on.

[0004] In one example, a circuit for controlling a switching element and a circuit for controlling a dead time of a switching element are configured to: generate a phase difference voltage using a voltage at a control node of a first switching element and a voltage at a control node of a second switching element, the first switching element is configured to couple a first node of a power supply and a switching node based on the voltage at the control node of the first switching element, the second switching element is configured to couple the switching node and a second node of the power supply based on the voltage at the control node of the second switching element, a first drive signal is generated based on a first PWM signal for the first switching element and the phase difference voltage, wherein the first drive signal includes a voltage-controlled delay module, and a second drive signal for driving the second switching element is generated based on a second PWM signal for the second switching element.

[0005] In another example, a method for controlling a switching element and controlling the dead time of a switching element includes: a processing circuit generates a phase difference voltage using a voltage at a control node of a first switching element and a voltage at a control node of a second switching element, the first switching element is configured to couple a first node of a power supply and a switching node based on the voltage at the control node of the first switching element, and the second switching element is configured to couple the switching node and a second node of the power supply based on the voltage at the control node of the second switching element, the processing circuit generates a first drive signal based on a first PWM signal for the first switching element and the phase difference voltage, wherein the first drive signal includes a voltage-controlled delay module, and the processing circuit generates a second drive signal for driving the second switching element based on a second PWM signal for the second switching element.

[0006] In another example, a system includes: a first switching element configured to couple a first node of a power supply and a switch node based on a voltage at a control node of the first switching element, a second switching element configured to couple the switch node and a second node of the power supply based on a voltage at a control node of the second switching element, and a processing circuit for controlling a dead time. The processing circuit is configured to: generate a phase difference voltage using a voltage at the control node of the first switching element and a voltage at a control node of the second switching element, generate a first drive signal based on a first PWM signal of the first switching element and the phase difference voltage, wherein the first drive signal includes a voltage-controlled delay module, and generate a second drive signal for driving the second switching element based on a second PWM signal for the second switching element.

[0007] The details of these and other examples are set forth in the drawings and the description that follows.Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a block diagram illustrating an example system in accordance with one or more techniques of this disclosure.

[0009] Figure 2 is a conceptual diagram illustrating an example circuit in accordance with one or more techniques of this disclosure.

[0010] Figure 3 is a conceptual diagram illustrating an example voltage-controlled delay module, according to one or more techniques of this disclosure.

[0011] Figure 4 According to one or more techniques of the present disclosure Figure 3 Figure 2 shows an example performance graph of a voltage controlled delay module.

[0012] Figure 5is a conceptual diagram illustrating an example phase detector in accordance with one or more techniques of this disclosure.

[0013] Figure 6 According to one or more techniques of the present disclosure Figure 1 Figure 1. First performance diagram of the system.

[0014] Fig. 7A According to one or more techniques of the present disclosure Figure 1 A graph of the second performance of the system.

[0015] Figure 7B According to one or more techniques of the present disclosure, Fig. 7A Part of the diagram.

[0016] Figure 8 is according to the present disclosure and can be Figure 1 A first flow chart of an example system performing a technique consistent with the present invention.

[0017] Fig. 9 is according to the present disclosure and can be Figure 1 A second flow chart consistent with the techniques performed by an example system. DETAILED DESCRIPTION

[0018] The present disclosure relates to techniques in the field of synchronous switching power supplies, particularly in the case where a half-bridge is used as a power stage (e.g., a buck regulator) to improve the efficiency of the regulator. For example, the techniques can be used in the control of the dead time required between the conduction phase of the low side of the half-bridge and the conduction phase of the high side of the half-bridge. In such a system, reducing the amount of dead time can result in higher efficiency and less power loss. However, the missing dead time can result in cross conduction, which can damage and / or weaken the half-bridge device. Therefore, the system can control the dead time to improve efficiency while avoiding harmful cross conduction between the switching elements of the half-bridge.

[0019] Some systems may use a constant and / or fixed delay block between the conduction phase of the low side of the half-bridge and the conduction phase of the high side of the half-bridge. Such a system may be easy to implement based on the introduction of a fixed delay block (e.g., dimensioned by simulation), but is not efficient due to the margin required in the worst case (e.g., considering driver voltage supply, process and temperature, etc.).

[0020] Some systems may use adaptive delays that depend on sensing the off state of the opposite power stage. For example, the low side power is allowed to be turned on only when the high side power is turned off. Such systems may be robust in avoiding cross conduction compared to systems using constant and / or fixed delay modules, but may limit the dead time of the propagation delays of the sensing structure and the driver stage.

[0021] Some systems can use digital predictive delay techniques that are based on cycle-by-cycle control of dead time and / or based on sensing of parameters in previous cycles. The sensed parameter can be a low-side body diode or a switch node or an input current. Systems using digital predictive delays can provide improved performance compared to constant delay systems or adaptive delay systems, but systems utilizing digital predictive delays are more complex than constant delay systems or adaptive delay systems. Such systems can rely on digital circuits by using a digital delay locked loop (DLL). Systems using digital DLLs may be limited by the granularity of the minimum delay and therefore may not be able to achieve zero dead time.

[0022] The technology described herein includes a process, which is based on a completely analog method and based on an indirect measure. Such a technology can use a method for sensing the gate voltage of a power element, which forms a half-bridge. The information of the sensed gate is provided as an input to a phase detector of an analog phase-locked loop (PLL) to allow synchronization between the rising edge of the sensed gate of the high-side power and the falling edge of the sensed gate of the low-side power. The phase error between the two inputs can be integrated by the voltage control of the delay element to form a dead time. The quantization limitation of a digital DLL can be overcome by analog control. In this way, the technology described herein can allow the system to switch between the on-stage of the low side of the half-bridge and the on-stage of the high side of the half-bridge with zero dead time.

[0023] Figure 1 is a block diagram illustrating an example system 100 according to one or more techniques of this disclosure. Figure 1 As shown in the example of , system 100 may include dead time processing circuit 101, power supply 102, pulse width modulation (PWM) controller 104, first switching element 106, second switching element 108, driver 116, driver 118, and one or more signal processing components 131 ("signal processing component 131"). In some examples, system 100 may be implemented as an analog circuit.

[0024] The power supply 102 may be configured to provide power to one or more other components of the system 100. For example, the power supply 102 may be configured to provide power to the switch node 111. In some examples, the power supply 102 includes a battery, which may be configured to store electrical energy. Examples of batteries may include, but are not limited to, nickel-cadmium, lead-acid, nickel-metal hydride, nickel-zinc, silver-oxide, lithium-ion, lithium polymer, any other type of rechargeable battery, or any combination of batteries. In some examples, the power supply 102 may include the output of a linear voltage regulator, the output of a power converter, or the output of a power inverter. For example, the power supply 102 may include the output of a DC to DC power converter, an AC to DC power converter, and the like. In some examples, the power supply 102 may represent a connection to a power grid. In some examples, the input power signal provided by the power supply 102 may be a DC input power signal. For example, in some examples, the power supply 102 may be configured to provide a power supply at approximately 5V. DC To about 40V DC range of DC input power signals.

[0025] The first switching element 106 can be configured to couple a first node (e.g., positive) of the power supply 102. The second switching element 108 can be configured to couple a switch node 111 and a second node (e.g., negative) of the power supply 102 based on a voltage at a control node 109 of the second switching element 108. The first switching element 106 and the second switching element 108 can form a half-bridge, for example, for switching a power supply. For example, the first switching element 106 can be a high-side switching element of the half-bridge, and the second switching element 108 can be a low-side switching element of the half-bridge.

[0026] Examples of switch elements may include, but are not limited to, silicon controlled rectifiers (SCRs), field effect transistors (FETs), and bipolar junction transistors (BJTs). Examples of FETs may include, but are not limited to, junction field effect transistors (JFETs), metal oxide semiconductor FETs (MOSFETs), dual gate MOSFETs, insulated gate bipolar transistors (IGBTs), any other type of FETs, or any combination of FETs. Examples of MOSFETs may include, but are not limited to, depletion mode p-channel MOSFETs (PMOS), enhancement mode PMOS, depletion mode n-channel MOSFETs (NMOS), enhancement mode NMOS, double diffused MOSFETs (DMOS), any other type of MOSFETs, or any combination of MOSFETs. Examples of BJTs may include, but are not limited to, PNP, NPN, heterojunction, or any other type of BJT or any combination of BJTs. The switch element may be a high-side switch element or a low-side switch element. Additionally, the switch element may be voltage controlled and / or current controlled. Examples of current controlled switch elements may include, but are not limited to, gallium nitride (GaN) MOSFETs, BJTs, or other current controlled elements.

[0027] The driver 116 may be configured to drive the first switch element 106 based on the first drive signal output by the dead time processing circuit 101. For example, the driver 116 may amplify the signal output by the dead time processing circuit 101 to drive the first switch element 106 to turn on to establish a channel electrically coupling the first node (e.g., positive) of the power source 102 and the switch node 111, or to drive the first switch element 106 to turn off to avoid establishing a channel electrically coupling the first node of the power source 102 and the switch node 111.

[0028] The driver 118 may be configured to drive the second switch element 108 based on the second drive signal output by the dead time processing circuit 101. For example, the driver 118 may amplify the signal output by the dead time processing circuit 101 to drive the second switch element 108 to turn on to establish a channel electrically coupling the second node (e.g., negative) of the power supply 102 and the switch node 111, or to drive the second switch element 108 to turn off to avoid establishing a channel electrically coupling the second node of the power supply 102 and the switch node 111. In some cases, the driver 116 may be referred to as a high-side driver, and the driver 118 may be referred to as a low-side driver.

[0029] The PWM controller 104 may be configured to generate a first PWM signal and a second PWM signal, the first PWM signal being used for the first switching element 106 and the second PWM signal being used for the second switching element 108. In some examples, the PWM controller 104 may be configured to generate a first PWM signal and a second PWM signal having zero dead time, the first PWM signal being used for the first switching element 106 and the second PWM signal being used for the second switching element 108. The PWM controller 104 may include analog circuits. The PWM controller 104 may be a microcontroller on a single integrated circuit including a processor core, a memory, inputs, and outputs. For example, the PWM controller 104 may include one or more processors including one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or any other equivalent integrated logic circuits or discrete logic circuits, and any combination of such components. The term "processor" or "processing circuit" generally refers to any of the aforementioned logic circuits, other logic circuits alone or in combination with other logic circuits, or any other equivalent circuits. In some examples, the PWM controller 104 may be a combination of one or more analog components and one or more digital components.

[0030] The dead time processing circuit 101 may be configured to switch the first switching element 106 and the second switching element 108 and control the dead time of the first switching element 106 and the dead time of the second switching element 108. The dead time processing circuit 101 may include a phase detector 110, a voltage controlled delay module 114 and a fixed delay module 120.

[0031] The phase detector 110 may be configured to generate a phase difference voltage using a voltage at a control node 107 of the first switching element 106 and a voltage at a control node 109 of the second switching element 108 , Figure 5 An example phase detector is shown in more detail.

[0032] Signal processing component 131 may process the output of phase detector 110 for use by voltage controlled delay module 114. For example, signal processing component 131 may include a charge pump, a low pass filter, logic components (eg, flip-flop or latch circuits), or other signal processing components.

[0033] The fixed delay module 120 can be configured to generate a second drive signal based on the second PWM signal output by the PWM controller 104 for the second switching element 108, the second drive signal being used to drive the second switching element 108. For example, the fixed delay module 120 can be configured to generate a second drive signal corresponding to the second PWM signal with a fixed delay. The fixed delay module 120 can apply a preconfigured fixed delay. For example, the fixed delay module 120 can apply a preconfigured fixed delay, the fixed delay being determined by simulation.

[0034] The voltage controlled delay module 114 may be configured to generate a first drive signal based on a PWM signal output by the PWM controller 104 for the first switching element 106 and a phase difference voltage output by the phase detector 110. The voltage controlled delay module 114 may be configured to generate the first drive signal to include a zero dead time with the second drive signal.

[0035] According to one or more techniques, the phase detector 110 may be configured to generate a phase difference voltage using a voltage at a control node 107 of the first switching element 106 and a voltage at a control node 109 of the second switching element 108. The voltage-controlled delay module 114 may be configured to generate a first drive signal based on a first PWM signal output by the PWM controller 104 for the first switching element 106 and the phase difference voltage. The fixed delay module 120 may be configured to generate a second drive signal for driving the second switching element 108 based on a second PWM signal output by the PWM controller 104 for the second switching element 108.

[0036] System 100 may represent a PLL-based analog loop capable of eliminating dead time in a half-bridge by sensing the gate-source voltage. In this manner, system 100 may allow for a higher level of integration (e.g., system level) of applications due to reduced power losses and consequent reduced cooling requirements.

[0037] Although Figure 1 The example shows a voltage-controlled delay module 114 that controls the delay of the high-side switching element and uses a fixed delay module for the low-side switching element, but in other examples, the voltage-controlled delay module 114 can be configured to control the delay of the low-side switching element and the fixed delay module can be used for the high-side switching element.

[0038] Figure 2 is a conceptual diagram illustrating an example circuit 200 according to one or more techniques of the present disclosure. Figure 1 Let's discuss Figure 2The circuit 200 may include a dead time processing circuit 201, a first switching element 206, a second switching element 208, a driver 216, and a driver 218. The dead time processing circuit 201, the first switching element 206, the second switching element 208, the driver 216, and the driver 218 may be examples of the dead time processing circuit 101, the first switching element 106, the second switching element 108, the driver 116, and the driver 118, respectively. The dead time processing circuit 201 may include a phase detector 210, a fixed delay module 220, and a voltage-controlled delay module 214. The phase detector 210, the fixed delay module 220, and the voltage-controlled delay module 214 may be examples of the phase detector 110, the fixed delay module 120, and the voltage-controlled delay module 114, respectively. As shown in the figure, the dead time processing circuit 201 also includes a charge pump 230 and a low-pass filter 232. The charge pump 230 and the low-pass filter 232 may be example components of the signal processing component 131. The circuit 200 may be an analog circuit. For example, the phase detector 210 , the charge pump 230 , the low pass filter 232 , and the voltage controlled delay module 214 may form an analog loop.

[0039] exist Figure 2 In the example of , the phase detector 210 can generate an unfiltered error signal 234 based on a voltage at a control node 207 of the first switching element 206 and a voltage at a control node 209 of the second switching element 208. The charge pump 230 can integrate the magnitude of the unfiltered error signal 234 before filtering. The low pass filter 232 filters the unfiltered error signal 234 to generate a phase difference voltage 236. The low pass filter 232 can include a resistor element 242 and a capacitor 244, the resistor element 242 including a first node 241 and a second node 243, the first node 241 being configured to receive the unfiltered error signal 234 from the charge pump 230, the second node 243 being configured to output the phase difference voltage 236, and the capacitor 244 being coupled to the second node 243 of the resistor element 242.

[0040] Figure 3 is a conceptual diagram illustrating an example voltage controlled delay module 314 according to one or more techniques of the present disclosure. Figure 1 to Figure 2 Let's discuss Figure 3. The voltage controlled delay module 314 may be an example of the voltage controlled delay module 114. As shown, the voltage controlled delay module 314 may include a current source 350, a capacitor 352, a switching element 354, and a comparator 356. The current source 350 may be configured to charge the capacitor 352 when the first PWM signal indicates an enabled state. The capacitor 352 may be configured to store a reference voltage. The switching element 354 may be configured to discharge the capacitor 352 when the first PWM signal is not in an enabled state. The comparator 356 may be configured to compare the reference voltage stored at the capacitor 352 and the phase difference voltage to generate a first drive signal.

[0041] To generate the first drive signal, the voltage control delay module 314 may be configured to generate the first drive signal based on the phase difference voltage and a reference voltage generated based on the first PWM signal. For example, the voltage control delay module 314 may be configured to generate the first drive signal based on the phase difference voltage and a reference voltage stored at the capacitor 352. More specifically, the comparator 356 may be configured to generate the first drive signal based on a comparison of the phase difference voltage with a reference voltage generated based on the first PWM signal. For example, the comparator 356 may be configured to generate the first drive signal based on a comparison of the phase difference voltage with a reference voltage stored at the capacitor 352.

[0042] According to the techniques described herein, the comparator 356 can be configured to generate a first drive signal that turns on a switching element (e.g., the first switching element 106) in response to the voltage at the capacitor 352 being greater than the phase difference voltage, and turns off the switching element in response to the voltage at the capacitor 352 being not greater than the phase difference voltage.

[0043] Figure 4 According to one or more techniques of the present disclosure Figure 3 314. For example purposes only, reference is made to Figures 1 to 3 Let's discuss Figure 4 . Figure 4 The abscissa axis (eg, horizontal) of represents time, and Figure 4 The ordinate axis (eg, vertical) of FIG. 1 represents the capacitor voltage 402 (“V CAP ”), a first PWM signal 404 received at the control node of the switching element 354, and a first drive signal 406 output by the comparator 356.

[0044] exist Figure 4In the example of FIG. 4 , at time 410, the switch element 354 is enabled (e.g., turned on), which causes the current source 350 to increase the capacitor voltage 402. At time 412, in response to the capacitor voltage 402 exceeding the phase difference voltage 408, the comparator 356 transitions the first drive signal 406 to an enabled state. In this way, the voltage-controlled delay module 314 can add the difference between time 410 and time 412 as a voltage-controlled delay module.

[0045] Figure 5 is a conceptual diagram illustrating an example phase detector 510 according to one or more techniques of the present disclosure. Figures 1 to 4 Let's discuss Figure 5 . Phase detector 510 may be an example of phase detector 110. As shown, phase detector 510 may receive an output from driver 516, which may be an example of driver 116, to drive first switching element 506, which may be an example of first switching element 106. Similarly, phase detector 510 may receive an output from driver 518, which may be an example of driver 118, to drive second switching element 508, which may be an example of second switching element 108. As shown, phase detector 510 may include a first source follower element 566, a first attenuation module 576, a first comparator 586, a second source follower element 568, a second attenuation module 578, and a second comparator 588.

[0046] The phase detector 510 may be configured to generate a state signal for the first switching element 506 using a comparison of the indication of the voltage at the control node 507 of the first switching element 506 with a first threshold. For example, the first source follower element 566 may be configured to generate a voltage signal corresponding to the voltage at the control node 507 of the first switching element 506. The first attenuation module 576 may be configured to generate an indication of the voltage at the control node 507 of the first switching element 506 using the voltage signal at the control node 507 of the first switching element 506. The first comparator 586 may be configured to compare the indication of the voltage at the control node 507 of the first switching element 506 with a first threshold and output a state signal for the first switching element 506. In some examples, the first threshold is slightly lower than a threshold of the first switching element 506 (VTH≤vth0).

[0047] The phase detector 510 may be configured to generate a state signal for the second switching element 508 using a comparison of the indication of the voltage at the control node 509 of the second switching element 508 with a second threshold. For example, the second source follower element 568 may be configured to generate a voltage signal corresponding to the voltage at the control node 509 of the second switching element 508. The second attenuation module 578 may be configured to generate an indication of the voltage at the control node 509 of the second switching element 508 using a voltage signal corresponding to the voltage at the control node 509 of the second switching element 508. The second comparator 588 may be configured to compare the indication of the voltage at the control node 509 of the second switching element 508 with a second threshold and output a state signal for the second switching element 508. In some examples, the second threshold is slightly lower than the threshold of the second switching element 508 (VTH≤vth0).

[0048] In this way, the dead time processing circuit 101 can be configured to generate a phase difference voltage using the state signal of the first switching element 506 and the state signal of the second switching element 508. For example, a charge pump can integrate the state signal for the first switching element 506 and the state signal for the second switching element 508, and a low pass filter can filter the output of the charge pump to generate a phase difference voltage (see Figure 2 ).

[0049] exist Figure 5 In the example of , the first attenuation module 576 can use the same type of N-MOS as the first source follower element 566 to clamp the harmful voltage, and at the same time safely propagate the information of the power supply gate-source voltage to the first comparator 586, such as a low voltage fast Schmitt trigger (other types of clamping structures and / or voltage comparators can also be considered). Similarly, the second attenuation module 578 can use the same type of N-MOS as the second source follower element 568 to clamp the harmful voltage, and at the same time safely propagate the information of the power supply gate-source voltage to the second comparator 588, such as a low voltage fast Schmitt trigger (other types of clamping structures and / or voltage comparators can also be considered).

[0050] Figure 6 According to one or more techniques of the present disclosure Figure 1 A diagram of the first performance of a system. For illustrative purposes only Figures 1 to 5 Let's discuss Figure 6 . Figure 6 The abscissa axis (eg, horizontal) of represents time, and Figure 6 The ordinate axis (eg, vertical) of the second switching element 108 represents the low-side gate voltage 602 (“V GS_LS”), the high-side gate voltage 604 (“V GS_HS ”), the low-side current 606 (“I DS_LS ”), the high-side current 608 (“I DS_HS ”), a switch node (SW) voltage 610 at the switch node 111, a high-side digitized output 612 (“hs_on_sensed”) for sensing in the high-side gate voltage of the first switch element 106, and a low-side digitized output 614 (“ls_on_sensed”) for sensing in the low-side gate voltage of the second switch element 108. The voltage threshold 630 (“V TH ”) corresponds to the conduction threshold of the first switching element 106 and the second switching element 108. For example, the voltage threshold 630 (“V TH ”) can be slightly smaller than the turn-on threshold of the first switching element 106 and the turn-on threshold of the second switching element 108.

[0051] Figure 6 An example voltage on the control node 107 of the first switching element 106 and the control node 109 of the second switching element 108 is shown in the case where a zero dead time condition can be achieved. For example, at time 620, the low side current 606 begins to decline. At time 622, the low side current 606 reaches zero, and the high side current 608 begins to rise. At time 624, the high side current 608 reaches a peak. Using the voltage threshold 630 as a voltage equal to or lower than the turn-on threshold ("vth0") of the first switching element 106 and the second switching element 108, the system 100 can help ensure that cross conduction on both the first switching element 106 and the second switching element 108 is avoided. Zeroing the phase error between the rising edge of the high side gate voltage 604 and the falling edge of the low side gate voltage 602 helps to minimize the dead time, which can maximize the switching efficiency of the first switching element 106 and the second switching element 108.

[0052] Fig. 7A According to one or more techniques of the present disclosure Figure 1 A diagram of the second performance of a system. For illustrative purposes only Figures 1 to 6 Let's discuss Fig. 7A The horizontal axis (eg, horizontal) of FIG. 7 represents time, and Fig. 7AThe ordinate axis (e.g., vertical) represents the sensed low-side digitized output 702 of the low-side gate voltage of the second switching element 108, the sensed high-side digitized output 704 of the high-side gate voltage of the first switching element 106, the low-side gate voltage 706 at the control node 109 of the second switching element 108, the high-side gate voltage 708 at the control node 107 of the first switching element 106, the switching node voltage 710 at the switching node 111, the inductor current 712 of the inductor coupled to the switching node 111, and the dead time 714. Fig. 7A An example of how the dead time 714 of the transition of the switch node from low to high is reduced cycle by cycle by the analog control loop of the system 100 is shown.

[0053] Figure 7B According to one or more techniques of the present disclosure, Fig. 7A FIG. 730 is a diagram of a portion of FIG. 730. For illustrative purposes only, reference is made to Figures 1 to 6 , Fig. 7A Let's discuss Figure 7B . Figure 7B How the system 100 can eliminate dead time 714 is shown. As shown, the switch node voltage 710 has a negligible undershoot below ground. For values ​​above the threshold voltage, the low side gate voltage 706 and the high side gate voltage 708 do not overlap. As shown, the low side digitized output 702 and the high side digitized output 704 overlap due to the different propagation delays of the low side chain and the high side chain. The dead time 714 remains constant at about zero.

[0054] Figure 8 is according to the present disclosure and can be Figure 1 The first flow chart of the technique performed by the example system is consistent with that of the example system. For example purposes only, reference Figures 1 to 6 , Fig. 7A , Figure 7B Let's discuss Figure 8 The phase detector 110 generates a phase difference (802) using a voltage at the control node 107 of the first switching element 106 and a voltage at the control node of the second switching element 108. The voltage-controlled delay module 114 generates a first drive signal (804) for driving the first switching element 106 based on the first PWM signal of the first switching element 106 and the phase difference voltage. The fixed delay module 120 generates a second drive signal (806) for driving the second switching element 108 based on the second PWM signal.

[0055] Fig. 9 is according to the present disclosure and can be Figure 1 A second flow chart of the technique performed by the example system is consistent with that of the example system. For example purposes only Figures 1 to 6 , Fig. 7A , Figure 7B , Figure 8 Let's discuss Fig. 9 . The phase detector 210 generates an error signal (902) based on the voltage at the control node 207 of the first switching element 206 and the voltage at the control node 209 of the second switching element 208. The charge pump 230 integrates the error signal (904). The low pass filter 232 filters the error signal to generate a phase difference voltage (906). The voltage controlled delay module 214 generates a reference voltage (908) at the capacitor using a current source controlled by the PWM signal for the first switching element 206. For example, the voltage controlled delay module 314 generates a reference voltage at the capacitor 352 using a current source 350 controlled by the PWM signal for the first switching element 206. The voltage controlled delay module 314 generates a first drive signal (910) for driving the first switching element 206 based on a comparison of the phase difference voltage and the reference voltage. For example, the comparator 356 generates a first drive signal for driving the first switching element 206 based on a comparison of the phase difference voltage at the capacitor 352 and the reference voltage. The fixed delay module 220 generates a second driving signal for driving the second switching element, the second driving signal corresponding to a second PWM signal of the second switching element with the fixed delay module (912).

[0056] The following examples may illustrate one or more aspects of the present invention.

[0057] Embodiment 1. A circuit for controlling a switching element and controlling a dead time of the switching element, the circuit being configured to: generate a phase difference voltage using a voltage at a control node of a first switching element and a voltage at a control node of a second switching element, the first switching element being configured to couple a first node of a power supply and a switching node based on the voltage at the control node of the first switching element, and the second switching element being configured to couple the switching node and a second node of the power supply based on the voltage at the control node of the second switching element; generate a first drive signal based on a first pulse width modulation (PWM) signal for the first switching element and the phase difference voltage, wherein the first drive signal includes a voltage-controlled delay module; and generate a second drive signal for driving the second switching element based on a second PWM signal for the second switching element.

[0058] Embodiment 2. The circuit according to Example 1, wherein, in order to generate the first drive signal, the circuit is configured to generate the first drive signal based on the phase difference voltage and a reference voltage generated based on the first PWM signal.

[0059] Embodiment 3. The circuit according to any combination of Examples 1 to 2, wherein, to generate the first drive signal, the circuit is configured to generate the first drive signal based on a comparison of the phase difference voltage and a reference voltage generated based on the first PWM signal.

[0060] Embodiment 4. A circuit according to any combination of Examples 1 to 3, wherein the circuit comprises: a capacitor configured to store a reference voltage; a current source configured to charge the capacitor when the first PWM signal indicates an enabled state; and a switch element configured to discharge the capacitor when the first PWM signal is not in the enabled state.

[0061] Embodiment 5. The circuit according to any combination of Examples 1 to 4, wherein the circuit comprises: a comparator configured to compare a reference voltage stored at the capacitor with a phase difference voltage to generate a first driving signal.

[0062] Embodiment 6. A circuit according to any combination of Examples 1 to 5, wherein, in order to generate a first drive signal, the circuit is configured to: generate the first drive signal to turn on the first switching element in response to the voltage at the capacitor being greater than the phase difference voltage, and turn off the first switching element in response to the voltage at the capacitor being not greater than the phase difference voltage.

[0063] Embodiment 7. A circuit according to any combination of Examples 1 to 6, wherein, to generate a first drive signal, the circuit is configured to: generate an unfiltered error signal based on a voltage at a control node of the first switching element and a voltage at a control node of the second switching element using a phase detector; and filter the unfiltered error signal using a low-pass filter to generate a phase difference voltage.

[0064] Embodiment 8. The circuit of any combination of Examples 1 to 7, wherein the circuit is configured to integrate the magnitude of the unfiltered error signal prior to filtering using a charge pump.

[0065] Embodiment 9. The circuit according to any combination of Examples 1 to 8, wherein the low pass filter comprises: a resistive element including a first node configured to receive an unfiltered error signal from a charge pump and a second node configured to output a phase difference voltage; and a capacitor coupled to the second node of the resistive element.

[0066] Embodiment 10. A circuit according to any combination of Examples 1 to 9, wherein, to generate a phase difference voltage, the circuit is configured to: generate a state signal of the first switching element using a comparison of an indication of a voltage at a control node of the first switching element with a first threshold; generate a state signal of the second switching element using a comparison of an indication of a voltage at a control node of the second switching element with a second threshold; and generate the phase difference voltage using the state signal for the first switching element and the state signal for the second switching element.

[0067] Embodiment 11. A circuit according to any combination of Examples 1 to 10, wherein the circuit comprises: a first source follower element configured to generate a voltage signal corresponding to a voltage at a control node of a first switch element; a first attenuation module configured to generate an indication of a voltage at the control node of the first switch element using a voltage signal of the voltage at the control node of the first switch element; a first comparator configured to compare the indication of the voltage at the control node of the first switch element with a first threshold value and output a state signal of the first switch element; a second source follower element configured to generate a voltage signal corresponding to a voltage at a control node of a second switch element; a second attenuation module configured to generate an indication of a voltage at the control node of the second switch element using a voltage signal corresponding to the voltage at the control node of the second switch element; and a second comparator configured to compare the indication of the voltage at the control node of the second switch element with a second threshold value and output a state signal of the second switch element.

[0068] Embodiment 12 The circuit according to any combination of Examples 1 to 11, wherein, in order to generate the second driving signal, the circuit is configured to: generate the second driving signal corresponding to the second PWM signal using a fixed delay module.

[0069] Embodiment 13. The circuit according to any combination of Examples 1 to 12, wherein, to generate the first drive signal, the circuit is configured to: generate the first drive signal to include a zero dead time with the second drive signal.

[0070] Embodiment 14. The circuit according to any combination of Examples 1 to 13, wherein the circuit is an analog circuit.

[0071] Embodiment 15. A method for controlling a switching element and controlling the dead time of the switching element, the method comprising: generating a phase difference voltage by a processing circuit using a voltage at a control node of a first switching element and a voltage at a control node of a second switching element, the first switching element being configured to couple a first node of a power supply and a switching node based on the voltage at the control node of the first switching element, and the second switching element being configured to couple the switching node and a second node of the power supply based on the voltage at the control node of the second switching element; generating a first drive signal by the processing circuit based on a first pulse width modulation (PWM) signal for the first switching element and the phase difference voltage, wherein the first drive signal includes a voltage-controlled delay module; and generating a second drive signal for driving the second switching element by the processing circuit based on a second PWM signal for the second switching element.

[0072] Example 16. The method according to Example 15, wherein generating the first drive signal is based on the phase difference voltage and a reference voltage generated based on the first PWM signal.

[0073] Embodiment 17. The method according to any combination of Examples 15 to 16, wherein, to generate the first drive signal, the circuit is configured to generate the first drive signal based on a comparison of the phase difference voltage and a reference voltage generated based on the first PWM signal.

[0074] Embodiment 18. The method of any combination of Examples 15 to 17, wherein the capacitor is configured to store a reference voltage; wherein the current source is configured to charge the capacitor when the first PWM signal indicates an enabled state; and wherein the switch element is configured to discharge the capacitor when the first PWM signal is not in an enabled state.

[0075] Embodiment 19. The method according to any combination of Examples 15 to 18, wherein the comparator is configured to compare a reference voltage stored at the capacitor and the phase difference voltage to generate the first drive signal.

[0076] Embodiment 20. A system comprising: a first switching element configured to couple a first node of a power supply and a switch node based on a voltage at a control node of the first switching element; a second switching element configured to couple the switch node and a second node of the power supply based on a voltage at a control node of the second switching element; and a processing circuit for controlling dead time, the processing circuit being configured to: generate a phase difference voltage using a voltage at the control node of the first switching element and a voltage at a control node of the second switching element; generate a first drive signal based on a first pulse width modulation (PWM) signal for the first switching element and the phase difference voltage, wherein the first drive signal includes a voltage-controlled delay module; and generate a second drive signal for driving the second switching element based on a second PWM signal for the second switching element.

[0077] The technology described in the present disclosure may be implemented at least in part in hardware, software, firmware, or any combination thereof. For example, various aspects of the described technology may be implemented in one or more processors (including one or more microprocessors, digital signal processors (DSPs)), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), or any other equivalent integrated or discrete logic circuits, and any combination of these components. The term "processor" or "processing circuit" may generally refer to any of the aforementioned logic circuits alone or may refer to a combination thereof with other logic circuits or any other equivalent circuits. A control unit including hardware may also perform one or more of the techniques disclosed herein.

[0078] Such hardware, software, and firmware may be implemented in the same device or in separate devices to support the various technologies described in this disclosure. In addition, any of the described units, modules, or components may be implemented together or separately as discrete but interoperable logical devices. Describing different features as modules or units is intended to highlight different functional aspects and does not necessarily mean that these modules or units must be implemented by separate hardware, firmware, or software components. On the contrary, the functions associated with one or more modules or units may be performed by separate hardware, firmware, or software components, or integrated in common or separate hardware, firmware, or software components.

[0079] Various aspects have been described in this disclosure. These and other aspects are within the scope of the following claims.

Claims

1. A circuit for controlling a switching element, the circuit also being used to control a dead time of the switching element, the circuit being configured as follows: generating a phase difference voltage using a voltage at a control node of a first switching element and a voltage at a control node of a second switching element, the first switching element being configured to couple a first node of a power source and a switch node based on the voltage at the control node of the first switching element, and the second switching element being configured to couple the switch node and a second node of the power source based on the voltage at the control node of the second switching element; generating a first drive signal based on a comparison of the phase difference voltage and a reference voltage generated based on a first PWM signal for the first switching element; as well as A second drive signal for driving the second switching element is generated based on a second PWM signal for the second switching element.

2. The circuit according to claim 1, wherein the circuit comprises: a capacitor configured to store the reference voltage; a current source configured to charge the capacitor when the first PWM signal indicates an enabled state; as well as A switching element is configured to discharge the capacitor when the first PWM signal is not in the enabled state.

3. The circuit according to claim 2, wherein the circuit comprises: A comparator is configured to compare the reference voltage stored at the capacitor with the phase difference voltage to generate the first driving signal.

4. The circuit according to claim 2, wherein: To generate the first drive signal, the circuit is configured to: The first drive signal is generated to turn on the first switching element in response to the voltage at the capacitor being greater than the phase difference voltage, and the first switching element is turned off in response to the voltage at the capacitor being not greater than the phase difference voltage.

5. The circuit according to claim 1, wherein to generate the second drive signal, the circuit is configured to: The second drive signal corresponding to the second PWM signal is generated with a fixed delay.

6. The circuit according to claim 1, wherein to generate the first drive signal, the circuit is configured to: The first drive signal is generated to include a zero dead time with the second drive signal.

7. The circuit of claim 1, wherein the circuit is an analog circuit.

8. A circuit for controlling a switching element, the circuit also being used to control a dead time of the switching element, the circuit being configured as follows: The phase difference voltage is generated using a voltage at a control node of a first switching element and a voltage at a control node of a second switching element, the first switching element being configured to couple a first node of a power source and a switch node based on the voltage at the control node of the first switching element, and the second switching element being configured to couple a second node of the power source and the switch node based on the voltage at the control node of the second switching element, wherein To generate the phase difference voltage, the circuit is configured to: generate an unfiltered error signal based on a voltage at the control node of the first switching element and a voltage at the control node of the second switching element using a phase detector, and filter the unfiltered error signal using a low pass filter to generate the phase difference voltage; generating a first drive signal based on a first pulse width modulation (PWM) signal for the first switching element and the phase difference voltage; as well as A second drive signal for driving the second switching element is generated based on a second PWM signal for the second switching element.

9. The circuit according to claim 8, wherein the circuit is configured to: A charge pump is used to integrate the magnitude of the unfiltered error signal prior to filtering.

10. The circuit of claim 9, wherein the low pass filter comprises: a resistor element including a first node configured to receive the unfiltered error signal from the charge pump and a second node configured to output the phase difference voltage; as well as A capacitor is coupled to the second node of the resistive element.

11. A circuit for controlling a switching element, the circuit also being used to control a dead time of the switching element, the circuit being configured as follows: The phase difference voltage is generated using a voltage at a control node of a first switching element and a voltage at a control node of a second switching element, the first switching element being configured to couple a first node of a power source and a switch node based on the voltage at the control node of the first switching element, and the second switching element being configured to couple a second node of the power source and the switch node based on the voltage at the control node of the second switching element, wherein In order to generate the phase difference voltage, the circuit is configured as follows: generating a state signal of the first switching element using a comparison of an indication of a voltage at the control node of the first switching element with a first threshold; generating a state signal of the second switching element using a comparison of an indication of a voltage at the control node of the second switching element with a second threshold; as well as generating the phase difference voltage using the state signal of the first switching element and the state signal of the second switching element; generating a first drive signal based on a first PWM signal for the first switching element and the phase difference voltage; as well as A second drive signal for driving the second switching element is generated based on a second PWM signal for the second switching element.

12. The circuit of claim 11, wherein the circuit comprises: a first source follower element configured to generate a voltage signal corresponding to a voltage at the control node of the first switching element; a first attenuation module configured to generate the indication of the voltage at the control node of the first switching element using the voltage signal of the voltage at the control node of the first switching element; a first comparator configured to compare the indication of the voltage at the control node of the first switching element with the first threshold value and to output the state signal of the first switching element; a second source follower element configured to generate a voltage signal corresponding to a voltage at the control node of the second switching element; a second attenuation module configured to generate the indication of the voltage at the control node of the second switching element using the voltage signal corresponding to the voltage at the control node of the second switching element; as well as A second comparator is configured to compare the indication of the voltage at the control node of the second switching element with the second threshold value and to output the state signal of the second switching element.

13. A method for controlling a switching element, the method further being used to control a dead time of the switching element, the method comprising: generating, by the processing circuit, a phase difference voltage using a voltage at a control node of a first switching element and a voltage at a control node of a second switching element, the first switching element being configured to couple a first node of a power supply and a switch node based on the voltage at the control node of the first switching element, and the second switching element being configured to couple the switch node and a second node of the power supply based on the voltage at the control node of the second switching element; generating, by the processing circuit, a first drive signal based on a first PWM signal for the first switching element and the phase difference voltage, wherein the first drive signal is generated based on a comparison of the phase difference voltage with a reference voltage generated based on the first PWM signal; as well as A second drive signal for driving the second switching element is generated by the processing circuit based on a second PWM signal for the second switching element.

14. The method according to claim 13, wherein the capacitor is configured to store the reference voltage; wherein the current source is configured to charge the capacitor when the first PWM signal indicates an enabled state; and The switch element is configured to discharge the capacitor when the first PWM signal is not in the enabled state. 15 . The method of claim 14 , wherein a comparator is configured to compare the reference voltage stored at the capacitor with the phase difference voltage to generate the first driving signal.

16. A control system comprising: a first switching element configured to couple a first node of a power source and a switching node based on a voltage at a control node of the first switching element; a second switching element configured to couple the switch node and a second node of the power supply based on a voltage at a control node of the second switching element; as well as A circuit for controlling dead time, the circuit being configured as: generating a phase difference voltage using a voltage at the control node of the first switching element and a voltage at the control node of the second switching element; generating a first drive signal based on a comparison of the phase difference voltage and a reference voltage generated based on a first PWM signal for the first switching element; as well as A second drive signal for driving the second switching element is generated based on a second PWM signal for the second switching element.

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