Display device

Abstract

A display device is disclosed. The display device includes a display substrate, a first connection line and a signal line. The display substrate includes a display area and a pad area arranged outside the display area. The first connection line is arranged on the pad area of ​​the display substrate. The signal line is arranged on the first connection line of the pad area of ​​the display substrate. The signal line is electrically connected to the first connection line through a first contact hole. The signal line includes at least one first opening at least partially surrounded by the signal line in a plan view. The first opening is arranged closer to the display area than the first contact hole.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2019-0028548, filed on Mar. 13, 2019, which is hereby incorporated by reference for all purposes as if fully set forth herein. Technical Field

[0003] Example embodiments generally relate to display devices. Background Art

[0004] A display device is a device for visually displaying data. Such a display device generally includes a substrate divided into a display area and a non-display area. A plurality of pixels may be arranged on the substrate in the display area, and a plurality of pads may be arranged on the substrate in the non-display area. A plurality of pads may be connected to a flexible film including a driver integrated circuit (IC) and the like, and mounted (or connected) thereon in the form of a chip on film (COF). The driver IC may be configured to transmit a drive signal to a pixel as a part of visually displaying data. The flexible film generally includes a plurality of leads connected to the plurality of pads. Each of the leads may be bonded to a separate pad. Bonding may be performed by an ultrasonic bonding process.

[0005] Methods for inspecting the ultrasonic bonding state between pads and leads include destructive inspection and non-destructive inspection. Destructive inspection is a method of observing the bonding interface between pads and leads by cutting one or more of the pads and leads in a direction such as a vertical direction and inspecting the state of the bonding interface. Non-destructive inspection is a method of observing the bonding interface using an imaging device or the like without destroying the pads and leads that are in contact with each other. The advantages of non-destructive inspection techniques are that they generally take less inspection time than destructive inspection techniques and the inspected structure does not need to be damaged.

[0006] The above information disclosed in this section is only for background understanding of the inventive concept and therefore it may contain information that does not form the prior art. Summary of the invention

[0007] Some example embodiments can provide an apparatus including an ultrasonic bond inspection unit that is configurable to easily receive a signal from a connection unit.

[0008] Additional aspects will be set forth in the detailed description which follows, and in part will be apparent from the disclosure, or may be learned by practice of the inventive concepts.

[0009] According to some exemplary embodiments, a display device includes a display substrate, a first connection line and a signal line. The display substrate includes a display area and a pad area arranged outside the display area. The first connection line is arranged on the pad area of ​​the display substrate. The signal line is arranged on the first connection line of the pad area of ​​the display substrate. The signal line is electrically connected to the first connection line through a first contact hole. The signal line includes at least one first opening at least partially surrounded by the signal line in a plan view. The first opening is arranged closer to the display area than the first contact hole.

[0010] According to some exemplary embodiments, a display device includes a display substrate, a connection line, a signal line, and a flexible circuit board. The display substrate includes a display area and a pad area arranged outside the display area. The connection line is arranged on the pad area of ​​the display substrate. The signal line is arranged on the connection line of the pad area of ​​the display substrate. The signal line is electrically connected to the connection line through a contact hole. The flexible circuit board is attached to the pad area of ​​the display substrate. The flexible circuit board includes a lead overlapping the signal line. The signal line includes a first opening at least partially surrounded by the signal line in a plan view. The connection line includes a second opening at least partially surrounded by the connection line in a plan view and overlapping the first opening in a thickness direction. The first opening and the second opening are arranged closer to the display area than the contact hole.

[0011] Both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings are included to provide a further understanding of the inventive concept and are incorporated in and constitute a part of this specification, and illustrate exemplary embodiments of the inventive concept and together with the description serve to explain the principles of the inventive concept. In the drawings:

[0013] Figure 1 is a plan layout diagram of a display device according to some exemplary embodiments;

[0014] Figure 2 According to some exemplary embodiments Figure 1 A partial cross-sectional view of a display device;

[0015] Figure 3 is a plan layout diagram of a panel pad region and a first circuit board of a display panel according to some exemplary embodiments;

[0016] Figure 4 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some exemplary embodiments;

[0017] Figure 5 According to some exemplary embodiments Figure 4 An enlarged plan view of

[0018] Figure 6 According to some exemplary embodiments, Figure 5 A cross-sectional view taken along section line VI-VI';

[0019] Figure 7 According to some exemplary embodiments, Figure 5 A cross-sectional view taken along section line VII-VII';

[0020] Figure 8 According to some exemplary embodiments, Figure 5 A cross-sectional view taken along section line VIII-VIII';

[0021] Fig. 9 is a conceptual diagram illustrating a case where an external signal is input and output through a lead line, a signal line, and a connection line according to some exemplary embodiments;

[0022] Fig.10 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some exemplary embodiments;

[0023] Fig.11 According to some exemplary embodiments Fig.10 sectional view of

[0024] Fig.12 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some exemplary embodiments;

[0025] Fig.13 According to some exemplary embodiments Fig.12 sectional view of

[0026] Fig.14 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some exemplary embodiments;

[0027] Fig.15 According to some exemplary embodiments Fig.14 sectional view of

[0028] Fig.16 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some exemplary embodiments;

[0029] Fig.17 According to some exemplary embodiments Fig.16 sectional view of

[0030] Fig.18 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some exemplary embodiments;

[0031] 19(a), 19(b) and 19(c) are cross-sectional views of a panel pad region of a display device according to various exemplary embodiments;

[0032] Fig. 20 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some exemplary embodiments;

[0033] Fig.21 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some exemplary embodiments;

[0034] Fig. 22 is a plan layout diagram of a display device according to some exemplary embodiments; and

[0035] Fig.23 is a cross-sectional view of a display device according to some example embodiments. DETAILED DESCRIPTION

[0036] In the following description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of various exemplary embodiments. As used herein, the terms "embodiment" and "implementation" are used interchangeably and are non-limiting examples of one or more of the inventive concepts disclosed herein. However, it is apparent that various exemplary embodiments may be practiced without specific details or with one or more equivalent arrangements. In other examples, known structures and devices are shown in block diagram form to avoid unnecessary confusion of various exemplary embodiments. In addition, various exemplary embodiments may be different, but not necessarily exclusive. For example, without departing from the inventive concept, the specific shape, configuration and characteristics of the exemplary embodiment may be used or implemented in another exemplary embodiment.

[0037] Unless otherwise specified, the exemplary embodiments shown should be understood as providing exemplary features of different details of some exemplary embodiments. Therefore, unless otherwise specified, the various described features, components, modules, layers, films, panels, regions, aspects, etc. (hereinafter individually or collectively referred to as "elements" or "elements") may be combined, separated, interchanged and / or rearranged in other ways without departing from the concept of the present invention.

[0038] The use of cross hatching and / or shadows in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross hatching or shadows will not convey or indicate any preference or requirement for a specific material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, performances, etc. of the elements. In addition, in the drawings, for the purpose of clarity and / or description, the size and relative size of the elements may be exaggerated. Thus, the size and relative size of each element are not necessarily limited to the size and relative size shown in the figures. When the exemplary embodiment can be implemented in different ways, the specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously or in an order opposite to the described order. In addition, similar reference numerals represent similar elements.

[0039] When an element (e.g., a layer) is referred to as being "on," "connected to," or "coupled to" another element, the element may be directly on, connected to, or coupled to another element, or there may be intermediate elements. However, when an element is referred to as being "directly" "on," "directly connected to," or "directly coupled to" another element, there are no intermediate elements. Other words and / or phrases used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between" versus "directly between," "adjacent" versus "directly adjacent," "on" versus "directly on," etc.). In addition, the wording "connected" may refer to a physical connection, an electrical connection, and / or a fluid connection. In addition, the DR1-axis, DR2-axis, and DR3-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted as having a broader meaning. For example, the DR1-axis, DR2-axis, and DR3-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0040] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0041] Spatially relative terms such as "beneath," "below," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein for descriptive purposes, and thus, to describe the relationship of one element to another element as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the figures. For example, if the device in the figures is turned over, elements described as being "below" or "beneath" other elements or features would subsequently be oriented to be "above" the other elements or features. Thus, the exemplary term "below" may include both orientations of above and below. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatially relative descriptors used herein are interpreted accordingly.

[0042] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" as used herein are also intended to include the plural forms. In addition, when the words "comprise", "comprising", "include" and / or "including" are used in this specification, the existence of the stated features, integers, steps, operations, elements, parts and / or clusters thereof is indicated, but the existence or addition of one or more other features, integers, steps, operations, elements, parts and / or clusters thereof is not excluded. It is also noted that, as used herein, the words "substantially", "about" and similar words are used as approximate words rather than words of degree, and thus, are used to take into account the inherent deviations of measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0043] Various exemplary embodiments are described herein with reference to cross-sectional views, isometric views, perspective views, plan views, and / or exploded views that are schematic illustrations of idealized exemplary embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations resulting from, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the exemplary embodiments disclosed herein should not be construed as limited to the specific illustrated shapes of the regions, but rather include deviations in shape resulting from, for example, manufacturing. To this end, the regions shown in the figures may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and are thus not intended to be limiting.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. Unless explicitly defined as such herein, terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and will not be interpreted in an idealized or overly formal sense.

[0045] As is customary in the art, in terms of functional blocks, units and / or modules, some exemplary embodiments are shown and described in the accompanying drawings. It will be appreciated by those skilled in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connections, etc. that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques). In the case of blocks, units and / or modules implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and can be selectively driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware and processors (e.g., one or more programmed microprocessors and associated circuits) that perform some functions to perform other functions. Moreover, without departing from the concept of the present invention, each block, unit and / or module of some exemplary embodiments can be physically separated into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some exemplary embodiments may be physically combined into more complex blocks, units and / or modules without departing from the concept of the present invention.

[0046] Hereinafter, various exemplary embodiments will be explained in detail with reference to the accompanying drawings.

[0047] Figure 1 is a plan layout diagram of a display device according to some example embodiments. Figure 2 According to some exemplary embodiments Figure 1 A partial cross-sectional view of a display device. Figure 3 is a plan layout diagram of a panel pad region of a display panel and a first circuit board according to some example embodiments. Figure 4 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some example embodiments. Figure 5 According to some exemplary embodiments Figure 4 Enlarged floor plan. Figure 6 According to some exemplary embodiments, Figure 5 A cross-sectional view taken along section line VI-VI'. Figure 7According to some exemplary embodiments, Figure 5 A cross-sectional view taken along section line VII-VII'. Figure 8 According to some exemplary embodiments, Figure 5 A cross-sectional view taken along section line VIII-VIII'. Fig. 9 is a conceptual diagram illustrating a case where an external signal is input and output through a lead line, a signal line, and a connection line according to some exemplary embodiments.

[0048] The display device 1 is a device for displaying moving images (e.g., video images) or still images, and can be used as a display screen for various products such as televisions, laptop computers, monitors, billboards, Internet of Things (IOT) devices, and portable electronic devices such as mobile phones, smartphones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebook computers, e-books, portable multimedia players (PMPs), navigation units, and ultra-mobile PCs.

[0049] Reference Figures 1 to 9 , the display device 1 may include a display panel 100 for displaying an image, a first circuit board 300 connected to the display panel 100 , and a second circuit board 500 connected to the first circuit board 300 .

[0050] As the display panel 100, for example, an organic light-emitting display panel may be applied. For the convenience of description and illustration, the exemplary embodiment will be described herein in association with the case where the organic light-emitting display panel is applied as the display panel 100, but the exemplary embodiment is not limited thereto. For example, various display panels such as a liquid crystal display panel (LCD), a quantum dot organic light-emitting display panel (QD-OLED), a quantum dot liquid crystal display panel (QD-LCD), a quantum nano-emission display panel (QNED), a micro LED, etc. may be applied.

[0051] The display panel 100 includes a display area DA including a plurality of pixel areas and a non-display area NA disposed outside (eg, around) the display area DA. A plurality of thin film transistors (TFTs) may be arranged in the display area DA.

[0052] The display area DA may have a rectangular shape having sharp or rounded corners. The display area DA may have short sides and long sides. The short sides of the display area DA may be sides extending in the first direction DR1. The long sides of the display area DA may be sides extending in the second direction DR2. However, it is contemplated that the planar shape of the display area DA is not limited to a rectangular shape, and may be any suitable shape, such as a circle, an ellipse, or any other suitable shape. The non-display area NA may be arranged adjacent to two short sides and two long sides of the display area DA. In this case, the non-display area NDA may surround all sides of the display area DA, and may constitute a frame of the display area DA. However, it should be noted that exemplary embodiments are not limited thereto. For example, the non-display area NA may be arranged adjacent to only two short sides or two long sides of the display area DA, or in any other suitable layout.

[0053] The non-display area NA of the display panel 100 includes a panel pad area P_PA. The panel pad area P_PA may be arranged, for example, along (or around) one short side of the display area DA. However, exemplary embodiments are not limited thereto. For example, the panel pad area P_PA may be arranged along two short sides of the display area DA, or may be arranged along two short sides and two long sides of the display area DA.

[0054] The first circuit board 300 may include a printed base film 310 and a driving integrated circuit 390 disposed on the printed base film 310. The printed base film 310 may include an insulating material.

[0055] The first circuit board 300 may include one or more circuit areas CA, such as a first circuit area CA1 whose one side is attached to the panel pad area P_PA of the display panel 100, a second circuit area CA2 arranged at one side in the second direction DR2 of the first circuit area CA1, and a third circuit area CA3 arranged at one side in the second direction DR2 of the second circuit area CA2 and attached to the second circuit board 500. The driving integrated circuit 390 may be arranged on one surface of the second circuit area CA2 of the first circuit board 300. The driving integrated circuit 390 may be, for example, a data driving integrated circuit, and a chip on film (COF) implemented by a data driving chip may be applied as the driving integrated circuit 390.

[0056] The second circuit board 500 may include a circuit pad area attached to the third circuit area CA3 of the first circuit board 300. A plurality of circuit pads in the circuit pad area of ​​the second circuit board 500 may be arranged to be connected to leads arranged in the third circuit area CA3 of the first circuit board 300.

[0057] Reference Figure 2, the display device 1 also includes a panel lower sheet 200 arranged below the display panel 100. The panel lower sheet 200 may be attached to the back surface of the display panel 100. The panel lower sheet 200 includes at least one functional layer. The functional layer may be a layer that performs at least one of a heat dissipation function, an electromagnetic wave blocking function, a grounding function, a buffering function, a strength enhancement function, a support function, and a digitization function. The functional layer may be at least one of a sheet layer, a film layer, a thin film layer, a coating, a panel, and a board. A functional layer may be formed as a single layer, but may also be formed as a plurality of stacked films or coatings. The functional layer may be, for example, a supporting substrate, a heat dissipation layer, an electromagnetic wave blocking layer, an impact absorbing layer, and / or a digital converter, etc.

[0058] like Figure 2 As shown in FIG. 1 , the first circuit board 300 may be bent downward in the third direction DR3. The other side of the first circuit board 300 and the second circuit board 500 may be located below the panel lower sheet 200. The lower surface of the panel lower sheet 200 may be attached to the second circuit board 500 by an adhesive layer, but exemplary embodiments are not limited thereto.

[0059] The display panel 100 may include a display substrate 101 , a plurality of conductive layers, a plurality of insulating layers insulating the plurality of conductive layers, and an organic layer EL.

[0060] The display substrate 101 may be arranged over the entire display area DA and the non-display area NA. The display substrate 101 may be used to support a plurality of overlying elements. In some exemplary embodiments, the display substrate 101 may be a rigid substrate including a rigid material such as glass, soft glass, quartz, etc. However, exemplary embodiments are not limited thereto. For example, the display substrate 101 may be a flexible substrate including a flexible material such as polyimide (PI).

[0061] A buffer layer 102 may be disposed on the display substrate 101. The buffer layer 102 may prevent (or at least reduce) the penetration of moisture and / or oxygen from the outside through the display substrate 101. The buffer layer 102 may include silicon nitride (SiN x ) film, silicon oxide (SiO 2 ) film and silicon oxynitride (SiO x N y ) membrane.

[0062] A semiconductor layer 105 may be disposed on the buffer layer 102. The semiconductor layer 105 forms a channel of the thin film transistor TFT. The semiconductor layer 105 may be disposed in each pixel in the display area DA, and in some cases, may also be disposed in the non-display area NA. The semiconductor layer 105 may include a source / drain region and an active region. The semiconductor layer 105 may include, for example, polysilicon.

[0063] A first insulating layer 111 may be disposed on the semiconductor layer 105. The first insulating layer 111 may be disposed over the entire surface of the display substrate 101. The first insulating layer 111 may be a gate insulating film having a gate insulating function. The first insulating layer 111 may include a silicon compound or a metal oxide. For example, the first insulating layer 111 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, and titanium oxide. These compounds may be used alone, or at least some of the above compounds may be used in combination with each other.

[0064] A first conductive layer 120 may be disposed on the first insulating layer 111. The first conductive layer 120 may include a gate electrode GE of a thin film transistor TFT, a first electrode CE1 of a storage capacitor Cst, and a connection line SL. The connection line SL may be disposed above the display area DA and the panel pad area P_PA. The connection line SL may be connected to the thin film transistor TFT disposed in the display area DA. That is, a signal line described later may be electrically connected to the thin film transistor TFT through the connection line SL.

[0065] The first conductive layer 120 may include at least one metal selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), or an alloy of at least one of the above materials. The first conductive layer 120 may be a single-layer film or a stacked film (e.g., multilayer) made of at least one of the above materials.

[0066] The second insulating layers 112a and 112b may be disposed on the first conductive layer 120. The second insulating layers 112a and 112b may insulate the first conductive layer 120 from the second conductive layer 130. The second insulating layer 112a may be substantially disposed in the display area DA, and the second insulating layer 112b may be substantially disposed in the panel pad area P_PA. The second insulating layers 112a and 112b may include a material selected from the exemplified materials of the first insulating layer 111. In the panel pad area P_PA, the second insulating layer 112b may include a plurality of contact holes CNT partially exposing the connection line SL. Although in Figure 2 2 shows that the second insulating layer 112b includes three contact holes CNT, but exemplary embodiments are not limited thereto. For example, the second insulating layer 112b may include two or less contact holes CNT or four or more contact holes CNT.

[0067] Materials included in the buffer layer 102, the first insulating layer 111, and the second insulating layers 112a and 112b may be optically transparent. As will be discussed in more detail later, the buffer layer 102, the first insulating layer 111, and the second insulating layers 112a and 112b may be stacked on the window portion of the panel pad area P_PA.

[0068] The second conductive layer 130 may be disposed on the second insulating layers 112a and 112b. The second conductive layer 130 may include a second electrode CE2 of the storage capacitor Cst. The material of the second conductive layer 130 may be selected from the example materials of the first conductive layer 120. The first electrode CE1 of the storage capacitor Cst and the second electrode CE2 of the storage capacitor Cst may form a capacitor through (or with) the second insulating layer 112a and the second insulating layer 112b.

[0069] A third insulating layer 113 may be disposed on the second conductive layer 130. The third insulating layer 113 may include at least one of the materials exemplified in the first insulating layer 111. In some exemplary embodiments, the third insulating layer 113 may include an organic insulating material. The organic insulating material may be selected from the materials exemplified in the first via layer VIA1 to be described later.

[0070] A third conductive layer 140 may be arranged on the third insulating layer 113. The third conductive layer 140 may include a source electrode SE, a drain electrode DE, a high potential voltage electrode ELVDDE, and a signal line PAD. The third conductive layer 140 may include at least one metal selected from a cluster consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), or an alloy containing at least one of the above metal materials. The third conductive layer 140 may be a single-layer film made of the materials exemplified above, however, exemplary embodiments are not limited thereto. For example, the third conductive layer 140 may be a stacked film. For example, the third conductive layer 140 may have a stacked structure of Ti / Al / Ti, Mo / Al / Mo, Mo / AlGe / Mo, or Ti / Cu.

[0071] The signal line PAD of the third conductive layer 140 may be arranged to overlap the connection line SL of the first conductive layer 120 in the thickness direction (eg, in the third direction DR3 ) and may be electrically connected to the connection line SL through the contact hole CNT of (or in) the second insulating layer 112 b .

[0072] A first via layer VIA1 may be disposed on the third conductive layer 140. The first via layer VIA1 may include an organic insulating material. The organic insulating material may include at least one of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene (BCB).

[0073] The upper structure of the third insulating layer 113 and the third conductive layer 140 may be removed or omitted in a portion of (or associated with) the signal line PAD on the panel pad area P_PA. In this way, the omitted or removed structure may expose the signal line PAD arranged in the panel pad area P_PA, and the upper surface of the exposed signal line PAD may be coupled to the lead LE of the first circuit board 300.

[0074] The first circuit board 300 further includes a lead LE located on one surface of the first circuit area CA1 of the printed base film 310 and a circuit lead C_LE located on one surface of the third circuit area CA3 of the printed base film 310. The lead LE is connected to the signal line PAD. In some exemplary embodiments, the lead LE may be directly connected to the upper surface of the exposed signal line PAD. For example, the lead LE may be ultrasonically bonded to the signal line PAD.

[0075] Each of the lead LE and the circuit lead C_LE may include a metal material. The material included in each of the lead LE and the circuit lead C_LE may be at least one selected from the group consisting of molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W) and copper (Cu) or an alloy of at least one of the above metal materials.

[0076] Ultrasonic bonding may be performed by an ultrasonic device 700. The ultrasonic device 700 may include a vibration generating unit 710, a vibration unit 720 connected to the vibration generating unit 710, a pressing unit 730 amplifying the amplitude of the vibration unit 720, a vibration transmitting unit 740 connected to the vibration unit 720, and a supporting unit 750 supporting at least the vibration unit 720.

[0077] The vibration generating unit 710 may convert electrical energy into vibration energy. The vibration unit 720 may vibrate with the vibration energy converted by the vibration generating unit 710. The vibration unit 720 may vibrate in a predetermined vibration direction and a predetermined amplitude. The vibration unit 720 may amplify the amplitude in a direction parallel to the vibration direction by a pressing unit 730 connected to the vibration unit 720. The vibration transmitting unit 740 may transmit the vibration of the vibration unit 720 to the ultrasonic bonding target. The supporting unit 750 may fix the upper and lower surfaces of the vibration unit 720 to prevent the vibration unit 720 and the vibration transmitting unit 740 from moving up and down due to vibration.

[0078] In the case of contacting with the other surface of the first circuit board 300, the ultrasonic device 700 is configured so that the vibration transfer unit 740 effectively transfers vibration to the first circuit board 300 while maintaining the constant pressurized state of the first circuit board 300. In this case, as Figure 2 As shown in , the vibration transfer unit 740 of the ultrasonic device 700 may perform ultrasonic bonding while overlapping the entire area (or, a substantial area) of the first circuit board 300 .

[0079] The ultrasonic device 700 may cause the lead LE to vibrate in a predetermined vibration direction when vibrating in the vibration direction. However, in this case, the signal line PAD may vibrate slightly in the vibration direction due to the vibration transmitted through the lead LE, but its vibration width may be ignored. Therefore, the vibration width of the vibration transfer unit 740 in the vibration direction may be considered to be substantially the same as the distance that the lead LE has moved (or moved) in the vibration direction on the signal line PAD. The vibration direction may be in the second direction DR2. That is, the vibration direction may be the direction in which the long sides of the signal line PAD and the lead LE extend.

[0080] When the lead LE is ultrasonically vibrated on one surface of the signal line PAD, a predetermined friction force is generated at the interface between one surface of the signal line PAD and one surface of the lead LE, and friction heat may be generated due to the friction force. When the friction heat is sufficient to melt at least some of the materials constituting the signal line PAD and the lead LE, the pad melting area PADb of the signal line PAD adjacent to the lead LE and the lead melting area LEb of the lead LE adjacent to the signal line PAD may melt. That is, the signal line PAD may include a pad non-melting area PADa and a pad melting area PADb. In addition, the lead LE may include a lead non-melting area LEa and a lead melting area LEb.

[0081] The pad non-melting region PADa may be a region including only a material included in the signal line PAD, and the lead non-melting region LEa may be a region including only a material included in the lead LE.

[0082] The pad melting area PADb may be an area in which the material included in the lead LE is diffused, and thus, the material of the signal line PAD and the material of the lead LE are mixed with each other, and the lead melting area LEb may be an area in which the material included in the signal line PAD is diffused, and thus, the material of the lead LE and the material of the signal line PAD are mixed with each other.

[0083] In the pad melting region PADb and the lead melting region LEb, the signal line PAD and the lead LE may be coupled to each other by solidification. An interface between the signal line PAD and the lead LE (ie, an interface between the pad melting region PADb and the lead melting region LEb) may have a non-flat shape.

[0084] According to some exemplary embodiments, the panel pad area P_PA may further include a window portion. As will be described later, the window portion indicates an area where openings of the signal line PAD and the connection line SL are arranged. The first circuit board 300 is attached to the panel pad area P_PA of the display panel 100 by the above-mentioned ultrasonic bonding process, and an area for checking the attachment state is provided.

[0085] The window portion of the panel pad area P_PA is an area where the connection line SL and the signal line PAD are not arranged and an optically transparent insulating layer is stacked, and the peripheral area of ​​the planar portion of the signal line PAD of the panel pad area P_PA except the window portion may be an area stacked with the connection line SL, the second insulating layer 112b and the signal line PAD. Therefore, the area around the window portion of the planar portion of the signal line PAD may have a step portion protruding in the thickness direction of the window portion. During the ultrasonic process of the signal line PAD and the lead LE, the step portion may cause cracks in the lead LE. These cracks may be a factor that interferes with the external signal smoothly transmitted through the lead LE. The details will be described later.

[0086] A fourth conductive layer 150 may be disposed on the first via layer VIA1. The fourth conductive layer 150 may include a data line DL, a connection electrode CNE, and a high potential voltage line ELVDDL. The data line DL may be electrically connected to the source electrode SE of the thin film transistor TFT through a contact hole penetrating the first via layer VIA1. The connection electrode CNE may be electrically connected to the drain electrode DE of the thin film transistor TFT through a contact hole penetrating the first via layer VIA1. The high potential voltage line ELVDDL may be electrically connected to the high potential voltage electrode ELVDDE through a contact hole penetrating the first via layer VIA1. The fourth conductive layer 150 may include a material selected from the exemplified materials of the third conductive layer 140.

[0087] A second via layer VIA2 is disposed on the fourth conductive layer 150. The second via layer VIA2 may include at least one of the exemplified materials of the first via layer VIA1.

[0088] An anode ANO is disposed on the second via layer VIA2 and can be connected to the connection electrode CNE through a contact hole penetrating the second via layer VIA2.

[0089] A bank layer BANK may be arranged on the anode ANO. The bank layer BANK may include a contact hole exposing the anode ANO. The bank layer BANK may include an organic insulating material or an inorganic insulating material. For example, the bank layer BANK may include at least one of a photoresist, a polyimide resin, an acrylic resin, a silicon compound, and a polyacrylic resin.

[0090] An organic layer EL may be disposed on the upper surface of the anode ANO and in the opening of the bank layer BANK. A cathode CAT may be disposed on the organic layer EL and the bank layer BANK. The cathode CAT may be a common electrode disposed above a plurality of pixels.

[0091] A thin film encapsulation layer 170 is arranged on the cathode CAT. The thin film encapsulation layer 170 may cover the organic light emitting element OLED, which may include an anode ANO, an organic layer EL, and a cathode CAT. The thin film encapsulation layer 170 may be a laminated film in which one or more inorganic films and one or more organic films are alternately laminated. For example, the thin film encapsulation layer 170 may include a first encapsulation inorganic film 171, an encapsulation organic film 172, and a second encapsulation inorganic film 173 that are sequentially laminated.

[0092] According to some exemplary embodiments, the stacking structure and shape of the connection line SL and the signal line PAD in the panel pad area P_PA may be deformed. For example, in some exemplary embodiments, the connection line SL may include a plurality of patterns, and considering the step portion of the pattern of the connection line SL, the signal line PAD arranged on the connection line SL may have surface unevenness.

[0093] In some exemplary embodiments, an auxiliary signal line of the second conductive layer 130 may be further arranged between the connection line SL and the signal line PAD. In this case, the plane size of the auxiliary signal line may be smaller than the plane size of the signal line PAD. The signal line PAD, the auxiliary signal line, and the connection line SL may overlap each other in the thickness direction and may be electrically connected to each other. In addition, in some exemplary embodiments, the connection line SL may be composed of the second conductive layer 130, and the signal line PAD may be composed of the fourth conductive layer 150.

[0094] Reference Figure 3 , a plurality of signal lines PAD may be arranged in a first direction DR1. The plurality of signal lines PAD may include, for example, a power pad, a data pad, and a panel dummy pad. The second direction DR2 may be a direction from an end of the panel pad area P_PA toward the display area DA. The first direction DR1 refers to a direction intersecting with the second direction DR2.

[0095] For example, when viewed in the third direction DR3, the signal line PAD may be substantially rectangular in a plan view. As will be described later, the signal line PAD may be provided with an opening therein. The signal line PAD may be used to output an external signal applied through the lead line LE to the thin film transistor TFT of the display area DA.

[0096] A plurality of leads LE may be arranged in the first circuit region CA1 and may be arranged in the first direction DR1. The plurality of leads LE may include a power lead, a data lead, and a dummy lead. The planar shape of the lead LE may be a rectangular shape. The lead LE may be used to transmit an external signal applied from the driving integrated circuit 390 to the signal line PAD.

[0097] Reference Figure 4 , a plurality of signal lines PAD may be connected to a plurality of lead lines LE. For example, the signal line PAD may be directly connected to the lead line LE, and the signal line PAD and the lead line LE may be ultrasonically bonded to each other. Figure 4 The first circuit area CA1 is attached to Figure 3 The lead line LE may be arranged to substantially overlap with the signal line PAD in the thickness direction. However, as will become more clear below, the lead line LE may be arranged to not overlap with the opening of the signal line PAD in the thickness direction.

[0098] Reference Figures 5 to 9 , in the plane of the signal line PAD, the signal line PAD in the panel pad area P_PA may include a window portion WR, first to fourth bonding portions BR1 to BR4 arranged around the window portion WR, and first and second crack portions CRK1 and CRK2 arranged in the window portion WR and the first to fourth bonding portions BR1 to BR4. As described above, the window portion WR may be a region for checking the attachment state after the ultrasonic bonding process of the lead LE of the first circuit board 300 and the signal line PAD of the panel pad area P_PA of the display panel 100, the first to fourth bonding portions BR1 to BR4 may be a region where the signal line PAD is directly connected to the lead LE, and the crack portions CRK1 and CRK2 may be a region where cracks are generated in the lead LE.

[0099] In a plan view, the window portion WR of the panel pad area P_PA may be arranged between the signal line PAD and the connection line SL. Figure 5As shown in , the planar shape of the window WR may be a rectangle. In some exemplary embodiments, the planar shape of the window WR may be a square, a circle, an ellipse or other suitable polygons. Hereinafter, the case where a rectangle is applied to (or is) the planar shape of the window WR will be mainly described. The window WR may include a long side extending in the second direction DR2 and a short side extending in the first direction DR1. The window WR may be provided with a first opening OP1 for the signal line PAD and a second opening OP2 for the connection line SL. The planar shape of each of the first opening OP1 and the second opening OP2 may be substantially the same as the planar shape of the panel pad area P_PA, however, exemplary embodiments are not limited thereto.

[0100] Reference Figure 5 and Figure 6 In the window portion WR, the display substrate 101, the optically transparent insulating layers 102, 111, and 112b, and the lead LE are stacked, and in the area around the window portion WR of the signal line PAD, the buffer layer 102, the first insulating layer 111, the connection line SL, the second insulating layer 112b, the signal line PAD, and the lead LE may be stacked. Thus, a step portion appears between the window portion WR and the area of ​​the signal line PAD around the window portion WR. At least partially due to the step portion, crack portions CRK1 and CRK2 may be formed in the lead LE.

[0101] like Figure 5 As shown in FIG. 1 , the first crack portion CRK1 and the second crack portion CRK2 of the panel pad area P_PA may be formed along the long side of the window portion WR. The first crack portion CRK1 may be arranged closer to the display area DA than the second crack portion CRK2. In a plan view, the first crack portion CRK1 and the second crack portion CRK2 may have a shape intersecting the long side of the lead line LE. As shown in FIG. Figure 2 As described, since the vibration direction of the ultrasonic device 700 is the direction in which the long sides of the signal line PAD and the lead LE extend, cracks may be formed around the window portion WR due to the lower step portion of the lead LE during the ultrasonic bonding process, and during the ultrasonic bonding process and / or when the display device 1 is used, the formed cracks gradually develop along the extension direction of the long sides of the window portion WR to have a shape that intersects (for example, completely intersects) the long sides of the lead LE.

[0102] In the plane portion of the signal line PAD of the panel pad area P_PA, the portion other than the window portion WR and the first crack portion CRK1 and the second crack portion CRK2 may be the first bonding portion BR1 to the fourth bonding portion BR4. The first bonding portion BR1 may be located at the upper end of the first crack portion CRK1 in the plan view, the second bonding portion BR2 may be located at the left end of the window portion WR in the plan view, the third bonding portion BR3 may be located at the right end of the window portion WR in the plan view, and the fourth bonding portion BR4 may be located at the lower end of the second crack portion CRK2 in the plan view. A plurality of contact holes CNT of the second insulating layer 112b may be arranged in the fourth bonding portion BR4.

[0103] As described above, the connection line SL may be arranged above the panel pad area P_PA and the display area DA. The connection line SL may have a shape whose width increases in the first direction DR1 in the area overlapping with the signal line PAD of the panel pad area P_PA. The connection line SL may be arranged in the first to fourth bonding portions BR1 to BR4 and the first and second crack portions CRK1 and CRK2 of the panel pad area P_PA.

[0104] The connection line SL may include a second opening OP2 at least surrounded by the connection line SL. The second opening OP2 may include a second through hole completely surrounded by the connection line SL and penetrating the connection line SL from the surface of the connection line SL. The connection line SL may be arranged in a first crack portion CRK1 located at the upper end of the window portion WR in a plan view, a first joint portion BR1, a second crack portion CRK2 located at the lower end of the window portion WR in a plan view, a fourth joint portion BR4, a second joint portion BR2 located at the left end of the window portion WR in a plan view, and a third joint portion BR3 located at the right end of the window portion WR in a plan view.

[0105] The width of the connection line SL in the first joint portion BR1, the first crack portion CRK1, the fourth joint portion BR4, and the second crack portion CRK2 in the first direction DR1 may be greater than the width of the connection line SL in the second joint portion BR2 and the third joint portion BR3 in the first direction DR1. Figure 5 As shown in , the connection line SL may be integrally formed in a plan view.

[0106] The signal line PAD may be arranged on the connection line SL, and the width of the signal line PAD in the first direction DR1 in the plan view may be greater than the width of the connection line SL in the first direction DR1 in the plan view. The signal line PAD may be arranged in the first to fourth bonding portions BR1 to BR4 and the first and second crack portions CRK1 and CRK2 of the panel pad area P_PA.

[0107] The signal line PAD may include a first opening OP1 at least surrounded by the signal line PAD. The first opening OP1 may include a first through hole that is completely surrounded by the signal line PAD and penetrates the signal line PAD from the surface of the signal line PAD. The first opening OP1 may be arranged to overlap with the second opening OP2 of the connection line SL. The signal line PAD may be arranged in a first crack portion CRK1 located at the upper end of the window portion WR in a plan view, a first joint portion BR1, a second crack portion CRK2 located at the lower end of the window portion WR in a plan view, a fourth joint portion BR4, a second joint portion BR2 located at the left end of the window portion WR in a plan view, and a third joint portion BR3 located at the right end of the window portion WR in a plan view.

[0108] The width of the signal line PAD in the first joint portion BR1, the first crack portion CRK1, the fourth joint portion BR4, and the second crack portion CRK2 in the first direction DR1 may be greater than the width of the signal line PAD in the first direction DR1 in the second joint portion BR2 and the third joint portion BR3. Similar to the connection line SL, the signal line PAD may be formed integrally in a plan view. The signal line PAD may be connected to the connection line SL through the contact hole CNT of the second insulating layer 112b in the fourth joint portion BR4.

[0109] The lead LE may be arranged on the window portion WR on the signal line PAD and on the first bonding portion BR1 to the fourth bonding portion BR4. The lead LE may include a plurality of lead patterns LP1 to LP5. The plurality of lead patterns LP1 to LP5 may include a first lead pattern LP1, a second lead pattern LP2, a third lead pattern LP3, a fourth lead pattern LP4, and a fifth lead pattern LP5. That is, the first lead pattern LP1 may be arranged on the first bonding portion BR1, the second lead pattern LP2 may be arranged on the second bonding portion BR2, the third lead pattern LP3 may be arranged on the third bonding portion BR3, the fourth lead pattern LP4 may be arranged on the fourth bonding portion BR4, and the fifth lead pattern LP5 may be arranged on the window portion WR.

[0110] The first crack portion CRK1 may be arranged between the first lead pattern LP1 and the second lead pattern LP2 and between the third lead pattern LP3 and the fifth lead pattern LP5. The second crack portion CRK2 may be arranged between the second lead pattern LP2 and the third lead pattern LP3 and between the fifth lead pattern LP5 and the fourth lead pattern LP4. The first crack portion CRK1 and the second crack portion CRK2 of the panel pad area P_PA may be an area where the lead LE is not arranged to completely penetrate the surface of the lead LE in the thickness direction. That is, the first lead pattern LP1 may be arranged to be separated from the second lead pattern LP2, the third lead pattern LP3 and the fifth lead pattern LP5, with the first crack portion CRK1 located therebetween; and the fourth lead pattern LP4 may be arranged to be separated from the second lead pattern LP2, the third lead pattern LP3 and the fifth lead pattern LP5, with the second crack portion CRK2 located therebetween. On the other hand, the second lead pattern LP2 and the fifth lead pattern LP5 may be connected to each other, and the third lead pattern LP3 and the fifth lead pattern LP5 may be connected to each other.

[0111] For each region, the lead line LE may have different thicknesses. The first to fourth lead patterns LP1 to LP4 of the lead line LE have substantially the same or similar thicknesses, and the fifth lead pattern LP5 of the lead line LE may have a thickness greater than that of each of the first to fourth lead patterns LP1 to LP4. For example, referring to Figure 6 , the first lead pattern LP1 may have a first thickness t1, the fourth lead pattern LP4 may have a second thickness t2, and the fifth lead pattern LP5 may have a third thickness t3. The first thickness t1 and the second thickness t2 may be substantially the same or similar to each other, and each of the first thickness t1 and the second thickness t2 may be smaller than the third thickness t3. This phenomenon (or structure) is due to the fact that the first lead pattern LP1, the fourth lead pattern LP4, and the fifth lead pattern LP5 are formed by partially molten materials of the signal line PAD and the lead LE moving from the first bonding portion BR1 to the fourth bonding portion BR4 adjacent to the window portion WR to the window portion WR.

[0112] The fourth lead pattern LP4 may directly contact the second insulating layer 112b at least exposed through the first opening OP1. Figures 6 to 8 , the fourth lead pattern LP4 is shown not to contact the second insulating layer 112b and the inner side surface of the signal line PAD, but exemplary embodiments are not limited thereto. For example, the fourth lead pattern LP4 may contact the second insulating layer 112b and the inner side surface of the signal line PAD.

[0113] Refer again Figure 5, the window portion WR in which the first opening OP1 of the signal line PAD and the second opening OP2 of the connection line SL are arranged may be arranged close to the display area DA. That is, the window portion WR may be closer to the display area DA than the plurality of contact holes CNT of the second insulating layer 112b. Therefore, the external signal applied through the lead line LE may be transmitted to the signal line PAD.

[0114] Reference Fig. 9 , the external signal applied through the lead line LE (i.e., the fourth lead pattern LP4) may not be directly transmitted to the second lead pattern LP2, the third lead pattern LP3, and the fifth lead pattern LP5 through the second crack portion CRK2 arranged between the fourth lead pattern LP4 and the second lead pattern LP2, between the fourth lead pattern LP4 and the third lead pattern LP3, and between the fourth lead pattern LP4 and the fifth lead pattern LP5. That is, the external signal applied through the fourth lead pattern LP4 may be transmitted only to the signal line PAD connected to the surface below, without passing through the fourth lead pattern LP4 to the second lead pattern LP2, the third lead pattern LP3, and the fifth lead pattern LP5. The external signal transmitted to the signal line PAD below may be output to the display area DA through the contact hole CNT between the integrally formed signal line PAD and the connection line SL arranged below the signal line PAD.

[0115] like Fig. 9 As shown in, in some exemplary embodiments, the external signal applied to the fourth lead pattern LP4 may be applied to the second lead pattern LP2, the third lead pattern LP3, and the fifth lead pattern LP5 whose surfaces are connected to the signal line PAD, and may be output to the display area DA through the signal line PAD and the connecting line SL again, but the signal transmission time may be delayed compared to the path in which the external signal applied to the fourth lead pattern LP4 is output through the signal line PAD and the connecting line SL.

[0116] Since the signal transmission time tends to be inversely proportional to the surface connection area between the fourth lead pattern LP4 and the signal line PAD surface-connected to the fourth lead pattern LP4, as the area occupied by the fourth lead pattern LP4 in the lead LE increases, the transmission efficiency of the external signal through the lead LE and the signal line PAD can be increased.

[0117] That is, in the display device 1 according to some exemplary embodiments, the window portion WR (i.e., the first opening OP1 of the signal line PAD and the second opening OP2 of the connecting line SL) for physically separating the lead LE from the panel pad area P_PA can be formed to be closest to the display area DA, and therefore, relative to the other lead patterns LP1, LP2, LP3 and LP5, the area of ​​the fourth lead pattern LP4 physically separated from the adjacent lead patterns LP1, LP2, LP3 and LP5 can be the largest, thereby increasing the transmission efficiency of the external signal through the lead LE and the signal line PAD.

[0118] Hereinafter, a display device according to various exemplary embodiments will be described. In the following exemplary embodiments, components identical to those in the previously described exemplary embodiments will be designated by the same reference numerals, and descriptions thereof will be omitted or simplified.

[0119] Fig.10 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some example embodiments. Fig.11 According to some exemplary embodiments Fig.10 Cross-sectional view of .

[0120] Reference Fig.10 and Fig.11 According to some exemplary embodiments, the display device 2 and Figures 1 to 9 The display device 1 is different in that the connection line SL_1 includes a plurality of patterns. For example, in the display device 2 according to some exemplary embodiments, the connection line SL_1 may include a first sub-connection line SL_1a for connecting the signal line PAD with the thin film transistor TFT of the display area DA and a second sub-connection line SL_1b substantially overlapping the signal line PAD and the lead line LE.

[0121] The first sub-connection line SL_1a may connect the signal line PAD to the thin film transistor TFT of the display area DA. That is, the first sub-connection line SL_1a may be arranged above the panel pad area P_PA and the display area DA. According to some exemplary embodiments, the first sub-connection line SL_1a may be arranged on (or in) the same layer as the connection line SL, and may include at least one of the materials of the first conductive layer 120. However, the exemplary embodiments are not limited thereto. For example, according to some exemplary embodiments, the first sub-connection line SL_1a may be arranged on the third conductive layer 140, and may include at least one of the materials of the third conductive layer 140.

[0122] The first sub-link wire SL_1a may be electrically connected to the overlying signal wire PAD through the sub-contact hole CNT_1. The second insulating layer 112bb may also be provided with a sub-contact hole CNT_1 therein.

[0123] The window portion WR may be disposed between the sub contact hole CNT_1 and the contact hole CNT in a plan view.

[0124] The second sub-connection line SL_1b may be arranged in the fourth bonding portion BR4 of the panel pad area P_PA and may be arranged not to overlap with the window portion WR. Although the second sub-connection line SL_1b may be used to reduce the surface resistance of the signal line PAD of the panel pad area P_PA, unlike the connection line SL according to some exemplary embodiments, the second sub-connection line SL_1b may not directly transmit an external signal to the thin film transistor TFT of the display area DA.

[0125] Even in the display device 2 according to some exemplary embodiments, the window portion WR (i.e., the first opening OP1 of the signal line PAD) for physically separating the lead LE from the panel pad area P_PA may be formed to be closest to the display area DA, and therefore, relative to the other lead patterns LP1, LP2, LP3 and LP5, the area of ​​the fourth lead pattern LP4 physically separated from the adjacent lead patterns LP1, LP2, LP3 and LP5 may be the largest, thereby increasing the transmission efficiency of the external signal through the lead LE and the signal line PAD.

[0126] Fig.12 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some example embodiments. Fig.13 According to some exemplary embodiments Fig.12 Cross-sectional view of .

[0127] Reference Fig.12 and Fig.13 , the display device 3 according to some exemplary embodiments is different from the display device 1 in that a plurality of window portions WR_1 are provided. For example, the window portions WR_1 according to some exemplary embodiments may be arranged to be spaced apart from each other along the first direction DR1 in a plan view. Fig.12 , the window portions WR_1 are spaced apart from each other and have the same shape and area, but the exemplary embodiment is not limited thereto. For example, the window portions WR_1 may be spaced apart from each other and may have different shapes and areas from each other. Fig.12 FIG. 5 shows that the number of window portions WR_1 is two, but exemplary embodiments are not limited thereto. For example, the number of window portions WR_1 may be three or more.

[0128] The fifth bonding portion BR5 of the panel pad area P_PA may also be arranged at Fig.12 In the space between the window portion WR_1.

[0129] The connection line SL_2 may include the second openings OP2_1 corresponding to the window portions WR_1 spaced apart from each other. That is, the second openings OP2_1 of the connection line SL_2 may be arranged to be spaced apart from each other along the first direction DR1.

[0130] The signal line PAD_1 may include the first openings OP1_1 corresponding to the window portions WR_1 spaced apart from each other. That is, the first openings OP1_1 of the signal line PAD_1 may be arranged to be spaced apart from each other along the first direction DR1.

[0131] The lead LE_1 may further include a sixth lead pattern LP6 arranged in the fifth bonding portion BR5 of the panel pad area P_PA. The sixth lead pattern LP6 may be physically connected to the fifth lead pattern LP5_1 arranged in the adjacent window portion WR_1. The thickness of the sixth lead pattern LP6 may be less than the thickness of the adjacent fifth lead pattern LP5_1. The sixth lead pattern LP6 may contact the signal line PAD_1 in the fifth bonding portion BR5, and the sixth lead pattern LP6 and the signal line PAD_1 may be ultrasonically bonded to each other.

[0132] In the display device 3 according to some exemplary embodiments, the window portions WR_1 are arranged to be spaced apart from each other, and thus, the width of the above-mentioned step portion of the panel pad area P_PA may be significantly reduced.

[0133] Even in the display device 3 according to some exemplary embodiments, the window portion WR_1 (i.e., the first opening OP1_1 of the signal line PAD_1) for physically separating the lead LE_1 from the panel pad area P_PA may be formed to be closest to the display area DA, and therefore, relative to the other lead patterns LP1, LP2, LP3, LP5_1 and LP6, the area of ​​the fourth lead pattern LP4 physically separated from the adjacent lead patterns LP1, LP2, LP3, LP5_1 and LP6 may be the largest, thereby increasing the transmission efficiency of the external signal through the lead LE_1 and the signal line PAD_1.

[0134] Fig.14 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some example embodiments. Fig.15 According to some exemplary embodiments Fig.14 Cross-sectional view of .

[0135] Reference Fig.14 and Fig.15 According to some exemplary embodiments, the display device 4 and Fig.12 and Fig.13The display device 3 of the embodiment of the present invention is different in that the plurality of window portions WR_2 are arranged to be spaced apart from each other along the second direction DR2. For example, the window portions WR_2 according to some exemplary embodiments may be arranged to be spaced apart from each other along the second direction DR2 in a plan view. The fifth bonding portion BR5_1 of the panel pad area P_PA may also be arranged at Fig.14 and Fig.15 In the space between the window portion WR_2.

[0136] The connection line SL_3 may include the second openings OP2_2 corresponding to the window portions WR_2 spaced apart from each other. For example, the second openings OP2_2 of the connection line SL_3 may be arranged to be spaced apart from each other along the second direction DR2.

[0137] The signal line PAD_2 may include the first openings OP1_2 corresponding to the window portions WR_2 spaced apart from each other. For example, the first openings OP1_2 of the signal line PAD_2 may be arranged to be spaced apart from each other along the second direction DR2.

[0138] Reference Fig.15 As described above, the display substrate 101, the optically transparent insulating layers 102, 111, and 112b, and the lead LE_2 are stacked in the window portions WR_2 spaced apart from each other, and the display substrate 101, the buffer layer 102, the first insulating layer 111, the connection line SL_3, the second insulating layer 112b, the signal line PAD_2, and the lead LE_2 may be stacked in the fifth bonding portion BR5_1 arranged in the space between the window portions WR_2. Therefore, a step portion appears between the window portion WR_2 and the area of ​​the signal line PAD_2 around the window portion WR_2. At least partially due to the step portion, crack portions CRK3 and CRK4 may also be formed in the lead LE_2.

[0139] like Fig.14 and Fig.15 As shown in , the third crack portion CRK3 and the fourth crack portion CRK4 of the panel pad area P_PA may be formed along the long side of the window portion WR_2. The third crack portion CRK3 may be arranged closer to the display area DA than the fourth crack portion CRK4. In a plan view, the third crack portion CRK3 and the fourth crack portion CRK4 may have a shape intersecting with the long side of the lead LE_2. Similar to the first crack portion CRK1 and the second crack portion CRK2, the third crack portion CRK3 and the fourth crack portion CRK4 may penetrate the lead LE_2 from the surface of the lead LE_2 in the thickness direction, and the lead LE_2 may be physically separated into a plurality of patterns.

[0140] The lead LE_2 may further include a sixth lead pattern LP6_1 disposed in the fifth bonding portion BR5_1 of the panel pad area P_PA. The sixth lead pattern LP6_1 may be physically separated from the fifth lead pattern LP5_2 disposed in the window portion WR_2 adjacently disposed in the upward and downward directions.

[0141] Even in the display device 4 according to some exemplary embodiments, the window portion WR_2 (i.e., the first opening OP1_2 of the signal line PAD_2) for physically separating the lead LE_2 from the panel pad area P_PA may be formed to be closest to the display area DA, and therefore, relative to the other lead patterns LP1, LP2, LP3, LP5_2 and LP6_1, the area of ​​the fourth lead pattern LP4 physically separated from the adjacent lead patterns LP1, LP2, LP3, LP5_2 and LP6_1 may be the largest, thereby increasing the transmission efficiency of the external signal through the lead LE_2 and the signal line PAD_2.

[0142] Fig.16 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some example embodiments. Fig.17 According to some exemplary embodiments Fig.16 Cross-sectional view of .

[0143] Reference Fig.16 and Fig.17 , the display device 5 according to some exemplary embodiments is different from the display device 1 in that adjacent lead patterns of the lead LE_3 are connected to each other in the first crack portion CRK1_1 and the second crack portion CRK2_1 of the panel pad area P_PA. For example, in the display device 5, adjacent lead patterns of the lead LE_3 are connected to each other in the first crack portion CRK1_1 and the second crack portion CRK2_1 of the panel pad area P_PA. That is, the first crack portion CRK1_1 and the second crack portion CRK2_1 of the panel pad area P_PA according to some exemplary embodiments may terminate internally without completely penetrating the lead LE_3 in the thickness direction of the lead LE_3.

[0144] like Fig.17As shown in , each of the first crack portion CRK1_1 and the second crack portion CRK2_1 of the panel pad area P_PA according to some exemplary embodiments may have a groove shape. The first lead pattern LP1_1 of the lead LE_3 may be physically connected to the adjacent second lead pattern LP2_1, the third lead pattern LP3_1, and the fifth lead pattern LP5_3, and the fourth lead pattern LP4_1 of the lead LE_3 may be physically connected to the adjacent second lead pattern LP2_1, the third lead pattern LP3_1, and the fifth lead pattern LP5_3. Unlike the lead LE, the lead LE_3 according to some exemplary embodiments may be integrally and physically connected to the adjacent lead patterns. However, in the first crack portion CRK1_1 and the second crack portion CRK2_1, the resistance of the lead LE_3 may increase rapidly, and therefore, external signal transmission may be disturbed.

[0145] Therefore, even in the display device 5 according to some exemplary embodiments, the window portion WR (i.e., the first opening OP1 of the signal line PAD) for forming the groove of the lead LE_3 in the panel pad area P_PA can be formed to be closest to the display area DA, and therefore, relative to the other lead patterns LP1_1, LP2_1, LP3_1 and LP5_3, the area of ​​the fourth lead pattern LP4_1 can be the largest, thereby increasing the transmission efficiency of the external signal through the lead LE_3 and the signal line PAD.

[0146] Fig.18 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some example embodiments.

[0147] In the display device 6 according to some exemplary embodiments, as Fig.18 As shown in , in a plan view, the first crack portion CRK1_2 and the second crack portion CRK2_2 of the panel pad area P_PA may be arranged between the long sides of the lead LE_4 without intersecting the long sides of the lead LE_4.

[0148] According to various exemplary embodiments, according to Fig.16 , Fig.17 and Fig.18 The shape of each of the crack portions and the shape of the associated lead according to the shape thereof may be differently applied to the lead LE and a lead to be described later.

[0149] Figure 19(a) to Figure 19(c) is a cross-sectional view of a panel pad region of a display device according to various exemplary embodiments.

[0150] exist Figure 19(a) to Figure 19(c) 2 shows that various modifications may be made to the stacked structure of the transparent insulating layers arranged in the associated window portions WR of the display devices 7 , 8 , and 9 .

[0151] 19( a ), the second insulating layer 112 b_1 may not be disposed in the window portion WR of the display device 7 . Therefore, the fifth lead pattern LP5_4 of the lead may directly contact the exposed portion of the first insulating layer 111 .

[0152] 19( b ), the second insulating layer 112 b_1 and the first insulating layer 111_1 may not be disposed in the window portion WR of the display device 8 . Therefore, the fifth lead pattern LP5_5 of the lead may directly contact the exposed portion of the buffer layer 102 .

[0153] 19( c ), the second insulating layer 112 b_1 , the first insulating layer 111_1 , and the buffer layer 102_1 may not be disposed in the window portion WR of the display device 9 . Therefore, the fifth lead pattern LP5_6 of the lead may directly contact the exposed portion of the display substrate 101 .

[0154] It is contemplated that the stacked structure of the window portion WR of the display devices 7 , 8 , and 9 may be variously applied to the various previously described window portions WR, WR_1 , and WR_2 and a window portion WR to be described later, and may be combined with each other.

[0155] Fig. 20 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some example embodiments.

[0156] Reference Fig. 20 , the shapes of the openings of the signal line PAD_3 and the connection line SL_4 of the display device 10 according to some exemplary embodiments are different from the shapes of the openings of the signal line PAD and the connection line SL of the display device 1. For example, the first opening OP1_3 of the signal line PAD_3 according to some exemplary embodiments may have a groove shape recessed from one edge of the signal line PAD_3, and the second opening OP2_3 of the connection line SL_4 may have a groove shape recessed from one edge of the connection line SL_4.

[0157] The signal line PAD_3 may include short edges SEG1 and SEG2 extending in the first direction DR1 and long edges LEG1 and LEG2 extending in the second direction DR2. The first short edge SEG1 may be arranged closer to the display area DA than the second short edge SEG2. Fig. 20As shown in , the first opening OP1_3 of the signal line PAD_3 may have a groove shape that is recessed in a direction opposite to the direction from the first short edge SEG1 of the signal line PAD_3 toward the display area DA. Similarly, the connection line SL_4 may include short edges and long edges corresponding to the short edges SEG1 and SEG2 and the long edges LEG1 and LEG2 of the signal line PAD_3. The second opening OP2_3 of the connection line SL_4 may have a groove shape that is recessed in a direction opposite to the direction from the first short edge of the connection line SL_4 adjacent to the first short edge SEG1 of the signal line PAD_3 toward the display area DA.

[0158] Fig.21 is a plan layout diagram of a state in which a panel pad region of a display panel is attached to a flexible printed circuit board according to some example embodiments.

[0159] Reference Fig.21 , the groove shapes of the openings of the signal line PAD_4 and the connection line SL_5 of the display device 11 according to some exemplary embodiments are different from the groove shapes of the openings of the signal line PAD_3 and the connection line SL_4 of the display device 10. For example, the signal line PAD_4 according to some exemplary embodiments may have a first long edge LEG1 located at the left side of the signal line PAD_4 and a second long edge LEG2 facing the first long edge LEG1. Fig.21 As shown in , the first opening OP1_4 of the signal line PAD_4 may have a groove shape that is recessed in a direction opposite to the direction from the first short edge SEG1 of the signal line PAD_4 toward the display area DA and is recessed in a direction from the first long edge LEG1 toward the center area of ​​the signal line PAD_4. However, exemplary embodiments are not limited thereto. For example, the first opening OP1_4 of the signal line PAD_4 may have a groove shape that is recessed in a direction opposite to the direction from the first short edge SEG1 of the signal line PAD_4 toward the display area DA and is recessed in a direction from the second long edge LEG2 toward the center area of ​​the signal line PAD_4.

[0160] Similar to the groove shape of the first opening OP1_4 of the signal line PAD_4 , the second opening OP2_4 of the connection line SL_5 may have a groove shape recessed from at least one of the first short edge SEG1 and the first long edge LEG1 adjacent to the display area DA.

[0161] Fig. 22 is a plan layout diagram of a display device according to some example embodiments. Fig.23 According to some exemplary embodiments Fig. 22 A cross-sectional view of a display device.

[0162] Reference Fig. 22 and Fig.23 , the display panel 100_1 of the display device 12 according to some exemplary embodiments may further include a bending area BA.

[0163] The display substrate 101 of the display panel 100_1 may be made of an insulating material such as a polymer resin. Examples of polymer resins may include polyethersulfone (PES), polyacrylate (PA), polyarylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyallyl ester, polyimide (PI), polycarbonate (PC), cellulose triacetate (CAT) and cellulose acetate propionate (CAP) at least one and / or a combination thereof. The display substrate 101 may be a flexible substrate that can be bent, folded, curled and / or folded, etc. An example of a material constituting the display substrate 101 may be polyimide (PI), but exemplary embodiments are not limited thereto.

[0164] The bending area BA may be arranged between the array of multiple pixels in the display area DA and the panel pad area P_PA_1. The bending area BA may be located in the non-display area NA. The display panel 100_1 may be folded (or otherwise bent, curled, folded, etc.) in one direction around a bending line, which is a reference line arranged in the bending area BA. The bending line may be a straight line parallel to the lower side (or upper side) of the display panel 100_1. Fig.23 As shown in FIG. 1 , the bending area BA of the display panel 100_1 may be bent downward in the third direction DR3. However, exemplary embodiments are not limited thereto. For example, the display area DA and the panel pad area P_PA_1 may be connected to each other without the bending area BA. That is, the display panel 100_1 may be flat throughout the display area DA and the non-display area NA without the bending area BA.

[0165] At least referenced Figure 5 The described plurality of connection lines SL, the plurality of signal lines PAD, and the plurality of lead lines LE are arranged in the panel pad area P_PA_1. Therefore, a redundant description will be omitted.

[0166] A driving integrated circuit 900 may be attached to the plurality of signal line PADs. In some exemplary embodiments, the driving integrated circuit 900 may be applied in a chip on plastic (COP) manner or a chip on glass (COG) manner. The driving integrated circuit 900 may include a plurality of bumps connected to the plurality of signal line PADs. The bumps may be formed of at least one of gold (Au), nickel (Ni), and tin (Sn), however, exemplary embodiments are not limited thereto.

[0167] According to some exemplary embodiments, the bumps of the driver integrated circuit 900 may be directly coupled to the respective signal lines PAD without intervening other layers or structures, and thereby contact the respective signal lines PAD. The direct coupling between the bumps of the driver integrated circuit 900 and the respective signal lines PAD may be performed by ultrasonic bonding.

[0168] According to various exemplary embodiments, transmission of a signal received from a connection unit can be prevented from being disturbed by cracks in a lead wire caused by an ultrasonic bonding inspection unit.The effects of various exemplary embodiments are not limited to the foregoing, and other various effects are expected.

[0169] Although certain exemplary embodiments and implementations have been described herein, other embodiments and variations will be apparent from this description. Accordingly, it will be apparent to those skilled in the art that the inventive concept is not limited to these embodiments, but to the broader scope of the appended claims and various obvious variations and equivalent arrangements.

Claims

1. A display device, comprising: A display substrate, the display substrate comprising: display area; and A pad area, the pad area is located outside the display area; a first connection line, wherein the first connection line is arranged on the pad area of ​​the display substrate; a signal line, the signal line being arranged on the first connection line of the pad region of the display substrate, the signal line being electrically connected to the first connection line through a first contact hole; and an insulating pattern, the insulating pattern being arranged between the first connection line and the signal line, the insulating pattern including the first contact hole therein, and the insulating pattern including an optically transparent inorganic material; wherein the signal line includes at least one first opening that is completely surrounded by the signal line in a plan view; and The first opening is arranged closer to the display area than the first contact hole.

2. The display device according to claim 1, wherein: The first connection line includes a second opening that is completely surrounded by the first connection line in the plan view; and The second opening overlaps the first opening in a thickness direction.

3. The display device according to claim 2, wherein: The first opening penetrates the signal line from a surface of the signal line in the thickness direction; and The second opening penetrates the first connection line from a surface of the first connection line in the thickness direction.

4. The display device according to claim 3, in, The insulation pattern overlaps the first opening in the thickness direction.

5. The display device according to claim 3, in, The insulating pattern does not overlap the first opening and the second opening.

6. The display device according to claim 3, wherein: The first opening includes a first through hole arranged in the signal line and completely surrounded by the signal line in the plan view; and The second opening includes a second through hole that is arranged in the first connecting line and is completely surrounded by the first connecting line in the plan view.

7. The display device according to claim 3, wherein: The display area includes a thin film transistor; and The first connection line is also arranged in the display area and connected to the thin film transistor.

8. The display device according to claim 3, further comprising: a second connection line, the second connection line being separated from the first connection line and connected to the signal line through a second contact hole; Wherein, the display area includes a thin film transistor; and The second connection line electrically connects the thin film transistor and the signal line.

9. The display device according to claim 8, wherein: The second connection line is arranged closer to the display area than the first connection line; and The second contact hole is arranged closer to the display area than the first contact hole.

10. The display device according to claim 9, wherein: The first opening is arranged between the first contact hole and the second contact hole.

11. A display device, comprising: A display substrate, the display substrate comprising: display area; and A pad area, the pad area is located outside the display area; A connecting line, wherein the connecting line is arranged on the pad area of ​​the display substrate; A signal line, wherein the signal line is arranged on the connection line of the pad region of the display substrate, and the signal line is electrically connected to the connection line through a contact hole; an insulating pattern, the insulating pattern being arranged between the connection line and the signal line, the insulating pattern including the contact hole therein, and the insulating pattern including an optically transparent inorganic material; and a flexible circuit board attached to the pad area of ​​the display substrate, the flexible circuit board including a lead overlapping the signal line, wherein the signal line includes a first opening completely surrounded by the signal line in a plan view; The connecting line includes a second opening that is completely surrounded by the connecting line in the plan view and overlaps the first opening in the thickness direction; and The first opening and the second opening are arranged closer to the display area than the contact hole.

12. The display device according to claim 11, wherein: The first opening penetrates the signal line from a surface of the signal line in the thickness direction; and The second opening penetrates the connection line from a surface of the connection line in the thickness direction.

13. The display device according to claim 12, in, The insulating pattern does not overlap the first opening and the second opening.

14. The display device according to claim 13, wherein: The signal line includes: a first short edge extending in a first direction in the plan view; and a second short edge, the second short edge being arranged closer to the display area than the first short edge; The first direction intersects with a direction from the pad area toward the display area; and The lead comprises: a first wiring pattern arranged between the first short edge and the first opening; and A second wiring pattern partially overlaps the first opening.

15. The display device according to claim 14, wherein: The lead further includes a lead crack disposed between the first lead pattern and the second lead pattern; and In the plan view, the lead crack penetrates the lead in the thickness direction to completely separate the first lead pattern from the second lead pattern along the first direction.

16. The display device according to claim 15, wherein: The thickness of the second wiring pattern overlapping the first opening is greater than the thickness of the first wiring pattern.

17. The display device according to claim 11, wherein: The signal line and the lead line are in direct contact with each other.

18. The display device according to claim 17, wherein: The signal wire and the lead wire are ultrasonically bonded to each other.

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