Display device

Abstract

A display device is disclosed. The display device includes a display unit, a controller, and an emission driver. Among them, the display unit includes a plurality of data lines, a plurality of scan lines, a plurality of emission control lines, and a plurality of pixels coupled to the plurality of data lines, the plurality of scan lines, and the plurality of emission control lines. The controller determines the width of the gate-off section of the emission control signal corresponding to the non-emission section of each of the plurality of frames belonging to the dimming period in response to a dimming signal, and the emission driver supplies the emission control signal in units of a plurality of consecutive pixel rows through the plurality of emission control lines.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10 - 2019 - 0029451, filed with the Korean Intellectual Property Office on March 14, 2019, the disclosure of which is incorporated herein by reference in its entirety. Technical field

[0003] Exemplary embodiments of the inventive concept generally relate to a display device, and more particularly, to a display device configured to control an emission control signal. Background art

[0004] A display device includes a timing - driving controller configured to control an overall driving timing, a scan driver configured to supply a gate signal to pixels, a data driver configured to supply a data signal to pixels, and an emission driver configured to supply an emission control signal to pixels.

[0005] To implement a dimming mode of a display device, dimming techniques may change all gray - scale voltages by using a gray - scale of a predetermined brightness level (e.g., a maximum brightness level), control a length of an emission section (or, a non - emission section) in a frame, etc. Summary of the invention

[0006] According to an exemplary embodiment of the inventive concept, a display device includes a display unit, a controller, and an emission driver, wherein the display unit includes a plurality of data lines, a plurality of scan lines, a plurality of emission control lines, and a plurality of pixels coupled to the plurality of data lines, the plurality of scan lines, and the plurality of emission control lines, the controller is configured to determine a width of a gate - off section of an emission control signal corresponding to a non - emission section of each of a plurality of frames belonging to a dimming period in response to a dimming signal, and the emission driver is configured to supply the emission control signal in units of a plurality of consecutive pixel rows through the plurality of emission control lines.

[0007] The dimming signal may include information about a dimming level corresponding to a display brightness of the display unit. The controller may determine a width of a gate - off section corresponding to a first reference dimming level as a first width, and determine a width of a gate - off section corresponding to a second reference dimming level higher than the first reference dimming level as a second width. The second width may be greater than the first width.

[0008] The width of the gate - off section corresponding to the first reference dimming level may be substantially equal to the first width, and the width of the gate - off section corresponding to the second reference dimming level may be substantially equal to the second width.

[0009] The gate-off section of the emission control signal corresponding to each of the dimming levels between the first reference dimming level and the second reference dimming level may include a combination of a first off section having a first width and a second off section having a second width, each in a dimming cycle.

[0010] In a range between the first reference dimming level and the second reference dimming level, as the dimming level increases, the number of the first off sections of the emission control signal may decrease, and the number of the second off sections of the emission control signal may increase.

[0011] The sum of the number of the first off sections included in the dimming cycle and the number of the second off sections included in the dimming cycle may be constant.

[0012] According to the lapse of frames in the dimming cycle, the arrangement of the first off section and the second off section may be set differently for the dimming level.

[0013] The average width of all the gate-off sections of the emission control signal included in each frame in the dimming cycle may be equal to the width of the gate-off section indicated by the dimming level.

[0014] The first width may correspond to k horizontal periods, and the second width may correspond to k + 4 horizontal periods, where k is a multiple of 4.

[0015] The interval between the first reference dimming level and the second reference dimming level may correspond to 4 horizontal periods.

[0016] The dimming cycle may correspond to 4 frames.

[0017] The emission driver may output an emission control signal having i gate-off sections corresponding to i non-emission sections in one frame, where i is an integer greater than 1.

[0018] The dimming cycle may correspond to 4 * i frames.

[0019] The difference in the dimming levels between the first reference dimming level and the second reference dimming level may correspond to 4 * i horizontal periods.

[0020] When the dimming level indicates k * i horizontal periods, each of the widths of the gate-off sections of the emission control signal may correspond to k horizontal periods. When the dimming level indicates (k + 4) * i horizontal periods, each of the widths of the gate-off sections of the emission control signal may correspond to k + 4 horizontal periods.

[0021] When the dimming level indicates horizontal periods between k * i horizontal periods and (k + 4) * i horizontal periods, the first width may correspond to k horizontal periods, and the second width may correspond to k + 4 horizontal periods.

[0022] The emission driver may supply an emission control signal to the (2n - 1)-th pixel row and the 2n-th pixel row substantially simultaneously, where n is a natural number.

[0023] The display device may further include a scan driver, where the scan driver is configured to sequentially supply a scan signal to the (2n - 1)-th pixel row and the 2n-th pixel row through a plurality of scan lines.

[0024] According to an exemplary embodiment of the inventive concept, a method for driving a display device includes: determining a first width of a gate-off section of an emission control signal indicated by a first reference dimming level and a second width of a gate-off section of the emission control signal indicated by a second reference dimming level; determining a combination of a first off section each having the first width and a second off section each having the second width in response to a first intermediate dimming level that is an intermediate value between the first reference dimming level and the second reference dimming level; and recombining an arrangement of the first off section and the second off section of the emission control signal output during a predetermined dimming period in response to a second intermediate dimming level that is an intermediate value between dimming levels determined by the combination of the first off section and the second off section.

[0025] The method may further include: outputting an emission control signal corresponding to a dimming level included in a dimming signal.

[0026] According to an exemplary embodiment of the inventive concept, a method for driving a display device includes: determining a first width of a gate-off section of an emission control signal indicated by a first reference dimming level and a second width of a gate-off section of the emission control signal indicated by a second reference dimming level in a dimming period; determining a first intermediate dimming level in the dimming period that is an intermediate value between the first reference dimming level and the second reference dimming level by combining a first off section each having the first width and a second off section each having the second width; setting the first intermediate dimming level as a third reference dimming level; and determining a second intermediate dimming level in the dimming period that is an intermediate value between the first reference dimming level and the third reference dimming level by combining the first off section and the second off section. The second width may be greater than the first width. The sum of the number of first off sections included in the dimming period and the number of second off sections included in the dimming period may be constant. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The above and other features of the inventive concept will be more fully understood by describing exemplary embodiments of the inventive concept in detail with reference to the accompanying drawings.

[0028] Figure 1 is a block diagram showing a display device according to an exemplary embodiment of the inventive concept.

[0029] Figure 2 is a circuit diagram showing pixels included in a display device shown in Figure 1 in accordance with an exemplary embodiment of the inventive concept.

[0030] Figure 3A and Figure 3B is a waveform diagram showing a method for driving a display device shown in Figure 1 in accordance with an exemplary embodiment of the inventive concept.

[0031] Figure 4 is a waveform diagram showing an output of a transmit driver included in a display device shown in Figure 1 in accordance with an exemplary embodiment of the inventive concept.

[0032] Figures 5A to 5C is a view showing a method for determining an output of a transmit driver for Figure 4 in accordance with an exemplary embodiment of the inventive concept.

[0033] Figure 6 is a conceptual diagram showing an output of a transmit driver for Figure 4 in accordance with an exemplary embodiment of the inventive concept.

[0034] Figure 7 is a waveform diagram showing an output of a transmit driver included in a display device shown in Figure 1 in accordance with an exemplary embodiment of the inventive concept.

[0035] Figures 8A to 8C is a view showing a method for determining an output of a transmit driver for Figure 7 in accordance with an exemplary embodiment of the inventive concept.

[0036] Figure 9 is a waveform diagram showing an output of a transmit driver included in a display device shown in Figure 1 in accordance with an exemplary embodiment of the inventive concept.

[0037] Figure 10 is a conceptual diagram showing dimming for a dimming level in accordance with an exemplary embodiment of the inventive concept. DETAILED DESCRIPTION

[0038] Exemplary embodiments of the inventive concept provide a display device configured to control a width of a gate-off section of a transmit control signal for each frame according to a dimming level, thereby implementing dimming for controlling display brightness.

[0039] Hereinafter, exemplary embodiments of the inventive concept will be described in more detail with reference to the accompanying drawings. Throughout this application, like reference numerals may indicate like elements.

[0040] It should be understood that when an element is referred to as being "between" two elements, the element may be the only element between the two elements, or one or more intermediate elements may also exist.

[0041] Figure 1 is a block diagram showing a display device according to an exemplary embodiment of the inventive concept.

[0042] Referring to Figure 1 , the display device 1000 may include a display unit 100, a scan driver 200, an emission driver 300, a data driver 400, and a controller 500.

[0043] The display unit 100 may include a plurality of scan lines S1 to Sn, a plurality of emission control lines E1 to E(n / 2), a plurality of data lines D1 to Dm, and a plurality of pixels P respectively connected to the scan lines S1 to Sn, the emission control lines E1 to E(n / 2), and the data lines D1 to Dm, where m is an integer greater than 1, and n is an even number. Each of the plurality of pixels P may include a driving transistor and a plurality of switching transistors.

[0044] The controller 500 may determine the output duty ratio (or the width of the gate-off section) of the emission control signal for each of the frames included in the dimming period in response to the dimming level DIL included in the dimming signal DIM. The dimming signal DIM is a signal for controlling the dimming level DIL or the brightness level. The dimming level DIL may be a predetermined command value obtained by digitizing the display brightness level for dimming. In an exemplary embodiment of the inventive concept, the dimming level DIL may be a command for determining the width (length) of the gate-off section of the emission control signal. For example, the dimming level DIL may indicate the total length of the gate-off section in one frame of the emission control signal to be output.

[0045] Meanwhile, in an exemplary embodiment of the inventive concept, according to the design conditions of the emission driver 300 and the display device 1000, the total length of the gate-off section of the emission control signal actually output from the emission driver 300 may not correspond to the total length of the gate-off section indicated by the dimming level DIL.

[0046] In an exemplary embodiment of the inventive concept, the controller 500 may generate a start emission control signal FLM having a predetermined gate-off section in response to a dimming level DIL. The gate-off section may correspond to the length (or, duty ratio) of a non-emission section that an emission control signal actually output from the emission driver 300 has in one frame (or, one period). Accordingly, when the input brightness level decreases (or, when the dimming level DIL increases), the width of the gate-off section of the emission control signal may increase. In addition, when the dimming level DIL decreases, the display brightness may increase.

[0047] The controller 500 may control the width of the gate-off section of the emission control signal in units of a predetermined horizontal period H. For example, the width of the gate-off section of the emission control signal may have horizontal periods corresponding to multiples of 4, such as 4 horizontal periods 4H, 8 horizontal periods 8H, 12 horizontal periods 12H, or 16 horizontal periods 16H. The emission control signal does not have a gate-off section of 5 horizontal periods 5H, 6 horizontal periods 6H, etc. Thus, when a gate-off section that exactly corresponds to the dimming level DIL is not generated, precise brightness control may not be possible according to a change in the dimming level DIL.

[0048] The controller 500 controls the width of the non-emission section (or, the width of the gate-off section) of each of the frames included in a dimming period to determine the output of the emission control signal corresponding to each of all dimming levels DIL. This will be described in detail with reference to Figure 4 This will be described in detail.

[0049] In an exemplary embodiment of the inventive concept, the controller 500 may control the driving of the scan driver 200, the emission driver 300, and the data driver 400. For example, the controller 500 may include a timing controller configured to control the scan driver 200, the emission driver 300, and the data driver 400.

[0050] The controller 500 may generate a first control signal SCS, a second control signal ECS, and a third control signal DCS corresponding to a synchronization signal supplied from the outside. The first control signal SCS may be supplied to the scan driver 200, the second control signal ECS may be supplied to the emission driver 300, and the third control signal DCS may be supplied to the data driver 400. In addition, the controller 500 may readjust image data supplied from the outside and supply the readjusted image data to the data driver 400.

[0051] The first control signal SCS may include a scan start signal and a clock signal. The scan start signal may control a first timing of a scan signal. The clock signal may be used to shift the scan start signal.

[0052] The second control signal ECS may include a firing control start signal FLM and a clock signal. The firing control start signal FLM may control a first timing of the firing control signal. The clock signal may be used to shift the firing control start signal FLM.

[0053] The third control signal DCS may include an active start pulse and a clock signal. The active start pulse may control a sampling start time of data. The clock signal may be used to control a sampling operation.

[0054] The scan driver 200 may receive a first control signal SCS from the controller 500 and supply scan signals to scan lines S1 to Sn based on the first control signal SCS. For example, the scan driver 200 may sequentially supply scan signals to scan lines S1 to Sn. When the scan signals are sequentially supplied, pixels P may be selected on a horizontal line basis (or, on a pixel row basis).

[0055] The scan signal may be set to a gate-on voltage (e.g., a low voltage). When the scan signal is supplied, a transistor included in the pixel P and receiving the scan signal may be set to an on state.

[0056] The firing driver 300 may receive a second control signal ECS from the controller 500 and supply firing control signals to firing control lines E1 to E(n / 2) based on the second control signal ECS. For example, the firing driver 300 may sequentially supply firing control signals to firing control lines E1 to E(n / 2).

[0057] The firing control signal may be set to a gate-on voltage (e.g., a low voltage). When the firing control signal is supplied, a transistor included in the pixel P and receiving the firing control signal may be turned on and may be set to an off state in other cases.

[0058] The firing control signal is used to control a firing time of the pixel P. To this end, the firing control signal may be set to have a width wider than a width of the scan signal.

[0059] In an exemplary embodiment of the inventive concept, as Figure 1As shown, the emission driver 300 may supply emission control signals in units of consecutive pixel rows through the emission control lines E1 to E(n / 2). For example, the emission driver 300 may supply the emission control signals to the (2i - 1)-th pixel row and the 2i-th pixel row substantially simultaneously, where i is a natural number. In other words, the same emission control signal may be supplied to two consecutive pixel rows substantially simultaneously. Therefore, the emissions of two pixel rows may be controlled substantially simultaneously. For example, during the gate-off section of one emission control signal (e.g., the section where the emission control signal has a gate-off voltage), initialization, compensation, and data writing operations may be performed on two pixel rows corresponding to one emission control signal. However, this is merely illustrative, and one emission control line may be commonly connected to three or more pixel rows.

[0060] Accordingly, compared with the configuration in which one emission control line is connected to one pixel row, the number of stages (or, shift registers) included in the emission driver 300 may be reduced to half or less. Thereby, the area of the bezel at the periphery of the display unit 100 may be reduced.

[0061] Each of the scan driver 200 and the emission driver 300 may be mounted on the substrate through a thin film process. Additionally, the scan driver 200 may be located on both sides of the display unit 100 with the display unit 100 interposed therebetween. The emission driver 300 may also be located on both sides of the display unit 100 with the display unit 100 interposed therebetween.

[0062] The data driver 400 may receive the third control signal DCS and the image data signal RGB from the controller 500. The data driver 400 may supply data signals to the data lines D1 to Dm corresponding to the third control signal DCS. The data signals supplied to the data lines D1 to Dm may be supplied to the pixels P selected by the scan lines S1 to Sn. To this end, the data driver 400 may supply the data signals to the data lines D1 to Dm synchronously with the scan signal.

[0063] Figure 2 is a circuit diagram showing a pixel included in the Figure 1 display device shown in accordance with an exemplary embodiment of the inventive concept.

[0064] For convenience of description, in Figure 2 a pixel P located on the q-th horizontal line (or, the q-th pixel row) and connected to the p-th data line Dp is shown, where p and q are natural numbers.

[0065] Referring to Figure 2 , the pixel P may include a light-emitting device LED, first transistors T1 to seventh transistors T7, and a storage capacitor Cst.

[0066] The first electrode of the light-emitting device LED may be connected to one electrode of the seventh transistor T7, and the second electrode of the light-emitting device LED may be connected to the second power supply VSS. The light-emitting device LED may generate light having a predetermined brightness corresponding to the amount of current (driving current) supplied from the first transistor T1. In an exemplary embodiment of the inventive concept, the light-emitting device LED may be an organic light-emitting diode including an organic emission layer or an inorganic light-emitting diode formed of an inorganic material.

[0067] The first transistor T1 may be connected between a second node N2 electrically connected to the first power supply VDD and a third node N3 electrically connected to the first electrode of the light-emitting device LED. The first transistor T1 may generate a driving current and supply the generated driving current to the light-emitting device LED. The gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 serves as a driving transistor of the pixel P.

[0068] The second transistor T2 may be connected between a data line (e.g., the p-th data line Dp) and the second node N2. The second transistor T2 may include a gate electrode that receives a scan signal. For example, the gate electrode of the second transistor T2 may be connected to the first scan line Sq of the q-th pixel row.

[0069] The third transistor T3 may be electrically connected between the first node N1 and the third node N3. The third transistor T3 may include a gate electrode connected to the first scan line Sq.

[0070] The fourth transistor T4 may be connected between the first power supply VDD and the second node N2. The fourth transistor T4 may include a gate electrode that receives an emission control signal. The gate electrode of the fourth transistor T4 may be connected to the emission control line Ei. In an exemplary embodiment of the inventive concept, the emission control line Ei may be commonly connected to two consecutive pixel rows. For example, the emission control line Ei may be commonly connected to the (q - 1)-th pixel row and the q-th pixel row, and the emission control signal may be supplied to the (q - 1)-th pixel row and the q-th pixel row substantially simultaneously.

[0071] The fifth transistor T5 may be connected between the third node N3 and the first electrode of the light-emitting device LED. The fifth transistor T5 may include a gate electrode that receives an emission control signal. The gate electrode of the fifth transistor T5 may be connected to the emission control line Ei.

[0072] The sixth transistor T6 may be connected between the first node N1 and the initialization power supply VINT. In an exemplary embodiment of the inventive concept, the sixth transistor T6 may include a gate electrode connected to the second scan line Sq - 1 of the q-th pixel row. For example, the second scan line Sq - 1 may coincide with the first scan line of the previous pixel row (e.g., the (q - 1)-th pixel row).

[0073] The seventh transistor T7 may be coupled between the initialization power supply VINT and the first electrode of the light-emitting device LED. The seventh transistor T7 may include a gate electrode coupled to the second scan line Sq-1. However, this is merely illustrative, and the scan lines coupled to each of the gate electrodes of the sixth transistor T6 and the seventh transistor T7 are not limited thereto. For example, scan lines that transmit scan signals at different timings may be respectively coupled to the sixth transistor T6 and the seventh transistor T7.

[0074] In an exemplary embodiment of the inventive concept, when the fourth transistor T4 and the fifth transistor T5 are turned on, the current flowing through the first transistor T1 may be transmitted to the light-emitting device LED, and the light-emitting device LED may emit light. The emission section of the light-emitting device LED may be determined corresponding to the turn-on sections of the fourth transistor T4 and the fifth transistor T5. In addition, the turn-on sections of the fourth transistor T4 and the fifth transistor T5 may correspond to the gate turn-on sections of the emission control signal, and the turn-off sections of the fourth transistor T4 and the fifth transistor T5 may correspond to the gate turn-off sections of the emission control signal.

[0075] Figure 3A and Figure 3B are waveform diagrams showing a method for driving the Figure 1 display device shown in.

[0076] Referring to Figure 3A and Figure 3B , the emission control signal Ei_1cyc or Ei_4cyc corresponding to one frame may define at least one emission section EP and at least one non-emission section NEP.

[0077] In an exemplary embodiment of the inventive concept, as shown in Figure 3A , the emission control signal Ei_1cyc may define one non-emission section NEP corresponding to a high level and one emission section EP corresponding to a low level. The non-emission section NEP may correspond to the gate turn-off section of the emission control signal Ei_1cyc.

[0078] The gate turn-off section (e.g., non-emission section NEP) of the emission control signal Ei_1cyc may correspond to a predetermined horizontal period. For example, the width of the gate turn-off section of the emission control signal Ei_1cyc may be set to about 4 horizontal periods 4H. As referred to Figure 1 and Figure 2As described, when the emission control signal Ei_1cyc is supplied to two consecutive pixel rows, the width of the gate-off section of the emission control signal Ei_1cyc can be substantially set to 4 horizontal periods so that the initialization and data writing operations of the two pixel rows are stably performed. One horizontal period 1H can be a period for shifting the scan signal or a period for applying a data signal in the pixel column direction.

[0079] In an exemplary embodiment of the inventive concept, when driving the display device in a dimming mode, in response to Figure 1 the dimming signal DIM shown in controls the length of the non-emission section NEP so that the display brightness can be controlled. For example, the dimming method for controlling the length of the non-emission section can be used in a low brightness range of about 100 nits or less. However, this is merely illustrative, and the dimming method for controlling the length of the non-emission section can be applied to any predetermined brightness range.

[0080] In an exemplary embodiment of the inventive concept, the width of the gate-off section of the emission control signal Ei_1cyc can be controlled in units of 4 horizontal periods (e.g., represented by (4k)H). For example, the width of the gate-off section of the emission control signal Ei_1cyc can be sequentially increased to 4 horizontal periods, 8 horizontal periods, and 12 horizontal periods. When the dimming level increases, the width of the gate-off section of the emission control signal Ei_1cyc increases, and thus, the display brightness can be reduced.

[0081] In an exemplary embodiment of the inventive concept, as Figure 3B shown, the emission control signal Ei_4cyc can define a plurality of non-emission sections NEP corresponding to a high level and a plurality of emission sections EP corresponding to a low level in one frame. For example, one consecutive non-emission section NEP and one emission section EP can define one emission cycle. In one frame, the lengths of the emission cycles CYC1 to CYC4 can be equal to each other. Although Figure 3B shows a case where the emission control signal Ei_4cyc has four emission cycles CYC1 to CYC4, the waveform of the emission control signal Ei_4cyc is not limited thereto. For example, according to the design of the display device, the emission control signal Ei_4cyc can include two emission cycles or eight emission cycles.

[0082] Figure 4 is a waveform diagram showing the output of the emission driver included in the Figure 1 display device shown in according to an exemplary embodiment of the inventive concept.

[0083] For convenience of description, the output of the emission control signal EM output to the i-th emission control line Ei is shown. Additionally, the gate-off section (e.g., non-emission section) of the emission control signal EM is the high-level section of the emission control signal EM.

[0084] Referring to Figures 1 to 4 , the emission driver 300 can output an emission control signal EM having one emission cycle.

[0085] In an exemplary embodiment of the inventive concept, when one frame includes one emission cycle, the dimming period DP may correspond to four frames. In other words, the first frame 1F to the fourth frame 4F may be included in the dimming period DP. The dimming period DP may be determined in one frame period for the corresponding emission cycle. The dimming period DP is determined by the arrangement rule of the gate-off sections output according to the passage of the frames.

[0086] For example, when one frame includes one emission cycle, the emission control signal EM having all dimming levels DIL may generally have the same width of the gate-off section for every fourth frame.

[0087] The width of the gate-off section of the emission control signal EM can be controlled in units of 4 horizontal periods. The dimming level DIL may be the width of the gate-off section of the emission control signal EM to be output (or, the length of the horizontal period corresponding to the gate-off section).

[0088] When the dimming level DIL is 4k (where k is a natural number), the width of the gate-off section of the emission control signal EM can be determined to be 4k horizontal periods (represented by (4k)H in Figure 4 . Thus, as shown in Figure 4 , an emission control signal EM having a gate-off section of 4k horizontal periods can be output for each frame. The display device 1000 can emit light having a brightness corresponding to the gate-off section of 4k horizontal periods. For example, the emission driver 300 can output an emission control signal EM having a gate-off section of 4 horizontal periods in response to a dimming level of 4 horizontal periods.

[0089] Similarly, when the dimming level DIL is 4(k + 1), the width of the gate-off section of the emission control signal EM can be determined to be 4(k + 1) horizontal periods (represented by (4(k + 1))H in Figure 4 . Thus, for every fourth dimming level DIL, the width of the gate-off section can be increased by 4 horizontal periods.

[0090] Hereinafter, for convenience of description, the gate-off section of 4k horizontal periods is described as the first off section DT1, and the gate-off section of 4(k + 1) horizontal periods is described as the second off section DT2.

[0091] In addition, the dimming level DIL indicating the output of the gate-off section for 4k horizontal periods may be set to a first reference dimming level RDL1, and the dimming level DIL indicating the output of the gate-off section for 4(k + 1) horizontal periods may be set to a second reference dimming level RDL2. In other words, the first reference dimming level RDL1 and the second reference dimming level RDL2 may be the dimming levels DIL indicating the outputs of the gate-off sections for 4k horizontal periods and 4(k + 1) horizontal periods, respectively.

[0092] In an exemplary embodiment of the inventive concept, a first width of the gate-off section indicated by the first reference dimming level RDL1 (e.g., DIL = 4k) may be equal to a width of a first off section DT1, and a second width of the gate-off section indicated by the second reference dimming level RDL2 (e.g., DIL = 4(k + 1)) may be equal to a width of a second off section DT2. In other words, a length (or, width) of the second off section DT2 may be greater than a length (or, width) of the first off section DT1.

[0093] As described above, the width of the gate-off section of the emission control signal EM changes for every fourth horizontal period. Accordingly, gate-off sections of 5 horizontal periods 5H, 6 horizontal periods 6H, etc. are not output.

[0094] A display device 1000 according to an exemplary embodiment of the inventive concept controls an output of a gate-off section of an emission control signal EM such that an average value of the gate-off sections of the emission control signal EM per frame corresponds to a horizontal period required for a dimming level DIL in a dimming cycle DP. For example, an emission control signal EM corresponding to each of dimming levels (e.g., Figure 4 DIL = 4k + 1, DIL = 4k + 2, and DIL = 4k + 3 in) between the first reference dimming level RDL1 and the second reference dimming level RDL2 may include a combination of a first off section DT1 and a second off section DT2 in a dimming cycle DP.

[0095] In response to a dimming level DIL corresponding to 4k + 1 horizontal periods, the emission control signal EM may have one second off period DT2 and three first off periods DT1 during the dimming period DP. For example, in response to a dimming level DIL of 5 horizontal periods, the emission control signal EM may have gate off period widths in the order of 8 - 4 - 4 - 4 horizontal periods during the dimming period DP. The average width of the gate off periods per frame may correspond to 5 horizontal periods (e.g., (8 + 4 + 4 + 4) / 4 = 5). Thus, from the combination of the first off period DT1 of 4 horizontal periods and the second off period DT2 of 8 horizontal periods, an image with a brightness corresponding to an average gate off period of 5 horizontal periods can be displayed during the dimming period DP.

[0096] Similarly, in response to a dimming level DIL corresponding to 4k + 2 horizontal periods, the emission control signal EM may have two second off periods DT2 and two first off periods DT1 during the dimming period DP. For example, in response to a dimming level DIL of 6 horizontal periods, the emission control signal EM may have gate off period widths in the order of 8 - 4 - 8 - 4 horizontal periods during the dimming period DP. The average width of the gate off periods per frame may correspond to 6 horizontal periods (e.g., (8 + 4 + 8 + 4) / 4 = 6). Thus, an image with a brightness corresponding to an average gate off period of 6 horizontal periods can be displayed.

[0097] In response to a dimming level DIL corresponding to 4k + 3 horizontal periods, the emission control signal EM may have three second off periods DT2 and one first off period DT1 during the dimming period DP. For example, in response to a dimming level DIL of 7 horizontal periods, the emission control signal EM may have gate off period widths in the order of 8 - 8 - 8 - 4 horizontal periods during the dimming period DP. The average width of the gate off periods per frame may correspond to 7 horizontal periods (e.g., (8 + 8 + 8 + 4) / 4 = 7). Thus, an image with a brightness corresponding to an average gate off period of 7 horizontal periods can be displayed.

[0098] The average width of all the gate off periods included in the dimming period DP per frame may be substantially equal to the width of the gate off period indicated by the dimming level DIL. At the same time, as Figure 4As shown, according to the progression of frames in the dimming period DP, the arrangement of the first off-segment DT1 and the second off-segment DT2 can be set differently for the dimming level DIL. In an exemplary embodiment of the inventive concept, within the range of dimming levels between the first reference dimming level RDL1 and the second reference dimming level RDL2, as the dimming level DIL increases, the number of the first off-segments DT1 can decrease, and the number of the second off-segments DT2 can increase. Accordingly, when the dimming level DIL increases, the display brightness can be smoothly reduced.

[0099] Meanwhile, the sum of the number of the first off-segments DT1 included in the dimming period DP and the number of the second off-segments DT2 included in the dimming period DP can be constant, regardless of the dimming level DIL. In other words, when the dimming period DP of the emission control signal EM including one emission cycle corresponds to 4 frames, the sum of the number of the first off-segments DT1 included in the dimming period DP and the number of the second off-segments DT2 included in the dimming period DP can be 4.

[0100] As described above, the display device 1000 according to an exemplary embodiment of the inventive concept controls and outputs the width of the gate off-segment of the emission control signal EM according to the dimming level DIL in the dimming period DP, so that the resolution of the display brightness using the dimming method for controlling the length of the non-emission segment can be improved. Therefore, smoother and more precise brightness dimming can be achieved.

[0101] Figures 5A to 5C is a view showing a method for determining Figure 4 the output of the emission driver according to an exemplary embodiment of the inventive concept. Figure 6 is a conceptual diagram showing Figure 4 the output of the emission driver according to an exemplary embodiment of the inventive concept.

[0102] Referring to Figures 4 to 6 , the emission control signal EM corresponding to each dimming level DIL can be output from the combination of the first off-segment DT1 and the second off-segment DT2 output during the dimming period DP.

[0103] First, the dimming level corresponding to 4k horizontal periods can be referred to as the first reference dimming level RDL1, and the dimming level corresponding to 4(k + 1) horizontal periods can be referred to as the second reference dimming level RDL2. The first off-segment DT1 (corresponding to 4k horizontal periods) can be determined from the first reference dimming level RDL1, and the second off-segment DT2 (corresponding to 4(k + 1) horizontal periods) can be determined from the second reference dimming level RDL2.

[0104] As Figure 5AAs shown, a first intermediate dimming level IDL1 (corresponding to 4k + 2 horizontal periods) is selected as the intermediate value between the first reference dimming level RDL1 and the second reference dimming level RDL2. Additionally, a combination of the first off period DT1 and the second off period DT2 included in the dimming period DP can be determined corresponding to the first intermediate dimming level IDL1. In an exemplary embodiment of the inventive concept, the width of the output gate off period of the first intermediate dimming level IDL1 corresponding to odd frames (e.g., the first frame 1F and the third frame 3F) can be selected from the second reference dimming level RDL2, and the width of the output gate off period of the first intermediate dimming level IDL1 corresponding to even frames (e.g., the second frame 2F and the fourth frame 4F) can be selected from the first reference dimming level RDL1.

[0105] In other words, the width of the output gate off period corresponding to the first intermediate dimming level IDL1 can be provided in the form of alternately outputting the second off period DT2 and the first off period DT1. Thus, the average length of the non-emission period per frame can correspond to 4k + 2 horizontal periods in the dimming period DP of the emission control signal EM corresponding to the first intermediate dimming level IDL1.

[0106] However, this is merely illustrative, and the output order of the first off period DT1 and the second off period DT2 corresponding to the first intermediate dimming level IDL1 is not limited thereto. For example, an emission control signal having the second off period DT2 can be output in the first frame 1F and the second frame 2F, and an emission control signal having the first off period DT1 can be output in the third frame 3F and the fourth frame 4F.

[0107] Meanwhile, as Figure 5B shown, the first intermediate dimming level IDL1 can be used or set as a new reference dimming level. For example, the first intermediate dimming level IDL1 can be determined as the third reference dimming level RDL3, and the width of the output gate off period corresponding to a second intermediate dimming level IDL2 (e.g., a dimming level corresponding to 4k + 1 horizontal periods), which is the intermediate value between the first reference dimming level RDL1 and the third reference dimming level RDL3, can be determined.

[0108] The output gate-off section corresponding to the second intermediate dimming level IDL2 can be determined from the combination of the output gate-off section corresponding to the first reference dimming level RDL1 and the output gate-off section corresponding to the third reference dimming level RDL3. For example, the output gate-off sections of the first frame 1F and the second frame 2F can be selected from the third reference dimming level RDL3, and the output gate-off sections of the third frame 3F and the fourth frame 4F can be selected from the first reference dimming level RDL1. In other words, the arrangement of the first off section DT1 and the second off section DT2 can be recombined to correspond to the second intermediate dimming level IDL2.

[0109] The average length of the non-emission section corresponding to the second intermediate dimming level IDL2 of each frame can correspond to 4k + 1 horizontal periods. For example, the dimming period DP may include three first off sections DT1 and one second off section DT2.

[0110] As Figure 5C shown, the gate-off section of the third intermediate dimming level IDL3 (for example, the dimming level corresponding to 4k + 3 horizontal periods), which is the intermediate value between the third reference dimming level RDL3 and the second reference dimming level RDL2, can be determined. The gate-off section of the third intermediate dimming level IDL3 can be determined using a method that is substantially the same as the method used to determine the gate-off section of the second intermediate dimming level IDL2.

[0111] For example, the widths of the gate-off sections of the first frame 1F and the second frame 2F can be selected from the second reference dimming level RDL2, and the widths of the gate-off sections of the third frame 3F and the fourth frame 4F can be selected from the third reference dimming level RDL3. In other words, the arrangement of the first off section DT1 and the second off section DT2 can be recombined to correspond to the third intermediate dimming level IDL3.

[0112] The average length of the non-emission section corresponding to the third intermediate dimming level IDL3 of each frame can correspond to 4k + 3 horizontal periods. For example, the dimming period DP may include three second off sections DT2 and one first off section DT1.

[0113] Figure 6Shows the gate-off section (non-emission section) of the emission control signal EM in the dimming period DP. The first off-section DT1 may correspond to 4 horizontal periods 4H, and the second off-section DT2 may correspond to 8 horizontal periods 8H. According to the progression of frames in the dimming period DP, the arrangement of the first off-section DT1 and the second off-section DT2 may be set differently for the dimming level DIL. In an exemplary embodiment of the inventive concept, when the dimming level DIL increases, the number of the first off-sections DT1 (e.g., 4H) may decrease, and the number of the second off-sections DT2 (e.g., 8H) may increase. Accordingly, when the dimming level DIL increases, the display brightness may be smoothly reduced. In the range of the dimming level DIL between the first reference dimming level RDL1 and the second reference dimming level RDL2, when the dimming level DIL increases, the number of the first off-sections DT1 of the emission control signal EM decreases, and the number of the second off-sections DT2 of the emission control signal EM increases.

[0114] Figure 7 Is a waveform diagram showing the output of the emission driver included in the Figure 1 display device shown in accordance with an exemplary embodiment of the inventive concept.

[0115] In Figure 7 those, components consistent with the components described with reference to Figure 4 are denoted by the same reference numerals, and their repeated description will be omitted. Additionally, except for the emission cycles included in a frame, Figure 7 the output of the emission driver shown in Figure 4 may have a configuration consistent with or similar to the output of the emission driver shown in

[0116] Referring to Figure 1 and Figure 7 , the emission driver 300 may output an emission control signal EM including a plurality of emission cycles.

[0117] The emission driver 300 may output an emission control signal EM including i gate-off sections corresponding to i non-emission sections in one frame, where i is an integer greater than 1. As Figure 7 shown, the emission control signal EM may be driven in two cycles including two non-emission sections (e.g., two gate-off sections) in one frame. One frame may include a first cycle and a second cycle.

[0118] When one frame has i gate-off sections, the dimming period DP may correspond to (4 * i) frames. In an exemplary embodiment of the inventive concept, when two gate-off sections (non-emission sections) are output in one frame, the dimming period DP may correspond to 8 frames.

[0119] The width of the gate-off section of the emission control signal EM can be controlled for every fourth horizontal period. The dimming level DIL can be the width of the gate-off section of the emission control signal EM to be output (or, the length of the horizontal period corresponding to the width of the gate-off section).

[0120] The dimming level DIL indicating the output of the gate-off section of 8k horizontal periods can be set to the first reference dimming level RDL1, and the dimming level indicating the output of the gate-off section of 8(k + 1) horizontal periods can be set to the second reference dimming level RDL2. The width of the gate-off section indicated by the first reference dimming level RDL1 (e.g., DIL = 8k) can be equal to the width of the first off section DT1, and the width of the gate-off section indicated by the second reference dimming level RDL2 (e.g., DIL = 8(k + 1)) can be equal to the width of the second off section DT2.

[0121] The emission control signal EM corresponding to each of the dimming levels between the first reference dimming level RDL1 and the second reference dimming level RDL2 (e.g., Figure 7 DIL = 8k + 1,...... and DIL = 8k + 7 in) can include a combination of the first off section DT1 and the second off section DT2 in the dimming period DP.

[0122] In response to the dimming level DIL corresponding to 8k + 1 horizontal periods, the emission control signal EM can have two second off sections DT2 and 14 first off sections DT1 during the dimming period DP. For example, the average length of the gate-off section of the emission control signal EM output in response to the dimming level DIL of 9 horizontal periods per frame can correspond to 9 horizontal periods 9H (e.g., (4 * 14 + 8 * 2) / 8 = 9). Therefore, from the combination of the first off section DT1 of 4 horizontal periods and the second off section DT2 of 8 horizontal periods, an image with a brightness corresponding to a non-emission section of 9 horizontal periods on average can be displayed during the dimming period DP.

[0123] Similarly, the gate-off section of the emission control signal EM having dimming levels corresponding to 8k + 2 horizontal periods to 8k + 7 horizontal periods respectively can be determined.

[0124] According to the progression of frames in the dimming period DP, the arrangement of the first off-segment DT1 and the second off-segment DT2 can be set differently for the dimming level DIL. In an exemplary embodiment of the inventive concept, within the range between the first reference dimming level RDL1 and the second reference dimming level RDL2, when the dimming level DIL increases, the number of the first off-segments DT1 can decrease, and the number of the second off-segments DT2 can increase. Accordingly, when the dimming level DIL increases, the display brightness can be smoothly reduced.

[0125] Meanwhile, the sum of the number of the first off-segments DT1 included in the dimming period DP and the number of the second off-segments DT2 included in the dimming period DP can be constant, regardless of the dimming level DIL. In other words, when the dimming period DP of the emission control signal EM including one emission cycle corresponds to 8 frames, the sum of the number of the first off-segments DT1 included in the dimming period DP and the number of the second off-segments DT2 included in the dimming period DP can be 16.

[0126] However, this is only illustrative, and the emission cycle is not limited thereto. For example, when 4 non-emission segments (4 driving cycles) are included in one frame, the dimming period DP can correspond to 16 frames, and 16 frames can be used as a period to change the output of the emission control signal for each dimming level DIL.

[0127] Figures 8A to 8C is a view showing a method for determining Figure 7 the output of the emission driver according to an exemplary embodiment of the inventive concept.

[0128] In Figures 8A to 8C the components consistent with the components described with reference to Figures 5A to 5C are denoted by the same reference numerals, and their repeated description will be omitted.

[0129] Referring to Figures 7 to 8C , the emission control signal EM corresponding to each dimming level DIL can be output from the combination of the first off-segment DT1 and the second off-segment DT2 output during the dimming period DP.

[0130] The combination of the off-segments of the first cycle and the second cycle in the frame is determined independently. The dimming level corresponding to 8k horizontal cycles can be referred to as the first reference dimming level RDL1, and the dimming level corresponding to 8(k + 1) horizontal cycles can be referred to as the second reference dimming level RDL2. The first off-segment DT1 (corresponding to 8k horizontal cycles) can be determined from the first reference dimming level RDL1, and the second off-segment DT2 (corresponding to 8(k + 1) horizontal cycles) can be determined from the second reference dimming level RDL2.

[0131] As shown Figure 8A select a first intermediate dimming level IDL1 (corresponding to 8k + 4 horizontal periods) that is the intermediate value between the first reference dimming level RDL1 and the second reference dimming level RDL2. Additionally, a combination of a first off period DT1 and a second off period DT2 included in the dimming period DP can be determined corresponding to the first intermediate dimming level IDL1.

[0132] In an exemplary embodiment of the inventive concept, the width of the gate off period of the first intermediate dimming level IDL1 corresponding to the first cycle of odd frames (e.g., 1F, 3F, 5F, and 7F) can be selected from the second reference dimming level RDL2, and the width of the gate off period of the first intermediate dimming level IDL1 corresponding to the second cycle of odd frames can be selected from the first reference dimming level RDL1. Additionally, the width of the gate off period of the first intermediate dimming level IDL1 corresponding to the first cycle of even frames (e.g., 2F, 4F, 6F, and 8F) can be selected from the first reference dimming level RDL1, and the width of the gate off period of the first intermediate dimming level IDL1 corresponding to the second cycle of even frames can be selected from the second reference dimming level RDL2.

[0133] The number of the first off periods DT1 corresponding to the first intermediate dimming level IDL1 and the number of the second off periods DT2 corresponding to the first intermediate dimming level IDL1 can be equal to each other. Accordingly, the emission control signal EM corresponding to the first intermediate dimming level IDL1 can have an average length of non - emission periods of 4k + 2 horizontal periods per frame.

[0134] As shown Figure 8B the first intermediate dimming level IDL1 can be used as a new reference dimming level. For example, the first intermediate dimming level IDL1 can be determined as a third reference dimming level RDL3, and the width of the gate off period corresponding to a second intermediate dimming level IDL2 (e.g., a dimming level corresponding to 8k + 2 horizontal periods), which is the intermediate value between the first reference dimming level RDL1 and the third reference dimming level RDL3, can be determined.

[0135] The width of the gate-off section corresponding to the second intermediate dimming level IDL2 can be determined from the combination of the width of the gate-off section corresponding to the first reference dimming level RDL1 and the width of the gate-off section corresponding to the third reference dimming level RDL3. For example, the width of the gate-off section of the first frame 1F and the second frame 2F can be selected from the third reference dimming level RDL3, and the width of the gate-off section of the third frame 3F and the fourth frame 4F can be selected from the first reference dimming level RDL1. In other words, the arrangement of the first off-section DT1 and the second off-section DT2 can be recombined to correspond to the second intermediate dimming level IDL2.

[0136] The average length of the non-emission section corresponding to the second intermediate dimming level IDL2 of each frame can correspond to 8k + 2 horizontal periods. For example, the dimming period DP may include twelve first off-sections DT1 and four second off-sections DT2.

[0137] As Figure 8C shown, the second intermediate dimming level IDL2 can be used as a new reference dimming level. For example, the second intermediate dimming level IDL2 can be determined as the fourth reference dimming level RDL4. The width of the gate-off section of the third intermediate dimming level IDL3 can be determined using a method substantially the same as the method for determining the width of the gate-off section of the second intermediate dimming level IDL2.

[0138] Regarding other dimming levels, a method substantially the same as or similar to the method Figure 8B and Figure 8C shown can be used to determine the width of the gate-off section. Accordingly, different outputs of the emission control signal EM can be determined according to Figure 7 the dimming level DIL shown. Therefore, in a display device configured to supply the emission control signal EM substantially simultaneously in units of multiple pixel rows, the resolution of the display brightness using a dimming method for controlling the length of the non-emission section can be improved. In addition, the smoothness in brightness dimming can be improved.

[0139] Figure 9 is a waveform diagram showing the output of the emission driver included in the display device shown in Figure 1 according to an exemplary embodiment of the inventive concept.

[0140] In Figure 9 , components consistent with the components described with reference to Figure 7 are denoted by the same reference numerals, and their repeated description will be omitted. Additionally, except for the output waveforms of some frames, Figure 9 the output of the emission driver shown in Figure 7 can have a configuration consistent with or similar to the output of the emission driver shown in

[0141] Reference Figure 7 and Figure 9 ,the emission driver 300 can output an emission control signal EM including a plurality of emission cycles.

[0142] In an exemplary embodiment of the inventive concept, the emission control signal EM can be driven in two cycles including two non-emission sections (e.g., two gate-off sections) in one frame. When displaying an image, it may occur that the dimming period DP is not fully represented. For example, when Figure 7 displaying one image only during four or five frames by the driving method shown in

[0143] To further improve the brightness resolution, in an exemplary embodiment of the inventive concept, Figure 7 the outputs of the gate-off sections of some frames of the emission control signal EM shown in

[0144] Accordingly, the change in the output of the gate-off section according to adjacent dimming levels DIL is further subdivided so that the resolution of the display brightness in the dimming of the display device can be further improved.

[0145] However, this is only illustrative, and the outputs of the emission control signal EM between other frame sections can be exchanged with each other.

[0146] Figure 10 is a conceptual diagram showing the dimming for the dimming level according to an exemplary embodiment of the inventive concept.

[0147] Reference Figure 10, the display brightness can be changed according to the change corresponding to the dimming level DIL in the gate-off section of the emission control signal EM.

[0148] The first curve L1 represents the display dimming of white 255 gray scale using a conventional dimming method, and the second curve L2 represents the display dimming of white 255 gray scale using the dimming method according to an exemplary embodiment of the inventive concept.

[0149] In the conventional dimming method in which the emission control signal is supplied for every fourth horizontal period, the display brightness changes at intervals of a predetermined dimming level DIL. Therefore, the dimming in the display device is not natural.

[0150] However, in the display device and its driving method according to an exemplary embodiment of the inventive concept, the width of the gate-off section of the emission control signal in the dimming period changes differently for the dimming level DIL, so that the resolution of the brightness display in the dimming of the display device can be improved. Therefore, when the display device is dimmed, smooth dimming can be observed, and the brightness quality of the display device can be improved.

[0151] Although the inventive concept has been shown and described with reference to exemplary embodiments of the inventive concept, those of ordinary skill in the art will understand that various changes may be made in form and detail without departing from the scope and spirit of the inventive concept as recited in the appended claims.

Claims

1. A display device, comprising: a display unit including a plurality of pixels coupled to a plurality of data lines, a plurality of scan lines, and a plurality of emission control lines; a controller configured to determine a width of a gate-off section of an emission control signal in units of a predetermined horizontal period in response to a dimming signal, the width of the gate-off section of the emission control signal corresponding to a non-emission section of each of a plurality of frames belonging to a dimming period; and an emission driver configured to supply the emission control signal in units of a plurality of consecutive pixel rows through the plurality of emission control lines, wherein the dimming signal includes information on a dimming level corresponding to a display brightness of the display unit, wherein the controller determines a first width in units of one horizontal period of the gate-off section of the emission control signal corresponding to a first reference dimming level among the plurality of dimming levels of the dimming signal, wherein the controller determines a second width different from the first width in units of one horizontal period of the gate-off section of the emission control signal corresponding to a second reference dimming level among the plurality of dimming levels of the dimming signal, wherein an average width of all gate-off sections of the emission control signal in the dimming period is adjusted in units of one horizontal period by determining a number of first off-sections having the first width in the dimming period, a number of second off-sections having the second width in the dimming period, and an order of the first off-sections and the second off-sections in the dimming period, wherein one horizontal period is a period for shifting a scan signal or a period for applying a data signal in a pixel column direction.

2. The display device according to claim 1, wherein, The second reference dimming level is higher than the first reference dimming level, and the second width is greater than the first width.

3. The display device according to claim 2, wherein, The gate-off section of the emission control signal corresponding to each dimming level among the plurality of dimming levels between the first reference dimming level and the second reference dimming level includes a combination of the first off-sections each having the first width and the second off-sections each having the second width in the dimming period.

4. The display device according to claim 3, wherein, In a range between the first reference dimming level and the second reference dimming level, when the dimming level increases, a number of the first off-sections of the emission control signal decreases, and a number of the second off-sections of the emission control signal increases, and, wherein a sum of the number of the first off-sections included in the dimming period and the number of the second off-sections included in the dimming period is constant.

5. The display device according to claim 3, wherein, According to a lapse of frames in the dimming period, an arrangement of the first off-sections and the second off-sections is set differently for the plurality of dimming levels.

6. The display device according to claim 2, wherein, An average width of all gate-off sections of the emission control signal included in each frame in the dimming period is equal to a width of the gate-off section indicated by a corresponding dimming level among the plurality of dimming levels.

7. The display device according to claim 2, wherein, The first width corresponds to k horizontal periods, and the second width corresponds to k + 4 horizontal periods, where k is a multiple of 4.

8. The display device according to claim 7, wherein, The interval between the first reference dimming level and the second reference dimming level corresponds to 4 horizontal periods, and wherein the dimming period corresponds to 4 frames.

9. The display device according to claim 7, wherein, The emission driver outputs the emission control signal having i gate-off periods corresponding to i non-emission sections in one frame, where i is an integer greater than 1, and wherein the dimming period corresponds to 4 * i frames.

10. The display device according to claim 9, wherein, The difference in the dimming levels between the first reference dimming level and the second reference dimming level corresponds to 4 * i horizontal periods.

11. The display device according to claim 9, wherein, When the dimming level among the plurality of dimming levels indicates k * i horizontal periods, each of the widths of the gate-off periods of the emission control signal corresponds to k horizontal periods, wherein when the dimming level among the plurality of dimming levels indicates (k + 4) * i horizontal periods, each of the widths of the gate-off periods of the emission control signal corresponds to k + 4 horizontal periods, and wherein when the dimming level among the plurality of dimming levels indicates the horizontal periods between k * i horizontal periods and (k + 4) * i horizontal periods, the first width corresponds to k horizontal periods, and the second width corresponds to k + 4 horizontal periods.

12. The display device according to claim 1, further comprising: A scan driver configured to sequentially supply scan signals to the (2n - 1)-th pixel row and the 2n-th pixel row through the plurality of scan lines, where n is a natural number, wherein the emission driver supplies the emission control signal to the (2n - 1)-th pixel row and the 2n-th pixel row simultaneously.

Images