Insulated gate field effect transistor structure with shielded source and method

Abstract

The present invention is entitled "Insulated Gate Field Effect Transistor Structure and Method with Shielded Source". The present invention provides a semiconductor device, which includes a semiconductor material region, which includes a semiconductor layer of a first conductivity type and has a first main surface. A body region of a second conductivity type opposite to the first conductivity type is arranged in a second semiconductor layer extending from the first main surface. The body region includes: a first segment having a first doping concentration; and a second segment laterally adjacent to the first segment and adjacent to the first main surface, the second segment having a second doping concentration less than the first doping concentration. A source region of the first conductivity type is arranged in the first segment, but not in at least a portion of the second segment. An insulated gate electrode is arranged adjacent to a semiconductor material region adjacent to the first segment, the second segment, and the source region. A conductive layer is electrically connected to the first segment, the second segment, and the first source region. During a linear operating mode, current first flows in the second segment, but not in the first segment, to reduce the possibility of thermal runaway.

Description

Technical Field

[0001] This document relates generally to semiconductor devices and, more particularly, to insulated gate device structures and methods. Background Art

[0002] Insulated gate field effect transistors (IGFETs), such as metal oxide semiconductor field effect transistors (MOSFETs), have been used in many power switching applications, such as dc-dc converters. In a typical MOSFET, the gate electrode provides on and off control by applying an appropriate gate voltage. By way of example, in an n-type enhancement MOSFET, conduction occurs when a conductive n-type inversion layer (i.e., channel region) is formed in the p-type body region in response to applying a positive gate voltage that exceeds an inherent threshold voltage. The inversion layer connects the n-type source region to the n-type drain region and allows majority carrier conduction between these regions.

[0003] The "safe operating area" or "SOA" of an IGFET device is defined as the voltage and current conditions under which the device can be expected to operate without self-destruction. In general, a typical enhancement-mode IGFET current-voltage output characteristic usually involves three operating conditions: a) the fully on condition, in which the gate-to-source voltage (V GS ) is biased well above the threshold voltage (V T ), and a good conductive channel region connects the source region to the drain region (where the drain-source voltage (V DS ) is low and the drain-source current (I DS ) is a high characteristic); b) off condition, where V GS <V T and no channel region is formed (where V DS is high and I DS is essentially zero); and c) a condition between a and b, where the channel region is clamped, referred to as the linear mode or constant current condition (where V DS and I DS Not low).

[0004] When the IGFET device is operated in the linear mode, the junction temperature (T J ) due to the high power dissipation through the device (this is because V DS and I DS As the junction temperature increases at certain gate biases (below the so-called zero temperature coefficient point), I DSThe current will increase, causing the junction temperature to increase further. This positive feedback effect can lead to a thermal runaway condition, resulting in device failure. This effect can be exacerbated by local current hot spots within the device, which are caused by, for example, local defects, process variations, or bond wire placement. In addition, as the industry continues to strive to reduce on-resistance, smaller clip-on devices have been developed to meet the demand for reduced on-resistance. However, in smaller clip-on devices, the current change with respect to the change in temperature or dI / DT can increase, exacerbating the thermal runaway condition during the linear mode of operation.

[0005] Therefore, there is a need for structures and methods that improve the ability of semiconductor devices, such as IGFET devices, to operate in linear mode conditions. It would be beneficial for such structures and methods to be cost effective and to minimize the impact on other device operating parameters. Summary of the invention

[0006] The present description includes, among other features, structures and methods for improving operation of semiconductor devices, such as insulated gate field effect transistor (IGFET) devices, including power metal oxide semiconductor FET (MOSFET) devices, in a linear operation mode in which higher power consumption occurs. Specifically, a structure and method are provided in which during the linear operation mode, a channel current is configured to flow only in certain sections of the device. In some examples, the structure includes a source region of a first conductivity type having a first section defined below by a first section of a well region of a second conductivity type. In some examples, the first section of the source region is laterally bounded by a second section of the well region, wherein the second section of the well region has a dopant concentration that is less than the dopant concentration of the first section of the well region. In operation, the second section of the well region has a lower threshold voltage V than the first section of the well region. T , and is turned on first to promote lateral and vertical current flow in the device. During the linear mode of operation, no channel is formed in the first section of the well region, which serves to shield the first section of the source region from vertical current flow in order to reduce the possibility of thermal runaway.

[0007] In some examples, the second section of the source region is configured to provide a series ballast resistor to provide negative feedback between current and junction temperature in a linear operating mode (i.e., as temperature increases, the series resistance also increases, thereby reducing the current through the ballast resistor portion of the source region), which improves current uniformity across the device, thereby improving the forward bias safe operating area (FBSOA). In addition, the first section of the well region having an increased dopant concentration is used to improve the on-resistance when the device is in a fully on condition.

[0008] More specifically, in one example, a semiconductor device structure includes a semiconductor material region including a first semiconductor layer of a first conductivity type and having a first main surface. A first body region of a second conductivity type opposite to the first conductivity type is disposed in a first semiconductor layer extending from the first main surface. The first body region includes: a first segment having a first doping concentration; and a second segment laterally adjacent to the first segment and adjacent to the first main surface, the second segment having a second doping concentration less than the first doping concentration. A first source region of the first conductivity type is disposed in the first segment of the body region, but not in at least a portion of the second segment. An insulated gate electrode is disposed adjacent to the semiconductor material region, thereby adjoining the first segment, the second segment, and the first source region. The first conductive layer is electrically connected to the first segment, the second segment, and the first source region. The second conductive layer is adjacent to a second main surface of the semiconductor material region opposite to the first main surface. In another example, the structure may include a ballast resistor structure electrically connected to the first source region, wherein the ballast resistor structure does not physically contact the first conductive layer.

[0009] In another example, the first body region includes a first strip region; and the semiconductor device structure also includes a second body region, the second body region including a second strip region substantially parallel to the first strip region; a second body region first segment having a first doping concentration; and a second body region second segment having a second doping concentration; and a second source region of the first conductivity type, the second source region being disposed in the second body region first segment and laterally offset relative to the first source region.

[0010] In another example, a semiconductor device structure includes a semiconductor material region including a first semiconductor layer of a first conductivity type and having a first main surface. A first body region of a second conductivity type opposite to the first conductivity type is disposed in a first semiconductor layer extending from the first main surface, wherein the first body region includes: a first body region first section having a first doping concentration; and a first body region second section laterally adjacent to the first body region first section and adjacent to the first main surface, the first body region second section having a second doping concentration less than the first doping concentration. A first source region of the first conductivity type is disposed in the first body region first section, but not in at least a portion of the first body region second section. An insulated gate electrode is disposed adjacent to the semiconductor material region, thereby adjoining the first body region first section, the first body region second section, and the first source region. A first conductive layer is disposed in a contact trench and electrically connected to the first body region first section, the first body region second section, and the first source region. In yet another example, the first body region first section extends into the first semiconductor layer to a first depth, and the first body region second section extends into the first semiconductor layer to a second depth different from the first depth.

[0011] In another example, the first doping concentration has a first peak dopant concentration, the second doping concentration has a second peak dopant concentration, and the first peak dopant concentration is at least twice the second peak dopant concentration.

[0012] In another example, a method of forming a semiconductor device structure includes providing a semiconductor material region including a first semiconductor layer of a first conductivity type and having a first main surface. The method includes providing a first body region of a second conductivity type opposite to the first conductivity type, the first body region being disposed in a first semiconductor layer extending from the first main surface, wherein the first body region includes: a first body region first section having a first doping concentration; and a first body region second section laterally adjacent to the first body region first section and adjacent to the first main surface, the first body region second section having a second doping concentration less than the first doping concentration. The method includes providing a first source region of the first conductivity type, the first source region being disposed in the first body region first section, but not disposed in at least a portion of the first body region second section. The method includes providing an insulated gate electrode disposed in the semiconductor material region so as to abut the first body region first section, the first body region second section, and the first source region. The method includes providing a first conductive layer disposed in a contact trench and electrically connected to the first body region first section, the first body region second section, and the first source region.

[0013] In another example, the method also includes providing a ballast resistor structure electrically connected to the first source region, wherein the ballast resistor structure does not physically contact the first conductive layer; and the ballast resistor structure includes a doped region of a first conductivity type disposed within a second segment of the first body region and extending laterally to overlap a portion of the first segment of the first body region.

[0014] Other examples are included in the present disclosure. Such examples can be found in the drawings, in the claims and / or in the description of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 shows a partial top plan view of a semiconductor device according to the present specification;

[0016] Figure 2 The image taken along the reference line 2-2 is shown. Figure 1 A partial cross-sectional view of a semiconductor device;

[0017] Figure 3 The image taken along the reference line 3-3 is shown. Figure 1 A partial cross-sectional view of a semiconductor device;

[0018] Figure 4 The image taken along the reference line 4-4 is shown. Figure 1 A partial cross-sectional view of a semiconductor device;

[0019] Figure 5 A partial cross-sectional view of a semiconductor device according to the present specification is shown;

[0020] Figure 6 A partial cross-sectional view of a semiconductor device according to the present specification is shown;

[0021] Figure 7 shows a partial top plan view of a semiconductor device according to the present specification;

[0022] Figure 8 The image taken along the reference line 8-8 is shown. Figure 7 A partial cross-sectional view of a semiconductor device;

[0023] Fig. 9 The image taken along the reference line 9-9 is shown. Figure 7 A partial cross-sectional view of a semiconductor device;

[0024] Fig.10 A cross-sectional view taken along reference line 10-10 is shown. Figure 7 A partial cross-sectional view of a semiconductor device;

[0025] Fig.11 The image taken along the reference line 11'-11' is shown. Figure 7A partial cross-sectional view of a semiconductor device; and

[0026] Fig.12 The image taken along the reference line 12'-12' is shown. Figure 7 A partial cross-sectional view of a semiconductor device;

[0027] Fig.13 is a graph showing parameter data of the semiconductor device of the present specification compared with related semiconductor devices; and

[0028] Fig.14 is a graph showing additional parameter data of the semiconductor device of the present specification compared with related semiconductor devices.

[0029] To make the illustration concise and clear, the elements in the figure may not be drawn to scale, and the same reference numerals in different figures indicate the same elements. In addition, to make the description concise, the description and details of the well-known steps and elements are omitted. For the clarity of the drawings, certain regions of the device structure such as doped regions or dielectric regions can be shown as having substantially straight edges and corners of precise angles. However, those skilled in the art understand that due to the diffusion and activation of dopants or the formation of layers, the edges of such regions may not be straight lines and the corners may not have precise angles. In addition, the term "main surface" when used in conjunction with a semiconductor region, a wafer or a substrate refers to the following surface of a semiconductor region, a wafer or a substrate: the surface forms an interface with another material (such as a dielectric, an insulator, a conductor or a polycrystalline semiconductor material). The main surface may have morphological features that vary along the x, y and z directions. As used herein, the term "and / or" includes any combination and all combinations of one or more associated items listed. In addition, the terms used herein are only used for the purpose of describing specific examples and are not intended to limit the present disclosure. As used herein, the singular form is intended to also include the plural form, unless the context explicitly indicates other situations. It should also be understood that when the term is used in this specification to include and / or include, the existence of the features, numbers, steps, operations, elements and / or parts is specified, but the existence or addition of one or more other features, numbers, steps, operations, elements, parts and / or their groups is not excluded. It should be understood that although the terms first, second, etc. can be used herein to describe various components, elements, regions, layers and / or sections, these components, elements, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish a component, element, region, layer and / or section from another component, element, region, layer and / or section. Therefore, without departing from the teachings of the present invention, for example, the first component, the first element, the first region, the first layer and / or the first section to be discussed below can be referred to as the second component, the second element, the second region, the second layer and / or the second section. It will be understood by those skilled in the art that the phrases "during", "at the same time" and "when" used herein in connection with circuit operation do not specifically refer to an action occurring immediately after an initiating action, but rather to the possibility that there may be some small but reasonable delay, such as a propagation delay, between the reaction initiated by the initial action. In addition, the term "at the same time" means that an action occurs at least for a period of time during the duration of the initiating action. The words "about", "approximately" or "substantially" are used to indicate that the value of an element is expected to be close to the declared value or position. However, it is well known in the art that there are always some minor deviations that prevent the value or position from being exactly the declared value or position. Unless otherwise indicated, the phrases "above" or "on" used herein include orientations, placements or relationships in which the specified elements may be in direct or indirect physical contact.Unless otherwise indicated, as used herein, the phrase "overlapping with" includes orientations, placements, or relationships in which the specified elements can be at least partially or completely overlapped or aligned on the same plane or on different planes. It should also be understood that the examples that will be appropriately illustrated and described below may have examples lacking any elements not explicitly disclosed herein and / or may be implemented in the absence of any elements not explicitly disclosed herein. DETAILED DESCRIPTION

[0030] Figure 1 A partial top plan view of an electronic device 100 , a semiconductor device structure 100 , or a semiconductor device 100 according to examples of the present description is shown. Figure 2 Shown along Figure 1 A partial cross-sectional view of the semiconductor device 100 taken along the reference line 2-2, Figure 3 Shown along Figure 1 A partial cross-sectional view of the semiconductor device 100 taken along the reference line 3-3 of FIG. Figure 4 Shown along Figure 1 A partial cross-sectional view of the semiconductor device 100 taken along the reference line 4-4. Figure 1 , the semiconductor device 100 is shown without the interlayer dielectric layer 41 and the conductive layer 44, which are Figure 2 , Figure 3 and Figure 4 Shown in.

[0031] The semiconductor device 100 includes a semiconductor material region 11, a semiconductor substrate 11 or a semiconductor region 11, which may include, for example, an N-type conductivity silicon substrate 12 having a resistivity in the range of about 0.001 ohm-cm to about 0.005 ohm-cm. By way of example, the substrate 12 may be doped with phosphorus, arsenic or antimony. In the example shown, the substrate 12 provides a drain region, a drain contact, or a first current-carrying contact for the semiconductor device 100. In this example, the semiconductor device 100 may be formed in an active region 102 of a semiconductor chip or die. Terminal structures and gate and shield electrode contacts are typically made in the peripheral region of the semiconductor device 100, which is not shown here. In this example, the semiconductor device 100 is configured as a vertical power MOSFET structure, but the present description is also applicable to insulated gate bipolar transistors (IGBTs), MOS gated thyristors, and other related or equivalent structures known to those of ordinary skill in the art. The semiconductor material region 11 includes a major surface 18 and an opposite major surface 19.

[0032] Semiconductor device 100 also includes a semiconductor layer 14, a drift region 14, or an extended drain region 14 formed in, on, partially inside, or over substrate 12. In some examples, semiconductor layer 14 may be formed using semiconductor epitaxial growth techniques. Alternatively, semiconductor layer 14 may be formed using semiconductor doping and diffusion techniques. In an example suitable for a 50 volt device, semiconductor layer 14 may be N-type conductive with a dopant concentration of approximately 1.0×10 16 Atom / cm 3 About 1.0×10 17 Atom / cm 3 , and may have a thickness of about 3 microns to about 5 microns. The desired drain-to-source breakdown voltage (BV DSS ) rating to increase or decrease the dopant concentration and thickness of semiconductor layer 14. In other examples, semiconductor layer 14 may have a graded dopant profile in which the dopant concentration varies by increasing or decreasing along the thickness of semiconductor layer 14. Semiconductor layer 14 provides a drift region for semiconductor device 100 and is configured to allow current flow in an on mode of operation and to withstand an applied drain-to-source voltage in an off mode of operation.

[0033] In an alternative example, the conductivity type of substrate 12 can be opposite to the conductivity type of semiconductor layer 14 (e.g., substrate 12 can be P-type conductivity) to form, for example, an IGBT implementation. In addition, it is contemplated that other materials can be used for semiconductor material region 11 or portions thereof, including silicon germanium, silicon germanium carbon, carbon-doped silicon, silicon carbide, gallium nitride, or other related or equivalent materials known to those of ordinary skill in the art.

[0034] In this example and if Figure 2 and Figure 3 As shown, semiconductor device 100 includes an insulated gate electrode 180 or an insulated gate structure 180, which in some examples may include a shielded gate structure including a trench structure 121 or trench 121 extending from main surface 18 into semiconductor material region 11. By way of example, a fluorocarbon chemistry or fluorinated chemistry (e.g., SF 6 / O 2) or other chemically acted plasma etching techniques or removal techniques known to those of ordinary skill in the art to etch the terminal trench 121. Shielding dielectric layer 261 is disposed along the lower surface of trench 121 and is used to isolate shielding electrode 228 from semiconductor material region 11. In some examples, shielding dielectric layer 261 includes one or more dielectric or insulating materials. By way of example, shielding dielectric layer 261 includes a thermal oxide of about 0.1 microns or greater. In other examples, shielding dielectric layer 261 may include one or more deposited dielectric materials. In some examples, shielding electrode 228 includes a doped polycrystalline semiconductor material, such as doped polysilicon. In some examples, shielding electrode 228 may be doped with an N-type conductivity dopant (such as phosphorus or arsenic). Shielding electrode 228 works in particular with other features of semiconductor device 100 to provide charge balance so as to reduce on-resistance.

[0035] The inter-electrode dielectric layer 227 is disposed to cover the shielding electrode 228, and the gate dielectric layer 226 is disposed along the upper sidewall surface of the trench 121. The gate layer 226 and the inter-electrode dielectric layer 227 may be oxides, nitrides, tantalum pentoxide, titanium dioxide, barium strontium titanate, high-k dielectric materials, combinations thereof, or other related or equivalent materials known to those of ordinary skill in the art. In one example, the gate dielectric layer 226 and the inter-electrode dielectric layer 227 may be silicon oxide. In some examples, the thickness of the gate dielectric layer 226 may be about 0.04 microns to about 0.1 microns, and the thickness of the inter-electrode dielectric layer 227 may be greater than the thickness of the gate dielectric layer 226. In some examples, the shielding dielectric layer 261 may have a greater thickness than the gate dielectric layer 226 and the inter-electrode dielectric layer 227.

[0036] The gate electrode 229 is disposed adjacent to the gate dielectric layer 226 and in some examples comprises a doped polycrystalline semiconductor material, a conductive material, or a combination of the two. In some examples, the gate electrode 229 comprises polycrystalline silicon doped with an N-type dopant, such as phosphorus or arsenic. The shield electrode 228 and the gate electrode 229 can be formed using a chemical vapor deposition (CVD) process technique and can be in-situ doped as part of the CVD process or subsequently using, for example, ion implantation and annealing process techniques. The gate electrode 229 is used to control the formation of a channel region in the semiconductor device 100.

[0037] The semiconductor device 100 also includes a body region 31, a base region 31, or a well region 31, which is disposed within the semiconductor material region 11 and extends inwardly from the main surface 18 into the semiconductor layer 14. The body region 31 includes a conductivity type opposite to the semiconductor layer 14, and in this example includes a P-type conductivity dopant (such as boron). The body region 31 can be formed using ion implantation and annealing process techniques or other doping techniques known to those of ordinary skill in the art.

[0038] According to the present specification, the body region 31 includes a plurality of segments or regions with different doping concentrations along its lateral extent or lateral dimension. More specifically, the body region 31 can be configured to have a strip shape with a laterally segmented body region structure, a multi-segment body region structure, or a multi-part body region structure. In some examples, the body region 31 includes a first segment 31A and a second segment 31B. In some examples, the body region 31 also includes a third segment 31C, which is laterally disposed between the first segment 31A and the second segment 31B.

[0039] According to the present specification, the first section 31A has a higher dopant concentration than the second section 31B, and the first section 31A can extend into the semiconductor material region 11 to a depth 310A greater than the depth 310B of the second section 31B. In some examples, the depth 310A is in a range of about 0.5 microns to about 2.0 microns, and the depth 310B is in a range of about 0.5 microns to about 2.0 microns. In some examples, the depth 310A and the depth 310B can be equal depending on the gate length, but in most examples, the depth 310A and the depth 310B are shallower than the gate electrode 229. The first section 31A can also be referred to as a high or higher concentration region 31A, and the second section 31B can be referred to as a low or lower concentration region 31B.

[0040] In some examples, the peak dopant concentration of first segment 31A is about twice or 2X the peak dopant concentration of second segment 31B. In some examples, the difference depends on the defined threshold voltage (V T ) requirements, which depend on the desired SOA relative to R dsonIn other examples, the peak dopant concentration of the first segment 31A is about 1.75X the peak dopant concentration of the second segment 31B. In another example, the peak dopant concentration of the first segment 31A is about 1.5X the peak dopant concentration of the second segment 31B. In yet another example, the peak dopant concentration of the first segment 31A is about 1.25X or more the peak dopant concentration of the second segment 31B. When used, the third segment 31C can have a dopant concentration between the first segment 31A and the second segment 31B, and can be configured as a transition region between the first segment 31A and the second segment 31B. In other examples, the third segment 31C can have a dopant concentration similar to the second segment 31B.

[0041] The dopant concentration of the body region 31 determines the threshold voltage (V T ), wherein an inversion layer operating as a conductive channel of the semiconductor device 100 is formed. In the present example, a first channel region 45A or channel 45A is formed in the first section 31A at a first threshold voltage, and a second channel region 45B or channel 45B is formed in the second section 31B at a second threshold voltage less than the first threshold voltage. Although not shown, a third channel region is formed in the third section 31C at a third threshold voltage between the first threshold voltage and the second threshold voltage. As will be described in more detail later, the doping concentrations of the first section 31A and the second section 31B are selected so that under a selected gate bias, the channel region 45B is formed during the linear operation mode of the semiconductor device, while the channel region 45A is not formed in the first section 31A. In this way, vertical conduction does not occur in the first section 31A during the linear operation mode.

[0042] Individual stripe portions of body region 31 may be connected to other stripe portions along one or more ends to provide a common base structure. In other examples, the stripe portions may be separate regions. In some examples, the depth 310A of first segment 31A is such that the junction formed between first segment 31A and semiconductor layer 14 is less than or close to the lower extent of gate electrode 229. In some examples, third segment 31C may have a depth similar to second segment 31B. In other examples, third segment 31C may have a depth between first segment 31A and second segment 31B.

[0043] Source region 33, current conducting region 33, or current carrying region 33 is disposed within, in, or above body region 31 and may extend from primary surface 18 to a depth of, for example, about 0.2 microns to about 0.4 microns. In some examples, source region 33 may have N-type conductivity and may be formed using, for example, a phosphorus or arsenic dopant source. By way of example, an ion implantation and annealing process may be used to form source region 33 within a selected portion of body region 31 using a masking technique.

[0044] According to the present specification, the source regions 33 are segmented regions (i.e., they are not continuous strips as in prior devices) and are disposed only within the first section 31A of the doped region 31, and when used, the source regions 33 may be further disposed within the third section 31C of the doped region 31. More specifically, the source regions 33 are not disposed within at least a portion of the second section 31B, such as in Figure 1 , Figure 3 and Figure 4 In other words, all or part of the second segment 31B is configured to lack or not have a source region 33. In this way, the source region 33 is shielded by the higher concentration first segment 31A, which cuts off the vertical current path in the linear operation mode within the first segment 31A. It should be noted that Figure 1 In FIG. 1 , the segmented source region 33 is represented using gray shading to illustrate that the source region 33 is disposed in the first segment 31A and the third segment 31C but not in the second segment 31B.

[0045] In some examples and as in Figure 1 , the first segments 31A and source regions 33 in a first column 100A of the semiconductor device 100 are laterally offset from the first segments 31A and source regions 33 in an adjacent second column 100B. More specifically, the first segments 31A and source regions 33 in the first column 100A are staggered relative to the first segments 31A and source regions 33 in the adjacent column 100B, which was unexpectedly found to help reduce the impact of the shielded source configuration on the on-resistance of the semiconductor device 100.

[0046] In some examples, the semiconductor device 100 also includes one or more layers 41 disposed above the main surface 18. By way of example, layer 41 includes one or more dielectric or insulating layers and can be configured as an interlayer dielectric (ILD) structure to electrically isolate a region of the semiconductor device 100 from a subsequent interconnect layer. In one example, layer 41 can be silicon oxide, such as doped or undoped deposited silicon oxide. In another example, layer 41 can include at least one layer of deposited silicon oxide doped with phosphorus or boron and phosphorus and at least one layer of undoped oxide. Layer 41 can have a thickness of about 0.4 microns to about 1.0 microns. In other examples, layer 41 can be planarized to provide a more uniform surface morphology, which improves manufacturability. Layer 41 is used to protect various regions of the semiconductor device 100.

[0047] In some examples, contact trenches 422 may be formed for contacting the source region 33 and the body region 31 including segments 31A-31C. In one embodiment, recess etching may be used to remove portions of the source region 33 and the doped region 31 to provide the contact trenches 422. The recess etching step may expose portions of the body region 31 below and near the source region 33. Additionally, a P-type body contact, enhancement region, or contact region (not shown) may be formed in the body region 31, which may be configured to provide a lower contact resistance to the body region 31. In some examples, contact with the source region 33 occurs primarily along the vertically oriented side surface having the contact trenches 422.

[0048] Conductive layer 44 may be formed to cover major surface 18, and conductive layer 46 may be formed to cover major surface 19. Conductive layers 44 and 46 may be configured to provide electrical connections between individual device components of semiconductor device 100 and next-level components. As previously described, electrical contact with gate electrode 229 and shield electrode 228 may be made in the peripheral portion of semiconductor device 100 using, for example, a trench contact structure.

[0049] In one example, the conductive layer 44 may be titanium / titanium nitride / aluminum copper or other related or equivalent materials known to those of ordinary skill in the art, and is configured as a source electrode or terminal. In one example, the conductive layer 46 may be a weldable metal structure, such as titanium nickel silver, chrome nickel gold, or other related or equivalent materials known to those of ordinary skill in the art, and is configured as a drain electrode or terminal. In some examples, a patterned passivation layer (not shown) may be formed to cover the conductive layer 44. In other examples, the shield electrode 228 may be connected (e.g., using a peripheral contact structure) to the conductive layer 44 so that when the semiconductor device 100 is operating, the shield electrode 228 is configured to be at the same potential as the source region 33. In other examples, the shield electrode 228 may be configured to be independently biased or may be electrically floating.

[0050] In the linear mode of operation of the semiconductor device 100 according to the present specification, it is assumed that the source electrode 44 and the shield electrode 228 are at a potential V of zero volts. S The gate electrode 229 will receive a control voltage V sufficient to form a channel 45B in the second section 31B of the doped region 31. G (3.0 volts to 5.0 volts in some examples), thereby turning on the semiconductor device 100 from the off state. At this point and in accordance with this specification, the control voltage V G As the semiconductor device 100 transitions from the off state, the drain-to-source voltage (V DS ) will initially be high (about 50 volts in some examples) and then drop to a lower voltage once semiconductor device 100 transitions to full conduction. During linear mode conditions, drain current I D will also be high, but will first flow vertically through channel 45B only within second section 31B and then laterally to source region 33. In the linear mode of operation, since V G is smaller than V of the first section 31A T When the channel 45A is not formed, the drain current I D does not flow vertically in the first section 31A. It should be noted that when the third section 31C is used, once V G It is sufficient to form a channel in the third section 31C or in the transition region between the first section 31A and the second section 31B, and some vertical conduction can occur in this region.

[0051] According to the present specification, because the source region 33 is shielded by the first section 31A of the doped region 31 (which has a higher doping concentration than the second section 31B of the doped region 31), the vertical current flow into the shielded source region 33 is reduced or prevented. Therefore, the shielded source region 33 exhibits less current increase at higher temperatures. Therefore, the inherent positive feedback effect between current and temperature observed in existing devices is suppressed. This improves the stability of the semiconductor device 100. When the semiconductor device 100 is operated in a fully on operating mode (i.e., V G Equal to V of the first section 31A T ), a channel 45A in the first section 31A of the body region 31 is formed and can facilitate current flow, thereby reducing any higher on-resistance effects exhibited prior to forming the channel 45A.

[0052] It should be understood that the length or size of the second section 31B and the first section 31A / third section 31C may be different depending on the location within the semiconductor device 100. That is, the length or size in the center of the semiconductor device 100 may be different than the length or size at the edge region of the semiconductor device 100. For example, the ratio of the length or size of the first section 31A to the length or size of the second section 31B may be smaller at the edge region of the semiconductor die 100 because the temperature effects may be less extreme at the edge region than at the center portion of the semiconductor device 100. Figure 1 and Figure 4 As shown, the source region 33 may extend laterally beyond the first segment 31A of the doped region 31. The above-described variations allow for additional fine-tuning of the semiconductor device 100 to improve performance during the linear mode of operation.

[0053] By way of example, Figure 5 A partial cross-sectional view of a variation of a semiconductor device according to the present specification is shown, in which the third section 31C is excluded and the source region 33 extends to a position close to the beginning of the second section 31B. By way of further example, Figure 6 1 shows a partial cross-sectional view of another variation of the semiconductor device according to the present specification, which includes a third section 31C, the first section 31A has a smaller lateral width, and the source region 33 extends into the second section 31B. It should be understood that Figure 5 and Figure 6 The examples can be combined as a combination of Figures 1 to 4 1. A portion of an example semiconductor device 100 is shown.

[0054] Figure 7 A partial top plan view of an electronic device 200 , a semiconductor device structure 200 , or a semiconductor device 200 according to examples of the present description is shown. Figure 8 Shown along Figure 7 A partial cross-sectional view of the semiconductor device 200 taken along the reference line 8-8, Fig. 9 Shown along Figure 7 A partial cross-sectional view of the semiconductor device 200 taken along the reference line 9-9, Fig.10 Shown along Figure 7 A partial cross-sectional view of the semiconductor device 200 taken along the reference line 10 - 10 , Fig.11 Shown along Figure 7 A partial cross-sectional view of the semiconductor device 200 taken along a reference line 11'-11', and Fig.12 Shown along Figure 7 1 is a partial cross-sectional view of the semiconductor device 200 taken along the reference line 12'-12' of FIG. The semiconductor device 200 is similar to the semiconductor device 100, and only the differences will be described in detail below.

[0055] According to this manual, Figure 7 The adjacent source regions 33 within the illustrated columns 200A, 200B, and 200C are electrically connected or interconnected with source ballast resistor structures 330 or ballast resistors 330. That is, in semiconductor device 200, the source structure is segmented and includes source regions 33 and connected ballast resistors 330. In some examples, ballast resistors 330 include a diffusion region disposed within body region 31 and include N-type conductivity dopants.

[0056] In this example, Figure 7 A lighter grey shade is used to represent the source region 33. Figure 7 The ballast resistor 330 is represented by a darker gray shade in FIG. According to the present example, the source region 33 is disposed within and shielded by the first section 31A or the higher concentration region 31A of the doped region 31. In some examples, the ballast resistor 330 extends to laterally overlap a portion of the first section 31A, wherein the ballast resistor 330 is connected to or contacts the source region 33, and laterally extends across the second section 31B or the lower concentration region 31B of the doped region 31, such as Figure 7 and Figure 8 In some examples, source regions 33 in a first column (eg, column 200A) are offset or staggered relative to source regions 33 in an adjacent column (eg, column 200B), which is unexpectedly found to help reduce the impact of the shielded source configuration on the on-resistance of the semiconductor device 200.

[0057] like Figure 7 As shown, the lateral width of the ballast resistor 330 is less than the lateral width of the source region 33. In this way, the ballast resistor is laterally separated or laterally spaced apart from the contact trench 422 so that the conductive layer 44 does not directly physically contact the ballast resistor 330. Instead, a portion of the first segment 31A and the second segment 31B is laterally interposed between the conductive layer 44 and the ballast resistor 330, as shown in FIG. Figure 7 , Fig.11 and Fig.12 In this example, the conductive layer 44 electrically contacts the source region 33 only through the contact groove 442, as shown in FIG. Fig.10 As shown generally in .

[0058] Similar to the semiconductor device 100, the threshold voltage of the second segment 31B is lower than the threshold voltage of the first segment 31A. Therefore, at a selected gate voltage V lower than the threshold voltage of the first segment 31A, GIn this case, the channel region 45B is first formed in the second section 31B, and the device current flows vertically in the second section 31B and then flows laterally through the ballast resistor 330 to the source region 33 in a linear operation mode. Similar to the semiconductor device 100, when the gate voltage V G Below the threshold voltage of the first segment 31A, the device current does not flow vertically within the first segment 31A, such that the first segment 31A serves to shield the source region 33 and prevent any vertical current from flowing directly to the source region 33. During the linear mode of operation, the ballast resistor 330 is configured to control the amount of current flow, such that as the junction temperature increases, the resistance of the ballast resistor 330 increases, thereby controlling or limiting the current flow in the semiconductor device 200. In this way, a negative feedback effect is provided, thereby reducing the likelihood of thermal runaway occurring during the linear mode of operation, as observed in prior devices.

[0059] Similar to the semiconductor device 100, when the semiconductor device 200 is operated in the full-on operation mode (ie, V G Equal to V of the first section 31A T ), a channel 45A in the first section 31A of the body region 31 is formed and can facilitate current flow, thereby reducing any higher on-resistance effects exhibited before the formation of the channel 45A. Since the semiconductor device 200 uses an N-type diffused resistor structure in this example, the semiconductor device 200 exhibits a lower on-resistance than the semiconductor device 100. In some examples, this helps the source region 33 in the semiconductor device 200 require less contact area than the semiconductor device 100.

[0060] Fig.13 is a graph showing the relationship between total drain current and gate overvoltage at about 25 degrees Celsius and about 155 degrees Celsius, which compares the semiconductor device 100 of the present invention with a prior art MOSFET device having a continuous source region strip. Curve 130A is the prior art MOSFET device at 25 degrees Celsius, curve 130B is the prior art MOSFET device at 155 degrees Celsius, curve 131A is the semiconductor device 100 at 25 degrees Celsius, and curve 131B is the semiconductor device 100 at 155 degrees Celsius. In this analysis, the drain voltage V D is 50 volts. Fig.13 As shown, the semiconductor device 100 having the shielded source region 33 has less incremental current increase at higher temperatures than the prior art MOSFET device. More specifically, this shows that the semiconductor device 100 suppresses the positive feedback effect found in prior art MOSFET devices, where current flow increases more dramatically as temperature increases. This provides improved thermal stability for the semiconductor device 100 compared to prior art MOSFET devices.

[0061] Fig.14 is a graph showing a comparison of the increase in forward bias SOA (FBSOA) in percent (%) and the trade-off increase in on-resistance (Rdson) in percent (%). Data point 140A represents the prior art MOSFET device described previously, data set 140B is for an exemplary semiconductor device 200, and data set 140C is for an exemplary semiconductor device 100. These results show that the example of semiconductor device 200 exhibits an increase of about 150% to about 190% in FBSOA compared to the prior art MOSFET device, while only exhibiting an increase of about 5% to about 20% in on-resistance. In addition, these results show that the example of semiconductor device 100 exhibits an increase of about 250% to about 350% in FBSOA compared to the prior art MOSFET device, while exhibiting an increase of about 85% to about 145% in on-resistance. This data also shows that semiconductor device 200 has better on-resistance performance than semiconductor device 100, but semiconductor device 100 has better FBSOA performance than semiconductor device 200.

[0062] The semiconductor devices 100 and 200 are suitable for use in power applications where, among other things, improved FBSOA performance is important and an associated increase in on-resistance is acceptable. Such applications include, but are not limited to, hot-swap applications.

[0063] Based on all of the foregoing, one of ordinary skill in the art can determine that, according to one example, the first doping concentration has a first peak dopant concentration; the second doping concentration has a second peak dopant concentration; and the first peak dopant concentration is approximately twice the second peak dopant concentration.

[0064] Based on all of the foregoing, a person of ordinary skill in the art can determine that, according to one example, the first body region includes a first strip region; and the semiconductor device structure also includes a second body region, the second body region including a second strip region substantially parallel to the first strip region; a second body region first segment having a first doping concentration; and a second body region second segment having a second doping concentration; and a second source region of the first conductivity type, the second source region being disposed within the second body region first segment and laterally offset relative to the first source region. In another example, the first body region first segment has a first width; and the second body region first segment has a second width different from the first width.

[0065] Based on all of the foregoing, a person of ordinary skill in the art can determine that, according to one example, a method of forming a semiconductor device structure includes: providing a semiconductor material region, the semiconductor material region including a first semiconductor layer of a first conductivity type and having a first main surface; providing a first body region of a second conductivity type opposite to the first conductivity type, the first body region being disposed in a second semiconductor layer extending from the first main surface, wherein the first body region includes: a first segment of a first body region having a first doping concentration; and a second segment of a first body region laterally adjacent to the first segment of the first body region and adjacent to the first main surface, the first body region second segment having a second doping concentration less than the first doping concentration; providing a first source region of the first conductivity type, the first source region being disposed in the first segment of the first body region, but not in at least a portion of the second segment of the first body region; providing an insulated gate electrode, the insulated gate electrode being disposed in a semiconductor material region adjacent to the first segment of the first body region, the second segment of the first body region, and the first source region; and providing a first conductive layer, the first conductive layer being disposed in a contact trench and electrically connected to the first segment of the first body region, the second segment of the first body region, and the first source region.

[0066] In another example, the method also includes providing a ballast resistor structure electrically connected to the first source region, wherein the ballast resistor structure does not physically contact the first conductive layer; and the ballast resistor structure includes a doped region of the first conductivity type, which is disposed within the second segment of the first body region and extends laterally to overlap with a portion of the first segment of the first body region.

[0067] In another example, the method includes providing a first body region, the first body region including providing a first stripe region; and the method also includes providing a second body region, the second body region including a second stripe region substantially parallel to the first stripe region; a second body region first segment having a first doping concentration; and a second body region second segment having a second doping concentration; and providing a second source region of the first conductivity type, the second source region being disposed within the second body region first segment and laterally offset relative to the first source region.

[0068] In yet another example, providing the first body region includes providing a first body region first segment having a first width; and providing the second body region includes providing a second body region first segment having a second width different from the first width.

[0069] In view of all of the above, it is apparent that a novel method and structure are disclosed. Specifically, a structure and method are provided in which during a linear mode of operation, a channel current is configured to flow only in certain sections of the device. In some examples, the structure includes a source region of a first conductivity type having a first section defined below by a first section of a well region of a second conductivity type. In some examples, the first section of the source region is laterally bounded by a second section of the well region, wherein the second section of the well region has a dopant concentration less than the dopant concentration of the first section of the well region. In operation, the second section of the well region has a lower threshold voltage V than the first section of the well region. T , and is turned on first to promote lateral and vertical current flow in the device. During the linear mode of operation, no channel is formed in the first section of the well region, which serves to shield the first section of the source region from vertical current flow in order to reduce the possibility of thermal runaway.

[0070] In some examples, the second section of the source region is configured to provide a series ballast resistor to provide negative feedback between the current and the junction temperature in a linear operating mode (i.e., as the temperature increases, the series resistance also increases, thereby reducing the current through the source region ballast resistor portion), which improves the current uniformity across the device, thereby improving the forward bias safe operating area (FBSOA). In addition, when the device is in a fully on condition, the first section of the well region with an increased dopant concentration is used to improve the on-resistance. In one embodiment, the device may include all of the above features. In another embodiment, the device may include at least one of the described features. In another embodiment, the device may include at least two of the described features. In another embodiment, the device may include at least three of the described features. In yet another embodiment, the device may include at least four of the described features.

[0071] Although the subject matter of the present invention is described in conjunction with specific preferred embodiments and exemplary embodiments, the aforementioned drawings and their descriptions are only used to describe typical embodiments of the subject matter of the present invention and should not be considered as limiting the scope of the subject matter of the present invention. It is obvious that many alternatives and variations will be apparent to those skilled in the art. For example, the subject matter has been described for a specific n-channel MOSFET structure with a narrow trench shielded gate, but the method and structure can be directly applied to other MOS transistors, such as unshielded MOS transistors and planar gate MOS transistors, as well as bipolar, BiCMOS, metal semiconductor FET (MESFET), HFET, thyristor, bidirectional transistor, and other transistor structures.

[0072] As reflected in the claims below, aspects of the present invention may have fewer than all of the features of a single embodiment disclosed herein. Therefore, the claims expressed below are hereby expressly incorporated into the detailed description, and each claim itself represents an independent embodiment of the present invention. In addition, although some embodiments described herein include some features included in other embodiments, but do not include other features included therein, it should be understood by those skilled in the art that the combination of features of different embodiments is intended to fall within the scope of the present invention and is intended to form different embodiments.

Claims

1. A semiconductor device structure, comprising: a semiconductor material region comprising a first semiconductor layer of a first conductivity type and having a first major surface; A first body region of a second conductivity type, the second conductivity type being opposite to the first conductivity type, the first body region being arranged in a first semiconductor layer extending from the first main surface, wherein the first body region comprises: a first region having a first doping concentration; and a second section laterally adjacent to the first section and adjacent to the first major surface, the second section having a second doping concentration less than the first doping concentration; a first source region of the first conductivity type, the first source region being disposed in the first section of the body region but not disposed in at least a portion of the second section; an insulated gate electrode disposed adjacent to the semiconductor material region, the semiconductor material region adjoining the first section and configured to provide a first channel in the first section, adjoining the second section and configured to provide a second channel in the second section, and adjoining the first source region; a first conductive layer electrically connected to the first segment, the second segment, and the first source region; and A second conductive layer is adjacent to a second major surface of the region of semiconductor material opposite the first major surface.

2. The semiconductor device structure according to claim 1, further comprising: A ballast resistor structure is electrically connected to the first source region, wherein the ballast resistor structure does not physically contact the first conductive layer.

3. The semiconductor device structure according to claim 2, wherein: The ballast resistor structure includes a doped region of the first conductivity type disposed within the first body region; and The doped region is disposed within the second segment and extends laterally to overlap a portion of the first segment.

4. The semiconductor device structure according to claim 1, wherein: The first segment extends into the first semiconductor layer to a first depth; The second segment extends into the first semiconductor layer to a second depth; and The first depth is greater than the second depth.

5. The semiconductor device structure according to claim 1, wherein: The first body region includes a first stripe region; and The semiconductor device structure further includes: A second body region, the second body region comprising: a second stripe region, the second stripe region being substantially parallel to the first stripe region; a second body region first section, the second body region first section having the first doping concentration; and a second body region second section, the second body region second section having the second doping concentration; and A second source region of the first conductivity type is disposed in the first section of the second body region and is laterally offset relative to the first source region.

6. The semiconductor device structure according to claim 5, wherein: The first section of the first body region has a first width; The second body region first section has a second width; and The second width is smaller than the first width.

7. The semiconductor device structure according to claim 1, wherein: the first body region includes a third segment laterally interposed between the first segment and the second segment; The third section comprises a third doping concentration between the first doping concentration and the second doping concentration; and The first source region extends laterally into at least a portion of the third segment.

8. A semiconductor device structure, comprising: a semiconductor material region comprising a first semiconductor layer of a first conductivity type and having a first major surface; A first body region of a second conductivity type, the second conductivity type being opposite to the first conductivity type, the first body region being arranged in a first semiconductor layer extending from the first main surface, wherein the first body region comprises: a first body region first section, the first body region first section having a first doping concentration; and a first body region second section, the first body region second section being laterally adjacent to the first body region first section and adjacent to the first main surface, the first body region second section having a second doping concentration that is less than the first doping concentration; a first source region of the first conductivity type, the first source region being disposed in the first section of the first body region but not disposed in at least a portion of the second section of the first body region; an insulated gate electrode disposed adjacent to the semiconductor material region, the semiconductor material region adjoining the first body region first section and configured to provide a first channel in the first body region first section, adjoining the first body region second section and configured to provide a second channel in the first body region second section, and adjoining the first source region; and A first conductive layer is disposed in the contact trench and is electrically connected to the first body region first section, the first body region second section, and the first source region.

9. The semiconductor device structure according to claim 8, further comprising: a ballast resistor structure electrically connected to the first source region, wherein the ballast resistor structure does not physically contact the first conductive layer, wherein the ballast resistor structure comprises: The doped region of the first conductivity type is disposed in the second section of the first body region and extends laterally to overlap a portion of the first section of the first body region.

10. The semiconductor device structure according to claim 8, wherein: The first body region first section extends into the first semiconductor layer to a first depth; and The first body region second section extends into the first semiconductor layer to a second depth different from the first depth.

11. The semiconductor device structure according to claim 8, wherein: The first doping concentration has a first peak dopant concentration; The second doping concentration has a second peak dopant concentration; and The first peak dopant concentration is twice the second peak dopant concentration.

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