Organic light emitting diode display device and emissive display device

Abstract

An organic light-emitting diode display device and an emissive display device are provided. The organic light-emitting diode display device includes a lower substrate, a subpixel structure, an upper substrate, a sealant, and a first power supply wiring. The lower substrate has a display area, a peripheral area, and a pad area. The subpixel structure is disposed in the display area on the lower substrate. The upper substrate is disposed on the subpixel structure. A sealant is disposed in the peripheral area between the lower substrate and the upper substrate. A first power supply wiring is disposed between the lower substrate and the sealant and overlaps the lower substrate and the sealant. The first power supply wiring includes a first protrusion protruding in a first direction in the first peripheral area, the first direction being a direction from the pad area to the display area.

Description

Technical Field

[0001] The present disclosure relates to an organic light emitting diode display device, and more particularly, to an organic light emitting diode (OLED) display device including a power wiring. Background Art

[0002] Flat panel display devices have rapidly replaced cathode ray tube (CRT) display devices because they are lighter and thinner than CRT display devices with equivalent display areas. Liquid crystal display (LCD) devices and organic light emitting diode (OLED) display devices are common examples of flat panel display devices.

[0003] An organic light emitting diode (OLED) display device may include a display area, a peripheral area surrounding the display area, and a pad area located on one side of the peripheral area. A plurality of pixel circuits and a plurality of organic light emitting diodes may be provided in the display area. Power wiring and a sealant may be provided in the peripheral area. In addition, a plurality of pad electrodes may be provided in the pad area. For example, a low power supply voltage may be generated from an external device, and the low power supply voltage may be provided to the power wiring through the pad electrode. In addition, the low power supply voltage applied to the power wiring may be provided to the cathode electrode of the organic light emitting diode. In addition, the power wiring provided in the peripheral area adjacent to the pad area may not overlap with the sealant. In this way, the power wiring is arranged parallel to the sealant in the peripheral area adjacent to the pad area. This arrangement creates a relatively large dead space of the organic light emitting diode display device where no image is displayed. Summary of the Invention

[0004] According to some exemplary embodiments of the present invention, an organic light-emitting diode display device includes a lower substrate, a subpixel structure, an upper substrate, a sealant, and a first power wiring. The lower substrate includes a display area, a peripheral area at least partially surrounding the display area, and a pad area located on one side of the peripheral area. The subpixel structure is disposed in the display area on the lower substrate. The upper substrate is disposed on the subpixel structure. A sealant is disposed in the peripheral area between the lower substrate and the upper substrate. The sealant includes a first sealing portion and a second sealing portion, the first sealing portion being located in a first peripheral area of ​​the peripheral area adjacent to the pad area, and the second sealing portion being located in a second peripheral area of ​​the peripheral area different from the first peripheral area. A first power wiring is disposed between the lower substrate and the sealant. The first power wiring overlaps both the lower substrate and the sealant. The first power wiring includes a first protrusion protruding from a first side of the first sealing portion along a first direction in the first peripheral area. The first direction is a direction from the pad area to the display area.

[0005] In an exemplary embodiment of the present inventive concept, the first power wiring may further include a second protrusion protruding from a second side of the first sealing portion in a second direction opposite to the first direction in the first peripheral region.

[0006] In an exemplary embodiment of the present inventive concept, the organic light emitting diode display device may further include a plurality of pad electrodes disposed in the pad region, and the pad electrodes may be arranged along a third direction orthogonal to the first direction and the second direction.

[0007] In an exemplary embodiment of the present inventive concept, the first protrusion may be adjacent to the sub-pixel structure, and the second protrusion may be adjacent to the pad electrode.

[0008] In an exemplary embodiment of the present inventive concept, the first power wiring may include a first wiring portion located in a portion of the first peripheral region and a second wiring portion located in the second peripheral region. The first wiring portion and the second wiring portion may be a single integrated unit, and the first power wiring may have a ring shape including an open lower portion.

[0009] In an exemplary embodiment of the present inventive concept, the organic light emitting diode display device may further include a second power wiring disposed within the first power wiring in the first peripheral region on the lower substrate. A high power voltage may be applied to the second power wiring.

[0010] In an exemplary embodiment of the present inventive concept, a first width of a first wiring portion of the first power wiring measured in the first direction may be greater than a second width of a second wiring portion of the first power wiring measured in a direction from the second peripheral area to the display area.

[0011] In an exemplary embodiment of the present inventive concept, the first power wiring may further include a third protrusion protruding from the second sealing portion in the second peripheral region in a direction from the second peripheral region to the display region.

[0012] In an exemplary embodiment of the present inventive concept, the first power wiring located in the second peripheral area may include a first end corresponding to the third protrusion protruding from the second sealing portion and a second end opposite to the first end, and the second sealing portion may cover the second end.

[0013] In an exemplary embodiment of the present inventive concept, the first sealing portion and the second sealing portion may be a single integrated unit.

[0014] In an exemplary embodiment of the present inventive concept, the subpixel structure may include a lower electrode disposed on a lower substrate, a light-emitting layer disposed on the lower electrode, and an upper electrode disposed on the light-emitting layer. A low power supply voltage may be applied to a first power supply wiring and may be provided to the upper electrode through the first power supply wiring.

[0015] In an exemplary embodiment of the present inventive concept, the organic light emitting diode display device may further include a connection pattern disposed between the upper electrode and the first power wiring. The upper electrode may be electrically connected to the first power wiring through the connection pattern.

[0016] In exemplary embodiments of the present inventive concept, the connection pattern may be formed simultaneously with the lower electrode using the same material.

[0017] In an exemplary embodiment of the present inventive concept, the organic light emitting diode display device may further include a semiconductor element disposed between the sub-pixel structure and the lower substrate, and a planarization layer disposed between the semiconductor element and the sub-pixel structure.

[0018] In an exemplary embodiment of the present invention, the semiconductor element may include an active layer arranged in a display area on a lower substrate, a gate insulating layer arranged on the active layer, a gate electrode arranged on the gate insulating layer, an interlayer insulating layer arranged on the gate electrode, and a source electrode and a drain electrode arranged on the interlayer insulating layer.

[0019] In an exemplary embodiment of the present inventive concept, the first power wiring may be located on the same layer as the source electrode and the drain electrode.

[0020] In an exemplary embodiment of the present inventive concept, the first sealing portion may contact the first power wiring, and the second sealing portion may contact each of the first power wiring and the interlayer insulating layer.

[0021] In an exemplary embodiment of the present inventive concept, the first power wiring may be separated from the planarization layer.

[0022] In an exemplary embodiment of the present inventive concept, the sealant may have a substantially rectangular planar shape having an opening exposing the display area in a plan view.

[0023] In an exemplary embodiment of the present inventive concept, a total length of the second peripheral region and the pad region extending in the first direction may be 2.22 mm or less.

[0024] In the organic light emitting diode display device according to an exemplary embodiment of the present invention, since the first power wiring at least partially overlaps the sealant in the first peripheral region, the dead space in the first peripheral region can be reduced. Therefore, the organic light emitting diode display device can be used as a full-screen display device, which is understood as a display device in which an image is displayed up to the edge of the display device without any visible border.

[0025] Furthermore, the first power supply wiring provided in the first peripheral region may have a relatively large first width, so that wiring resistance may be reduced. Therefore, the driving voltage and power consumption of the organic light emitting diode display device may be reduced.

[0026] Furthermore, the power wiring can serve as both a wiring capable of providing a low power supply voltage and a metal layer capable of absorbing and reflecting laser energy. Therefore, there is no need to additionally provide a metal layer capable of absorbing and reflecting laser energy, thereby reducing the manufacturing cost of the organic light-emitting diode display device.

[0027] According to some exemplary embodiments of the present invention, an emissive display device includes a base substrate, a first power wiring, a second power wiring, a top substrate, and a sealant. The base substrate includes a display area, a pad area, a first peripheral area, and a second peripheral area, an image is displayed in the display area, a plurality of connection pads are arranged in the pad area, the first peripheral area is arranged between the display area and the pad area, and the second peripheral area at least partially surrounds the display area. The first power wiring is arranged in the first peripheral area of ​​the base substrate. The second power wiring is arranged in the second peripheral area of ​​the base substrate. The top substrate is formed on the base substrate. The sealant is arranged between the base substrate and the top substrate and surrounds the display area of ​​the base substrate. The first power wiring is arranged between the sealant and the base substrate to overlap with the sealant. A portion of the second power wiring is arranged between the display area and the sealant so as not to overlap with the sealant. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Exemplary embodiments of the present inventive concept may be understood in more detail through the following description in conjunction with the accompanying drawings, in which:

[0029] Figure 1 is a plan view showing an organic light emitting diode display according to an exemplary embodiment of the present invention;

[0030] Figure 2 It is shown that the Figure 1 A plan view of power supply wiring in an organic light emitting diode display;

[0031] Figure 3 It shows the settings Figure 2 A plan view of the sealant on the power wiring;

[0032] Figure 4 is shown electrically connected to Figure 2 a block diagram of an external device of an organic light emitting diode display device;

[0033] Figure 5 It shows the settings Figure 2 a circuit diagram of a sub-pixel circuit and an organic light emitting diode in a sub-pixel circuit region;

[0034] Figure 6 It is along Figure 2 A sectional view taken along line II' in FIG.

[0035] Figure 7 It is along Figure 2 A sectional view taken along line II-II';

[0036] Figures 8 to 17 is a cross-sectional view illustrating a method of manufacturing an organic light emitting diode display device according to an exemplary embodiment of the present invention;

[0037] Figure 18 is a plan view showing an organic light emitting diode display device according to an exemplary embodiment of the present invention;

[0038] Figure 19 It is along Figure 18 A sectional view taken along line III-III' in FIG.

[0039] Figure 20 It is along Figure 18 A cross-sectional view taken along line IV-IV'. DETAILED DESCRIPTION

[0040] Hereinafter, an organic light emitting diode display device and a method for manufacturing an organic light emitting diode display device according to exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the drawings and the description, the same or similar reference numerals may represent the same or similar elements. Similar elements are elements that are different but perform similar or identical functions in a similar or identical manner.

[0041] Figure 1 is a plan view illustrating an organic light emitting diode display according to an exemplary embodiment of the present invention. Figure 2 It is shown that the Figure 1 A plan view of power supply wiring in an organic light-emitting diode display. Figure 3 It shows the settings Figure 2 Plan view of the sealant on the power wiring. Figure 4 is shown electrically connected to Figure 2 A block diagram of external devices of an organic light emitting diode display device.

[0042] Reference Figure 1 、 Figure 2 、 Figure 3 and Figure 4The organic light-emitting diode display device 100 may include a first power supply wiring 350, a second power supply wiring 380, a sealant 390, a pad electrode 470, and the like, and may include a display area 10, a peripheral area 20, and a pad area 60. Here, the peripheral area 20 may substantially or at least partially surround the display area 10, and the pad area 60 may be located on one side of the peripheral area 20. In addition, the display area 10 may include a plurality of sub-pixel circuit areas 30. The peripheral area 20 may include a first peripheral area 21 and a second peripheral area 22. For example, the first peripheral area 21 may be located in the peripheral area 20 adjacent to the pad area 60, and the second peripheral area 22 may correspond to the remaining portion of the peripheral area 20 other than the first peripheral area 21. For example, the first peripheral area 21 and the second peripheral area 22 may be different from each other and may not overlap each other. For example, the peripheral area 20 may have a hollow rectangular shape in a plan view. For example, the peripheral area 20 may have a rectangular planar shape with an opening that exposes the display area 10.

[0043] The sub-pixel circuit region 30 may be entirely disposed within the display region 10. For example, a sub-pixel circuit (SPC; e.g., Figure 6 and Figure 7 The semiconductor element 250 in the sub-pixel circuit region 30 may be provided in each of the sub-pixel circuit regions 30, and an organic light emitting diode (OLED; e.g., Figure 6 and Figure 7 The sub-pixel structure 200 in FIG. 2 may be disposed on the sub-pixel circuit (SPC). An image may be displayed on the display area 10 through the sub-pixel circuit (SPC) and the organic light emitting diode (OLED).

[0044] For example, a first sub-pixel circuit, a second sub-pixel circuit, and a third sub-pixel circuit may be provided in the sub-pixel circuit region 30. The first sub-pixel circuit may be connected to a first organic light-emitting diode configured to emit red light, the second sub-pixel circuit may be connected to a second organic light-emitting diode configured to emit green light, and the third sub-pixel circuit may be connected to a third organic light-emitting diode configured to emit blue light. In an exemplary embodiment, the first organic light-emitting diode may at least partially overlap with the first sub-pixel circuit, the second organic light-emitting diode may at least partially overlap with the second sub-pixel circuit, and the third organic light-emitting diode may at least partially overlap with the third sub-pixel circuit. Alternatively, the first organic light-emitting diode may at least partially overlap with a portion of the first sub-pixel circuit and a portion of the sub-pixel circuit different from the first sub-pixel circuit, the second organic light-emitting diode may at least partially overlap with a portion of the second sub-pixel circuit and a portion of the sub-pixel circuit different from the second sub-pixel circuit, and the third organic light-emitting diode may at least partially overlap with a portion of the third sub-pixel circuit and a portion of the sub-pixel circuit different from the third sub-pixel circuit. For example, the first to third organic light emitting diodes may be arranged using schemes such as an RGB stripe scheme in which rectangles having the same size are sequentially arranged, an S-strip scheme including a blue organic light emitting diode having a relatively large area, a WRGB scheme also including a white organic light emitting diode, and a PenTile scheme arranged to have an RG-GB repeating pattern.

[0045] In addition, at least one driving transistor, at least one switching transistor, at least one capacitor, etc. may be provided in each of the sub-pixel circuit regions 30. In an exemplary embodiment, one driving transistor (e.g., Figure 5 The first transistor TR1 in the embodiment), six switching transistors (eg, Figure 5 a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a sixth transistor TR6, and a seventh transistor TR7), a storage capacitor (eg, Figure 5 The storage capacitor CST) and the like may be provided in each of the sub-pixel circuit regions 30.

[0046] Although the display region 10, the sub-pixel circuit region 30, and the pad region 60 of the present invention have a rectangular shape in a plan view, the shape is not limited thereto. For example, each of the display region 10, the sub-pixel circuit region 30, and the pad region 60 may have a triangular shape, a diamond shape, a polygonal shape, a circular shape, a stadium shape, or an elliptical shape in a plan view.

[0047] A plurality of wirings may be provided in the peripheral region 20. For example, the plurality of wirings may include data signal wirings, gate signal wirings, light emission control signal wirings, gate initialization signal wirings, initialization voltage wirings, power supply voltage wirings, and the like. The wirings may extend from the peripheral region 20 to the display region 10 to electrically connect to the sub-pixel circuits (SPCs) and the organic light emitting diodes (OLEDs). In addition, a gate driver, a data driver, and the like may be provided in the peripheral region 20.

[0048] In an exemplary embodiment, as Figure 2 and Figure 3 As shown in , the first power wiring 350 may be provided in a portion of the peripheral region 20. For example, the first power wiring 350 may be provided in a portion of the first peripheral region 21 and in the second peripheral region 22. The first power wiring 350 may have a shape of a hook including an open lower portion (for example, a loop with an open lower portion such as an incomplete frame shape). In an exemplary embodiment, the first power wiring 350 may have a first width W1 in the first peripheral region 21 and may have a second width W2 smaller than the first width W1 in the second peripheral region 22. The first power wiring 350 may be electrically connected to the pad electrode 470 in the first peripheral region 21. For example, the first power wiring 350 may be electrically connected to the outermost pad electrode 470 among the pad electrodes 470. A low power supply voltage may be applied to the first power wiring 350, and the low power supply voltage may be provided to the cathode electrode (for example, Figure 6 The upper electrode 340 in the embodiment.

[0049] In addition, the second power wiring 380 may be provided in a portion of the peripheral region 20. For example, the second power wiring 380 may be provided in a portion of the first peripheral region 21. The second power wiring 380 may be provided between the ends of the first power wiring 350 in the first peripheral region 21. Alternatively, the second power wiring 380 may extend from the first peripheral region 21 to the display region 10 and have a lattice shape in the display region 10. The second power wiring 380 may be electrically connected to the pad electrode 470 in the first peripheral region 21. For example, the second power wiring 380 may be electrically connected to the pad electrode 470 located at the inner side of the pad electrode 470 connected to the first power wiring 350 among the pad electrodes 470. A high power supply voltage may be applied to the second power wiring 380, and the high power supply voltage may be provided to the anode electrode (e.g., Figure 6 The lower electrode 290 in the embodiment of the present invention.

[0050] In addition, the sealant 390 may be provided in the peripheral region 20. When the peripheral region 20 has a hollow rectangular shape in a plan view, the sealant 390 provided in the peripheral region 20 may also have a hollow rectangular shape in a plan view.

[0051] The first power wiring 350 and the second power wiring 380 may be provided in the peripheral region 20 on the lower substrate 110 included in the organic light emitting diode display device 100 to be described below, and the sealant 390 may be provided on the first power wiring 350 and the second power wiring 380. Here, the sealant 390 may include a first sealing portion 391 located in the first peripheral region 21 and a second sealing portion 392 located in the second peripheral region 22. The first sealing portion 391 may be formed integrally with the second sealing portion 392.

[0052] It will be understood that in the drawings, where a reference numeral is shown pointing to a dashed box, the reference numeral is intended to refer to the component shown in the dashed box and not the dashed box itself, unless explicitly stated to the contrary.

[0053] The first power wiring 350 may be overlapped between the lower substrate 110 and the sealant 390. The first power wiring 350 located in the first peripheral region 21 may include a first protrusion (e.g., a first protrusion) protruding from a first side of the first sealing portion 391 (e.g., an inner side of the first sealing portion 391) in a first direction D1 directed from the pad region 60 to the display region 10. Figure 6 In addition, the first power wiring 350 located in the first peripheral region 21 may include a second protrusion (e.g., a second protrusion) protruding from a second side opposite to the first side of the first sealing portion 391 (e.g., an outer side of the first sealing portion 391) in a second direction D2 opposite to the first direction D1. Figure 6 For example, the first protrusion may be adjacent to the sub-pixel structure, and the second protrusion may be adjacent to the pad electrode 470.

[0054] The first power wiring 350 located in the second peripheral area 22 may include a third protrusion protruding from a first side of the second sealing portion 392 (e.g., an inner side of the second sealing portion 392) in a direction from the second peripheral area 22 to the display area 10. Here, the third protrusion may be defined as a first end (e.g., an inner side) of the first power wiring 350 located in the second peripheral area 22. Figure 7 For example, the first power wiring 350 located in the second peripheral region 22 may include a first end and a second end opposite to the first end (eg, Figure 7 For example, the first end may be adjacent to the sub-pixel structure, and the second end may be covered by the second sealing portion 392.

[0055] For example, the first power wiring 350 may be divided into a first wiring portion 361 located in the first peripheral region 21 and a second wiring portion 362 located in the second peripheral region 22. A first width W1 of the first wiring portion 361 of the first power wiring 350 extending in the first direction D1 may be greater than a second width W2 of the second wiring portion 362 of the first power wiring 350 extending in a direction from the second peripheral region 22 to the display region 10. Although the first power wiring 350 is divided into the first wiring portion 361 and the second wiring portion 362, the first wiring portion 361 and the second wiring portion 362 may be a single integrated unit.

[0056] A conventional organic light-emitting diode display device may include a lower substrate, an upper substrate, a first power wiring, and a sealant, and the first power wiring and the sealant may be arranged in a peripheral region on the lower substrate. Here, the first power wiring may not overlap with the sealant in a peripheral region (e.g., the first peripheral region) adjacent to the pad region on the lower substrate. Therefore, according to conventional organic light-emitting diode display devices, the power wiring may be arranged adjacent to the display region in the first peripheral region, and the sealant may be arranged adjacent to the pad region to separate the power wiring. In this case, conventional organic light-emitting diode display devices may have a relatively large dead space in the first peripheral region. According to the organic light-emitting diode display device 100, according to an exemplary embodiment of the present invention, the first power wiring 350 at least partially overlaps with the sealant 390 in the first peripheral region 21, thereby reducing the dead space of the organic light-emitting diode display device 100. For example, the total length of the first peripheral region 21 and the pad region 60 extending along the first direction D1 (or second direction D2) may be 2.22 mm or less.

[0057] Refer again Figures 1 to 4 , a pad electrode 470 electrically connected to the external device 101 may be provided in the pad region 60. Furthermore, a connection electrode may be provided between the pad electrode 470 and the first and second power wirings 350 and 380. For example, the connection electrode may electrically connect the pad electrode 470 to the first and second power wirings 350 and 380. In some exemplary embodiments, the lower substrate 110 included in the organic light emitting diode display device 100 may have the same length in a lateral direction (e.g., the third direction D3) in the display region 10, the peripheral region 20, and the pad region 60. In some exemplary embodiments, the lateral width of the pad region 60 may be smaller than the lateral widths of the display region 10 and the peripheral region 20.

[0058] The external device 101 may be electrically connected to the organic light emitting diode display device 100 through a flexible printed circuit board or a printed circuit board. For example, one side of the flexible printed circuit board may be in direct contact with the pad electrode 470, and the other side of the flexible printed circuit board may be in direct contact with the external device 101. The external device 101 may provide a data signal, a gate signal, a light emission control signal, a gate initialization signal, an initialization voltage, a power supply voltage, etc. to the organic light emitting diode display device 100. In an exemplary embodiment, a low power supply voltage (e.g., Figure 5 The low power supply voltage ELVSS in the first power supply wiring 350 can be provided through the flexible printed circuit board, the pad electrode 470 and the connection electrode. In addition, a high power supply voltage (eg, Figure 5 The high power supply voltage ELVDD in the organic light emitting diode display device 100 can be supplied to the second power supply wiring 380 through the flexible printed circuit board, the pad electrode 470, and the connection electrode. In addition, the driver integrated circuit can be mounted on the flexible printed circuit board. In some exemplary embodiments, the driver integrated circuit can be mounted on the organic light emitting diode display device 100 so as to be adjacent to the pad electrode 470.

[0059] Figure 5 It shows the settings Figure 2 Circuit diagram of a sub-pixel circuit and an organic light-emitting diode in a sub-pixel circuit area.

[0060] Reference Figure 5 , a sub-pixel circuit (SPC) and an organic light emitting diode OLED may be provided in each of the sub-pixel circuit regions 30 of the organic light emitting diode display device 100, wherein one sub-pixel circuit (SPC) may include an organic light emitting diode OLED (e.g., Figure 6 ), a first transistor TR1, a second transistor TR2, a third transistor TR3, a fourth transistor TR4, a fifth transistor TR5, a sixth transistor TR6, a seventh transistor TR7 (eg, Figure 6 ), the semiconductor element 250 in the storage capacitor CST, the high power supply voltage ELVDD wiring (eg, Figure 2 and Figure 3 The second power supply wiring 380 in FIG), the low power supply voltage ELVSS wiring (eg, Figure 2 、 Figure 3 、 Figure 6 and Figure 7), initialization voltage VINT wiring, data signal DATA wiring, gate signal GW wiring, gate initialization signal GI wiring, emission control signal EM wiring, diode initialization signal GB wiring, etc. As described above, the first transistor TR1 can correspond to a drive transistor, and the second transistor TR2, the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5, the sixth transistor TR6, and the seventh transistor TR7 can each correspond to a switching transistor. Each of the first transistor TR1, the second transistor TR2, the third transistor TR3, the fourth transistor TR4, the fifth transistor TR5, the sixth transistor TR6, and the seventh transistor TR7 may include a first terminal, a second terminal, a channel, and a gate terminal. In an exemplary embodiment, the first terminal may be a source terminal and the second terminal may be a drain terminal. Alternatively, the first terminal may be a drain terminal and the second terminal may be a source terminal.

[0061] The organic light emitting diode OLED may output light based on a driving current ID. The organic light emitting diode OLED may include a first terminal and a second terminal. In an exemplary embodiment, the second terminal of the organic light emitting diode OLED may be supplied with a low power supply voltage ELVSS. For example, the first terminal of the organic light emitting diode OLED may be an anode terminal, and the second terminal of the organic light emitting diode OLED may be a cathode terminal. Alternatively, the first terminal of the organic light emitting diode OLED may be a cathode terminal, and the second terminal of the organic light emitting diode OLED may be an anode terminal. In an exemplary embodiment, the anode terminal of the organic light emitting diode OLED may correspond to Figure 6 The lower electrode 290 in the organic light emitting diode OLED may correspond to the cathode terminal Figure 6 The upper electrode 340 in.

[0062] The first transistor TR1 may generate a drive current ID. In an exemplary embodiment, the first transistor TR1 may operate in a saturation region. In this case, the first transistor TR1 may generate the drive current ID based on a voltage difference between a gate terminal and a source terminal. In addition, a tone wedge may be expressed based on the magnitude of the drive current ID supplied to the organic light emitting diode OLED. Alternatively, the first transistor TR1 may operate in a linear region. In this case, the tone wedge may be expressed based on the total number of times the drive current ID is supplied to the organic light emitting diode OLED within a frame.

[0063] The gate terminal of the second transistor TR2 may be supplied with a gate signal GW. The first terminal of the second transistor TR2 may be supplied with a data signal DATA. The second terminal of the second transistor TR2 may be connected to the first terminal of the first transistor TR1. For example, the gate signal GW may be provided by a gate driving unit and applied to the gate terminal of the second transistor TR2 via a gate signal GW wiring. The second transistor TR2 may supply the data signal DATA to the first terminal of the first transistor TR1 during an activation period of the gate signal GW. In this case, the second transistor TR2 may operate in a linear region.

[0064] The gate terminal of the third transistor TR3 may be supplied with a gate signal GW. The first terminal of the third transistor TR3 may be connected to the gate terminal of the first transistor TR1. The second terminal of the third transistor TR3 may be connected to the second terminal of the first transistor TR1. For example, the gate signal GW may be provided by a gate driving unit and applied to the gate terminal of the third transistor TR3 via the gate signal GW wiring. The third transistor TR3 may connect the gate terminal of the first transistor TR1 to the second terminal of the first transistor TR1 during the activation period of the gate signal GW. In this case, the third transistor TR3 may operate in a linear region. For example, the third transistor TR3 may be diode-connected to the first transistor TR1 during the activation period of the gate signal GW. Since the first transistor TR1 is diode-connected, a voltage difference equal to the threshold voltage of the first transistor TR1 may occur between the first terminal of the first transistor TR1 and the gate terminal of the first transistor TR1. As a result, a voltage obtained by adding the voltage difference (e.g., the threshold voltage) to the voltage of the data signal DATA supplied to the first terminal of the first transistor TR1 during the activation period of the gate signal GW may be supplied to the gate terminal of the first transistor TR1. For example, the data signal DATA may be compensated for the threshold voltage of the first transistor TR1 and the compensated data signal DATA may be supplied to the gate terminal of the first transistor TR1. Compensation for the threshold voltage may solve the problem of uneven driving current caused by the deviation of the threshold voltage of the first transistor TR1.

[0065] An input terminal of the initialization voltage VINT wiring supplied with the initialization voltage VINT may be connected to a first terminal of the fourth transistor TR4 and a first terminal of the seventh transistor TR7 , and an output terminal of the initialization voltage VINT wiring may be connected to a second terminal of the fourth transistor TR4 and a first terminal of the storage capacitor CST.

[0066] A gate terminal of the fourth transistor TR4 may be supplied with a gate initialization signal GI. A first terminal of the fourth transistor TR4 may be supplied with an initialization voltage VINT. A second terminal of the fourth transistor TR4 may be connected to a gate terminal of the first transistor TR1.

[0067] The fourth transistor TR4 can supply the initialization voltage VINT to the gate terminal of the first transistor TR1 during the activation period of the gate initialization signal GI. In this case, the fourth transistor TR4 can operate in the linear region. For example, the fourth transistor TR4 can initialize the gate terminal of the first transistor TR1 to the initialization voltage VINT during the activation period of the gate initialization signal GI. In an exemplary embodiment, the initialization voltage VINT may have a voltage level sufficiently lower than the voltage level of the data signal DATA maintained by the storage capacitor CST in the previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1. In some exemplary embodiments, the initialization voltage VINT may have a voltage level sufficiently higher than the voltage level of the data signal DATA maintained by the storage capacitor CST in the previous frame, and the initialization voltage VINT may be supplied to the gate terminal of the first transistor TR1.

[0068] In an exemplary embodiment, the gate initialization signal GI may be substantially the same as the gate signal GW one horizontal time ago. For example, the gate initialization signal GI supplied to the sub-pixel circuit of the nth (where n is an integer of 2 or greater) row among the sub-pixel circuits (SPC) included in the organic light emitting diode display device 100 may be a signal substantially the same as the gate signal GW supplied to the sub-pixel circuit of the n-1th row. For example, the activated gate signal GW is supplied to the first sub-pixel circuit of the n-1th row among the sub-pixel circuits (SPC), so that the activated gate initialization signal GI may be supplied to the first sub-pixel circuit of the nth row among the sub-pixel circuits (SPC). As a result, the data signal DATA may be supplied to the first sub-pixel circuit of the n-1th row among the sub-pixel circuits (SPC), and at the same time, the gate terminal of the first transistor TR1 included in the first sub-pixel circuit of the nth row among the sub-pixel circuits (SPC) may be initialized to the initialization voltage VINT.

[0069] The gate terminal of the fifth transistor TR5 may be supplied with the emission control signal EM. The first terminal of the fifth transistor TR5 may be connected to a high power supply voltage ELVDD wiring. The second terminal of the fifth transistor TR5 may be connected to the first terminal of the first transistor TR1. For example, the emission control signal EM may be provided by the emission control driving unit and applied to the gate terminal of the fifth transistor TR5 via the emission control signal EM wiring. The fifth transistor TR5 may supply the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during the activation period of the emission control signal EM. The fifth transistor TR5 may also block the supply of the high power supply voltage ELVDD during the inactive period of the emission control signal EM. In this case, the fifth transistor TR5 may operate in a linear region. The fifth transistor TR5 may supply the high power supply voltage ELVDD to the first terminal of the first transistor TR1 during the activation period of the emission control signal EM, allowing the first transistor TR1 to generate a drive current ID. Furthermore, the fifth transistor TR5 may block the supply of the high power supply voltage ELVDD during the inactive period of the emission control signal EM, allowing the data signal DATA supplied to the first terminal of the first transistor TR1 to be supplied to the gate terminal of the first transistor TR1.

[0070] The gate terminal of the sixth transistor TR6 (eg, Figure 6 The semiconductor element 250 in the sixth transistor TR6 may be supplied with a light emission control signal EM. The first terminal of the sixth transistor TR6 may be connected to the second terminal of the first transistor TR1. The second terminal of the sixth transistor TR6 may be connected to the first terminal of the organic light emitting diode OLED. The sixth transistor TR6 may supply the drive current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation period of the light emission control signal EM. In this case, the sixth transistor TR6 may operate in a linear region. For example, the sixth transistor TR6 may supply the drive current ID generated by the first transistor TR1 to the organic light emitting diode OLED during the activation period of the light emission control signal EM, so that the organic light emitting diode OLED can output light. In addition, the sixth transistor TR6 electrically isolates the first transistor TR1 and the organic light emitting diode OLED from each other during the inactive period of the light emission control signal EM, so that the data signal DATA supplied to the first terminal of the first transistor TR1 (more precisely, the data signal compensating the threshold voltage) can be supplied to the gate terminal of the first transistor TR1.

[0071] The gate terminal of the seventh transistor TR7 may be supplied with a diode initialization signal GB. The first terminal of the seventh transistor TR7 may be supplied with an initialization voltage VINT. The second terminal of the seventh transistor TR7 may be connected to the first terminal of the organic light emitting diode OLED. The seventh transistor TR7 may supply the initialization voltage VINT to the first terminal of the organic light emitting diode OLED during the activation period of the diode initialization signal GB. In this case, the seventh transistor TR7 may operate in a linear region. For example, the seventh transistor TR7 may initialize the first terminal of the organic light emitting diode OLED to the initialization voltage VINT during the activation period of the diode initialization signal GB.

[0072] Alternatively, the gate initialization signal GI may be substantially the same as the diode initialization signal GB. Initializing the gate terminal of the first transistor TR1 and initializing the first terminal of the organic light-emitting diode OLED may not affect each other. For example, initializing the gate terminal of the first transistor TR1 and initializing the first terminal of the organic light-emitting diode OLED may be independent of each other. Therefore, the diode initialization signal GB is not generated separately, thereby making processing more efficient.

[0073] The storage capacitor CST may include a first terminal and a second terminal. The storage capacitor CST may be connected between the high power supply voltage ELVDD wiring and the gate terminal of the first transistor TR1. For example, the first terminal of the storage capacitor CST may be connected to the gate terminal of the first transistor TR1, and the second terminal of the storage capacitor CST may be connected to the high power supply voltage ELVDD wiring. The storage capacitor CST may maintain the voltage level of the gate terminal of the first transistor TR1 during the inactive period of the gate signal GW. The inactive period of the gate signal GW may include the active period of the emission control signal EM, and the drive current ID generated by the first transistor TR1 during the active period of the emission control signal EM may be supplied to the organic light emitting diode OLED. Therefore, based on the voltage level maintained by the storage capacitor CST, the drive current ID generated by the first transistor TR1 may be supplied to the organic light emitting diode OLED.

[0074] Although the sub-pixel circuit (SPC) of the present invention has been described as including seven transistors and one storage capacitor, the configuration of the sub-pixel circuit (SPC) of the present invention is not limited thereto. For example, the sub-pixel circuit (SPC) can be configured to include at least one transistor and at least one storage capacitor.

[0075] Figure 6 It is along Figure 2 A cross-sectional view taken along line II' in FIG. Figure 7 It is along Figure 2A cross-sectional view taken along line II-II'.

[0076] Reference Figure 2 、 Figure 3 、 Figure 6 and Figure 7 The organic light-emitting diode display device 100 may include a lower substrate 110, a semiconductor element 250, a first power wiring 350, a second power wiring 380, a planarization layer 270, a connection pattern 295, a pixel defining layer 310, a sub-pixel structure 200, a sealant 390, an upper substrate 410, and the like. Here, the semiconductor element 250 may include an active layer 130, a gate insulating layer 150, a gate electrode 170, an interlayer insulating layer 190, a source electrode 210, and a drain electrode 230. The sub-pixel structure 200 may include a lower electrode 290, a light-emitting layer 330, and an upper electrode 340. In an exemplary embodiment, the sealant 390 may be divided into a first sealing portion 391 and a second sealing portion 392, and the first power wiring 350 may be divided into a first wiring portion 361 at least partially overlapping the first sealing portion 391 and a second wiring portion 362 at least partially overlapping the second sealing portion 392.

[0077] The lower substrate 110 may include a transparent material or an opaque material. The lower substrate 110 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped (F-doped) quartz substrate, a soda-lime glass substrate, a non-alkali glass substrate, etc. As described above, the organic light emitting diode display device 100 includes a display area 10, a peripheral area 20 and a pad area 60, and the peripheral area 20 includes a first peripheral area 21 and a second peripheral area 22. Therefore, the lower substrate 110 can also be divided into the display area 10, the first peripheral area 21, the second peripheral area 22 and the pad area 60. Optionally, the lower substrate 110 can be formed of a transparent resin substrate having flexibility. Examples of transparent resin substrates that can be used for the lower substrate 110 include polyimide substrates.

[0078] A buffer layer may be provided on the lower substrate 110. The buffer layer may be provided entirely on the lower substrate 110. The buffer layer may prevent metal atoms or impurities from diffusing from the lower substrate 110 to the semiconductor element 250 and the sub-pixel structure 200, and may be capable of obtaining a substantially uniform active layer 130 by adjusting the heat transfer rate during the crystallization process for forming the active layer 130. In addition, when the surface of the lower substrate 110 is uneven, the buffer layer may be used to flatten the surface of the lower substrate 110. Depending on the type of the lower substrate 110, at least two buffer layers may be provided on the lower substrate 110, or no buffer layer may be provided on the lower substrate 110. For example, the buffer layer may include an organic material or an inorganic material.

[0079] The active layer 130 may be provided in the display region 10 on the lower substrate 110. For example, the active layer 130 may include an oxide semiconductor, an inorganic semiconductor (such as amorphous silicon and polycrystalline silicon), an organic semiconductor, etc. The active layer 130 may have a source region, a drain region, and a channel region.

[0080] The gate insulating layer 150 may be disposed on the active layer 130. The gate insulating layer 150 may cover the active layer 130 in the display area 10 on the lower substrate 110 and may be entirely disposed on the lower substrate 110. In an exemplary embodiment, the gate insulating layer 150 may fully cover the active layer 130 on the lower substrate 110 and have a substantially flat top surface without generating steps around the active layer 130. Alternatively, the gate insulating layer 150 may cover the active layer 130 on the lower substrate 110 and have a uniform thickness along the contour of the active layer 130. The gate insulating layer 150 may include a silicon compound, a metal oxide, or the like. For example, the gate insulating layer 150 may include silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), silicon oxycarbide (SiO x C y ), silicon carbide nitride (SiC x N y ), aluminum oxide (AlO x ), aluminum nitride (AlN x ), tantalum oxide (TaO x ), hafnium oxide (HfO x ), zirconium oxide (ZrO x ), titanium oxide (TiO x ) etc. Optionally, the gate insulating layer 150 may have a multi-layer structure having a plurality of insulating layers including different materials. In some exemplary embodiments, the gate insulating layer 150 may be provided only in the display region 10 and may not be provided in the peripheral region 20 or the pad region 60.

[0081] The gate electrode 170 may be disposed on the gate insulating layer 150. For example, the gate electrode 170 may be disposed on a portion of the gate insulating layer 150 under which the active layer 130 is located. The gate electrode 170 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination. Alternatively, the gate electrode 170 may have a multilayer structure including a plurality of layers.

[0082] An interlayer insulating layer 190 may be provided on the gate electrode 170. The interlayer insulating layer 190 may cover the gate electrode 170 in the display region 10 on the gate insulating layer 150 and may be provided entirely on the gate insulating layer 150. In an exemplary embodiment, the interlayer insulating layer 190 may fully cover the gate electrode 170 on the gate insulating layer 150 and have a substantially flat top surface without generating steps around the gate electrode 170. Alternatively, the interlayer insulating layer 190 may have a uniform thickness along the contour of the gate electrode 170 while covering the gate electrode 170 on the gate insulating layer 150. The interlayer insulating layer 190 may include a silicon compound, a metal oxide, or the like. Alternatively, the interlayer insulating layer 190 may have a multilayer structure having a plurality of insulating layers including different materials. In some exemplary embodiments, the interlayer insulating layer 190 may be provided solely in the display region 10 and may not be provided in the peripheral region 20 and the pad region 60.

[0083] The source electrode 210 and the drain electrode 230 may be provided in the display area 10 on the interlayer insulating layer 190. The source electrode 210 may be connected to the source region of the active layer 130 via a contact hole formed by removing the first portion of the gate insulating layer 150 and the interlayer insulating layer 190, and the drain electrode 230 may be connected to the drain region of the active layer 130 via a contact hole formed by removing the second portion of the gate insulating layer 150 and the interlayer insulating layer 190. Each of the source electrode 210 and the drain electrode 230 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination. Alternatively, each of the source electrode 210 and the drain electrode 230 may have a multilayer structure including multiple layers. Thus, a semiconductor element 250 including the active layer 130, the gate insulating layer 150, the gate electrode 170, the interlayer insulating layer 190, the source electrode 210, and the drain electrode 230 may be provided.

[0084] Although the organic light emitting diode display device 100 has been described as including one transistor (such as the semiconductor element 250), the configuration of the present invention is not limited thereto. For example, the organic light emitting diode display device 100 may be configured to include at least two transistors and at least one capacitor.

[0085] Furthermore, although the semiconductor element 250 has been described as having a top gate structure, the configuration of the present invention is not limited thereto. For example, the semiconductor element 250 may have a bottom gate structure and / or a dual gate structure.

[0086] Although for ease of description, Figure 6 The semiconductor element 250 and Figure 7 The semiconductor elements 250 in FIG. 1 have the same reference numerals, but Figure 6 The semiconductor element 250 and Figure 7 The semiconductor element 250 in the embodiment may be a different semiconductor element. For example, Figure 6 The semiconductor element 250 may be a semiconductor element adjacent to the first peripheral region 21. Figure 7 The semiconductor element 250 in FIG. 2 may be a semiconductor element adjacent to the second peripheral region 22 .

[0087] The first power wiring 350 may be provided in the peripheral region 20 on the interlayer insulating layer 190. For example, the first power wiring 350 may be provided on the interlayer insulating layer 190 to be separated from the source electrode 210 and the drain electrode 230. In an exemplary embodiment, a low power supply voltage may be applied to the first power wiring 350. For example, the first power wiring 350 may be electrically connected to at least one of the pad electrodes 470 and supplied with a low power supply voltage (e.g., Figure 5 In addition, the low power supply voltage may be supplied to the upper electrode 340.

[0088] For example, Figure 6 As shown in FIG, the first power wiring 350 (e.g., the first wiring portion 361) may be overlapped between the interlayer insulating layer 190 and the first sealing portion 391. The first power wiring 350 located in the first peripheral region 21 may include a first protrusion 351 protruding from a first side of the first sealing portion 391 along the first direction D1 and a second protrusion 352 protruding from a second side of the first sealing portion 391 along the second direction D2. For example, the first protrusion 351 may be adjacent to the sub-pixel structure 200, and the second protrusion 352 may be adjacent to the pad electrode 470 (see FIG. Figure 2 and Figure 3 ) adjacent to the first peripheral region 21. In an exemplary embodiment, the first power wiring 350 (e.g., the first wiring portion 361) located in the first peripheral region 21 may have a first width W1. In addition, the first protrusion 351 may be exposed and separated from the planarization layer 270 located in the display region 10 adjacent to the first peripheral region 21. The second protrusion 352 may be electrically connected to the pad electrode 470 and may be covered by the planarization layer 270 adjacent to the pad region 60. In addition, the connection pattern 295 may not be provided in the first peripheral region 21 on the lower substrate 110, and the first wiring portion 361 may not be in direct contact with the connection pattern 295. Alternatively, the connection pattern 295 may be provided in the first peripheral region 21, and the connection pattern 295 may electrically connect the upper electrode 340 to the first wiring portion 361.

[0089] In addition, if Figure 7As shown in , the first power wiring 350 (e.g., the second wiring portion 362) may be overlapped between the interlayer insulating layer 190 and the second sealing portion 392. The first power wiring 350 located in the second peripheral area 22 may include a third protrusion protruding from the first side of the second sealing portion 392 along the third direction D3. Here, the third protrusion may be defined as the first end 353 of the first power wiring 350 located in the second peripheral area 22. For example, the first power wiring 350 located in the second peripheral area 22 may include a first end 353 and a second end 354. For example, the first end 353 may be adjacent to the sub-pixel structure 200, and the second end 354 may at least partially overlap with the second sealing portion 392. In an exemplary embodiment, the first power wiring 350 (e.g., the second wiring portion 362) located in the second peripheral area 22 may have a second width W2 that is smaller than the first width W1. In addition, the first end 353 may be covered by the planarization layer 270 and the pixel defining layer 310 located in the display area 10 adjacent to the second peripheral area 22, and the second end 354 may be covered by the second sealing portion 392. For example, the first end 353 and the second end 354 may not be exposed. In addition, the first end 353 may be in direct contact with the connection pattern 295.

[0090] The first power wiring 350 can absorb and / or reflect the energy of the laser irradiating the sealant 390 so that the lower substrate 110 and the upper substrate 410 are sealed and bonded to each other, and can contribute to the state change of the material of the sealant 390. For example, the first power wiring 350 can be used as a wiring capable of providing a low power supply voltage and a metal layer capable of absorbing and reflecting the energy of the laser. The first power wiring 350 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the first power wiring 350 may include gold (Au), silver (Ag), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), palladium (Pd), magnesium (Mg), calcium (Ca), lithium (Li), chromium (Cr), tantalum (Ta), tungsten (W), copper (Cu), molybdenum (Mo), scandium (Sc), neodymium (Nd), iridium (Ir), an alloy containing aluminum, aluminum nitride (AlN), etc. x ), alloys containing silver, tungsten nitride (WN x ), alloys containing copper, alloys containing molybdenum, titanium nitride (TiN x ), chromium nitride (CrN x ), tantalum nitride (TaN x ), strontium ruthenium oxide (SrRu x O y ), zinc oxide (ZnO x ), indium tin oxide (ITO), tin oxide (SnO x ), indium oxide (InO x), gallium oxide (GaO x ), indium zinc oxide (IZO), etc. These may be used alone or in combination with each other. Alternatively, the first power wiring 350 may have a multilayer structure including a plurality of layers.

[0091] The second power wiring 380 may be provided in the first peripheral region 21 on the interlayer insulating layer 190. For example, the second power wiring 380 may be provided between the first power wiring 350 and the source electrode 210 and the drain electrode 230 on the interlayer insulating layer 190. In an exemplary embodiment, a high power supply voltage may be applied to the second power wiring 380. For example, the second power wiring 380 may be electrically connected to at least one of the pad electrodes 470 and supplied with a high power supply voltage (e.g., Figure 5 In addition, the high power supply voltage is supplied to the lower electrode 290.

[0092] The second power wiring 380 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination. Alternatively, the second power wiring 380 may have a multilayer structure including multiple layers. In an exemplary embodiment, the second power wiring 380, the first power wiring 350, the source electrode 210, and the drain electrode 230 may be located on the same layer.

[0093] The planarization layer 270 may be provided on the interlayer insulating layer 190, the second power wiring 380, a portion of the first power wiring 350, the source electrode 210, and the drain electrode 230. As described above, the planarization layer 270 located in the display region 10 adjacent to the first peripheral region 21 may be separated from the first power wiring 350 and may cover the second power wiring 380. The planarization layer 270 located in the first peripheral region 21 adjacent to the pad region 60 may cover the second protrusion 352. Furthermore, the planarization layer 270 located in the display region 10 adjacent to the second peripheral region 22 may cover the first end 353. Alternatively, the planarization layer 270 may not be provided in the pad region 60, and the second protrusion 352 may be exposed.

[0094] The planarization layer 270 located in the display area 10 can be relatively thick to fully cover the source electrode 210 and the drain electrode 230. In this case, the planarization layer 270 can have a substantially flat top surface, and a planarization process can be added to the planarization layer 270 to achieve the above-mentioned flat top surface of the planarization layer 270. A portion of the top surface of the drain electrode 230 can be exposed through a contact hole formed by removing a portion of the planarization layer 270. The planarization layer 270 may include an organic material or an inorganic material. In an exemplary embodiment, the planarization layer 270 may include an organic material. For example, the planarization layer 270 may include a photoresist, a polyacrylate resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, an epoxy resin, etc.

[0095] The lower electrode 290 may be provided in the display region 10 on the planarization layer 270. The lower electrode 290 may be connected to the drain electrode 230 after passing through a contact hole in the planarization layer 270. In addition, the lower electrode 290 may be electrically connected to the semiconductor element 250. The lower electrode 290 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination with one another. Alternatively, the lower electrode 290 may have a multilayer structure including a plurality of layers.

[0096] The connection pattern 295 may be provided in the peripheral region 20 over a portion of the first power wiring 350 and a portion of the planarization layer 270. In an exemplary embodiment, the connection pattern 295 may directly contact the top surface of the planarization layer 270, a sidewall portion of the planarization layer 270, and a portion of the top surface of the first end 353 in the second peripheral region 22. For example, one side of the connection pattern 295 may directly contact the upper electrode 340, the other side of the connection pattern 295 may directly contact the first power wiring 350, and the connection pattern 295 may electrically connect the second wiring portion 362 to the upper electrode 340. Furthermore, the connection pattern 295 may not be provided in the first peripheral region 21. Alternatively, the connection pattern 295 may be provided in the first peripheral region 21 and electrically connected to the first wiring portion 361. The connection pattern 295 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination. Alternatively, the connection pattern 295 may have a multilayer structure comprising multiple layers. In exemplary embodiments, the lower electrode 290 and the connection pattern 295 may be located on the same layer.

[0097] The pixel defining layer 310 may be disposed on a portion of the lower electrode 290, a portion of the connection pattern 295, and the planarization layer 270. The pixel defining layer 310 may cover both sides of the lower electrode 290 and at least one side of the connection pattern 295, and expose a portion of the top surface of the lower electrode 290. In an exemplary embodiment, the portion of the pixel defining layer 310 located in the first peripheral region 21 may not be in direct contact with the first wiring portion 361, and the portion of the pixel defining layer 310 located in the second peripheral region 22 may be in direct contact with a portion of the second wiring portion 362. Alternatively, the pixel defining layer 310 may not be disposed in the pad region 60. The pixel defining layer 310 may be formed of an organic material or an inorganic material. In an exemplary embodiment, the pixel defining layer 310 may include an organic material.

[0098] The light-emitting layer 330 may be disposed on the lower electrode 290 exposed by the pixel defining layer 310. The light-emitting layer 330 may be formed by using at least one of the light-emitting materials configured to emit light of different colors (such as red, green, and blue) according to the sub-pixels. Alternatively, the light-emitting layer 330 may be formed by laminating a plurality of light-emitting materials capable of producing light of different colors (such as red, green, and blue) so that white light can be emitted thereby. In this case, a color filter may be disposed on the light-emitting layer 330 (for example, the color filter is disposed on the bottom surface or top surface of the upper substrate 410 to at least partially overlap with the light-emitting layer 330). The color filter may include a red color filter, a green color filter, and / or a blue color filter. Alternatively, the color filter may further include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may include a photosensitive resin, a color photoresist, and the like.

[0099] The upper electrode 340 may be disposed on a portion of the connection pattern 295, on the pixel defining layer 310, and on the light-emitting layer 330. In an exemplary embodiment, the upper electrode 340 may cover the light-emitting layer 330 and the pixel defining layer 310 and extend from the display area 10 to the peripheral area 20. In an exemplary embodiment, the upper electrode 340 located in the second peripheral area 22 may directly contact a portion of the top surface of the connection pattern 295, and the connection pattern 295 may be electrically connected to the upper electrode 340. In addition, the upper electrode 340 located in the first peripheral area 21 may not directly contact the first wiring portion 361. The upper electrode 340 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination with each other. Alternatively, the upper electrode 340 may have a multilayer structure including multiple layers. Therefore, a sub-pixel structure 200 including a lower electrode 290, a light-emitting layer 330, and an upper electrode 340 may be provided.

[0100] Although for ease of description the Figure 6The sub-pixel structure 200 and Figure 7 The sub-pixel structure 200 is assumed to have the same reference numerals, but Figure 6 The sub-pixel structure 200 and Figure 7 The sub-pixel structure 200 can be a different sub-pixel structure. For example, Figure 6 The sub-pixel structure 200 may be a sub-pixel structure disposed adjacent to the first peripheral region 21. Figure 7 The sub-pixel structure 200 may be a sub-pixel structure disposed adjacent to the second peripheral region 22 .

[0101] The sealant 390 may be provided in the peripheral region 20 on the first power wiring 350. For example, the sealant 390 may be provided in the peripheral region 20 between the lower substrate 110 and the upper substrate 410. A top surface of the sealant 390 may be in direct contact with a bottom surface of the upper substrate 410, and a bottom surface of the sealant 390 may be in direct contact with a portion of the interlayer insulating layer 190 and / or a portion of the first power wiring 350.

[0102] For example, Figure 6 As shown in FIG, the first sealing portion 391 may be provided only on the first power wiring 350. For example, the bottom surface of the first sealing portion 391 may be in direct contact with the top surface of the first power wiring 350.

[0103] In addition, if Figure 7 , the second sealing portion 392 may be disposed on both the first power wiring 350 and the interlayer insulating layer 190. For example, the bottom surface of the second sealing portion 392 may directly contact the upper surface of the first power wiring 350 and the top surface of the interlayer insulating layer 190 at the same time.

[0104] The sealant 390 may include glass frit, etc. In addition, the sealant 390 may also include a photocurable material. For example, the sealant 390 may include a mixture of an organic material and a photocurable material, and the sealant 390 may be obtained by irradiating the mixture with ultraviolet (UV), laser, visible light, etc. and thereby curing the mixture. The photocurable material included in the sealant 390 may include epoxy acrylate resin, polyester acrylate resin, urethane acrylate resin, polybutadiene acrylate resin, silicone acrylate resin, alkyl acrylate resin, etc.

[0105] For example, a mixture of an organic material and a photocurable material can be irradiated with a laser. Once the mixture is irradiated, the mixture can change from a solid state to a liquid state, and after a predetermined time, the mixture in a liquid state can be cured into a solid state. The upper substrate 410 can be sealed and bonded to the lower substrate 110 according to the state change of the mixture. The first power wiring 350 in the peripheral area 20 can absorb and / or reflect the energy of the laser during exposure. The energy reflected and absorbed by the first power wiring 350 can be transmitted to the mixture, thereby contributing to the state change of the mixture.

[0106] Although the sealant 390 has a trapezoidal shape in which the width of the top surface is smaller than the width of the bottom surface, the configuration of the present invention is not limited thereto. For example, the sealant 390 may have a trapezoidal shape having a top surface width greater than the bottom surface width, a rectangular shape, a square shape, etc.

[0107] The upper substrate 410 may be disposed on the sealant 390 and the upper electrode 340. The upper substrate 410 may include a material substantially the same as that of the lower substrate 110. For example, the upper substrate 410 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped (F-doped) quartz substrate, a soda-lime glass substrate, a non-alkali glass substrate, or the like. In some exemplary embodiments, the upper substrate 410 may be formed using a transparent inorganic material or a flexible plastic. For example, the upper substrate 410 may be formed of a flexible transparent resin substrate. Thus, an organic light emitting diode display device 100 may be provided.

[0108] In the organic light emitting diode display device 100, according to an exemplary embodiment of the present invention, the first power wiring 350 may not be in direct contact with the planarization layer 270, so that heat generated by the laser may not be transferred to the planarization layer 270. Therefore, the organic light emitting diode display device 100 can prevent the sub-pixel structure 200 from being damaged.

[0109] Furthermore, the first power wiring 350 at least partially overlaps the sealant 390 in the first peripheral region 21, thereby reducing the dead space of the organic light emitting diode display device 100. Therefore, the organic light emitting diode display device 100 can be used as a full-screen display device.

[0110] Furthermore, the first power wiring 350 disposed in the first peripheral region 21 may have a relatively large first width W1, so that wiring resistance may be reduced. Therefore, driving voltage and power consumption of the organic light emitting diode display device 100 may be reduced.

[0111] In addition, the first power wiring 350 can function as a wiring capable of providing a low power voltage and a metal layer capable of simultaneously absorbing and reflecting laser energy. Therefore, the metal layer capable of absorbing and reflecting laser energy can be omitted, thereby reducing the manufacturing cost of the organic light emitting diode display device 100.

[0112] Figures 8 to 17 is a cross-sectional view illustrating a method for manufacturing an organic light emitting diode display device according to an exemplary embodiment of the present invention. Figure 8 、 Figure 10 、 Figure 12 、 Figure 14 and Figure 16 is a cross-sectional view showing the first peripheral region 21 and the display region 10 and the pad region 60 adjacent to the first peripheral region 21, Figure 9 、 Figure 11 、 Figure 13 、 Figure 15 and Figure 17 2 is a cross-sectional view showing the second peripheral region 22 and the display region 10 adjacent to the second peripheral region 22 .

[0113] Reference Figure 8 and Figure 9 The lower substrate 110 may include a transparent material or an opaque material. The lower substrate 110 may be formed using a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped (F-doped) quartz substrate, a soda-lime glass substrate, a non-alkali glass substrate, or the like. In an exemplary embodiment, the lower substrate 110 may include a display area 10, a first peripheral area 21, and a second peripheral area 22. The lower substrate 110 may include a peripheral area 20 at least partially surrounding the display area 10 and a pad area 60 located on one side of the peripheral area 20.

[0114] A buffer layer may be formed on the lower substrate 110. The buffer layer may be entirely formed on the lower substrate 110. Depending on the type of the lower substrate 110, at least two buffer layers may be provided on the lower substrate 110, or no buffer layer may be formed on the lower substrate 110. For example, the buffer layer may be formed using an organic material or an inorganic material.

[0115] Active layers 130 may be formed on the lower substrate 110 and in the display region 10. For example, each of the active layers 130 may be formed using an oxide semiconductor, an inorganic semiconductor, an organic semiconductor, etc. Each of the active layers 130 may have a source region, a drain region, and a channel region.

[0116] A gate insulating layer 150 may be formed on the active layer 130. The gate insulating layer 150 may cover the active layer 130 in the display area 10 on the lower substrate 110 and may be formed entirely on the lower substrate 110. In an exemplary embodiment, the gate insulating layer 150 may fully cover the active layer 130 on the lower substrate 110 and have a substantially flat top surface without creating steps around the active layer 130. Alternatively, the gate insulating layer 150 may be formed to have a uniform thickness along the contour of the active layer 130 while covering the active layer 130 on the lower substrate 110. The gate insulating layer 150 may be formed using a silicon compound, a metal oxide, or the like. For example, the gate insulating layer 150 may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbide nitride, aluminum oxide, aluminum nitride, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or the like. Alternatively, the gate insulating layer 150 may have a multilayer structure having multiple insulating layers formed of different materials. In some exemplary embodiments, the gate insulating layer 150 may be formed only in the display region 10 , and may not be formed in the peripheral region 20 or the pad region 60 .

[0117] Reference Figure 10 and Figure 11 , a gate electrode 170 may be formed on the gate insulating layer 150. For example, the gate electrode 170 may be formed on a portion of the gate insulating layer 150 under which the active layer 130 is positioned. Each of the gate electrodes 170 may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination with one another. Alternatively, each of the gate electrodes 170 may have a multilayer structure including a plurality of layers.

[0118] An interlayer insulating layer 190 may be formed on the gate electrode 170. The interlayer insulating layer 190 may cover the gate electrode 170 in the display region 10 on the gate insulating layer 150 and may be formed entirely on the gate insulating layer 150. In exemplary embodiments, the interlayer insulating layer 190 may fully cover the gate electrode 170 on the gate insulating layer 150 and have a substantially flat top surface without creating steps around the gate electrode 170. Alternatively, the interlayer insulating layer 190 may be formed to have a uniform thickness along the contour of the gate electrode 170 while covering the gate electrode 170 on the gate insulating layer 150. The interlayer insulating layer 190 may be formed using a silicon compound, a metal oxide, or the like. Alternatively, the interlayer insulating layer 190 may have a multilayer structure having multiple insulating layers made of different materials. In some exemplary embodiments, the interlayer insulating layer 190 may be formed only in the display region 10 and may not be formed in the peripheral region 20 or the pad region 60.

[0119] A source electrode 210 and a drain electrode 230 may be formed on the interlayer insulating layer 190 and in the display area 10. The source electrode 210 may be connected to the source region of the active layer 130 through contact holes formed by removing first portions of the gate insulating layer 150 and the interlayer insulating layer 190, respectively. The drain electrode 230 may be connected to the drain region of the active layer 130 through contact holes formed by removing second portions of the gate insulating layer 150 and the interlayer insulating layer 190. Each of the source electrode 210 and the drain electrode 230 may be formed using metals, alloys, metal nitrides, conductive metal oxides, transparent conductive materials, or the like. These materials may be used alone or in combination. Alternatively, each of the source electrode 210 and the drain electrode 230 may have a multilayer structure including multiple layers. Thus, a semiconductor element 250 including the active layer 130, the gate insulating layer 150, the gate electrode 170, the interlayer insulating layer 190, the source electrode 210, and the drain electrode 230 may be formed.

[0120] The first power wiring 350 may be formed in the peripheral region 20 on the interlayer insulating layer 190. For example, the first power wiring 350 may be formed on the interlayer insulating layer 190 so as to be separated from the source electrode 210 and the drain electrode 230. The first power wiring 350 may be formed along the shape of the peripheral region 20, and the first power wiring 350 may have a substantially hollow rectangular planar shape (or a rectangular planar shape having an opening exposing the display region 10). In an exemplary embodiment, the first power wiring 350 may have different widths in the peripheral region 20. For example, the width of the first power wiring 350 located in the first peripheral region 21 may be different from the width of the first power wiring 350 located in the second peripheral region 22 (see FIG. 2 ). Figure 2 ). In addition, the first power supply wiring 350 may be integrally formed in the peripheral region 20 .

[0121] like Figure 10 As shown in FIG, the first power wiring 350 (eg, the first wiring portion 361) located in the first peripheral region 21 may have a first width W1 extending in the first direction D1 and may have a first protrusion 351 and a second protrusion 352. Figure 11 As shown in FIG, the first power wiring 350 (e.g., the second wiring portion 362) located in the second peripheral region 22 may have a second width W2 extending along a third direction D3 (e.g., in a direction from the second peripheral region 22 to the display region 10), and have a first end 353 and a second end 354. The first width W1 may be greater than the second width W2.

[0122] The first power wiring 350 can be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. For example, the first power wiring 350 can include gold, silver, aluminum, platinum, nickel, titanium, palladium, magnesium, calcium, lithium, chromium, tantalum, tungsten, copper, molybdenum, scandium, neodymium, iridium, an aluminum-containing alloy, aluminum nitride, a silver-containing alloy, tungsten nitride, a copper-containing alloy, a molybdenum-containing alloy, titanium nitride, tantalum nitride, strontium ruthenium oxide, zinc oxide, indium tin oxide, tin oxide, indium oxide, gallium oxide, gallium oxide, indium zinc oxide, or the like. These can be used alone or in combination with one another. Alternatively, the first power wiring 350 can have a multilayer structure including a plurality of layers.

[0123] A second power wiring 380 may be formed on the interlayer insulating layer 190 and in the first peripheral region 21. For example, the second power wiring 380 may be formed on the interlayer insulating layer 190 and between the first power wiring 350 and the source electrode 210 and the drain electrode 230. The second power wiring 380 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination. Alternatively, the second power wiring 380 may have a multilayer structure including multiple layers. In an exemplary embodiment, the second power wiring 380, the first power wiring 350, the source electrode 210, and the drain electrode 230 may be located on the same layer and may be formed simultaneously using the same material. For example, after forming the first preliminary electrode layer entirely on the interlayer insulating layer 190, the first preliminary electrode layer is selectively etched, so that the source electrode 210, the drain electrode 230, the second power wiring 380, and the first power wiring 350 may be formed simultaneously.

[0124] Reference Figure 12 and Figure 13 A planarization layer 270 may be formed on the interlayer insulating layer 190, the second power wiring 380, a portion of the first power wiring 350, the source electrode 210, and the drain electrode 230. In an exemplary embodiment, the planarization layer 270 located in the display region 10 adjacent to the first peripheral region 21 may be separated from the first power wiring 350 and may cover the second power wiring 380. The planarization layer 270 located in the first peripheral region 21 adjacent to the pad region 60 may cover the second protrusion 352. Furthermore, the planarization layer 270 located in the display region 10 adjacent to the second peripheral region 22 may cover the first end 353.

[0125] The planarization layer 270 located in the display area 10 may be formed to be relatively thick so as to sufficiently cover the source electrode 210 and the drain electrode 230. In this case, the planarization layer 270 may have a substantially flat top surface, and a planarization process may be added to the planarization layer 270 to achieve the above-mentioned flat top surface of the planarization layer 270. The planarization layer 270 may be formed using an organic material such as a photoresist, a polyacrylate resin, a polyimide resin, a polyamide resin, a siloxane resin, an acrylic resin, and / or an epoxy resin.

[0126] Reference Figure 14 and Figure 15 , a lower electrode 290 may be formed on the planarization layer 270 and in the display area 10. The lower electrode 290 may be connected to the drain electrode 230 through a contact hole formed by removing a portion of the planarization layer 270. Each of the lower electrodes 290 may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination with one another. Alternatively, the lower electrode 290 may have a multilayer structure including a plurality of layers.

[0127] A connection pattern 295 may be formed on a portion of the first power wiring 350 and a portion of the planarization layer 270 in the peripheral region 20. In an exemplary embodiment, the connection pattern 295 may directly contact the top surface of the planarization layer 270, the sidewalls of the planarization layer 270, and a portion of the top surface of the first end 353 in the second peripheral region 22. Furthermore, the connection pattern 295 may not be formed in the first peripheral region 21. The connection pattern 295 may be formed using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These materials may be used alone or in combination. Alternatively, the connection pattern 295 may have a multilayer structure comprising multiple layers. In an exemplary embodiment, the lower electrode 290 and the connection pattern 295 may be located on the same layer. For example, after forming the second initial electrode layer entirely on the lower substrate 110, the second initial electrode layer is selectively etched, so that the lower electrode 290 and the connection pattern 295 can be formed simultaneously.

[0128] A pixel-defining layer 310 may be formed on a portion of the lower electrode 290, a portion of the connection pattern 295, and the planarization layer 270. The pixel-defining layer 310 may cover both sides of the lower electrode 290 and one side of the connection pattern 295, while exposing a portion of the top surface of the lower electrode 290. In an exemplary embodiment, the pixel-defining layer 310 adjacent to the first peripheral region 21 may not directly contact the first wiring portion 361, and the pixel-defining layer 310 adjacent to the second peripheral region 22 may directly contact a portion of the second wiring portion 362. The pixel-defining layer 310 may be formed using an organic material.

[0129] A light-emitting layer 330 may be formed on the lower electrode 290 exposed by the pixel defining layer 310. The light-emitting layer 330 may be formed by using at least one light-emitting material configured to emit light of different colors (such as red, green, and blue) according to the sub-pixel. Alternatively, the light-emitting layer 330 may be formed by laminating a plurality of light-emitting materials capable of producing light of different colors (such as red, green, and blue) so that white light can be emitted. In this case, a color filter may be formed on the light-emitting layer 330. The color filter may include at least one of a red color filter, a green color filter, and a blue color filter. Alternatively, the color filter may further include a yellow color filter, a cyan color filter, and a magenta color filter. The color filter may be formed using a photosensitive resin, a color photoresist, or the like.

[0130] The upper electrode 340 may be formed on a portion of the connection pattern 295, on the pixel defining layer 310, and on the light emitting layer 330. In an exemplary embodiment, the upper electrode 340 may cover the light emitting layer 330 and the pixel defining layer 310 and extend from the display area 10 to the peripheral area 20. In an exemplary embodiment, the upper electrode 340 located in the second peripheral area 22 may be in direct contact with a portion of the top surface of the connection pattern 295. In addition, the upper electrode 340 located in the first peripheral area 21 may not be in direct contact with the first wiring portion 361. The upper electrode 340 may be formed by using a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, or the like. These may be used alone or in combination with each other. Alternatively, the upper electrode 340 may have a multilayer structure including a plurality of layers. Thus, a sub-pixel structure 200 including a lower electrode 290, a light emitting layer 330, and an upper electrode 340 may be formed.

[0131] Reference Figure 16 and Figure 17 , a sealant 390 may be formed on the first power wiring 350 and in the peripheral region 20. For example, the sealant 390 formed in the first peripheral region 21 is defined as a first seal portion 391. The sealant 390 formed in the second peripheral region 22 is defined as a second seal portion 392. However, the first seal portion 391 and the second seal portion 392 may be a single integrated unit (see FIG. Figure 3 A bottom surface of the sealant 390 may be in direct contact with a portion of the interlayer insulating layer 190 and / or a portion of the first power wiring 350 .

[0132] For example, Figure 16 As shown in FIG, the first sealing portion 391 may be formed solely on the first power wiring 350. For example, a bottom surface of the first sealing portion 391 may be in direct contact with a top surface of the first power wiring 350.

[0133] In addition, if Figure 17 , a second sealing portion 392 may be formed simultaneously on the first power wiring 350 and the interlayer insulating layer 190. For example, the bottom surface of the second sealing portion 392 may directly contact the upper surface of the first power wiring 350 and the top surface of the interlayer insulating layer 190 at the same time.

[0134] The sealant 390 may be formed by using glass frit or the like. Furthermore, the sealant 390 may further include a photocurable material. For example, the sealant 390 may include a mixture of an organic material and a photocurable material, and the photocurable material included in the sealant 390 may include epoxy acrylate resin, polyester acrylate resin, urethane acrylate resin, polybutadiene acrylate resin, silicone acrylate resin, alkyl acrylate resin, or the like.

[0135] An upper substrate 410 may be formed on the sealant 390 and the upper electrode 340. The upper substrate 410 may be formed using the same material as that of the lower substrate 110. For example, the upper substrate 410 may include a quartz substrate, a synthetic quartz substrate, a calcium fluoride substrate, a fluorine-doped (F-doped) quartz substrate, a soda-lime glass substrate, a non-alkali glass substrate, or the like. Alternatively, after the sealant 390 is formed on the bottom surface of the upper substrate 410, the lower substrate 110 may be bonded to the sealant 390.

[0136] After forming the upper substrate 410 on the sealant 390, the portion of the upper substrate 410 under which the sealant 390 is disposed can be exposed using ultraviolet rays, laser, visible light, or the like, and the mixture of the sealant 390 can be cured to obtain the sealant 390. For example, after irradiating a mixture of an organic material and a photocurable material with a laser, the mixture can change from a solid state to a liquid state under the irradiation of the laser, and the mixture in the liquid state can be cured to a solid state after a predetermined time. The upper substrate 410 can be sealed and bonded to the lower substrate 110 according to the state change of the mixture. Thus, it is possible to manufacture Figure 6 and Figure 7 The organic light emitting diode display device 100 shown in FIG.

[0137] Figure 18 is a plan view illustrating an organic light emitting diode display device according to an exemplary embodiment of the present invention. Figure 19 It is along Figure 18 A cross-sectional view taken along line III-III'. Figure 20 It is along Figure 18 In addition to the first power supply wiring 350, Figure 18 and Figure 19 The organic light emitting diode display device 500 shown in FIG may have the same Figures 1 to 7The configuration of the organic light emitting diode display device 100 described above is substantially the same or similar. Figure 18 、 Figure 19 and Figure 20 In the reference Figures 1 to 7 The description of components that are substantially identical or similar is repeated. Therefore, it can be assumed that those elements that are not described in detail here are at least similar to the corresponding elements that have already been described.

[0138] Reference Figure 18 and Figure 20 The organic light emitting diode display device 500 may include a lower substrate 110, a semiconductor element 250, a first power wiring 350, a second power wiring 380, a planarization layer 270, a connection pattern 295, a pixel defining layer 310, a sub-pixel structure 200, a sealant 390, an upper substrate 410, etc. In an exemplary embodiment, the sealant 390 may be divided into a first sealing portion 391 and a second sealing portion 392, and the first power wiring 350 may be divided into a first wiring portion 361 at least partially overlapping the first sealing portion 391 and a second wiring portion 362 at least partially overlapping the second sealing portion 392.

[0139] The first power wiring 350 may be disposed in the peripheral region 20 on the interlayer insulating layer 190. For example, the first power wiring 350 may be disposed on the interlayer insulating layer 190 to be spaced apart from the source electrode 210 and the drain electrode 230.

[0140] The first power wiring 350 (e.g., the first wiring portion 361) may be overlapped between the interlayer insulating layer 190 and the first sealing portion 391. The first power wiring 350 located in the first peripheral region 21 may include a protrusion that protrudes from a first side of the first sealing portion 391 along the first direction D1. Here, the protrusion may be defined as the first end 351 of the first power wiring 350 located in the first peripheral region 21. For example, the first power wiring 350 located in the first peripheral region 21 may include a first end 351 and a second end 352. For example, the first end 351 may be adjacent to the subpixel structure 200, and the second end 352 may at least partially overlap with the first sealing portion 391. For example, the first end 351 may be exposed and separated from the planarization layer 270 located in the display area 10 adjacent to the first peripheral region 21. The second end 352 may be covered by the first sealing portion 391 and may not be exposed. The first power wiring 350 located in the first peripheral region 21 may have a first width W1.

[0141] The first power wiring 350 (e.g., the second wiring portion 362) may be stacked between the interlayer insulating layer 190 and the second sealing portion 392. The first power wiring 350 located in the second peripheral region 22 may include a protrusion protruding from a first side of the second sealing portion 392 along the third direction D3. The first power wiring 350 located in the second peripheral region 22 may have a first width W1 (see FIG. Figure 18 For example, the first power wiring 350 may have the same width in the peripheral region 20, and the shape overlapped between the first power wiring 350 and the sealant 390 located in the first peripheral region 21 may be substantially the same as the shape overlapped between the first power wiring 350 and the sealant 390 located in the second peripheral region 22.

[0142] The present invention can be applied to various display devices including OLED display devices. For example, the present invention can be applied to vehicle-mounted display devices, ship-mounted display devices, aircraft-mounted display devices, portable communication devices, display devices for display or for information transmission, medical display devices, etc.

[0143] The foregoing is an illustration of exemplary embodiments of the present inventive concept. Although some exemplary embodiments of the present inventive concept have been described, those skilled in the art will readily appreciate that many modifications of the exemplary embodiments are possible without materially departing from the novel teachings and aspects of the present inventive concept. Therefore, all such modifications are intended to be included within the scope of this disclosure.

Claims

1. An organic light emitting diode display device, comprising: a lower substrate comprising a display area, a peripheral area and a pad area, wherein the peripheral area comprises a first peripheral area and a second peripheral area; a sub-pixel structure, arranged in the display area of ​​the lower substrate; a planarization layer, disposed between the lower substrate and the sub-pixel structure; an interlayer insulating layer, disposed between the lower substrate and the planarization layer; an upper substrate, disposed on the sub-pixel structure; a sealant disposed in the peripheral region of the lower substrate between the interlayer insulating layer and the upper substrate, the sealant comprising: a first sealing portion disposed in the first peripheral region adjacent to the pad region; and a second sealing portion disposed in the second peripheral region; and a first power wiring disposed between the interlayer insulating layer and the sealant, the first power wiring at least partially overlapping each of the interlayer insulating layer and the sealant, the first power wiring including a first protrusion protruding from a first side of the first sealing portion in a first direction in the first peripheral region, the first direction being a direction from the pad region to the display region, wherein the first protruding portion of the first power wiring is separated from the planarization layer, and The upper surface of the interlayer insulating layer is in contact with the lower surface of the planarization layer and the lower surface of the first power wiring, and the lower surface of the first power wiring is in contact only with the upper surface of the interlayer insulating layer.

2. The organic light emitting diode display device according to claim 1, wherein: The first power wiring further includes a second protrusion protruding from a second side of the first sealing portion in the first peripheral region in a second direction opposite to the first direction.

3. The organic light emitting diode display device according to claim 2, further comprising a plurality of pad electrodes disposed in the pad region, wherein: Each of the plurality of pad electrodes is arranged along a third direction that is orthogonal to the first direction and the second direction.

4. The organic light emitting diode display device according to claim 3, wherein: The first protrusion is adjacent to the sub-pixel structure, and the second protrusion is adjacent to the plurality of pad electrodes.

5. The organic light emitting diode display device according to claim 4, wherein: The first power supply wiring includes a first wiring portion located in a portion of the first peripheral region and a second wiring portion located in the second peripheral region, and Here, the first wiring portion and the second wiring portion together are a single integrated unit, and the first power wiring has a ring shape with an open lower portion.

6. The organic light emitting diode display device according to claim 5, further comprising a second power wiring provided on the lower substrate between ends of the first power wiring in the first peripheral region, wherein The second power supply wiring is configured to receive a high power supply voltage.

7. The organic light emitting diode display device according to claim 5, wherein: A first width of the first wiring portion of the first power wiring measured in the first direction is greater than a second width of the second wiring portion of the first power wiring measured in a third direction from the second peripheral area to the display area.

8. The organic light emitting diode display device according to claim 1, wherein: The first power wiring further includes a third protrusion protruding from the second sealing portion in the second peripheral region in a direction from the second peripheral region to the display region.

9. The organic light emitting diode display device according to claim 8, wherein: the first power supply wiring provided in the second peripheral area includes a first end corresponding to the third protrusion protruding from the second sealing portion and a second end opposite to the first end; and Wherein, the second sealing portion at least partially covers the second end.

10. The organic light emitting diode display device according to claim 1, wherein: The first sealing portion and the second sealing portion are a single integrated unit.

11. The organic light emitting diode display device according to claim 6, wherein: The sub-pixel structure includes: a lower electrode disposed on the lower substrate; a light-emitting layer disposed on the lower electrode; and an upper electrode disposed on the light-emitting layer. wherein the first power supply wiring is configured to receive a low power supply voltage lower than the high power supply voltage, and The low power supply voltage is supplied to the upper electrode through the first power supply wiring.

12. The organic light emitting diode display device according to claim 11, further comprising a connection pattern provided between the upper electrode and the first power wiring, in, The upper electrode is electrically connected to the first power wiring through the connection pattern.

13. The organic light emitting diode display device according to claim 12, wherein: The connection pattern and the lower electrode are formed simultaneously using the same material.

14. The organic light emitting diode display device according to claim 1, further comprising: A semiconductor element is disposed between the sub-pixel structure and the lower substrate, Wherein, the planarization layer is arranged between the semiconductor element and the sub-pixel structure.

15. The organic light emitting diode display device according to claim 14, wherein: The semiconductor element includes: an active layer, which is arranged in the display area on the lower substrate; a gate insulating layer, which is arranged on the active layer; a gate electrode, which is arranged on the gate insulating layer; the interlayer insulating layer, which is arranged on the gate electrode; and a source electrode and a drain electrode, both of which are arranged on the interlayer insulating layer.

16. The organic light emitting diode display device according to claim 15, wherein: The first power supply wiring is provided on the same layer as the source electrode and the drain electrode.

17. The organic light emitting diode display device according to claim 15, wherein: The first sealing portion contacts the first power wiring, and the second sealing portion contacts both the first power wiring and the interlayer insulating layer.

18. The organic light emitting diode display device according to claim 1, wherein: When viewed from the top, the sealant has a rectangular planar shape having an opening exposing the display area.

19. The organic light emitting diode display device according to claim 1, wherein: A total length of the second peripheral region and the pad region extending along the first direction is 2.22 mm or less.

20. The organic light emitting diode display device according to claim 1, wherein: The peripheral area at least partially surrounds the display area, and the pad area is provided at one side of the peripheral area.

21. An emissive display device, comprising: a base substrate comprising a display area, a pad area, a first peripheral area, and a second peripheral area, wherein an image is displayed in the display area, a plurality of connection pads are disposed in the pad area, the first peripheral area is disposed between the display area and the pad area, and the second peripheral area at least partially surrounds the display area; a first power supply wiring disposed in the first peripheral region of the base substrate; a second power supply wiring disposed in the second peripheral region of the base substrate; a planarization layer, disposed on the base substrate to cover the second power wiring; an interlayer insulating layer, disposed between the base substrate and the planarization layer; a top substrate formed on the base substrate; as well as a sealant surrounding the display area of ​​the base substrate and disposed between the interlayer insulating layer and the top substrate, wherein the first power wiring is provided between the sealant and the interlayer insulating layer to overlap with the sealant, wherein a portion of the second power wiring is disposed between the display area and the sealant so as not to overlap with the sealant; wherein the first power wiring includes a first protrusion protruding from a first side of the sealant in a first direction in the first peripheral region, the first direction being a direction from the pad region to the display region, wherein the first protruding portion of the first power wiring is separated from the planarization layer, and The upper surface of the interlayer insulating layer is in contact with the lower surface of the planarization layer and the lower surface of the first power wiring, and the lower surface of the first power wiring is in contact only with the upper surface of the interlayer insulating layer.

22. The emissive display device according to claim 21, wherein The first power supply wiring has a width greater than that of the second power supply wiring.

23. The emissive display device according to claim 21, wherein The first power supply wiring is configured to absorb and reflect laser light.

24. The emissive display device according to claim 21, wherein The first power supply wiring is configured to receive a first power supply voltage, and the second power supply wiring is configured to receive a second power supply voltage higher than the first power supply voltage.

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