Display device, method of manufacturing a polysilicon layer and display device

Abstract

A display device and a method of manufacturing a polysilicon layer and a display device are provided. The display device can include a substrate, a thin film transistor disposed on the substrate, and a display element electrically connected to the thin film transistor. The thin film transistor can include an active pattern including polysilicon, a gate insulating layer disposed on the active pattern, and a gate electrode disposed on the gate insulating layer. An average value of a grain size of the active pattern can be in a range of about 400 nm to about 800 nm. An RMS value of a surface roughness of the active pattern can be about 4 nm or less. A method of manufacturing a polysilicon layer can include cleaning an amorphous silicon layer with hydrofluoric acid, rinsing the amorphous silicon layer with hydrogenated deionized water, and irradiating the amorphous silicon layer with a laser beam having an energy density of about 440 mJ / cm 2 to about 490 mJ / cm 2 .

Description

Technical Field

[0001] This disclosure relates to a display device. More specifically, this disclosure relates to a method for manufacturing a polysilicon layer, a display device including the polysilicon layer, and a method for manufacturing the display device. Background Technology

[0002] Active matrix (AM) type organic light-emitting display devices can include pixel circuitry in each pixel. Pixel circuitry can include silicon-based thin-film transistors (TFTs). TFTs can be formed from amorphous silicon or polycrystalline silicon. In an example where the active layer of the TFT, including the source, drain, and channel, is formed from amorphous silicon (a-Si), the a-Si TFT used in the pixel circuitry can have low electron mobility, for example, approximately 1 cm⁻¹. 2 / Vs or even smaller mobility. Therefore, a-Si TFTs have recently been replaced by polysilicon (poly-Si) TFTs, which have higher electron mobility and safer illumination than a-Si TFTs. Therefore, polysilicon (poly-Si) TFTs can be used as the active layer for driving TFTs and / or switching TFTs in AM-type organic light-emitting display devices.

[0003] Polycrystalline Si materials used in polycrystalline Si TFTs can be manufactured using several methods. These methods can generally be categorized into methods for depositing polycrystalline Si or methods for depositing a-Si and crystallizing it. Examples of methods for depositing polycrystalline Si include chemical vapor deposition (CVD), sputtering, and vacuum evaporation. Examples of methods for depositing a-Si and crystallizing it include solid-state crystallization (SPC), excimer laser crystallization (ELC), metal-induced crystallization (MIC), metal-induced lateral crystallization (MILC), and sequential lateral curing (SLS). Summary of the Invention

[0004] An embodiment provides a display device including a thin-film transistor with improved characteristics.

[0005] The embodiments provide a method for manufacturing a polycrystalline silicon layer having a large grain size and a small surface roughness.

[0006] The embodiments provide a method for manufacturing a display device for improving the characteristics of thin-film transistors.

[0007] The display device may include a substrate, a thin-film transistor disposed on the substrate, and a display element electrically connected to the thin-film transistor. The thin-film transistor may include an active pattern disposed on the substrate, an insulating layer disposed on the active pattern, and a gate electrode disposed on the insulating layer. The active pattern may include polysilicon. The active pattern may include a die, and the average size of the die may be in the range of approximately 400 nm to approximately 800 nm.

[0008] Active patterns may include surfaces with protrusions formed thereon between adjacent grains in a die, and the thickness of the protrusions may be approximately 4 nm or less. The thickness of the protrusions may correspond to the distance between the top of the protrusion and the surface of the active pattern in the adjacent grain. Active patterns may include rough surfaces with a roughness having a root mean square value equal to or less than approximately 4 nm. Active patterns may include grain boundaries, each of which may be formed between adjacent grains in a die, and the size of the grains may correspond to the distance between adjacent grain boundaries.

[0009] Each grain may include one or more crystal faces, and the ratio of the (111) orientation crystal face to the total number of crystal faces in the active pattern may be greater than the ratio of the (001) orientation crystal face to the total number of crystal faces.

[0010] The value obtained by dividing the sum of the ratio of the (001) orientation crystal plane to the total crystal plane of the active pattern and the ratio of the (101) orientation crystal plane to the total crystal plane by the ratio of the (111) orientation crystal plane to the total crystal plane can be approximately 0.7 or less.

[0011] An active pattern may include a source region, a drain region, and a channel region formed between the source region and the drain region.

[0012] The gate electrode can be stacked with the channel region of the active pattern.

[0013] The thin-film transistor may also include a source electrode and a drain electrode disposed on the gate electrode, and the source electrode and the drain electrode may be electrically connected to the source region and the drain region of the active pattern, respectively.

[0014] A display element may include a first electrode electrically connected to a thin-film transistor, an emitter layer disposed on the first electrode, and a second electrode disposed on the emitter layer.

[0015] A method for manufacturing a polycrystalline silicon layer may include forming an amorphous silicon layer on a substrate, cleaning the amorphous silicon layer with hydrofluoric acid, rinsing the amorphous silicon layer with hydrogenated deionized water, and using a solution having a concentration of approximately 440 mJ / cm². 2 Up to approximately 490 mJ / cm 2 A laser beam with energy density within the range is used to irradiate an amorphous silicon layer to form a polycrystalline silicon layer.

[0016] The thickness of the amorphous silicon layer can be approximately up to approximately Within the range.

[0017] Hydrofluoric acid can include approximately 0.5% hydrogen fluoride by mass.

[0018] The cleaning process for the amorphous silicon layer can be performed in a timeframe of approximately 60 to 120 seconds.

[0019] The hydrogen concentration in hydrogenated deionized water can be approximately 1.0 ppm.

[0020] The wavelength of the laser beam can be approximately 308 nm.

[0021] The scanning spacing of the laser beam can be approximately 10 μm or less.

[0022] The step of forming a polycrystalline silicon layer may include forming grains in the polycrystalline silicon layer, and the average size of the grains in the polycrystalline silicon layer may be in the range of about 400 nm to about 800 nm.

[0023] The step of forming a polysilicon layer may include forming a rough surface of the polysilicon layer, and the root mean square (RMS) value of the roughness of the rough surface of the polysilicon layer may be about 4 nm or less.

[0024] A method for manufacturing a display device may include the following steps: forming an amorphous silicon layer on a substrate; cleaning the amorphous silicon layer with hydrofluoric acid; rinsing the amorphous silicon layer with hydrogenated deionized water; and using a solution having approximately 440 mJ / cm². 2 Up to approximately 490 mJ / cm 2 A laser beam of energy density is used to irradiate an amorphous silicon layer to form a polycrystalline silicon layer; the polycrystalline silicon layer is etched to form a polycrystalline silicon pattern; a gate insulating layer is formed on the polycrystalline silicon pattern; a gate electrode is formed on the gate insulating layer; ions are implanted at portions of the polycrystalline silicon pattern to form an active pattern; and a display element is formed on the gate electrode.

[0025] The steps of forming a display element may include forming a first electrode on a gate electrode, forming an emitter layer on the first electrode, and forming a second electrode on the emitter layer, wherein the first electrode is electrically connected to an active pattern.

[0026] In display devices, the active patterns of thin-film transistors (TFTs), including those made of polycrystalline silicon, can have relatively large grain sizes and relatively small surface roughness. Therefore, characteristics of TFTs such as charge mobility and hysteresis can be improved.

[0027] In methods for manufacturing polycrystalline silicon layers, the amorphous silicon layer can be cleaned and rinsed before crystallizing to form the polycrystalline silicon layer, and the amorphous silicon layer can be irradiated with a laser beam having a relatively high energy density. Therefore, a polycrystalline silicon layer with a relatively large grain size and a relatively small surface roughness can be formed.

[0028] In a method for manufacturing a display device, before crystallizing the amorphous silicon layer to form an active pattern including polycrystalline silicon, the amorphous silicon layer can be cleaned and rinsed, and the amorphous silicon layer can be irradiated with a laser beam having a relatively high energy density. Therefore, characteristics of thin-film transistors such as charge mobility and hysteresis can be improved. Attached Figure Description

[0029] The illustrative and non-limiting embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings.

[0030] Figure 1 This is a flowchart illustrating a method for manufacturing a polycrystalline silicon layer according to an embodiment.

[0031] Figure 2 , Figure 3 , Figure 4 and Figure 5 This is a schematic diagram illustrating a method for manufacturing a polycrystalline silicon layer according to an embodiment.

[0032] Figure 6 and Figure 7 This is a schematic diagram explaining the polysilicon layer according to an embodiment.

[0033] Figure 8 This is a schematic cross-sectional view showing a thin-film transistor substrate according to an embodiment.

[0034] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 This is a schematic cross-sectional view illustrating a method for manufacturing a thin-film transistor substrate according to an embodiment.

[0035] Figure 16 This is a schematic diagram of the equivalent circuit of a pixel in a display device according to an embodiment.

[0036] Figure 17 This is a schematic cross-sectional view showing a display device according to an embodiment.

[0037] Figure 18 and Figure 19 This is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an embodiment. Detailed Implementation

[0038] In the following sections, examples of methods for manufacturing polycrystalline silicon layers, thin-film transistor substrates, and methods for manufacturing thin-film transistor substrates, as well as display devices and methods for manufacturing display devices, will be explained in detail with reference to the accompanying drawings.

[0039] Specific examples are shown in the accompanying drawings and described in detail in the specification. However, the disclosed systems and apparatus can be modified in various ways and take various forms different from the detailed drawings but consistent with this disclosure. Therefore, it should be understood that this disclosure is not intended to be limited to the specific forms disclosed. Furthermore, it should be understood that the disclosure is intended to cover all modifications, equivalents, and substitutions within the spirit and technical scope of the disclosure. It should be further understood that in this application, the terms "comprising" or "having," etc., are used to describe the presence of features, numbers, steps, operations, elements, components, or combinations thereof described in the specification, but do not preclude the possibility of the presence or addition of one or more other features, numbers, steps, operations, elements, components, or combinations thereof.

[0040] When a layer, membrane, region, substrate, or area is referred to as being "on" another layer, membrane, region, substrate, or area, it may be directly on said other layer, membrane, region, substrate, or area, or there may be an intermediate layer, membrane, region, substrate, or area therein. Conversely, when a layer, membrane, region, substrate, or area is referred to as being "directly on" another layer, membrane, region, substrate, or area, there may be no intermediate layer, membrane, region, substrate, or area therein. Furthermore, when a layer, membrane, region, substrate, or area is referred to as being "below" another layer, membrane, region, substrate, or area, it may be directly below said other layer, membrane, region, substrate, or area, or there may be an intermediate layer, membrane, region, substrate, or area therein. Conversely, when a layer, membrane, region, substrate, or area is referred to as being "directly below" another layer, membrane, region, substrate, or area, there may be no intermediate layer, membrane, region, substrate, or area therein. Furthermore, "above" or "on" can include being positioned on or below a target and does not necessarily imply a direction based on gravity.

[0041] Furthermore, for ease of description, the spatial relative terms "below," "under," "down," "above," or "above," etc., may be used herein to describe the relationship between one element or component and another, as shown in the accompanying drawings. It will be understood that the spatial relative terms are intended to include different orientations of the device in use or operation, and more specifically, to include the orientation depicted in the accompanying drawings. In different examples, where the device shown in the accompanying drawings is flipped, a device positioned "below" or "under" another device may be placed "above" another device. Therefore, the illustrative term "below" can include both a lower and upper position. The device may also be positioned in other orientations, and thus the spatial relative terms may be interpreted differently depending on the orientation.

[0042] Throughout this specification, when an element is referred to as being “connected” to another element, the element may be “directly connected” to said other element or “indirectly connected” to said other element with one or more intermediate elements situated therebetween. It will also be understood that when the terms “comprising” and / or “including” and variations thereof are used in this specification, they or they may indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integrals, steps, operations, elements, components, and / or any combination thereof.

[0043] It will also be understood that although the terms "first," "second," or "third," etc., may be used herein to describe various elements, such elements should not be limited by these terms. These terms are used to distinguish one element from another or for ease of description and explanation. In different examples, when "first element" is discussed in the description, it may be referred to as "second element" or "third element," and "second element" and "third element" may be named in a similar manner without departing from the teaching. In different examples, the first color filter may be any one of a red color filter, a green color filter, and a blue color filter. The second color filter may be any one of a red color filter, a green color filter, and a blue color filter. The third color filter may be any one of a red color filter, a green color filter, and a blue color filter. The terms "first" and "second" relative to the light-blocking member may be used interchangeably in the specification.

[0044] Furthermore, taking into account the measurements discussed and the errors associated with the measurement of specific quantities (i.e., limitations of the measurement system), the terms "approximately" or "roughly" as used herein include stated values ​​and indicate an acceptable range of deviation from the specific value as determined by one of ordinary skill in the art. In various examples, "approximately" may mean within one or more standard deviations, or within ±5%, ±10%, ±20%, ±30%, or ±80% of said value.

[0045] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless clearly defined in the specification. Furthermore, the phrase "in a plan view" refers to the view of the target portion from above, and the phrase "in a sectional view" refers to the view of the cross-section taken by vertically cutting the target portion from the side.

[0046] In view of this disclosure, those skilled in the art will understand that, although for ease of explanation, various processes / operations of the various methods discussed below may be shown according to one or more specific sequences, certain processes / operations may be performed in different sequences or in parallel in different method examples. It will also be understood that certain processes / operations may be omitted in the various examples of the disclosed methods. Therefore, the specific order of processes / operations should be determined by the language of the claims, rather than inferred from the description.

[0047] Switch to the attached image. Figure 1 This is a flowchart illustrating an embodiment of a method for manufacturing a polycrystalline silicon layer. Figure 2 , Figure 3 , Figure 4 and Figure 5 This is a schematic diagram illustrating an embodiment of a method for manufacturing a polycrystalline silicon layer.

[0048] Reference Figure 1 and Figure 2 An amorphous silicon layer 132 (S110) can be formed on the substrate 110. The substrate 110 can be an insulating substrate including glass, quartz, ceramic, etc. The substrate 110 can also be an insulating flexible substrate including plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyetheretherketone (PEEK), polycarbonate (PC), polyarylate, polyethersulfone (PES), polyimide (PI), etc.

[0049] A buffer layer 120 may be formed on the substrate 110. The buffer layer 120 may provide a flat or planarized surface above the substrate 110. The buffer layer 120 may prevent impurities from penetrating through the substrate 110. For example, the buffer layer 120 may be formed of silicon oxide, silicon nitride, or combinations thereof.

[0050] An amorphous silicon layer 132 can be formed on the buffer layer 120. The amorphous silicon layer 132 can be formed by methods such as low-pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, vacuum evaporation, or combinations thereof.

[0051] The thickness of the amorphous silicon layer 132 can be approximately up to approximately Within the range. If the thickness of the amorphous silicon layer 132 is less than approximately This could lead to a decrease in the hysteresis characteristics of thin-film transistors formed by crystallizing amorphous silicon layer 132 into polycrystalline silicon layer.

[0052] A native oxide layer (NOL) can be formed on the amorphous silicon layer 132. The native oxide layer (NOL) can be formed when the upper part of the amorphous silicon layer 132 is exposed to air. When the native oxide layer (NOL) remains on the amorphous silicon layer 132, in subsequent processes used to crystallize the amorphous silicon layer 132 to form a polycrystalline silicon layer, protrusions with a relatively large thickness can be formed on the surface of the polycrystalline silicon layer by the native oxide layer (NOL).

[0053] Reference Figure 1 and Figure 3 It can clean the amorphous silicon layer 132 (S120).

[0054] Hydrofluoric acid 210 can be used, for example, to clean the amorphous silicon layer 132. Hydrofluoric acid 210 can be an aqueous solution in which hydrogen fluoride (HF) is dissolved. For example, hydrofluoric acid 210 may include approximately 0.5% hydrogen fluoride by mass. The amorphous silicon layer 132 can be cleaned with hydrofluoric acid 210 to remove the native oxide layer NOL formed on the amorphous silicon layer 132.

[0055] The amorphous silicon layer 132 can be cleaned for approximately 60 seconds to approximately 120 seconds. If the amorphous silicon layer 132 is cleaned for less than approximately 60 seconds, the native oxide layer NOL formed on the amorphous silicon layer 132 cannot be sufficiently or properly removed, and the grains of the subsequently formed polycrystalline silicon layer cannot grow adequately. If the amorphous silicon layer 132 is cleaned for more than approximately 120 seconds, the amorphous silicon layer 132 may be affected by hydrofluoric acid 210, and the grains of the subsequently formed polycrystalline silicon layer may crack.

[0056] Reference Figure 1 and Figure 4 The amorphous silicon layer 132 can be rinsed (S130). Hydrogenated deionized water 220 can be used, for example, to rinse the amorphous silicon layer 132. The hydrogen concentration of the hydrogenated deionized water 220 can be approximately 1.0 ppm. The hydrogenated deionized water 220 can be supplied to the amorphous silicon layer 132 via a nozzle 230. In an embodiment, the substrate 110 disposed below the nozzle 230 is movable, and the nozzle 230 can be fixed. Hydrofluoric acid 210 remaining on the amorphous silicon layer 132 can be removed by rinsing the amorphous silicon layer 132 with hydrogenated deionized water 220.

[0057] If the amorphous silicon layer 132 is rinsed with dehydrogenated deionized water, oxygen from the deionized water may remain on the amorphous silicon layer 132, which could cause or lead to visible circular defects due to oxygen after the crystallization process. However, in this example and other possible examples, the amorphous silicon layer 132 can be rinsed with hydrogenated deionized water 220 to prevent such circular defects.

[0058] Reference Figure 1 and Figure 5A polycrystalline silicon layer 134 (S140) can be formed. The polycrystalline silicon layer 134 can be formed by irradiating the amorphous silicon layer 132 with a laser beam 240. A laser 250 can generate a laser beam 240 to irradiate the amorphous silicon layer 132. The laser 250 can generate the laser beam 240 intermittently. The laser 250 can be an excimer laser for generating the laser beam 240, which can have a relatively short wavelength, relatively high power, and / or relatively high efficiency. The excimer laser can include, for example, inert gases, inert gas halides, mercury halides, inert gas acid compounds, polyatomic excimers, or combinations thereof. Examples of inert gases are Ar2, Kr2, and Xe2. Examples of inert gas halides are ArF, ArCl, KrF, KrCl, XeF, and XeCl. Examples of mercury halides are HgCl, HgBr, and HgI. Examples of inert gas acid compounds are ArO, KrO, and XeO. Examples of polyatomic excimers are Kr2F and Xe2F.

[0059] The amorphous silicon layer 132 can be crystallized into a polycrystalline silicon layer 134 by irradiating it with a laser beam 240 emitted from the laser 250. For example... Figure 5 As shown, the substrate 110 can be moved along direction D1. In other embodiments, the laser can be moved along the substrate to irradiate an amorphous silicon layer disposed on the substrate with a laser beam. The wavelength of the laser beam 240 irradiating the amorphous silicon layer 132 can be approximately 308 nm.

[0060] Laser 250 can operate at approximately 440 mJ / cm². 2 Up to approximately 490 mJ / cm 2 A laser beam 240 with an energy density within the range of approximately 440 mJ / cm² is used to irradiate the amorphous silicon layer 132. If the energy density of the laser beam 240 is less than approximately 440 mJ / cm², then... 2 Then the grain size of the polycrystalline silicon layer 134 may be relatively small. If the energy density of the laser beam 240 is greater than approximately 490 mJ / cm², then... 2 If this happens, the amorphous silicon layer 132 may be completely liquefied by the laser beam 240, making it impossible to form seed crystals for silicon crystallization.

[0061] The scanning spacing of the laser beam 240 can be approximately 10 μm or less. When the scanning spacing of the laser beam 240 is approximately 10 μm or less, a polycrystalline silicon layer 134 with a relatively large grain size can be formed. For example... Figure 5 As shown, the region in which the crystallization process is performed using the laser beam 240 can be converted from amorphous silicon to polycrystalline silicon, such that the polycrystalline silicon layer 134 can be formed from the amorphous silicon layer 132.

[0062] Figure 6 and Figure 7This is a schematic diagram illustrating a polysilicon layer according to an embodiment. It can be seen, for example, by referring to... Figures 1 to 5 The described manufacturing method forms Figure 6 and Figure 7 The polycrystalline silicon layer 134 shown is illustrated.

[0063] Reference Figure 5 , Figure 6 and Figure 7 One or more grains 134a can be formed in the polycrystalline silicon layer 134. When the laser beam 240 irradiates the solid amorphous silicon layer 132, the amorphous silicon layer 132 can absorb heat and change to a liquid state. The amorphous silicon layer 132 can release heat and change to a solid state again. Through irradiation by the laser beam 240, and due to the irradiation by the laser beam 240, crystals can grow from seed crystals to form grains 134a. When there is a difference in the cooling rate of the amorphous silicon layer 132 during the process of the amorphous silicon layer 132 changing from a liquid state to a solid state, because the grains 134a grow from the region with a relatively high cooling rate to the region with a relatively slow cooling rate, grain boundaries 134b can be formed in the region with a relatively slow cooling rate.

[0064] When using a wavelength of approximately 308 nm and approximately 440 mJ / cm 2 Up to approximately 490 mJ / cm 2 When a laser beam 240 of a certain energy density irradiates the amorphous silicon layer 132 with a scanning interval of approximately 10 μm or less as described above, the average grain size can be in the range of approximately 400 nm to approximately 800 nm. Here, the grain size of grain 134a can represent the width of grain 134a in a planar view. The grain size can be the distance between adjacent grain boundaries 134b. The size of grain 134a of polysilicon layer 134 can be determined by the wavelength, scanning interval, energy density, etc., or combinations thereof, of the laser beam 240 irradiated from laser 250. For example, the larger the wavelength of laser beam 240, the smaller the scanning interval of laser beam 240, and the greater the energy density of laser beam 240, the larger the size of grain 134a of polysilicon layer 134.

[0065] In conventional methods for fabricating polycrystalline silicon layers, wavelengths of approximately 308 nm and relatively low energy densities (e.g., approximately 410 mJ / cm²) can be used. 2 Up to approximately 440 mJ / cm 2A laser beam can be used to irradiate an amorphous silicon layer with a relatively large scanning interval (e.g., approximately 15 μm to approximately 25 μm), and a polycrystalline silicon layer with a relatively small grain size (e.g., an average grain size of less than approximately 300 nm) can be formed. However, in this embodiment of the invention and other possible embodiments, a wavelength of approximately 308 nm and a relatively large energy density (e.g., approximately 440 mJ / cm²) can be used. 2 Up to approximately 490 mJ / cm 2 A laser beam 240 irradiates an amorphous silicon layer 132 at a relatively small scanning interval (e.g., approximately 10 μm or less), and can form a polycrystalline silicon layer 134 with a relatively large grain size (e.g., an average grain size in the range of approximately 400 nm to approximately 800 nm). Each grain 134a of the polycrystalline silicon layer 134 may include one or more crystal faces. The crystal faces of each grain 134a may include crystal faces with different orientations.

[0066] The ratio of the (111) orientation crystal plane to the total number of crystal planes in the polysilicon layer 134 can be larger than the ratio of the (001) orientation crystal plane to the total number of crystal planes in the polysilicon layer 134. In conventional methods of manufacturing polysilicon layers, this results in a relatively low energy density (e.g., approximately 410 mJ / cm²). 2 Up to approximately 440 mJ / cm 2 When an amorphous silicon layer is irradiated with a laser beam having a relatively high energy density (e.g., approximately 440 mJ / cm²), the ratio of the (111) orientation crystal plane to the total number of crystal planes will be smaller than that of the (001) orientation crystal plane. However, in the method of manufacturing a polycrystalline silicon layer according to this embodiment and other possible embodiments, when a laser beam having a relatively high energy density (e.g., approximately 440 mJ / cm²) is used... 2 Up to approximately 490 mJ / cm 2 When the laser beam 240 irradiates the amorphous silicon layer 132, the ratio of the (111) orientation crystal plane to the total number of crystal planes can be greater than the ratio of the (001) orientation crystal plane to the total number of crystal planes. The value obtained by dividing the sum of the ratio of the (001) orientation crystal plane to the total number of crystal planes and the ratio of the (101) orientation crystal plane to the total number of crystal planes by the ratio of the (111) orientation crystal plane to the total number of crystal planes can be approximately 0.7 or less. Here, "(111), (001), and (101)" represent the orientation index or Miller index.

[0067] Protrusions 134c can be formed at grain boundaries 134b on the surface of the polycrystalline silicon layer 134 formed by the above crystallization process. The amorphous silicon layer 132, melted by the laser beam 240, can be recrystallized to form grains 134a of the polycrystalline silicon layer 134. Protrusions 134c can be formed at grain boundaries 134b.

[0068] The size of the grain 134a and the number of protrusions 134c formed at the grain boundary 134b can be inversely proportional. For example, the larger the size of the grain 134a, the fewer the number of protrusions 134c. Since the size of the grain 134a of the polysilicon layer 134 can be relatively large, the number of protrusions 134c included per unit area can be relatively small.

[0069] The protrusions 134c may project upward from the surface of the polysilicon layer 134 and may have sharp tips. Each protrusion 134c may have a thickness TH corresponding to the distance from the surface of the polysilicon layer 134 to the tip of each protrusion 134c. For example, in a grain 134a adjacent to a protrusion 134c, the thickness TH of each protrusion 134c may be the distance between the top of the sharp tip of the protrusion 134c and the lowest level of the surface of the polysilicon layer 134. In each grain 134a, the lowest level of the surface of the polysilicon layer 134 may correspond to the surface level at the center of the grain 134a or the surface level around the center of the grain 134a.

[0070] The surface of the polysilicon layer 134 can be rough. The root mean square (RMS) value of the surface roughness of the polysilicon layer 134 can be about 4 nm or less. The RMS value of the thickness of the protrusions 134c formed on the surface of the polysilicon layer 134 can be about 4 nm or less.

[0071] A cleaning process using hydrofluoric acid 210 (S120) and a rinsing process using hydrogenated deionized water 220 (S130) can be performed before the crystallization process (S140). The crystallization process (S140) can be performed by irradiating the amorphous silicon layer 132 with a laser beam having a relatively large energy density at a relatively small scanning interval. Therefore, a polycrystalline silicon layer 134 with a relatively large grain size and a relatively small surface roughness can be formed.

[0072] The cleaning process (S120), rinsing process (S130), and crystallization process (S140) for forming the polysilicon layer 134 have been described above. However, it is possible to add processes and / or operations for forming the polysilicon layer 134 other than those described above, or to omit some of the processes and / or operations described above. It is also possible to perform different processes and / or operations at different times or within the same time period, or to perform the same processes and / or operations at different times or multiple times. For example, in different examples, the crystallization process (S140) may be performed two or more times.

[0073] In the following text, reference will be made to Figures 8 to 15 Describes thin-film transistor substrates and methods for manufacturing thin-film transistor substrates. Figure 8 This is a schematic cross-sectional view showing a thin-film transistor substrate according to an embodiment.

[0074] Reference Figure 8 The thin-film transistor substrate 100 may include a substrate 110 and a thin-film transistor TR disposed on the substrate 110. The thin-film transistor TR may include an active pattern AP, a gate insulating layer 140, a gate electrode GE, a source electrode SE, and a drain electrode DE, which are sequentially stacked. The thin-film transistor TR can perform a switching operation to allow current to flow through the active pattern AP based on a signal applied to the gate electrode GE. The thin-film transistor TR may have a top-gate structure in which the gate electrode GE is positioned above the active pattern AP. However, this example and other specific examples are not limited thereto, and the thin-film transistor TR may have a bottom-gate structure in which the gate electrode is positioned below the active pattern AP.

[0075] Figure 9 , Figure 10 , Figure 11 , Figure 12 , Figure 13 , Figure 14 and Figure 15 This explains the fabrication of thin-film transistor substrates (e.g., Figure 8 A schematic cross-sectional view of a method for fabricating a thin-film transistor substrate. In the following description of the method for fabricating a thin-film transistor substrate, the same or similar descriptions provided above for the method of fabricating a polycrystalline silicon layer will be avoided. See also... Figure 9 An amorphous silicon layer 132 can be formed on the substrate 110.

[0076] The substrate 110 may be an insulating substrate including glass, quartz, ceramic, or combinations thereof. The substrate 110 may also be an insulating flexible substrate including plastics such as PET, PEN, PEEK, PC, polyarylate, PES, PI, or combinations thereof. A barrier layer including silicon oxide, silicon nitride, amorphous silicon, or combinations thereof may be additionally formed on the substrate 110.

[0077] A buffer layer 120 can be formed on the substrate 110. The buffer layer 120 can provide a flat or planarized surface above the substrate 110. The buffer layer 120 can prevent impurities from penetrating through the substrate 110.

[0078] An amorphous silicon layer 132 can be formed on the buffer layer 120. The amorphous silicon layer 132 can be formed by methods such as LPCVD, APCVD, PECVD, sputtering, vacuum evaporation, or combinations thereof. A native oxide layer can be formed on the amorphous silicon layer 132.

[0079] The amorphous silicon layer 132 can be cleaned using hydrofluoric acid. The hydrofluoric acid may comprise approximately 0.5% hydrogen fluoride by mass. Cleaning the amorphous silicon layer 132 with hydrofluoric acid removes the native oxide layer formed on it. The cleaning time for the amorphous silicon layer 132 can be approximately 60 seconds to approximately 120 seconds. The amorphous silicon layer 132 can be rinsed with hydrogenated deionized water. The hydrogen concentration of the hydrogenated deionized water may be approximately 1.0 ppm. Rinsing the amorphous silicon layer 132 with hydrogenated deionized water removes any residual hydrofluoric acid.

[0080] Reference Figure 10 The amorphous silicon layer 132 can be crystallized to form a polycrystalline silicon layer 134. The polycrystalline silicon layer 134 can be formed by irradiating the amorphous silicon layer 132 with a laser beam. The laser can generate a laser beam to irradiate the amorphous silicon layer 132. The laser can generate the laser beam intermittently. The laser can use a laser with a voltage of approximately 440 mJ / cm². 2 Up to approximately 490 mJ / cm 2 An amorphous silicon layer 132 is irradiated with a laser beam of energy density within a certain range. The wavelength of the laser beam can be approximately 308 nm. The scanning spacing of the laser beam can be approximately 10 μm or less.

[0081] When a laser beam irradiates the solid amorphous silicon layer 132, the amorphous silicon layer 132 can absorb heat and change to a liquid state. The amorphous silicon layer 132 can release heat and change back to a solid state. Through irradiation by the laser beam 240, and due to the irradiation of the laser beam 240, crystals can grow from seed crystals to form grains. In cases where there is a difference in the cooling rate of the amorphous silicon layer 132 during the process of changing from a liquid to a solid state, grain boundaries can be formed in regions with relatively slow cooling rates because the grains grow from regions with relatively high cooling rates towards regions with relatively slow cooling rates.

[0082] One or more grains can be formed in the polysilicon layer 134. The average grain size can be in the range of approximately 400 nm to approximately 800 nm. Protrusions can be formed at the grain boundaries on the surface of the polysilicon layer 134 formed by the crystallization process. The protrusions can project upward from the surface of the polysilicon layer 134 and can have sharp tips. The protrusions can have a thickness corresponding to the distance from the surface of the polysilicon layer 134 to the tip of the protrusion. The RMS value of the surface roughness of the polysilicon layer 134 can be approximately 4 nm or less. The RMS value of the thickness of the protrusions formed on the surface of the polysilicon layer 134 can be approximately 4 nm or less.

[0083] Reference Figure 11The polysilicon layer 134 can be etched to form a polysilicon pattern 136. The polysilicon layer 134 can be etched by photolithography. A photoresist pattern can be formed on the polysilicon layer 134 using an exposure process and a development process, and the photoresist pattern can be used as an etching block to etch the polysilicon layer 134.

[0084] Reference Figure 12 A gate insulating layer 140 can be formed on the polysilicon pattern 136. The gate insulating layer 140 can be disposed on the buffer layer 120, and the gate insulating layer 140 can cover the polysilicon pattern 136. The gate insulating layer 140 can be formed of silicon oxide, silicon nitride, or a combination thereof.

[0085] A polysilicon pattern 136 with an RMS surface roughness of approximately 4 nm or less can be formed, allowing the polysilicon pattern 136 to have a relatively small surface roughness. Therefore, the influence of protrusions formed on the surface of the polysilicon pattern 136 on the gate insulating layer 140 formed on the polysilicon pattern 136 can be minimized, and the gate insulating layer 140 can be relatively thin. The thickness of the gate insulating layer 140 can range from approximately 30 nm to approximately 200 nm.

[0086] Reference Figure 13 A gate electrode GE can be formed on the gate insulating layer 140. The gate electrode GE can be stacked with the polysilicon pattern 136. The gate electrode GE may include gold (Au), silver (Ag), aluminum (Al), copper (Cu), nickel (Ni), platinum (Pt), magnesium (Mg), chromium (Cr), tungsten (W), molybdenum (Mo), titanium (Ti), or alloys thereof, and the gate electrode GE may have a single-layer structure or a multi-layer structure including different metal layers. For example, the gate electrode GE may include a three-layer structure of Mo, Al, and Mo, or a two-layer structure of Cu and Ti, etc. A first metal layer and a photoresist pattern stacked with the polysilicon pattern 136 can be formed on the gate insulating layer 140. The first metal layer can be etched using the photoresist pattern to form the gate electrode GE.

[0087] Reference Figure 14Ions can be implanted into multiple portions of a polysilicon pattern 136 to form an active pattern AP. The polysilicon pattern 136 can be partially doped using an ion implantation process to form an active pattern AP comprising a source region (SR), a channel region (CR), and a drain region (DR). The ions can be n-type or p-type impurities. Ions can also remain undoped in the portions of the polysilicon pattern 136 superimposed with the gate electrode (GE) to form the channel region (CR). The ion-doped portions of the polysilicon pattern 136 can have increased conductivity and conductor properties, allowing the formation of the source region (SR) and the drain region (DR). The channel region (CR) can be formed between the source region (SR) and the drain region (DR). By doping with impurities at a lower concentration than that obtained using the ion implantation process, low-concentration doped regions can be formed between the channel region (CR) and the source region (SR), and between the channel region (CR) and the drain region (DR), respectively. These low-concentration doped regions can serve as buffer layers in the active pattern AP, thereby improving the electrical characteristics of the thin-film transistor.

[0088] Reference Figure 15 An insulating intermediate layer 150 can be formed on the gate electrode GE. The insulating intermediate layer 150 can be disposed on the gate insulating layer 140, and the insulating intermediate layer 150 can cover the gate electrode GE. The insulating intermediate layer 150 can include an inorganic insulating layer, an organic insulating layer, or a combination thereof. The insulating intermediate layer 150 can include silicon oxide, silicon nitride, silicon carbide, or a combination thereof. The insulating intermediate layer 150 can also include insulating metal oxides such as aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, or combinations thereof. When the insulating intermediate layer 150 includes an organic insulating layer, the insulating intermediate layer 150 can include polyimide, polyamide, acrylic resin, phenolic resin, benzocyclobutene (BCB), or a combination thereof. The insulating intermediate layer 150 and the gate insulating layer 140 can be partially etched to form a first contact hole CH1 and a second contact hole CH2 that expose the source region SR and the drain region DR, respectively.

[0089] Reference Figure 8 Source electrodes SE and drain electrodes DE, electrically connected to the source region SR and drain region DR of the active pattern AP, can be formed on the insulating intermediate layer 150. A second metal layer can be formed on the insulating intermediate layer 150 and patterned to form the source electrode SE in contact with the source region SR and the drain electrode DE in contact with the drain region DR. Each of the source electrode SE and drain electrode DE may include Au, Ag, Al, Cu, Ni, Pt, Mg, Cr, W, Mo, Ti, or alloys thereof. Each of the source electrode SE and drain electrode DE may have a single-layer structure or a multilayer structure including different metal layers. Each of the source electrode SE and drain electrode DE may include a three-layer structure of Mo, Al, and Mo, or a two-layer structure of Cu and Ti, etc.

[0090] A cleaning process using hydrofluoric acid and a rinsing process using hydrogenated deionized water can be performed prior to the crystallization process. A crystallization process in which the amorphous silicon layer is irradiated with a laser beam having a relatively high energy density at a relatively small scanning interval can be performed. The thin-film transistor TR can be formed comprising an active pattern AP having a relatively large grain size and a relatively small surface roughness. Because the grain size of the active pattern AP is relatively large, the number of grain boundaries per unit area can be reduced. Therefore, the charge mobility of the thin-film transistor TR comprising the active pattern AP can be increased. Because the surface roughness of the active pattern AP is relatively small, the interface area between the active pattern AP and the gate insulating layer 140 positioned on the active pattern AP can be reduced. Therefore, the hysteresis characteristics of the thin-film transistor TR comprising the active pattern AP can be improved, and a gate insulating layer 140 with a relatively small thickness can be formed on the active pattern AP.

[0091] Table 1 below shows the charge mobility and threshold voltage deviation of a thin-film transistor including an active pattern according to a comparative example of the prior art (the active pattern having a relatively small grain size and relatively large surface roughness by being crystallized with a laser beam having a relatively small energy density), and the charge mobility and threshold voltage deviation of a thin-film transistor TR including an active pattern AP according to one or more examples of the present disclosure (the active pattern AP having a relatively small grain size and relatively large surface roughness by being crystallized with a laser beam having a relatively large energy density (e.g., approximately 480 mJ / cm²)). 2 (The laser beam crystallizes the material, resulting in a relatively large grain size and relatively small surface roughness). The threshold voltage deviation is the difference between the threshold voltage when the pixel brightness changes from high grayscale (e.g., white grayscale) to low grayscale (e.g., black grayscale) and the threshold voltage when the pixel brightness changes from low grayscale to high grayscale, and the hysteresis characteristics of the thin-film transistor can decrease as the threshold voltage deviation increases.

[0092] [Table 1]

[0093] Comparison Examples Example <![CDATA[Charge mobility (cm 2 / V·s)]]> 89.85 92 Threshold voltage deviation (V) 0.2662 0.1874

[0094] Referring to Table 1, the charge mobility of the thin-film transistor in the comparative example is less than 90 cm⁻¹. 2 / V·s. Conversely, the charge mobility of the thin-film transistor TR according to embodiments of the invention can be greater than approximately 90 cm⁻¹. 2 / V·s. Furthermore, the threshold voltage deviation of the thin-film transistor according to the comparative example is greater than 0.22V. Conversely, the threshold voltage deviation of the thin-film transistor TR according to an embodiment of the invention can be less than approximately 0.2V. Therefore, the thin-film transistor substrate 100 according to an embodiment of the invention may include a thin-film transistor TR having relatively high charge mobility and improved hysteresis characteristics.

[0095] In the following text, reference will be made to Figures 16 to 19 A display device and a method for manufacturing a display device are described. Figure 16 This is a schematic diagram illustrating the equivalent circuitry of pixels in a display device according to one or more examples. The display device according to an embodiment may include signal lines and pixels PX connected to the signal lines and arranged in a basic matrix form.

[0096] The signal lines may include a gate line GL for transmitting gate signals (or scan signals), a data line DL for transmitting data voltages, and a drive voltage line PL for transmitting drive voltage ELVDD. The gate line GL may extend along the basic row direction. The data line DL and drive voltage line PL may intersect the gate line GL and may extend along the basic column direction. (See reference...) Figure 16 Each pixel PX may include a driving transistor TR1, a switching transistor TR2, a storage capacitor CST, and an organic light-emitting diode (OLED).

[0097] The driving transistor TR1 may include a control terminal connected to the switching transistor TR2, an input terminal connected to the driving voltage line PL, and an output terminal connected to the organic light-emitting diode (OLED). The driving transistor TR1 can transmit an output current Id to the OLED, and the magnitude of the output current Id varies according to the voltage between the control terminal and the output terminal of the driving transistor TR1.

[0098] The switching transistor TR2 may include a control terminal connected to the gate line GL, an input terminal connected to the data line DL, and an output terminal connected to the driving transistor TR1. The switching transistor TR2 can transmit the data voltage applied to the data line DL to the driving transistor TR1 in response to a gate signal applied to the gate line GL.

[0099] The storage capacitor CST connects the control terminal and input terminal of the drive transistor TR1. The storage capacitor CST stores the data voltage applied to the control terminal of the drive transistor TR1 and retains the data voltage after the switching transistor TR2 is turned off.

[0100] An organic light-emitting diode (OLED) can include an anode connected to the output terminal of a driving transistor TR1 and a cathode connected to a common voltage ELVSS. An OLED can emit light with different brightness levels depending on the output current Id of the driving transistor TR1, thereby displaying an image.

[0101] In one embodiment, each pixel PX may include two thin-film transistors TR1 and TR2 and a capacitor CST; however, the number of transistors and / or capacitors and their configuration are not limited thereto. In other embodiments, each pixel PX may include three or more thin-film transistors and two or more capacitors.

[0102] Figure 17 This is a schematic cross-sectional view showing a display device according to an embodiment.

[0103] Reference Figure 17 The display device may include a substrate 110, a thin-film transistor TR1 disposed on the substrate 110, and a display element disposed on the thin-film transistor TR1. The display device may include an organic light-emitting diode as the display element. However, in other embodiments, the display device may include a liquid crystal element, an electrophoretic element, an electrowetting element, or the like as the display element.

[0104] Figure 17 The thin-film transistor TR1 and organic light-emitting diode OLED shown can be respectively connected with Figure 16 The driving transistor TR1 shown corresponds to an organic light-emitting diode (OLED). The display device may include, for example... Figure 8 The thin-film transistor substrate 100 shown is illustrated.

[0105] An organic light-emitting diode (OLED) may include a first electrode E1, an emitting layer 180, and a second electrode E2, which are stacked sequentially. An OLED can emit light based on a driving current received from a thin-film transistor TR1 to display an image.

[0106] Figure 18 and Figure 19 This explains the manufacture of a display device according to an embodiment (e.g., Figure 17 A schematic cross-sectional view of the method for manufacturing the display device shown. In the following description of the method for manufacturing the display device, the same or similar descriptions provided above for the method for manufacturing a thin-film transistor substrate will be avoided.

[0107] Reference Figure 18 A first electrode E1 can be formed on the thin-film transistor TR1. A planarization layer (or passivation layer) 160 can be formed on the source electrode SE and the drain electrode DE. The planarization layer 160 can be disposed on the insulating intermediate layer 150, and the planarization layer 160 can cover the source electrode SE and the drain electrode DE. The planarization layer 160 can protect the thin-film transistor TR1. The planarization layer 160 can provide a planarized surface above the thin-film transistor TR1.

[0108] Planarization layer 160 may include an inorganic insulating layer, an organic insulating layer, or a combination thereof. In various examples, planarization layer 160 may have a single-layer structure or a multi-layer structure including silicon nitride or silicon oxide. When planarization layer 160 includes an organic insulating layer, planarization layer 160 may include polyimide, polyamide, acrylic resin, phenolic resin, BCB, etc., or a combination thereof.

[0109] The planarization layer 160 can be patterned to form contact holes that expose the drain electrode DE. A first electrode E1 can be formed on the planarization layer 160. The first electrode E1 can be connected to the drain electrode DE. A third metal layer can be formed on the planarization layer 160 and patterned to form the first electrode E1 that contacts the drain electrode DE.

[0110] The first electrode E1 can be a pixel electrode of the display device. The first electrode E1 can be formed as a transmissive electrode or a reflective electrode depending on the emission type of the display device. When the first electrode E1 is formed as a transmissive electrode, it can include indium tin oxide (ITO), indium zinc oxide (IZO), zinc tin oxide (ZTO), indium oxide (In₂O₃), zinc oxide (ZnO), tin oxide (SnO₂), or combinations thereof. When the first electrode E1 is formed as a reflective electrode, it can include Au, Ag, Al, Cu, Ni, Pt, Mg, Cr, W, Mo, Ti, or combinations thereof. The first electrode E1 can have a multilayer structure including materials used in the transmissive electrode.

[0111] A pixel defining layer 170 may be formed on the planarization layer 160. The pixel defining layer 170 may have an opening that exposes at least a portion of the first electrode E1. The pixel defining layer 170 may include an organic insulating material.

[0112] Reference Figure 19 An emission layer 180 can be formed on the first electrode E1. The emission layer 180 can be formed on the upper surface of the first electrode E1 exposed by the opening portion of the pixel-defined layer 170. The emission layer 180 can be formed by methods such as screen printing, inkjet printing, evaporation, etc.

[0113] The emitting layer 180 may comprise a low-molecular-weight polymer or a high-molecular-weight polymer. The emitting layer 180 may comprise copper phthalocyanine, N,N'-diphenylbenzidine, tri-(8-hydroxyquinoline)aluminum, or combinations thereof as low-molecular-weight polymers. The emitting layer 180 may comprise poly(3,4-ethylenedioxythiophene), polyaniline, poly(p-phenylacetylene), polyfluorene, or combinations thereof as high-molecular-weight polymers. The emitting layer 180 may emit red, green, or blue light. In other embodiments, the emitting layer 180 may emit white light. In that case, the emitting layer 180 may have a multilayer structure including a red emitting layer, a green emitting layer, and a blue emitting layer, or a single-layer structure including a red emitting material, a green emitting material, and a blue emitting material. A hole injection layer and / or a hole transport layer may be further formed between the first electrode E1 and the emitting layer 180, or an electron transport layer and / or an electron injection layer may be further formed on the emitting layer 180.

[0114] Reference Figure 17 A second electrode E2 can be formed on the emitting layer 180. The second electrode E2 can be the common electrode of the display device. The second electrode E2 can be formed as a transmission electrode or a reflection electrode depending on the emission type of the display device. When the second electrode E2 is formed as a transmission electrode, the second electrode E2 may include lithium (Li), calcium (Ca), lithium fluoride (LiF), aluminum (Al), magnesium (Mg), or a combination thereof.

[0115] The display device can be a top-emitting type, in which light is emitted toward the second electrode E2. However, the emission type is not limited to this. The display device can also be a bottom-emitting type.

[0116] The display device according to the published examples can be applied to display devices including computers, laptops, mobile phones, smartphones, smart tablets, PMPs, PDAs, or MP3 players.

[0117] Although methods for manufacturing polycrystalline silicon layers, thin-film transistor substrates and methods for manufacturing the same, and display devices and methods for manufacturing the same have been described with reference to the accompanying drawings, the examples shown may be modified and altered by those skilled in the art without departing from the spirit of the art as described in the claims.

Claims

1. A display device, the display device comprising: Base; Thin-film transistors are disposed on the substrate; as well as The display element is electrically connected to the thin-film transistor. The thin-film transistor includes: an active pattern disposed on the substrate, the active pattern comprising polysilicon; an insulating layer disposed on the active pattern; and a gate electrode disposed on the insulating layer. The active pattern comprises grains, and the average size of the grains is in the range of 400 nm to 800 nm. This involves rinsing the amorphous silicon layer, which has already been cleaned with hydrofluoric acid, with hydrogenated deionized water, and then utilizing a material with a flux of 440 mJ / cm⁻¹. 2 Up to 490mJ / cm 2 The polycrystalline silicon is formed by irradiating the amorphous silicon layer with a laser beam of energy density within the range of the specified range to form the active pattern.

2. The display device according to claim 1, wherein, The active pattern includes a surface on which protrusions are formed between adjacent grains in the grain, and the thickness of the protrusions is 4 nm or less.

3. The display device according to claim 2, wherein, The thickness of the protrusion corresponds to the distance between the top of the protrusion and the surface of the active pattern in the grain adjacent to the protrusion.

4. The display device according to claim 1, wherein, The active pattern includes a rough surface having a roughness with a root mean square value equal to or less than 4 nm.

5. The display device according to claim 1, wherein, The active pattern includes grain boundaries, each of which is formed between adjacent grains in the grain, and the size of the grain corresponds to the distance between adjacent grain boundaries in the grain.

6. A method for manufacturing a polycrystalline silicon layer, the method comprising the following steps: An amorphous silicon layer is formed on the substrate; The amorphous silicon layer was cleaned with hydrofluoric acid. The amorphous silicon layer was rinsed with hydrogenated deionized water. as well as With a capacity of 440mJ / cm 2 Up to 490mJ / cm 2 A laser beam with an energy density within the range is used to irradiate the amorphous silicon layer to form the polycrystalline silicon layer.

7. The method according to claim 6, wherein, The scanning spacing of the laser beam is 10 μm or less.

8. The method according to claim 6, wherein, The step of forming the polycrystalline silicon layer includes forming grains in the polycrystalline silicon layer, wherein the average size of the grains in the polycrystalline silicon layer is in the range of 400 nm to 800 nm.

9. A method for manufacturing a display device, the method comprising the following steps: An amorphous silicon layer is formed on the substrate; The amorphous silicon layer was cleaned with hydrofluoric acid. The amorphous silicon layer was rinsed with hydrogenated deionized water. With a capacity of 440mJ / cm 2 Up to 490mJ / cm 2 A laser beam with an energy density within the range of the amorphous silicon layer is used to irradiate the amorphous silicon layer to form a polycrystalline silicon layer; The polysilicon layer is etched to form a polysilicon pattern; A gate insulating layer is formed on the polysilicon pattern; A gate electrode is formed on the gate insulating layer; Ions are implanted at portions of the polycrystalline silicon pattern to form an active pattern; as well as A display element is formed on the gate electrode.

10. The method according to claim 9, wherein, The scanning spacing of the laser beam is 10 μm or less.

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